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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -S -passes=msan -mattr=+sme2 -mattr=+sme-i16i64 -mattr=+sme-f64f64 -o - %s | FileCheck %s3 4; Forked from llvm/test/CodeGen/AArch64/sme2-intrinsics-add.ll5 6target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"7target triple = "aarch64--linux-android9001"8 9define void @multi_vector_add_write_single_za_vg1x2_i32(i32 %slice, <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zm) sanitize_memory {10; CHECK-LABEL: @multi_vector_add_write_single_za_vg1x2_i32(11; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 812; CHECK-NEXT: call void @llvm.donothing()13; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP1]], 014; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1:![0-9]+]]15; CHECK: 2:16; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7:[0-9]+]]17; CHECK-NEXT: unreachable18; CHECK: 3:19; CHECK-NEXT: call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv4i32(i32 [[SLICE:%.*]], <vscale x 4 x i32> [[ZN0:%.*]], <vscale x 4 x i32> [[ZN1:%.*]], <vscale x 4 x i32> [[ZM:%.*]])20; CHECK-NEXT: [[_MSPROP:%.*]] = or i32 [[TMP1]], 021; CHECK-NEXT: [[SLICE_7:%.*]] = add i32 [[SLICE]], 722; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i32 [[_MSPROP]], 023; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF1]]24; CHECK: 4:25; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]]26; CHECK-NEXT: unreachable27; CHECK: 5:28; CHECK-NEXT: call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv4i32(i32 [[SLICE_7]], <vscale x 4 x i32> [[ZN0]], <vscale x 4 x i32> [[ZN1]], <vscale x 4 x i32> [[ZM]])29; CHECK-NEXT: ret void30;31 call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv4i32(i32 %slice,32 <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1,33 <vscale x 4 x i32> %zm)34 %slice.7 = add i32 %slice, 735 call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv4i32(i32 %slice.7,36 <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1,37 <vscale x 4 x i32> %zm)38 ret void39}40 41define void @multi_vector_add_write_single_za_vg1x2_i64(i32 %slice, <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1, <vscale x 2 x i64> %zm) sanitize_memory {42; CHECK-LABEL: @multi_vector_add_write_single_za_vg1x2_i64(43; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 844; CHECK-NEXT: call void @llvm.donothing()45; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP1]], 046; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]47; CHECK: 2:48; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]]49; CHECK-NEXT: unreachable50; CHECK: 3:51; CHECK-NEXT: call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv2i64(i32 [[SLICE:%.*]], <vscale x 2 x i64> [[ZN0:%.*]], <vscale x 2 x i64> [[ZN1:%.*]], <vscale x 2 x i64> [[ZM:%.*]])52; CHECK-NEXT: [[_MSPROP:%.*]] = or i32 [[TMP1]], 053; CHECK-NEXT: [[SLICE_7:%.*]] = add i32 [[SLICE]], 754; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i32 [[_MSPROP]], 055; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF1]]56; CHECK: 4:57; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]]58; CHECK-NEXT: unreachable59; CHECK: 5:60; CHECK-NEXT: call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv2i64(i32 [[SLICE_7]], <vscale x 2 x i64> [[ZN0]], <vscale x 2 x i64> [[ZN1]], <vscale x 2 x i64> [[ZM]])61; CHECK-NEXT: ret void62;63 call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv2i64(i32 %slice,64 <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1,65 <vscale x 2 x i64> %zm)66 %slice.7 = add i32 %slice, 767 call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv2i64(i32 %slice.7,68 <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1,69 <vscale x 2 x i64> %zm)70 ret void71}72 73 74define void @multi_vector_add_write_single_za_vg1x4_i32(i32 %slice, <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1,75; CHECK-LABEL: @multi_vector_add_write_single_za_vg1x4_i32(76; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 877; CHECK-NEXT: call void @llvm.donothing()78; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP1]], 079; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]80; CHECK: 2:81; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]]82; CHECK-NEXT: unreachable83; CHECK: 3:84; CHECK-NEXT: call void @llvm.aarch64.sme.add.write.single.za.vg1x4.nxv4i32(i32 [[SLICE:%.*]], <vscale x 4 x i32> [[ZN0:%.*]], <vscale x 4 x i32> [[ZN1:%.*]], <vscale x 4 x i32> [[ZN2:%.*]], <vscale x 4 x i32> [[ZN3:%.*]], <vscale x 4 x i32> [[ZM:%.*]])85; CHECK-NEXT: [[_MSPROP:%.*]] = or i32 [[TMP1]], 086; CHECK-NEXT: [[SLICE_7:%.*]] = add i32 [[SLICE]], 787; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i32 [[_MSPROP]], 088; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF1]]89; CHECK: 4:90; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]]91; CHECK-NEXT: unreachable92; CHECK: 5:93; CHECK-NEXT: call void @llvm.aarch64.sme.add.write.single.za.vg1x4.nxv4i32(i32 [[SLICE_7]], <vscale x 4 x i32> [[ZN0]], <vscale x 4 x i32> [[ZN1]], <vscale x 4 x i32> [[ZN2]], <vscale x 4 x i32> [[ZN3]], <vscale x 4 x i32> [[ZM]])94; CHECK-NEXT: ret void95;96 <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3,97 <vscale x 4 x i32> %zm) sanitize_memory {98 call void @llvm.aarch64.sme.add.write.single.za.vg1x4.nxv4i32(i32 %slice,99 <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1,100 <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3,101 <vscale x 4 x i32> %zm)102 %slice.7 = add i32 %slice, 7103 call void @llvm.aarch64.sme.add.write.single.za.vg1x4.nxv4i32(i32 %slice.7,104 <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1,105 <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3,106 <vscale x 4 x i32> %zm)107 ret void108}109 110define void @multi_vector_add_write_single_za_vg1x4_i64(i32 %slice,111; CHECK-LABEL: @multi_vector_add_write_single_za_vg1x4_i64(112; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8113; CHECK-NEXT: call void @llvm.donothing()114; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP1]], 0115; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]116; CHECK: 2:117; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]]118; CHECK-NEXT: unreachable119; CHECK: 3:120; CHECK-NEXT: call void @llvm.aarch64.sme.add.write.single.za.vg1x4.nxv2i64(i32 [[SLICE:%.*]], <vscale x 2 x i64> [[ZN0:%.*]], <vscale x 2 x i64> [[ZN1:%.*]], <vscale x 2 x i64> [[ZN2:%.*]], <vscale x 2 x i64> [[ZN3:%.*]], <vscale x 2 x i64> [[ZM:%.*]])121; CHECK-NEXT: [[_MSPROP:%.*]] = or i32 [[TMP1]], 0122; CHECK-NEXT: [[SLICE_7:%.*]] = add i32 [[SLICE]], 7123; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i32 [[_MSPROP]], 0124; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF1]]125; CHECK: 4:126; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]]127; CHECK-NEXT: unreachable128; CHECK: 5:129; CHECK-NEXT: call void @llvm.aarch64.sme.add.write.single.za.vg1x4.nxv2i64(i32 [[SLICE_7]], <vscale x 2 x i64> [[ZN0]], <vscale x 2 x i64> [[ZN1]], <vscale x 2 x i64> [[ZN2]], <vscale x 2 x i64> [[ZN3]], <vscale x 2 x i64> [[ZM]])130; CHECK-NEXT: ret void131;132 <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1,133 <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zn3,134 <vscale x 2 x i64> %zm) sanitize_memory {135 call void @llvm.aarch64.sme.add.write.single.za.vg1x4.nxv2i64(i32 %slice,136 <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1,137 <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zn3,138 <vscale x 2 x i64> %zm)139 %slice.7 = add i32 %slice, 7140 call void @llvm.aarch64.sme.add.write.single.za.vg1x4.nxv2i64(i32 %slice.7,141 <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1,142 <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zn3,143 <vscale x 2 x i64> %zm)144 ret void145}146 147 148define void @multi_vector_add_write_za_vg1x2_i32(i32 %slice, <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1,149; CHECK-LABEL: @multi_vector_add_write_za_vg1x2_i32(150; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8151; CHECK-NEXT: call void @llvm.donothing()152; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP1]], 0153; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]154; CHECK: 2:155; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]]156; CHECK-NEXT: unreachable157; CHECK: 3:158; CHECK-NEXT: call void @llvm.aarch64.sme.add.write.za.vg1x2.nxv4i32(i32 [[SLICE:%.*]], <vscale x 4 x i32> [[ZN0:%.*]], <vscale x 4 x i32> [[ZN1:%.*]], <vscale x 4 x i32> [[ZM1:%.*]], <vscale x 4 x i32> [[ZM2:%.*]])159; CHECK-NEXT: [[_MSPROP:%.*]] = or i32 [[TMP1]], 0160; CHECK-NEXT: [[SLICE_7:%.*]] = add i32 [[SLICE]], 7161; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i32 [[_MSPROP]], 0162; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF1]]163; CHECK: 4:164; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]]165; CHECK-NEXT: unreachable166; CHECK: 5:167; CHECK-NEXT: call void @llvm.aarch64.sme.add.write.za.vg1x2.nxv4i32(i32 [[SLICE_7]], <vscale x 4 x i32> [[ZN0]], <vscale x 4 x i32> [[ZN1]], <vscale x 4 x i32> [[ZM1]], <vscale x 4 x i32> [[ZM2]])168; CHECK-NEXT: ret void169;170 <vscale x 4 x i32> %zm1, <vscale x 4 x i32> %zm2) sanitize_memory {171 call void @llvm.aarch64.sme.add.write.za.vg1x2.nxv4i32(i32 %slice,172 <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1,173 <vscale x 4 x i32> %zm1, <vscale x 4 x i32> %zm2)174 %slice.7 = add i32 %slice, 7175 call void @llvm.aarch64.sme.add.write.za.vg1x2.nxv4i32(i32 %slice.7,176 <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1,177 <vscale x 4 x i32> %zm1, <vscale x 4 x i32> %zm2)178 ret void179}180 181 182define void @multi_vector_add_write_za_vg1x2_i64(i32 %slice, <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1,183; CHECK-LABEL: @multi_vector_add_write_za_vg1x2_i64(184; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8185; CHECK-NEXT: call void @llvm.donothing()186; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP1]], 0187; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]188; CHECK: 2:189; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]]190; CHECK-NEXT: unreachable191; CHECK: 3:192; CHECK-NEXT: call void @llvm.aarch64.sme.add.write.za.vg1x2.nxv2i64(i32 [[SLICE:%.*]], <vscale x 2 x i64> [[ZN0:%.*]], <vscale x 2 x i64> [[ZN1:%.*]], <vscale x 2 x i64> [[ZM1:%.*]], <vscale x 2 x i64> [[ZM2:%.*]])193; CHECK-NEXT: [[_MSPROP:%.*]] = or i32 [[TMP1]], 0194; CHECK-NEXT: [[SLICE_7:%.*]] = add i32 [[SLICE]], 7195; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i32 [[_MSPROP]], 0196; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF1]]197; CHECK: 4:198; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]]199; CHECK-NEXT: unreachable200; CHECK: 5:201; CHECK-NEXT: call void @llvm.aarch64.sme.add.write.za.vg1x2.nxv2i64(i32 [[SLICE_7]], <vscale x 2 x i64> [[ZN0]], <vscale x 2 x i64> [[ZN1]], <vscale x 2 x i64> [[ZM1]], <vscale x 2 x i64> [[ZM2]])202; CHECK-NEXT: ret void203;204 <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2) sanitize_memory {205 call void @llvm.aarch64.sme.add.write.za.vg1x2.nxv2i64(i32 %slice,206 <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1,207 <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2)208 %slice.7 = add i32 %slice, 7209 call void @llvm.aarch64.sme.add.write.za.vg1x2.nxv2i64(i32 %slice.7,210 <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1,211 <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2)212 ret void213}214 215 216 217define void @multi_vector_add_write_za_vg1x4_i32(i32 %slice, <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1,218; CHECK-LABEL: @multi_vector_add_write_za_vg1x4_i32(219; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8220; CHECK-NEXT: call void @llvm.donothing()221; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP1]], 0222; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]223; CHECK: 2:224; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]]225; CHECK-NEXT: unreachable226; CHECK: 3:227; CHECK-NEXT: call void @llvm.aarch64.sme.add.write.za.vg1x4.nxv4i32(i32 [[SLICE:%.*]], <vscale x 4 x i32> [[ZN0:%.*]], <vscale x 4 x i32> [[ZN1:%.*]], <vscale x 4 x i32> [[ZN2:%.*]], <vscale x 4 x i32> [[ZN3:%.*]], <vscale x 4 x i32> [[ZM0:%.*]], <vscale x 4 x i32> [[ZM1:%.*]], <vscale x 4 x i32> [[ZM2:%.*]], <vscale x 4 x i32> [[ZM3:%.*]])228; CHECK-NEXT: [[_MSPROP:%.*]] = or i32 [[TMP1]], 0229; CHECK-NEXT: [[SLICE_7:%.*]] = add i32 [[SLICE]], 7230; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i32 [[_MSPROP]], 0231; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF1]]232; CHECK: 4:233; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]]234; CHECK-NEXT: unreachable235; CHECK: 5:236; CHECK-NEXT: call void @llvm.aarch64.sme.add.write.za.vg1x4.nxv4i32(i32 [[SLICE_7]], <vscale x 4 x i32> [[ZN0]], <vscale x 4 x i32> [[ZN1]], <vscale x 4 x i32> [[ZN2]], <vscale x 4 x i32> [[ZN3]], <vscale x 4 x i32> [[ZM0]], <vscale x 4 x i32> [[ZM1]], <vscale x 4 x i32> [[ZM2]], <vscale x 4 x i32> [[ZM3]])237; CHECK-NEXT: ret void238;239 <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3,240 <vscale x 4 x i32> %zm0, <vscale x 4 x i32> %zm1,241 <vscale x 4 x i32> %zm2, <vscale x 4 x i32> %zm3) sanitize_memory {242 call void @llvm.aarch64.sme.add.write.za.vg1x4.nxv4i32(i32 %slice,243 <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1,244 <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3,245 <vscale x 4 x i32> %zm0, <vscale x 4 x i32> %zm1,246 <vscale x 4 x i32> %zm2, <vscale x 4 x i32> %zm3)247 %slice.7 = add i32 %slice, 7248 call void @llvm.aarch64.sme.add.write.za.vg1x4.nxv4i32(i32 %slice.7,249 <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1,250 <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3,251 <vscale x 4 x i32> %zm0, <vscale x 4 x i32> %zm1,252 <vscale x 4 x i32> %zm2, <vscale x 4 x i32> %zm3)253 ret void254}255 256define void @multi_vector_add_write_za_vg1x4_i64(i32 %slice, <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1,257; CHECK-LABEL: @multi_vector_add_write_za_vg1x4_i64(258; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8259; CHECK-NEXT: call void @llvm.donothing()260; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP1]], 0261; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]262; CHECK: 2:263; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]]264; CHECK-NEXT: unreachable265; CHECK: 3:266; CHECK-NEXT: call void @llvm.aarch64.sme.add.write.za.vg1x4.nxv2i64(i32 [[SLICE:%.*]], <vscale x 2 x i64> [[ZN0:%.*]], <vscale x 2 x i64> [[ZN1:%.*]], <vscale x 2 x i64> [[ZN2:%.*]], <vscale x 2 x i64> [[ZN3:%.*]], <vscale x 2 x i64> [[ZM0:%.*]], <vscale x 2 x i64> [[ZM1:%.*]], <vscale x 2 x i64> [[ZM2:%.*]], <vscale x 2 x i64> [[ZM3:%.*]])267; CHECK-NEXT: [[_MSPROP:%.*]] = or i32 [[TMP1]], 0268; CHECK-NEXT: [[SLICE_7:%.*]] = add i32 [[SLICE]], 7269; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i32 [[_MSPROP]], 0270; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF1]]271; CHECK: 4:272; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]]273; CHECK-NEXT: unreachable274; CHECK: 5:275; CHECK-NEXT: call void @llvm.aarch64.sme.add.write.za.vg1x4.nxv2i64(i32 [[SLICE_7]], <vscale x 2 x i64> [[ZN0]], <vscale x 2 x i64> [[ZN1]], <vscale x 2 x i64> [[ZN2]], <vscale x 2 x i64> [[ZN3]], <vscale x 2 x i64> [[ZM0]], <vscale x 2 x i64> [[ZM1]], <vscale x 2 x i64> [[ZM2]], <vscale x 2 x i64> [[ZM3]])276; CHECK-NEXT: ret void277;278 <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zn3,279 <vscale x 2 x i64> %zm0, <vscale x 2 x i64> %zm1,280 <vscale x 2 x i64> %zm2, <vscale x 2 x i64> %zm3) sanitize_memory {281 call void @llvm.aarch64.sme.add.write.za.vg1x4.nxv2i64(i32 %slice,282 <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1,283 <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zn3,284 <vscale x 2 x i64> %zm0, <vscale x 2 x i64> %zm1,285 <vscale x 2 x i64> %zm2, <vscale x 2 x i64> %zm3)286 %slice.7 = add i32 %slice, 7287 call void @llvm.aarch64.sme.add.write.za.vg1x4.nxv2i64(i32 %slice.7,288 <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1,289 <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zn3,290 <vscale x 2 x i64> %zm0, <vscale x 2 x i64> %zm1,291 <vscale x 2 x i64> %zm2, <vscale x 2 x i64> %zm3)292 ret void293}294 295define void @multi_vector_add_za_vg1x2_i32(i32 %slice, <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1) sanitize_memory {296; CHECK-LABEL: @multi_vector_add_za_vg1x2_i32(297; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8298; CHECK-NEXT: call void @llvm.donothing()299; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP1]], 0300; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]301; CHECK: 2:302; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]]303; CHECK-NEXT: unreachable304; CHECK: 3:305; CHECK-NEXT: call void @llvm.aarch64.sme.add.za32.vg1x2.nxv4i32(i32 [[SLICE:%.*]], <vscale x 4 x i32> [[ZN0:%.*]], <vscale x 4 x i32> [[ZN1:%.*]])306; CHECK-NEXT: [[_MSPROP:%.*]] = or i32 [[TMP1]], 0307; CHECK-NEXT: [[SLICE_7:%.*]] = add i32 [[SLICE]], 7308; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i32 [[_MSPROP]], 0309; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF1]]310; CHECK: 4:311; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]]312; CHECK-NEXT: unreachable313; CHECK: 5:314; CHECK-NEXT: call void @llvm.aarch64.sme.add.za32.vg1x2.nxv4i32(i32 [[SLICE_7]], <vscale x 4 x i32> [[ZN0]], <vscale x 4 x i32> [[ZN1]])315; CHECK-NEXT: ret void316;317 call void @llvm.aarch64.sme.add.za32.vg1x2.nxv4i32(i32 %slice,<vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1)318 %slice.7 = add i32 %slice, 7319 call void @llvm.aarch64.sme.add.za32.vg1x2.nxv4i32(i32 %slice.7, <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1)320 ret void321}322 323define void @multi_vector_add_za_vg1x2_i64(i32 %slice, <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1) sanitize_memory {324; CHECK-LABEL: @multi_vector_add_za_vg1x2_i64(325; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8326; CHECK-NEXT: call void @llvm.donothing()327; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP1]], 0328; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]329; CHECK: 2:330; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]]331; CHECK-NEXT: unreachable332; CHECK: 3:333; CHECK-NEXT: call void @llvm.aarch64.sme.add.za64.vg1x2.nxv2i64(i32 [[SLICE:%.*]], <vscale x 2 x i64> [[ZN0:%.*]], <vscale x 2 x i64> [[ZN1:%.*]])334; CHECK-NEXT: [[_MSPROP:%.*]] = or i32 [[TMP1]], 0335; CHECK-NEXT: [[SLICE_7:%.*]] = add i32 [[SLICE]], 7336; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i32 [[_MSPROP]], 0337; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF1]]338; CHECK: 4:339; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]]340; CHECK-NEXT: unreachable341; CHECK: 5:342; CHECK-NEXT: call void @llvm.aarch64.sme.add.za64.vg1x2.nxv2i64(i32 [[SLICE_7]], <vscale x 2 x i64> [[ZN0]], <vscale x 2 x i64> [[ZN1]])343; CHECK-NEXT: ret void344;345 call void @llvm.aarch64.sme.add.za64.vg1x2.nxv2i64(i32 %slice, <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1)346 %slice.7 = add i32 %slice, 7347 call void @llvm.aarch64.sme.add.za64.vg1x2.nxv2i64(i32 %slice.7, <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1)348 ret void349}350 351define void @multi_vector_add_za_vg1x2_f32(i32 %slice, <vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1) sanitize_memory {352; CHECK-LABEL: @multi_vector_add_za_vg1x2_f32(353; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8354; CHECK-NEXT: call void @llvm.donothing()355; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP1]], 0356; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]357; CHECK: 2:358; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]]359; CHECK-NEXT: unreachable360; CHECK: 3:361; CHECK-NEXT: call void @llvm.aarch64.sme.add.za32.vg1x2.nxv4f32(i32 [[SLICE:%.*]], <vscale x 4 x float> [[ZN0:%.*]], <vscale x 4 x float> [[ZN1:%.*]])362; CHECK-NEXT: [[_MSPROP:%.*]] = or i32 [[TMP1]], 0363; CHECK-NEXT: [[SLICE_7:%.*]] = add i32 [[SLICE]], 7364; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i32 [[_MSPROP]], 0365; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF1]]366; CHECK: 4:367; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]]368; CHECK-NEXT: unreachable369; CHECK: 5:370; CHECK-NEXT: call void @llvm.aarch64.sme.add.za32.vg1x2.nxv4f32(i32 [[SLICE_7]], <vscale x 4 x float> [[ZN0]], <vscale x 4 x float> [[ZN1]])371; CHECK-NEXT: ret void372;373 call void @llvm.aarch64.sme.add.za32.vg1x2.nxv4f32(i32 %slice,374 <vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1)375 %slice.7 = add i32 %slice, 7376 call void @llvm.aarch64.sme.add.za32.vg1x2.nxv4f32(i32 %slice.7,377 <vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1)378 ret void379}380 381define void @multi_vector_add_za_vg1x2_f64(i32 %slice, <vscale x 2 x double> %zn0, <vscale x 2 x double> %zn1) sanitize_memory {382; CHECK-LABEL: @multi_vector_add_za_vg1x2_f64(383; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8384; CHECK-NEXT: call void @llvm.donothing()385; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP1]], 0386; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]387; CHECK: 2:388; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]]389; CHECK-NEXT: unreachable390; CHECK: 3:391; CHECK-NEXT: call void @llvm.aarch64.sme.add.za64.vg1x2.nxv2f64(i32 [[SLICE:%.*]], <vscale x 2 x double> [[ZN0:%.*]], <vscale x 2 x double> [[ZN1:%.*]])392; CHECK-NEXT: [[_MSPROP:%.*]] = or i32 [[TMP1]], 0393; CHECK-NEXT: [[SLICE_7:%.*]] = add i32 [[SLICE]], 7394; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i32 [[_MSPROP]], 0395; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF1]]396; CHECK: 4:397; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]]398; CHECK-NEXT: unreachable399; CHECK: 5:400; CHECK-NEXT: call void @llvm.aarch64.sme.add.za64.vg1x2.nxv2f64(i32 [[SLICE_7]], <vscale x 2 x double> [[ZN0]], <vscale x 2 x double> [[ZN1]])401; CHECK-NEXT: ret void402;403 call void @llvm.aarch64.sme.add.za64.vg1x2.nxv2f64(i32 %slice,404 <vscale x 2 x double> %zn0, <vscale x 2 x double> %zn1)405 %slice.7 = add i32 %slice, 7406 call void @llvm.aarch64.sme.add.za64.vg1x2.nxv2f64(i32 %slice.7,407 <vscale x 2 x double> %zn0, <vscale x 2 x double> %zn1)408 ret void409}410 411define void @multi_vector_add_za_vg1x2_f64_tuple(i64 %stride, ptr %ptr) sanitize_memory {412; CHECK-LABEL: @multi_vector_add_za_vg1x2_f64_tuple(413; CHECK-NEXT: entry:414; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8415; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8416; CHECK-NEXT: call void @llvm.donothing()417; CHECK-NEXT: [[TMP2:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.ptrue.c8()418; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP0]], 0419; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]420; CHECK: 3:421; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]]422; CHECK-NEXT: unreachable423; CHECK: 4:424; CHECK-NEXT: [[TMP5:%.*]] = tail call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.ld1.pn.x2.nxv2f64(target("aarch64.svcount") [[TMP2]], ptr [[PTR:%.*]])425; CHECK-NEXT: [[TMP6:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } [[TMP5]], 0426; CHECK-NEXT: [[TMP7:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } [[TMP5]], 1427; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP0]], [[TMP1]]428; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[PTR]], i64 [[STRIDE:%.*]]429; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[_MSPROP]], 0430; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]431; CHECK: 8:432; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]]433; CHECK-NEXT: unreachable434; CHECK: 9:435; CHECK-NEXT: [[TMP10:%.*]] = tail call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.ld1.pn.x2.nxv2f64(target("aarch64.svcount") [[TMP2]], ptr [[ARRAYIDX2]])436; CHECK-NEXT: [[TMP11:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } [[TMP10]], 0437; CHECK-NEXT: [[TMP12:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } [[TMP10]], 1438; CHECK-NEXT: call void @llvm.aarch64.sme.add.za64.vg1x2.nxv2f64(i32 0, <vscale x 2 x double> [[TMP6]], <vscale x 2 x double> [[TMP11]])439; CHECK-NEXT: call void @llvm.aarch64.sme.add.za64.vg1x2.nxv2f64(i32 0, <vscale x 2 x double> [[TMP7]], <vscale x 2 x double> [[TMP12]])440; CHECK-NEXT: ret void441;442entry:443 %0 = tail call target("aarch64.svcount") @llvm.aarch64.sve.ptrue.c8()444 %1 = tail call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.ld1.pn.x2.nxv2f64(target("aarch64.svcount") %0, ptr %ptr)445 %2 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %1, 0446 %3 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %1, 1447 %arrayidx2 = getelementptr inbounds i8, ptr %ptr, i64 %stride448 %4 = tail call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.ld1.pn.x2.nxv2f64(target("aarch64.svcount") %0, ptr %arrayidx2)449 %5 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %4, 0450 %6 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %4, 1451 call void @llvm.aarch64.sme.add.za64.vg1x2.nxv2f64(i32 0, <vscale x 2 x double> %2, <vscale x 2 x double> %5)452 call void @llvm.aarch64.sme.add.za64.vg1x2.nxv2f64(i32 0, <vscale x 2 x double> %3, <vscale x 2 x double> %6)453 ret void454}455 456 457define void @multi_vector_add_za_vg1x4_i32(i32 %slice, <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3) sanitize_memory {458; CHECK-LABEL: @multi_vector_add_za_vg1x4_i32(459; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8460; CHECK-NEXT: call void @llvm.donothing()461; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP1]], 0462; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]463; CHECK: 2:464; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]]465; CHECK-NEXT: unreachable466; CHECK: 3:467; CHECK-NEXT: call void @llvm.aarch64.sme.add.za32.vg1x4.nxv4i32(i32 [[SLICE:%.*]], <vscale x 4 x i32> [[ZN0:%.*]], <vscale x 4 x i32> [[ZN1:%.*]], <vscale x 4 x i32> [[ZN2:%.*]], <vscale x 4 x i32> [[ZN3:%.*]])468; CHECK-NEXT: [[_MSPROP:%.*]] = or i32 [[TMP1]], 0469; CHECK-NEXT: [[SLICE_7:%.*]] = add i32 [[SLICE]], 7470; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i32 [[_MSPROP]], 0471; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF1]]472; CHECK: 4:473; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]]474; CHECK-NEXT: unreachable475; CHECK: 5:476; CHECK-NEXT: call void @llvm.aarch64.sme.add.za32.vg1x4.nxv4i32(i32 [[SLICE_7]], <vscale x 4 x i32> [[ZN0]], <vscale x 4 x i32> [[ZN1]], <vscale x 4 x i32> [[ZN2]], <vscale x 4 x i32> [[ZN3]])477; CHECK-NEXT: ret void478;479 call void @llvm.aarch64.sme.add.za32.vg1x4.nxv4i32(i32 %slice,480 <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1,481 <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3)482 %slice.7 = add i32 %slice, 7483 call void @llvm.aarch64.sme.add.za32.vg1x4.nxv4i32(i32 %slice.7,484 <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1,485 <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3)486 ret void487}488 489define void @multi_vector_add_za_vg1x4_i64(i32 %slice, <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1, <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zn3) sanitize_memory {490; CHECK-LABEL: @multi_vector_add_za_vg1x4_i64(491; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8492; CHECK-NEXT: call void @llvm.donothing()493; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP1]], 0494; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]495; CHECK: 2:496; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]]497; CHECK-NEXT: unreachable498; CHECK: 3:499; CHECK-NEXT: call void @llvm.aarch64.sme.add.za64.vg1x4.nxv2i64(i32 [[SLICE:%.*]], <vscale x 2 x i64> [[ZN0:%.*]], <vscale x 2 x i64> [[ZN1:%.*]], <vscale x 2 x i64> [[ZN2:%.*]], <vscale x 2 x i64> [[ZN3:%.*]])500; CHECK-NEXT: [[_MSPROP:%.*]] = or i32 [[TMP1]], 0501; CHECK-NEXT: [[SLICE_7:%.*]] = add i32 [[SLICE]], 7502; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i32 [[_MSPROP]], 0503; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF1]]504; CHECK: 4:505; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]]506; CHECK-NEXT: unreachable507; CHECK: 5:508; CHECK-NEXT: call void @llvm.aarch64.sme.add.za64.vg1x4.nxv2i64(i32 [[SLICE_7]], <vscale x 2 x i64> [[ZN0]], <vscale x 2 x i64> [[ZN1]], <vscale x 2 x i64> [[ZN2]], <vscale x 2 x i64> [[ZN3]])509; CHECK-NEXT: ret void510;511 call void @llvm.aarch64.sme.add.za64.vg1x4.nxv2i64(i32 %slice,512 <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1,513 <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zn3)514 %slice.7 = add i32 %slice, 7515 call void @llvm.aarch64.sme.add.za64.vg1x4.nxv2i64(i32 %slice.7,516 <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1,517 <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zn3)518 ret void519}520 521define void @multi_vector_add_za_vg1x4_f32(i32 %slice, <vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2, <vscale x 4 x float> %zn3) sanitize_memory {522; CHECK-LABEL: @multi_vector_add_za_vg1x4_f32(523; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8524; CHECK-NEXT: call void @llvm.donothing()525; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP1]], 0526; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]527; CHECK: 2:528; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]]529; CHECK-NEXT: unreachable530; CHECK: 3:531; CHECK-NEXT: call void @llvm.aarch64.sme.add.za32.vg1x4.nxv4f32(i32 [[SLICE:%.*]], <vscale x 4 x float> [[ZN0:%.*]], <vscale x 4 x float> [[ZN1:%.*]], <vscale x 4 x float> [[ZN2:%.*]], <vscale x 4 x float> [[ZN3:%.*]])532; CHECK-NEXT: [[_MSPROP:%.*]] = or i32 [[TMP1]], 0533; CHECK-NEXT: [[SLICE_7:%.*]] = add i32 [[SLICE]], 7534; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i32 [[_MSPROP]], 0535; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF1]]536; CHECK: 4:537; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]]538; CHECK-NEXT: unreachable539; CHECK: 5:540; CHECK-NEXT: call void @llvm.aarch64.sme.add.za32.vg1x4.nxv4f32(i32 [[SLICE_7]], <vscale x 4 x float> [[ZN0]], <vscale x 4 x float> [[ZN1]], <vscale x 4 x float> [[ZN2]], <vscale x 4 x float> [[ZN3]])541; CHECK-NEXT: ret void542;543 call void @llvm.aarch64.sme.add.za32.vg1x4.nxv4f32(i32 %slice,544 <vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1,545 <vscale x 4 x float> %zn2, <vscale x 4 x float> %zn3)546 %slice.7 = add i32 %slice, 7547 call void @llvm.aarch64.sme.add.za32.vg1x4.nxv4f32(i32 %slice.7,548 <vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1,549 <vscale x 4 x float> %zn2, <vscale x 4 x float> %zn3)550 ret void551}552 553define void @multi_vector_add_za_vg1x4_f32_tuple(i64 %stride, ptr %ptr) sanitize_memory {554; CHECK-LABEL: @multi_vector_add_za_vg1x4_f32_tuple(555; CHECK-NEXT: entry:556; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8557; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8558; CHECK-NEXT: call void @llvm.donothing()559; CHECK-NEXT: [[TMP2:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.ptrue.c8()560; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP0]], 0561; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]562; CHECK: 3:563; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]]564; CHECK-NEXT: unreachable565; CHECK: 4:566; CHECK-NEXT: [[TMP5:%.*]] = tail call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld1.pn.x4.nxv4f32(target("aarch64.svcount") [[TMP2]], ptr [[PTR:%.*]])567; CHECK-NEXT: [[TMP6:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP5]], 0568; CHECK-NEXT: [[TMP7:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP5]], 1569; CHECK-NEXT: [[TMP8:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP5]], 2570; CHECK-NEXT: [[TMP9:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP5]], 3571; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP0]], [[TMP1]]572; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[PTR]], i64 [[STRIDE:%.*]]573; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[_MSPROP]], 0574; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP10:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]575; CHECK: 10:576; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]]577; CHECK-NEXT: unreachable578; CHECK: 11:579; CHECK-NEXT: [[TMP12:%.*]] = tail call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld1.pn.x4.nxv4f32(target("aarch64.svcount") [[TMP2]], ptr [[ARRAYIDX2]])580; CHECK-NEXT: [[TMP13:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP12]], 0581; CHECK-NEXT: [[TMP14:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP12]], 1582; CHECK-NEXT: [[TMP15:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP12]], 2583; CHECK-NEXT: [[TMP16:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP12]], 3584; CHECK-NEXT: [[TMP17:%.*]] = shl i64 [[TMP1]], 1585; CHECK-NEXT: [[TMP18:%.*]] = or i64 [[TMP17]], 0586; CHECK-NEXT: [[MUL3:%.*]] = shl i64 [[STRIDE]], 1587; CHECK-NEXT: [[_MSPROP1:%.*]] = or i64 [[TMP0]], [[TMP18]]588; CHECK-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[PTR]], i64 [[MUL3]]589; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i64 [[_MSPROP1]], 0590; CHECK-NEXT: br i1 [[_MSCMP4]], label [[TMP19:%.*]], label [[TMP20:%.*]], !prof [[PROF1]]591; CHECK: 19:592; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]]593; CHECK-NEXT: unreachable594; CHECK: 20:595; CHECK-NEXT: [[TMP21:%.*]] = tail call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld1.pn.x4.nxv4f32(target("aarch64.svcount") [[TMP2]], ptr [[ARRAYIDX4]])596; CHECK-NEXT: [[TMP22:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP21]], 0597; CHECK-NEXT: [[TMP23:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP21]], 1598; CHECK-NEXT: [[TMP24:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP21]], 2599; CHECK-NEXT: [[TMP25:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP21]], 3600; CHECK-NEXT: [[MSPROP_MUL_CST:%.*]] = mul i64 [[TMP1]], 1601; CHECK-NEXT: [[MUL5:%.*]] = mul i64 [[STRIDE]], 3602; CHECK-NEXT: [[_MSPROP2:%.*]] = or i64 [[TMP0]], [[MSPROP_MUL_CST]]603; CHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i8, ptr [[PTR]], i64 [[MUL5]]604; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i64 [[_MSPROP2]], 0605; CHECK-NEXT: br i1 [[_MSCMP5]], label [[TMP26:%.*]], label [[TMP27:%.*]], !prof [[PROF1]]606; CHECK: 26:607; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]]608; CHECK-NEXT: unreachable609; CHECK: 27:610; CHECK-NEXT: [[TMP28:%.*]] = tail call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld1.pn.x4.nxv4f32(target("aarch64.svcount") [[TMP2]], ptr [[ARRAYIDX6]])611; CHECK-NEXT: [[TMP29:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP28]], 0612; CHECK-NEXT: [[TMP30:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP28]], 1613; CHECK-NEXT: [[TMP31:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP28]], 2614; CHECK-NEXT: [[TMP32:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP28]], 3615; CHECK-NEXT: call void @llvm.aarch64.sme.add.za32.vg1x4.nxv4f32(i32 0, <vscale x 4 x float> [[TMP6]], <vscale x 4 x float> [[TMP13]], <vscale x 4 x float> [[TMP22]], <vscale x 4 x float> [[TMP29]])616; CHECK-NEXT: call void @llvm.aarch64.sme.add.za32.vg1x4.nxv4f32(i32 0, <vscale x 4 x float> [[TMP7]], <vscale x 4 x float> [[TMP14]], <vscale x 4 x float> [[TMP23]], <vscale x 4 x float> [[TMP30]])617; CHECK-NEXT: call void @llvm.aarch64.sme.add.za32.vg1x4.nxv4f32(i32 0, <vscale x 4 x float> [[TMP8]], <vscale x 4 x float> [[TMP15]], <vscale x 4 x float> [[TMP24]], <vscale x 4 x float> [[TMP31]])618; CHECK-NEXT: call void @llvm.aarch64.sme.add.za32.vg1x4.nxv4f32(i32 0, <vscale x 4 x float> [[TMP9]], <vscale x 4 x float> [[TMP16]], <vscale x 4 x float> [[TMP25]], <vscale x 4 x float> [[TMP32]])619; CHECK-NEXT: ret void620;621entry:622 %0 = tail call target("aarch64.svcount") @llvm.aarch64.sve.ptrue.c8()623 %1 = tail call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld1.pn.x4.nxv4f32(target("aarch64.svcount") %0, ptr %ptr)624 %2 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, 0625 %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, 1626 %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, 2627 %5 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, 3628 %arrayidx2 = getelementptr inbounds i8, ptr %ptr, i64 %stride629 %6 = tail call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld1.pn.x4.nxv4f32(target("aarch64.svcount") %0, ptr %arrayidx2)630 %7 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %6, 0631 %8 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %6, 1632 %9 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %6, 2633 %10 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %6, 3634 %mul3 = shl i64 %stride, 1635 %arrayidx4 = getelementptr inbounds i8, ptr %ptr, i64 %mul3636 %11 = tail call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld1.pn.x4.nxv4f32(target("aarch64.svcount") %0, ptr %arrayidx4)637 %12 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %11, 0638 %13 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %11, 1639 %14 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %11, 2640 %15 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %11, 3641 %mul5 = mul i64 %stride, 3642 %arrayidx6 = getelementptr inbounds i8, ptr %ptr, i64 %mul5643 %16 = tail call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld1.pn.x4.nxv4f32(target("aarch64.svcount") %0, ptr %arrayidx6)644 %17 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %16, 0645 %18 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %16, 1646 %19 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %16, 2647 %20 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %16, 3648 call void @llvm.aarch64.sme.add.za32.vg1x4.nxv4f32(i32 0, <vscale x 4 x float> %2, <vscale x 4 x float> %7, <vscale x 4 x float> %12, <vscale x 4 x float> %17)649 call void @llvm.aarch64.sme.add.za32.vg1x4.nxv4f32(i32 0, <vscale x 4 x float> %3, <vscale x 4 x float> %8, <vscale x 4 x float> %13, <vscale x 4 x float> %18)650 call void @llvm.aarch64.sme.add.za32.vg1x4.nxv4f32(i32 0, <vscale x 4 x float> %4, <vscale x 4 x float> %9, <vscale x 4 x float> %14, <vscale x 4 x float> %19)651 call void @llvm.aarch64.sme.add.za32.vg1x4.nxv4f32(i32 0, <vscale x 4 x float> %5, <vscale x 4 x float> %10, <vscale x 4 x float> %15, <vscale x 4 x float> %20)652 ret void653}654 655define void @multi_vector_add_za_vg1x4_f64(i32 %slice, <vscale x 2 x double> %zn0, <vscale x 2 x double> %zn1, <vscale x 2 x double> %zn2, <vscale x 2 x double> %zn3) sanitize_memory {656; CHECK-LABEL: @multi_vector_add_za_vg1x4_f64(657; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8658; CHECK-NEXT: call void @llvm.donothing()659; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP1]], 0660; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]661; CHECK: 2:662; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]]663; CHECK-NEXT: unreachable664; CHECK: 3:665; CHECK-NEXT: call void @llvm.aarch64.sme.add.za64.vg1x4.nxv2f64(i32 [[SLICE:%.*]], <vscale x 2 x double> [[ZN0:%.*]], <vscale x 2 x double> [[ZN1:%.*]], <vscale x 2 x double> [[ZN2:%.*]], <vscale x 2 x double> [[ZN3:%.*]])666; CHECK-NEXT: [[_MSPROP:%.*]] = or i32 [[TMP1]], 0667; CHECK-NEXT: [[SLICE_7:%.*]] = add i32 [[SLICE]], 7668; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i32 [[_MSPROP]], 0669; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF1]]670; CHECK: 4:671; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]]672; CHECK-NEXT: unreachable673; CHECK: 5:674; CHECK-NEXT: call void @llvm.aarch64.sme.add.za64.vg1x4.nxv2f64(i32 [[SLICE_7]], <vscale x 2 x double> [[ZN0]], <vscale x 2 x double> [[ZN1]], <vscale x 2 x double> [[ZN2]], <vscale x 2 x double> [[ZN3]])675; CHECK-NEXT: ret void676;677 call void @llvm.aarch64.sme.add.za64.vg1x4.nxv2f64(i32 %slice,678 <vscale x 2 x double> %zn0, <vscale x 2 x double> %zn1,679 <vscale x 2 x double> %zn2, <vscale x 2 x double> %zn3)680 %slice.7 = add i32 %slice, 7681 call void @llvm.aarch64.sme.add.za64.vg1x4.nxv2f64(i32 %slice.7,682 <vscale x 2 x double> %zn0, <vscale x 2 x double> %zn1,683 <vscale x 2 x double> %zn2, <vscale x 2 x double> %zn3)684 ret void685}686 687 688define { <vscale x 16 x i8>, <vscale x 16 x i8> } @multi_vec_add_single_x2_s8(<vscale x 16 x i8> %unused, <vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zm) sanitize_memory {689; CHECK-LABEL: @multi_vec_add_single_x2_s8(690; CHECK-NEXT: call void @llvm.donothing()691; CHECK-NEXT: [[RES:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.add.single.x2.nxv16i8(<vscale x 16 x i8> [[ZDN1:%.*]], <vscale x 16 x i8> [[ZDN2:%.*]], <vscale x 16 x i8> [[ZM:%.*]])692; CHECK-NEXT: store { <vscale x 16 x i8>, <vscale x 16 x i8> } zeroinitializer, ptr @__msan_retval_tls, align 8693; CHECK-NEXT: ret { <vscale x 16 x i8>, <vscale x 16 x i8> } [[RES]]694;695 %res = call { <vscale x 16 x i8>, <vscale x 16 x i8> }696 @llvm.aarch64.sve.add.single.x2.nxv16i8(<vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2,697 <vscale x 16 x i8> %zm)698 ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %res699}700 701define { <vscale x 8 x i16>, <vscale x 8 x i16> } @multi_vec_add_single_x2_s16(<vscale x 8 x i16> %unused, <vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zm) sanitize_memory {702; CHECK-LABEL: @multi_vec_add_single_x2_s16(703; CHECK-NEXT: call void @llvm.donothing()704; CHECK-NEXT: [[RES:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.add.single.x2.nxv8i16(<vscale x 8 x i16> [[ZDN1:%.*]], <vscale x 8 x i16> [[ZDN2:%.*]], <vscale x 8 x i16> [[ZM:%.*]])705; CHECK-NEXT: store { <vscale x 8 x i16>, <vscale x 8 x i16> } zeroinitializer, ptr @__msan_retval_tls, align 8706; CHECK-NEXT: ret { <vscale x 8 x i16>, <vscale x 8 x i16> } [[RES]]707;708 %res = call { <vscale x 8 x i16>, <vscale x 8 x i16> }709 @llvm.aarch64.sve.add.single.x2.nxv8i16(<vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2,710 <vscale x 8 x i16> %zm)711 ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %res712}713 714define { <vscale x 4 x i32>, <vscale x 4 x i32> } @multi_vec_add_single_x2_s32(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zm) sanitize_memory {715; CHECK-LABEL: @multi_vec_add_single_x2_s32(716; CHECK-NEXT: call void @llvm.donothing()717; CHECK-NEXT: [[RES:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.add.single.x2.nxv4i32(<vscale x 4 x i32> [[ZDN1:%.*]], <vscale x 4 x i32> [[ZDN2:%.*]], <vscale x 4 x i32> [[ZM:%.*]])718; CHECK-NEXT: store { <vscale x 4 x i32>, <vscale x 4 x i32> } zeroinitializer, ptr @__msan_retval_tls, align 8719; CHECK-NEXT: ret { <vscale x 4 x i32>, <vscale x 4 x i32> } [[RES]]720;721 %res = call { <vscale x 4 x i32>, <vscale x 4 x i32> }722 @llvm.aarch64.sve.add.single.x2.nxv4i32(<vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2,723 <vscale x 4 x i32> %zm)724 ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %res725}726 727define { <vscale x 2 x i64>, <vscale x 2 x i64> } @multi_vec_add_single_x2_s64(<vscale x 2 x i64> %unused, <vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zm) sanitize_memory {728; CHECK-LABEL: @multi_vec_add_single_x2_s64(729; CHECK-NEXT: call void @llvm.donothing()730; CHECK-NEXT: [[RES:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.add.single.x2.nxv2i64(<vscale x 2 x i64> [[ZDN1:%.*]], <vscale x 2 x i64> [[ZDN2:%.*]], <vscale x 2 x i64> [[ZM:%.*]])731; CHECK-NEXT: store { <vscale x 2 x i64>, <vscale x 2 x i64> } zeroinitializer, ptr @__msan_retval_tls, align 8732; CHECK-NEXT: ret { <vscale x 2 x i64>, <vscale x 2 x i64> } [[RES]]733;734 %res = call { <vscale x 2 x i64>, <vscale x 2 x i64> }735 @llvm.aarch64.sve.add.single.x2.nxv2i64(<vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2,736 <vscale x 2 x i64> %zm)737 ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %res738}739 740 741define { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @multi_vec_add_single_x4_s8(<vscale x 16 x i8> %unused, <vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zdn3, <vscale x 16 x i8> %zdn4, <vscale x 16 x i8>%zm) sanitize_memory {742; CHECK-LABEL: @multi_vec_add_single_x4_s8(743; CHECK-NEXT: call void @llvm.donothing()744; CHECK-NEXT: [[RES:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.add.single.x4.nxv16i8(<vscale x 16 x i8> [[ZDN1:%.*]], <vscale x 16 x i8> [[ZDN2:%.*]], <vscale x 16 x i8> [[ZDN3:%.*]], <vscale x 16 x i8> [[ZDN4:%.*]], <vscale x 16 x i8> [[ZM:%.*]])745; CHECK-NEXT: store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } zeroinitializer, ptr @__msan_retval_tls, align 8746; CHECK-NEXT: ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[RES]]747;748 %res = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }749 @llvm.aarch64.sve.add.single.x4.nxv16i8(<vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2,750 <vscale x 16 x i8> %zdn3, <vscale x 16 x i8> %zdn4,751 <vscale x 16 x i8> %zm)752 ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %res753}754 755define { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @multi_vec_add_x4_single_s16(<vscale x 8 x i16> %unused, <vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zdn3, <vscale x 8 x i16> %zdn4, <vscale x 8 x i16> %zm) sanitize_memory {756; CHECK-LABEL: @multi_vec_add_x4_single_s16(757; CHECK-NEXT: call void @llvm.donothing()758; CHECK-NEXT: [[RES:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.add.single.x4.nxv8i16(<vscale x 8 x i16> [[ZDN1:%.*]], <vscale x 8 x i16> [[ZDN2:%.*]], <vscale x 8 x i16> [[ZDN3:%.*]], <vscale x 8 x i16> [[ZDN4:%.*]], <vscale x 8 x i16> [[ZM:%.*]])759; CHECK-NEXT: store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } zeroinitializer, ptr @__msan_retval_tls, align 8760; CHECK-NEXT: ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[RES]]761;762 %res = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }763 @llvm.aarch64.sve.add.single.x4.nxv8i16(<vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2,764 <vscale x 8 x i16> %zdn3, <vscale x 8 x i16> %zdn4,765 <vscale x 8 x i16> %zm)766 ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %res767}768 769define { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @multi_vec_add_x4_single_s32(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zdn3, <vscale x 4 x i32> %zdn4, <vscale x 4 x i32> %zm) sanitize_memory {770; CHECK-LABEL: @multi_vec_add_x4_single_s32(771; CHECK-NEXT: call void @llvm.donothing()772; CHECK-NEXT: [[RES:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.add.single.x4.nxv4i32(<vscale x 4 x i32> [[ZDN1:%.*]], <vscale x 4 x i32> [[ZDN2:%.*]], <vscale x 4 x i32> [[ZDN3:%.*]], <vscale x 4 x i32> [[ZDN4:%.*]], <vscale x 4 x i32> [[ZM:%.*]])773; CHECK-NEXT: store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } zeroinitializer, ptr @__msan_retval_tls, align 8774; CHECK-NEXT: ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[RES]]775;776 %res = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }777 @llvm.aarch64.sve.add.single.x4.nxv4i32(<vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2,778 <vscale x 4 x i32> %zdn3, <vscale x 4 x i32> %zdn4,779 <vscale x 4 x i32> %zm)780 ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %res781}782 783define { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @multi_vec_add_x4_single_s64(<vscale x 2 x i64> %unused, <vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zdn3, <vscale x 2 x i64> %zdn4, <vscale x 2 x i64> %zm) sanitize_memory {784; CHECK-LABEL: @multi_vec_add_x4_single_s64(785; CHECK-NEXT: call void @llvm.donothing()786; CHECK-NEXT: [[RES:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.add.single.x4.nxv2i64(<vscale x 2 x i64> [[ZDN1:%.*]], <vscale x 2 x i64> [[ZDN2:%.*]], <vscale x 2 x i64> [[ZDN3:%.*]], <vscale x 2 x i64> [[ZDN4:%.*]], <vscale x 2 x i64> [[ZM:%.*]])787; CHECK-NEXT: store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } zeroinitializer, ptr @__msan_retval_tls, align 8788; CHECK-NEXT: ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[RES]]789;790 %res = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }791 @llvm.aarch64.sve.add.single.x4.nxv2i64(<vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2,792 <vscale x 2 x i64> %zdn3, <vscale x 2 x i64> %zdn4,793 <vscale x 2 x i64> %zm)794 ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %res795}796declare void@llvm.aarch64.sme.add.write.single.za.vg1x2.nxv4i32(i32, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)797declare void@llvm.aarch64.sme.add.write.single.za.vg1x2.nxv2i64(i32, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)798declare void@llvm.aarch64.sme.add.write.single.za.vg1x4.nxv4i32(i32, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)799declare void@llvm.aarch64.sme.add.write.single.za.vg1x4.nxv2i64(i32, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)800declare void@llvm.aarch64.sme.add.write.za.vg1x2.nxv4i32(i32, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)801declare void@llvm.aarch64.sme.add.write.za.vg1x2.nxv2i64(i32, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)802declare void@llvm.aarch64.sme.add.write.za.vg1x4.nxv4i32(i32, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)803declare void@llvm.aarch64.sme.add.write.za.vg1x4.nxv2i64(i32, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)804declare void@llvm.aarch64.sme.add.za32.vg1x2.nxv4i32(i32, <vscale x 4 x i32>,<vscale x 4 x i32>)805declare void@llvm.aarch64.sme.add.za64.vg1x2.nxv2i64(i32, <vscale x 2 x i64>,<vscale x 2 x i64>)806declare void@llvm.aarch64.sme.add.za32.vg1x4.nxv4i32(i32, <vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>)807declare void@llvm.aarch64.sme.add.za64.vg1x4.nxv2i64(i32, <vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, <vscale x 2 x i64>)808declare void@llvm.aarch64.sme.add.za32.vg1x2.nxv4f32(i32, <vscale x 4 x float>, <vscale x 4 x float>)809declare void@llvm.aarch64.sme.add.za64.vg1x2.nxv2f64(i32, <vscale x 2 x double>, <vscale x 2 x double>)810declare void@llvm.aarch64.sme.add.za32.vg1x4.nxv4f32(i32, <vscale x 4 x float>, <vscale x 4 x float>,<vscale x 4 x float>, <vscale x 4 x float>)811declare void@llvm.aarch64.sme.add.za64.vg1x4.nxv2f64(i32, <vscale x 2 x double>, <vscale x 2 x double>,<vscale x 2 x double>, <vscale x 2 x double>)812declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.add.single.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>)813declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.add.single.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>)814declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.add.single.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)815declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.add.single.x2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)816declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.add.single.x4.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>)817declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.add.single.x4.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>)818declare { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.add.single.x4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)819declare { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.add.single.x4.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)820