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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt %s -S -passes=msan 2>&1 | FileCheck %s3 4target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"5target triple = "x86_64-unknown-linux-gnu"6 7define <16 x i16> @test_x86_avx2_packssdw(<8 x i32> %a0, <8 x i32> %a1) #0 {8; CHECK-LABEL: @test_x86_avx2_packssdw(9; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 810; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 811; CHECK-NEXT: call void @llvm.donothing()12; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <8 x i32> [[TMP1]], zeroinitializer13; CHECK-NEXT: [[TMP4:%.*]] = sext <8 x i1> [[TMP3]] to <8 x i32>14; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <8 x i32> [[TMP2]], zeroinitializer15; CHECK-NEXT: [[TMP6:%.*]] = sext <8 x i1> [[TMP5]] to <8 x i32>16; CHECK-NEXT: [[_MSPROP_VECTOR_PACK:%.*]] = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> [[TMP4]], <8 x i32> [[TMP6]])17; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> [[A0:%.*]], <8 x i32> [[A1:%.*]])18; CHECK-NEXT: store <16 x i16> [[_MSPROP_VECTOR_PACK]], ptr @__msan_retval_tls, align 819; CHECK-NEXT: ret <16 x i16> [[RES]]20;21 %res = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> %a0, <8 x i32> %a1) ; <<16 x i16>> [#uses=1]22 ret <16 x i16> %res23}24declare <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32>, <8 x i32>) nounwind readnone25 26 27define <16 x i16> @test_x86_avx2_packssdw_fold() #0 {28; CHECK-LABEL: @test_x86_avx2_packssdw_fold(29; CHECK-NEXT: call void @llvm.donothing()30; CHECK-NEXT: [[_MSPROP_VECTOR_PACK:%.*]] = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> zeroinitializer, <8 x i32> zeroinitializer)31; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> zeroinitializer, <8 x i32> <i32 255, i32 32767, i32 65535, i32 -1, i32 -32767, i32 -65535, i32 0, i32 -256>)32; CHECK-NEXT: store <16 x i16> [[_MSPROP_VECTOR_PACK]], ptr @__msan_retval_tls, align 833; CHECK-NEXT: ret <16 x i16> [[RES]]34;35 %res = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> zeroinitializer, <8 x i32> <i32 255, i32 32767, i32 65535, i32 -1, i32 -32767, i32 -65535, i32 0, i32 -256>)36 ret <16 x i16> %res37}38 39 40define <32 x i8> @test_x86_avx2_packsswb(<16 x i16> %a0, <16 x i16> %a1) #0 {41; CHECK-LABEL: @test_x86_avx2_packsswb(42; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 843; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 844; CHECK-NEXT: call void @llvm.donothing()45; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <16 x i16> [[TMP1]], zeroinitializer46; CHECK-NEXT: [[TMP4:%.*]] = sext <16 x i1> [[TMP3]] to <16 x i16>47; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <16 x i16> [[TMP2]], zeroinitializer48; CHECK-NEXT: [[TMP6:%.*]] = sext <16 x i1> [[TMP5]] to <16 x i16>49; CHECK-NEXT: [[_MSPROP_VECTOR_PACK:%.*]] = call <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16> [[TMP4]], <16 x i16> [[TMP6]])50; CHECK-NEXT: [[RES:%.*]] = call <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16> [[A0:%.*]], <16 x i16> [[A1:%.*]])51; CHECK-NEXT: store <32 x i8> [[_MSPROP_VECTOR_PACK]], ptr @__msan_retval_tls, align 852; CHECK-NEXT: ret <32 x i8> [[RES]]53;54 %res = call <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16> %a0, <16 x i16> %a1) ; <<32 x i8>> [#uses=1]55 ret <32 x i8> %res56}57declare <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16>, <16 x i16>) nounwind readnone58 59 60define <32 x i8> @test_x86_avx2_packsswb_fold() #0 {61; CHECK-LABEL: @test_x86_avx2_packsswb_fold(62; CHECK-NEXT: call void @llvm.donothing()63; CHECK-NEXT: [[_MSPROP_VECTOR_PACK:%.*]] = call <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16> zeroinitializer, <16 x i16> zeroinitializer)64; CHECK-NEXT: [[RES:%.*]] = call <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16> <i16 0, i16 255, i16 256, i16 -1, i16 -1, i16 -255, i16 -256, i16 -32678, i16 0, i16 255, i16 256, i16 -1, i16 -1, i16 -255, i16 -256, i16 -32678>, <16 x i16> zeroinitializer)65; CHECK-NEXT: store <32 x i8> [[_MSPROP_VECTOR_PACK]], ptr @__msan_retval_tls, align 866; CHECK-NEXT: ret <32 x i8> [[RES]]67;68 %res = call <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16> <i16 0, i16 255, i16 256, i16 65535, i16 -1, i16 -255, i16 -256, i16 -32678, i16 0, i16 255, i16 256, i16 65535, i16 -1, i16 -255, i16 -256, i16 -32678>, <16 x i16> zeroinitializer)69 ret <32 x i8> %res70}71 72 73define <32 x i8> @test_x86_avx2_packuswb(<16 x i16> %a0, <16 x i16> %a1) #0 {74; CHECK-LABEL: @test_x86_avx2_packuswb(75; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 876; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 877; CHECK-NEXT: call void @llvm.donothing()78; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <16 x i16> [[TMP1]], zeroinitializer79; CHECK-NEXT: [[TMP4:%.*]] = sext <16 x i1> [[TMP3]] to <16 x i16>80; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <16 x i16> [[TMP2]], zeroinitializer81; CHECK-NEXT: [[TMP6:%.*]] = sext <16 x i1> [[TMP5]] to <16 x i16>82; CHECK-NEXT: [[_MSPROP_VECTOR_PACK:%.*]] = call <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16> [[TMP4]], <16 x i16> [[TMP6]])83; CHECK-NEXT: [[RES:%.*]] = call <32 x i8> @llvm.x86.avx2.packuswb(<16 x i16> [[A0:%.*]], <16 x i16> [[A1:%.*]])84; CHECK-NEXT: store <32 x i8> [[_MSPROP_VECTOR_PACK]], ptr @__msan_retval_tls, align 885; CHECK-NEXT: ret <32 x i8> [[RES]]86;87 %res = call <32 x i8> @llvm.x86.avx2.packuswb(<16 x i16> %a0, <16 x i16> %a1) ; <<32 x i8>> [#uses=1]88 ret <32 x i8> %res89}90declare <32 x i8> @llvm.x86.avx2.packuswb(<16 x i16>, <16 x i16>) nounwind readnone91 92 93define <32 x i8> @test_x86_avx2_packuswb_fold() #0 {94; CHECK-LABEL: @test_x86_avx2_packuswb_fold(95; CHECK-NEXT: call void @llvm.donothing()96; CHECK-NEXT: [[_MSPROP_VECTOR_PACK:%.*]] = call <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16> zeroinitializer, <16 x i16> zeroinitializer)97; CHECK-NEXT: [[RES:%.*]] = call <32 x i8> @llvm.x86.avx2.packuswb(<16 x i16> <i16 0, i16 255, i16 256, i16 -1, i16 -1, i16 -255, i16 -256, i16 -32678, i16 0, i16 255, i16 256, i16 -1, i16 -1, i16 -255, i16 -256, i16 -32678>, <16 x i16> zeroinitializer)98; CHECK-NEXT: store <32 x i8> [[_MSPROP_VECTOR_PACK]], ptr @__msan_retval_tls, align 899; CHECK-NEXT: ret <32 x i8> [[RES]]100;101 %res = call <32 x i8> @llvm.x86.avx2.packuswb(<16 x i16> <i16 0, i16 255, i16 256, i16 65535, i16 -1, i16 -255, i16 -256, i16 -32678, i16 0, i16 255, i16 256, i16 65535, i16 -1, i16 -255, i16 -256, i16 -32678>, <16 x i16> zeroinitializer)102 ret <32 x i8> %res103}104 105 106define <32 x i8> @test_x86_avx2_pavg_b(<32 x i8> %a0, <32 x i8> %a1) #0 {107; CHECK-LABEL: @test_x86_avx2_pavg_b(108; CHECK-NEXT: [[TMP1:%.*]] = load <32 x i8>, ptr @__msan_param_tls, align 8109; CHECK-NEXT: [[TMP2:%.*]] = load <32 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8110; CHECK-NEXT: call void @llvm.donothing()111; CHECK-NEXT: [[_MSPROP:%.*]] = or <32 x i8> [[TMP1]], [[TMP2]]112; CHECK-NEXT: [[RES:%.*]] = call <32 x i8> @llvm.x86.avx2.pavg.b(<32 x i8> [[A0:%.*]], <32 x i8> [[A1:%.*]])113; CHECK-NEXT: store <32 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 8114; CHECK-NEXT: ret <32 x i8> [[RES]]115;116 %res = call <32 x i8> @llvm.x86.avx2.pavg.b(<32 x i8> %a0, <32 x i8> %a1) ; <<32 x i8>> [#uses=1]117 ret <32 x i8> %res118}119declare <32 x i8> @llvm.x86.avx2.pavg.b(<32 x i8>, <32 x i8>) nounwind readnone120 121 122define <16 x i16> @test_x86_avx2_pavg_w(<16 x i16> %a0, <16 x i16> %a1) #0 {123; CHECK-LABEL: @test_x86_avx2_pavg_w(124; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8125; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8126; CHECK-NEXT: call void @llvm.donothing()127; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i16> [[TMP1]], [[TMP2]]128; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.pavg.w(<16 x i16> [[A0:%.*]], <16 x i16> [[A1:%.*]])129; CHECK-NEXT: store <16 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8130; CHECK-NEXT: ret <16 x i16> [[RES]]131;132 %res = call <16 x i16> @llvm.x86.avx2.pavg.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]133 ret <16 x i16> %res134}135declare <16 x i16> @llvm.x86.avx2.pavg.w(<16 x i16>, <16 x i16>) nounwind readnone136 137 138define <8 x i32> @test_x86_avx2_pmadd_wd(<16 x i16> %a0, <16 x i16> %a1) #0 {139; CHECK-LABEL: @test_x86_avx2_pmadd_wd(140; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8141; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8142; CHECK-NEXT: call void @llvm.donothing()143; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <16 x i16> [[TMP1]], zeroinitializer144; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <16 x i16> [[TMP2]], zeroinitializer145; CHECK-NEXT: [[TMP12:%.*]] = icmp ne <16 x i16> [[A0:%.*]], zeroinitializer146; CHECK-NEXT: [[TMP13:%.*]] = icmp ne <16 x i16> [[A1:%.*]], zeroinitializer147; CHECK-NEXT: [[TMP11:%.*]] = and <16 x i1> [[TMP4]], [[TMP5]]148; CHECK-NEXT: [[TMP14:%.*]] = and <16 x i1> [[TMP12]], [[TMP5]]149; CHECK-NEXT: [[TMP15:%.*]] = and <16 x i1> [[TMP4]], [[TMP13]]150; CHECK-NEXT: [[TMP16:%.*]] = or <16 x i1> [[TMP11]], [[TMP14]]151; CHECK-NEXT: [[TMP17:%.*]] = or <16 x i1> [[TMP16]], [[TMP15]]152; CHECK-NEXT: [[TMP7:%.*]] = sext <16 x i1> [[TMP17]] to <16 x i16>153; CHECK-NEXT: [[TMP18:%.*]] = bitcast <16 x i16> [[TMP7]] to <8 x i32>154; CHECK-NEXT: [[TMP19:%.*]] = icmp ne <8 x i32> [[TMP18]], zeroinitializer155; CHECK-NEXT: [[TMP6:%.*]] = sext <8 x i1> [[TMP19]] to <8 x i32>156; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16> [[A0]], <16 x i16> [[A1]])157; CHECK-NEXT: store <8 x i32> [[TMP6]], ptr @__msan_retval_tls, align 8158; CHECK-NEXT: ret <8 x i32> [[RES]]159;160 %res = call <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16> %a0, <16 x i16> %a1) ; <<8 x i32>> [#uses=1]161 ret <8 x i32> %res162}163declare <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16>, <16 x i16>) nounwind readnone164 165 166define i32 @test_x86_avx2_pmovmskb(<32 x i8> %a0) #0 {167; CHECK-LABEL: @test_x86_avx2_pmovmskb(168; CHECK-NEXT: [[TMP1:%.*]] = load <32 x i8>, ptr @__msan_param_tls, align 8169; CHECK-NEXT: call void @llvm.donothing()170; CHECK-NEXT: [[TMP2:%.*]] = bitcast <32 x i8> [[TMP1]] to i256171; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP2]], 0172; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1:![0-9]+]]173; CHECK: 3:174; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6:[0-9]+]]175; CHECK-NEXT: unreachable176; CHECK: 4:177; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx2.pmovmskb(<32 x i8> [[A0:%.*]])178; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8179; CHECK-NEXT: ret i32 [[RES]]180;181 %res = call i32 @llvm.x86.avx2.pmovmskb(<32 x i8> %a0) ; <i32> [#uses=1]182 ret i32 %res183}184declare i32 @llvm.x86.avx2.pmovmskb(<32 x i8>) nounwind readnone185 186 187define <16 x i16> @test_x86_avx2_pmulh_w(<16 x i16> %a0, <16 x i16> %a1) #0 {188; CHECK-LABEL: @test_x86_avx2_pmulh_w(189; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8190; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8191; CHECK-NEXT: call void @llvm.donothing()192; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i16> [[TMP1]], [[TMP2]]193; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.pmulh.w(<16 x i16> [[A0:%.*]], <16 x i16> [[A1:%.*]])194; CHECK-NEXT: store <16 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8195; CHECK-NEXT: ret <16 x i16> [[RES]]196;197 %res = call <16 x i16> @llvm.x86.avx2.pmulh.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]198 ret <16 x i16> %res199}200declare <16 x i16> @llvm.x86.avx2.pmulh.w(<16 x i16>, <16 x i16>) nounwind readnone201 202 203define <16 x i16> @test_x86_avx2_pmulhu_w(<16 x i16> %a0, <16 x i16> %a1) #0 {204; CHECK-LABEL: @test_x86_avx2_pmulhu_w(205; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8206; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8207; CHECK-NEXT: call void @llvm.donothing()208; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i16> [[TMP1]], [[TMP2]]209; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.pmulhu.w(<16 x i16> [[A0:%.*]], <16 x i16> [[A1:%.*]])210; CHECK-NEXT: store <16 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8211; CHECK-NEXT: ret <16 x i16> [[RES]]212;213 %res = call <16 x i16> @llvm.x86.avx2.pmulhu.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]214 ret <16 x i16> %res215}216declare <16 x i16> @llvm.x86.avx2.pmulhu.w(<16 x i16>, <16 x i16>) nounwind readnone217 218 219define <4 x i64> @test_x86_avx2_psad_bw(<32 x i8> %a0, <32 x i8> %a1) #0 {220; CHECK-LABEL: @test_x86_avx2_psad_bw(221; CHECK-NEXT: [[TMP1:%.*]] = load <32 x i8>, ptr @__msan_param_tls, align 8222; CHECK-NEXT: [[TMP2:%.*]] = load <32 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8223; CHECK-NEXT: call void @llvm.donothing()224; CHECK-NEXT: [[TMP3:%.*]] = or <32 x i8> [[TMP1]], [[TMP2]]225; CHECK-NEXT: [[TMP4:%.*]] = bitcast <32 x i8> [[TMP3]] to <4 x i64>226; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <4 x i64> [[TMP4]], zeroinitializer227; CHECK-NEXT: [[TMP6:%.*]] = sext <4 x i1> [[TMP5]] to <4 x i64>228; CHECK-NEXT: [[TMP7:%.*]] = lshr <4 x i64> [[TMP6]], splat (i64 48)229; CHECK-NEXT: [[RES:%.*]] = call <4 x i64> @llvm.x86.avx2.psad.bw(<32 x i8> [[A0:%.*]], <32 x i8> [[A1:%.*]])230; CHECK-NEXT: store <4 x i64> [[TMP7]], ptr @__msan_retval_tls, align 8231; CHECK-NEXT: ret <4 x i64> [[RES]]232;233 %res = call <4 x i64> @llvm.x86.avx2.psad.bw(<32 x i8> %a0, <32 x i8> %a1) ; <<4 x i64>> [#uses=1]234 ret <4 x i64> %res235}236declare <4 x i64> @llvm.x86.avx2.psad.bw(<32 x i8>, <32 x i8>) nounwind readnone237 238 239define <8 x i32> @test_x86_avx2_psll_d(<8 x i32> %a0, <4 x i32> %a1) #0 {240; CHECK-LABEL: @test_x86_avx2_psll_d(241; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8242; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8243; CHECK-NEXT: call void @llvm.donothing()244; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP2]] to i128245; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i64246; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 0247; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i256248; CHECK-NEXT: [[TMP7:%.*]] = bitcast i256 [[TMP6]] to <8 x i32>249; CHECK-NEXT: [[TMP8:%.*]] = call <8 x i32> @llvm.x86.avx2.psll.d(<8 x i32> [[TMP1]], <4 x i32> [[A1:%.*]])250; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i32> [[TMP8]], [[TMP7]]251; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx2.psll.d(<8 x i32> [[A0:%.*]], <4 x i32> [[A1]])252; CHECK-NEXT: store <8 x i32> [[TMP9]], ptr @__msan_retval_tls, align 8253; CHECK-NEXT: ret <8 x i32> [[RES]]254;255 %res = call <8 x i32> @llvm.x86.avx2.psll.d(<8 x i32> %a0, <4 x i32> %a1) ; <<8 x i32>> [#uses=1]256 ret <8 x i32> %res257}258declare <8 x i32> @llvm.x86.avx2.psll.d(<8 x i32>, <4 x i32>) nounwind readnone259 260 261define <4 x i64> @test_x86_avx2_psll_q(<4 x i64> %a0, <2 x i64> %a1) #0 {262; CHECK-LABEL: @test_x86_avx2_psll_q(263; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8264; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8265; CHECK-NEXT: call void @llvm.donothing()266; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP2]] to i128267; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i64268; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 0269; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i256270; CHECK-NEXT: [[TMP7:%.*]] = bitcast i256 [[TMP6]] to <4 x i64>271; CHECK-NEXT: [[TMP8:%.*]] = call <4 x i64> @llvm.x86.avx2.psll.q(<4 x i64> [[TMP1]], <2 x i64> [[A1:%.*]])272; CHECK-NEXT: [[TMP9:%.*]] = or <4 x i64> [[TMP8]], [[TMP7]]273; CHECK-NEXT: [[RES:%.*]] = call <4 x i64> @llvm.x86.avx2.psll.q(<4 x i64> [[A0:%.*]], <2 x i64> [[A1]])274; CHECK-NEXT: store <4 x i64> [[TMP9]], ptr @__msan_retval_tls, align 8275; CHECK-NEXT: ret <4 x i64> [[RES]]276;277 %res = call <4 x i64> @llvm.x86.avx2.psll.q(<4 x i64> %a0, <2 x i64> %a1) ; <<4 x i64>> [#uses=1]278 ret <4 x i64> %res279}280declare <4 x i64> @llvm.x86.avx2.psll.q(<4 x i64>, <2 x i64>) nounwind readnone281 282 283define <16 x i16> @test_x86_avx2_psll_w(<16 x i16> %a0, <8 x i16> %a1) #0 {284; CHECK-LABEL: @test_x86_avx2_psll_w(285; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8286; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8287; CHECK-NEXT: call void @llvm.donothing()288; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP2]] to i128289; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i64290; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 0291; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i256292; CHECK-NEXT: [[TMP7:%.*]] = bitcast i256 [[TMP6]] to <16 x i16>293; CHECK-NEXT: [[TMP8:%.*]] = call <16 x i16> @llvm.x86.avx2.psll.w(<16 x i16> [[TMP1]], <8 x i16> [[A1:%.*]])294; CHECK-NEXT: [[TMP9:%.*]] = or <16 x i16> [[TMP8]], [[TMP7]]295; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.psll.w(<16 x i16> [[A0:%.*]], <8 x i16> [[A1]])296; CHECK-NEXT: store <16 x i16> [[TMP9]], ptr @__msan_retval_tls, align 8297; CHECK-NEXT: ret <16 x i16> [[RES]]298;299 %res = call <16 x i16> @llvm.x86.avx2.psll.w(<16 x i16> %a0, <8 x i16> %a1) ; <<16 x i16>> [#uses=1]300 ret <16 x i16> %res301}302declare <16 x i16> @llvm.x86.avx2.psll.w(<16 x i16>, <8 x i16>) nounwind readnone303 304 305define <8 x i32> @test_x86_avx2_pslli_d(<8 x i32> %a0) #0 {306; CHECK-LABEL: @test_x86_avx2_pslli_d(307; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8308; CHECK-NEXT: call void @llvm.donothing()309; CHECK-NEXT: [[TMP2:%.*]] = call <8 x i32> @llvm.x86.avx2.pslli.d(<8 x i32> [[TMP1]], i32 7)310; CHECK-NEXT: [[TMP3:%.*]] = or <8 x i32> [[TMP2]], zeroinitializer311; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx2.pslli.d(<8 x i32> [[A0:%.*]], i32 7)312; CHECK-NEXT: store <8 x i32> [[TMP3]], ptr @__msan_retval_tls, align 8313; CHECK-NEXT: ret <8 x i32> [[RES]]314;315 %res = call <8 x i32> @llvm.x86.avx2.pslli.d(<8 x i32> %a0, i32 7) ; <<8 x i32>> [#uses=1]316 ret <8 x i32> %res317}318declare <8 x i32> @llvm.x86.avx2.pslli.d(<8 x i32>, i32) nounwind readnone319 320 321define <4 x i64> @test_x86_avx2_pslli_q(<4 x i64> %a0) #0 {322; CHECK-LABEL: @test_x86_avx2_pslli_q(323; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8324; CHECK-NEXT: call void @llvm.donothing()325; CHECK-NEXT: [[TMP2:%.*]] = call <4 x i64> @llvm.x86.avx2.pslli.q(<4 x i64> [[TMP1]], i32 7)326; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i64> [[TMP2]], zeroinitializer327; CHECK-NEXT: [[RES:%.*]] = call <4 x i64> @llvm.x86.avx2.pslli.q(<4 x i64> [[A0:%.*]], i32 7)328; CHECK-NEXT: store <4 x i64> [[TMP3]], ptr @__msan_retval_tls, align 8329; CHECK-NEXT: ret <4 x i64> [[RES]]330;331 %res = call <4 x i64> @llvm.x86.avx2.pslli.q(<4 x i64> %a0, i32 7) ; <<4 x i64>> [#uses=1]332 ret <4 x i64> %res333}334declare <4 x i64> @llvm.x86.avx2.pslli.q(<4 x i64>, i32) nounwind readnone335 336 337define <16 x i16> @test_x86_avx2_pslli_w(<16 x i16> %a0) #0 {338; CHECK-LABEL: @test_x86_avx2_pslli_w(339; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8340; CHECK-NEXT: call void @llvm.donothing()341; CHECK-NEXT: [[TMP2:%.*]] = call <16 x i16> @llvm.x86.avx2.pslli.w(<16 x i16> [[TMP1]], i32 7)342; CHECK-NEXT: [[TMP3:%.*]] = or <16 x i16> [[TMP2]], zeroinitializer343; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.pslli.w(<16 x i16> [[A0:%.*]], i32 7)344; CHECK-NEXT: store <16 x i16> [[TMP3]], ptr @__msan_retval_tls, align 8345; CHECK-NEXT: ret <16 x i16> [[RES]]346;347 %res = call <16 x i16> @llvm.x86.avx2.pslli.w(<16 x i16> %a0, i32 7) ; <<16 x i16>> [#uses=1]348 ret <16 x i16> %res349}350declare <16 x i16> @llvm.x86.avx2.pslli.w(<16 x i16>, i32) nounwind readnone351 352 353define <8 x i32> @test_x86_avx2_psra_d(<8 x i32> %a0, <4 x i32> %a1) #0 {354; CHECK-LABEL: @test_x86_avx2_psra_d(355; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8356; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8357; CHECK-NEXT: call void @llvm.donothing()358; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP2]] to i128359; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i64360; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 0361; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i256362; CHECK-NEXT: [[TMP7:%.*]] = bitcast i256 [[TMP6]] to <8 x i32>363; CHECK-NEXT: [[TMP8:%.*]] = call <8 x i32> @llvm.x86.avx2.psra.d(<8 x i32> [[TMP1]], <4 x i32> [[A1:%.*]])364; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i32> [[TMP8]], [[TMP7]]365; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx2.psra.d(<8 x i32> [[A0:%.*]], <4 x i32> [[A1]])366; CHECK-NEXT: store <8 x i32> [[TMP9]], ptr @__msan_retval_tls, align 8367; CHECK-NEXT: ret <8 x i32> [[RES]]368;369 %res = call <8 x i32> @llvm.x86.avx2.psra.d(<8 x i32> %a0, <4 x i32> %a1) ; <<8 x i32>> [#uses=1]370 ret <8 x i32> %res371}372declare <8 x i32> @llvm.x86.avx2.psra.d(<8 x i32>, <4 x i32>) nounwind readnone373 374 375define <16 x i16> @test_x86_avx2_psra_w(<16 x i16> %a0, <8 x i16> %a1) #0 {376; CHECK-LABEL: @test_x86_avx2_psra_w(377; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8378; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8379; CHECK-NEXT: call void @llvm.donothing()380; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP2]] to i128381; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i64382; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 0383; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i256384; CHECK-NEXT: [[TMP7:%.*]] = bitcast i256 [[TMP6]] to <16 x i16>385; CHECK-NEXT: [[TMP8:%.*]] = call <16 x i16> @llvm.x86.avx2.psra.w(<16 x i16> [[TMP1]], <8 x i16> [[A1:%.*]])386; CHECK-NEXT: [[TMP9:%.*]] = or <16 x i16> [[TMP8]], [[TMP7]]387; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.psra.w(<16 x i16> [[A0:%.*]], <8 x i16> [[A1]])388; CHECK-NEXT: store <16 x i16> [[TMP9]], ptr @__msan_retval_tls, align 8389; CHECK-NEXT: ret <16 x i16> [[RES]]390;391 %res = call <16 x i16> @llvm.x86.avx2.psra.w(<16 x i16> %a0, <8 x i16> %a1) ; <<16 x i16>> [#uses=1]392 ret <16 x i16> %res393}394declare <16 x i16> @llvm.x86.avx2.psra.w(<16 x i16>, <8 x i16>) nounwind readnone395 396 397define <8 x i32> @test_x86_avx2_psrai_d(<8 x i32> %a0) #0 {398; CHECK-LABEL: @test_x86_avx2_psrai_d(399; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8400; CHECK-NEXT: call void @llvm.donothing()401; CHECK-NEXT: [[TMP2:%.*]] = call <8 x i32> @llvm.x86.avx2.psrai.d(<8 x i32> [[TMP1]], i32 7)402; CHECK-NEXT: [[TMP3:%.*]] = or <8 x i32> [[TMP2]], zeroinitializer403; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx2.psrai.d(<8 x i32> [[A0:%.*]], i32 7)404; CHECK-NEXT: store <8 x i32> [[TMP3]], ptr @__msan_retval_tls, align 8405; CHECK-NEXT: ret <8 x i32> [[RES]]406;407 %res = call <8 x i32> @llvm.x86.avx2.psrai.d(<8 x i32> %a0, i32 7) ; <<8 x i32>> [#uses=1]408 ret <8 x i32> %res409}410declare <8 x i32> @llvm.x86.avx2.psrai.d(<8 x i32>, i32) nounwind readnone411 412 413define <16 x i16> @test_x86_avx2_psrai_w(<16 x i16> %a0) #0 {414; CHECK-LABEL: @test_x86_avx2_psrai_w(415; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8416; CHECK-NEXT: call void @llvm.donothing()417; CHECK-NEXT: [[TMP2:%.*]] = call <16 x i16> @llvm.x86.avx2.psrai.w(<16 x i16> [[TMP1]], i32 7)418; CHECK-NEXT: [[TMP3:%.*]] = or <16 x i16> [[TMP2]], zeroinitializer419; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.psrai.w(<16 x i16> [[A0:%.*]], i32 7)420; CHECK-NEXT: store <16 x i16> [[TMP3]], ptr @__msan_retval_tls, align 8421; CHECK-NEXT: ret <16 x i16> [[RES]]422;423 %res = call <16 x i16> @llvm.x86.avx2.psrai.w(<16 x i16> %a0, i32 7) ; <<16 x i16>> [#uses=1]424 ret <16 x i16> %res425}426declare <16 x i16> @llvm.x86.avx2.psrai.w(<16 x i16>, i32) nounwind readnone427 428 429define <8 x i32> @test_x86_avx2_psrl_d(<8 x i32> %a0, <4 x i32> %a1) #0 {430; CHECK-LABEL: @test_x86_avx2_psrl_d(431; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8432; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8433; CHECK-NEXT: call void @llvm.donothing()434; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP2]] to i128435; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i64436; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 0437; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i256438; CHECK-NEXT: [[TMP7:%.*]] = bitcast i256 [[TMP6]] to <8 x i32>439; CHECK-NEXT: [[TMP8:%.*]] = call <8 x i32> @llvm.x86.avx2.psrl.d(<8 x i32> [[TMP1]], <4 x i32> [[A1:%.*]])440; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i32> [[TMP8]], [[TMP7]]441; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx2.psrl.d(<8 x i32> [[A0:%.*]], <4 x i32> [[A1]])442; CHECK-NEXT: store <8 x i32> [[TMP9]], ptr @__msan_retval_tls, align 8443; CHECK-NEXT: ret <8 x i32> [[RES]]444;445 %res = call <8 x i32> @llvm.x86.avx2.psrl.d(<8 x i32> %a0, <4 x i32> %a1) ; <<8 x i32>> [#uses=1]446 ret <8 x i32> %res447}448declare <8 x i32> @llvm.x86.avx2.psrl.d(<8 x i32>, <4 x i32>) nounwind readnone449 450 451define <4 x i64> @test_x86_avx2_psrl_q(<4 x i64> %a0, <2 x i64> %a1) #0 {452; CHECK-LABEL: @test_x86_avx2_psrl_q(453; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8454; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8455; CHECK-NEXT: call void @llvm.donothing()456; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP2]] to i128457; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i64458; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 0459; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i256460; CHECK-NEXT: [[TMP7:%.*]] = bitcast i256 [[TMP6]] to <4 x i64>461; CHECK-NEXT: [[TMP8:%.*]] = call <4 x i64> @llvm.x86.avx2.psrl.q(<4 x i64> [[TMP1]], <2 x i64> [[A1:%.*]])462; CHECK-NEXT: [[TMP9:%.*]] = or <4 x i64> [[TMP8]], [[TMP7]]463; CHECK-NEXT: [[RES:%.*]] = call <4 x i64> @llvm.x86.avx2.psrl.q(<4 x i64> [[A0:%.*]], <2 x i64> [[A1]])464; CHECK-NEXT: store <4 x i64> [[TMP9]], ptr @__msan_retval_tls, align 8465; CHECK-NEXT: ret <4 x i64> [[RES]]466;467 %res = call <4 x i64> @llvm.x86.avx2.psrl.q(<4 x i64> %a0, <2 x i64> %a1) ; <<4 x i64>> [#uses=1]468 ret <4 x i64> %res469}470declare <4 x i64> @llvm.x86.avx2.psrl.q(<4 x i64>, <2 x i64>) nounwind readnone471 472 473define <16 x i16> @test_x86_avx2_psrl_w(<16 x i16> %a0, <8 x i16> %a1) #0 {474; CHECK-LABEL: @test_x86_avx2_psrl_w(475; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8476; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8477; CHECK-NEXT: call void @llvm.donothing()478; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP2]] to i128479; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i64480; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 0481; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i256482; CHECK-NEXT: [[TMP7:%.*]] = bitcast i256 [[TMP6]] to <16 x i16>483; CHECK-NEXT: [[TMP8:%.*]] = call <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16> [[TMP1]], <8 x i16> [[A1:%.*]])484; CHECK-NEXT: [[TMP9:%.*]] = or <16 x i16> [[TMP8]], [[TMP7]]485; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16> [[A0:%.*]], <8 x i16> [[A1]])486; CHECK-NEXT: store <16 x i16> [[TMP9]], ptr @__msan_retval_tls, align 8487; CHECK-NEXT: ret <16 x i16> [[RES]]488;489 %res = call <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16> %a0, <8 x i16> %a1) ; <<16 x i16>> [#uses=1]490 ret <16 x i16> %res491}492declare <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16>, <8 x i16>) nounwind readnone493 494 495define <16 x i16> @test_x86_avx2_psrl_w_load(<16 x i16> %a0, ptr %p) #0 {496; CHECK-LABEL: @test_x86_avx2_psrl_w_load(497; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8498; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8499; CHECK-NEXT: call void @llvm.donothing()500; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0501; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]502; CHECK: 3:503; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]504; CHECK-NEXT: unreachable505; CHECK: 4:506; CHECK-NEXT: [[A1:%.*]] = load <8 x i16>, ptr [[P:%.*]], align 16507; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[P]] to i64508; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 87960930222080509; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr510; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP7]], align 16511; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i16> [[_MSLD]] to i128512; CHECK-NEXT: [[TMP9:%.*]] = trunc i128 [[TMP8]] to i64513; CHECK-NEXT: [[TMP10:%.*]] = icmp ne i64 [[TMP9]], 0514; CHECK-NEXT: [[TMP11:%.*]] = sext i1 [[TMP10]] to i256515; CHECK-NEXT: [[TMP12:%.*]] = bitcast i256 [[TMP11]] to <16 x i16>516; CHECK-NEXT: [[TMP13:%.*]] = call <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16> [[TMP2]], <8 x i16> [[A1]])517; CHECK-NEXT: [[TMP14:%.*]] = or <16 x i16> [[TMP13]], [[TMP12]]518; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16> [[A0:%.*]], <8 x i16> [[A1]])519; CHECK-NEXT: store <16 x i16> [[TMP14]], ptr @__msan_retval_tls, align 8520; CHECK-NEXT: ret <16 x i16> [[RES]]521;522 %a1 = load <8 x i16>, ptr %p523 %res = call <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16> %a0, <8 x i16> %a1) ; <<16 x i16>> [#uses=1]524 ret <16 x i16> %res525}526 527 528define <8 x i32> @test_x86_avx2_psrli_d(<8 x i32> %a0) #0 {529; CHECK-LABEL: @test_x86_avx2_psrli_d(530; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8531; CHECK-NEXT: call void @llvm.donothing()532; CHECK-NEXT: [[TMP2:%.*]] = call <8 x i32> @llvm.x86.avx2.psrli.d(<8 x i32> [[TMP1]], i32 7)533; CHECK-NEXT: [[TMP3:%.*]] = or <8 x i32> [[TMP2]], zeroinitializer534; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx2.psrli.d(<8 x i32> [[A0:%.*]], i32 7)535; CHECK-NEXT: store <8 x i32> [[TMP3]], ptr @__msan_retval_tls, align 8536; CHECK-NEXT: ret <8 x i32> [[RES]]537;538 %res = call <8 x i32> @llvm.x86.avx2.psrli.d(<8 x i32> %a0, i32 7) ; <<8 x i32>> [#uses=1]539 ret <8 x i32> %res540}541declare <8 x i32> @llvm.x86.avx2.psrli.d(<8 x i32>, i32) nounwind readnone542 543 544define <4 x i64> @test_x86_avx2_psrli_q(<4 x i64> %a0) #0 {545; CHECK-LABEL: @test_x86_avx2_psrli_q(546; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8547; CHECK-NEXT: call void @llvm.donothing()548; CHECK-NEXT: [[TMP2:%.*]] = call <4 x i64> @llvm.x86.avx2.psrli.q(<4 x i64> [[TMP1]], i32 7)549; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i64> [[TMP2]], zeroinitializer550; CHECK-NEXT: [[RES:%.*]] = call <4 x i64> @llvm.x86.avx2.psrli.q(<4 x i64> [[A0:%.*]], i32 7)551; CHECK-NEXT: store <4 x i64> [[TMP3]], ptr @__msan_retval_tls, align 8552; CHECK-NEXT: ret <4 x i64> [[RES]]553;554 %res = call <4 x i64> @llvm.x86.avx2.psrli.q(<4 x i64> %a0, i32 7) ; <<4 x i64>> [#uses=1]555 ret <4 x i64> %res556}557declare <4 x i64> @llvm.x86.avx2.psrli.q(<4 x i64>, i32) nounwind readnone558 559 560define <16 x i16> @test_x86_avx2_psrli_w(<16 x i16> %a0) #0 {561; CHECK-LABEL: @test_x86_avx2_psrli_w(562; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8563; CHECK-NEXT: call void @llvm.donothing()564; CHECK-NEXT: [[TMP2:%.*]] = call <16 x i16> @llvm.x86.avx2.psrli.w(<16 x i16> [[TMP1]], i32 7)565; CHECK-NEXT: [[TMP3:%.*]] = or <16 x i16> [[TMP2]], zeroinitializer566; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.psrli.w(<16 x i16> [[A0:%.*]], i32 7)567; CHECK-NEXT: store <16 x i16> [[TMP3]], ptr @__msan_retval_tls, align 8568; CHECK-NEXT: ret <16 x i16> [[RES]]569;570 %res = call <16 x i16> @llvm.x86.avx2.psrli.w(<16 x i16> %a0, i32 7) ; <<16 x i16>> [#uses=1]571 ret <16 x i16> %res572}573declare <16 x i16> @llvm.x86.avx2.psrli.w(<16 x i16>, i32) nounwind readnone574 575 576define <8 x i32> @test_x86_avx2_phadd_d(<8 x i32> %a0, <8 x i32> %a1) #0 {577; CHECK-LABEL: @test_x86_avx2_phadd_d(578; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8579; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8580; CHECK-NEXT: call void @llvm.donothing()581; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> [[TMP2]], <8 x i32> <i32 0, i32 2, i32 8, i32 10, i32 4, i32 6, i32 12, i32 14>582; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> [[TMP2]], <8 x i32> <i32 1, i32 3, i32 9, i32 11, i32 5, i32 7, i32 13, i32 15>583; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> [[TMP9]], [[TMP10]]584; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx2.phadd.d(<8 x i32> [[A0:%.*]], <8 x i32> [[A1:%.*]])585; CHECK-NEXT: store <8 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8586; CHECK-NEXT: ret <8 x i32> [[RES]]587;588 %res = call <8 x i32> @llvm.x86.avx2.phadd.d(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1]589 ret <8 x i32> %res590}591declare <8 x i32> @llvm.x86.avx2.phadd.d(<8 x i32>, <8 x i32>) nounwind readnone592 593 594define <16 x i16> @test_x86_avx2_phadd_sw(<16 x i16> %a0, <16 x i16> %a1) #0 {595; CHECK-LABEL: @test_x86_avx2_phadd_sw(596; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8597; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8598; CHECK-NEXT: call void @llvm.donothing()599; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <16 x i16> [[TMP1]], <16 x i16> [[TMP2]], <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 16, i32 18, i32 20, i32 22, i32 8, i32 10, i32 12, i32 14, i32 24, i32 26, i32 28, i32 30>600; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <16 x i16> [[TMP1]], <16 x i16> [[TMP2]], <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 17, i32 19, i32 21, i32 23, i32 9, i32 11, i32 13, i32 15, i32 25, i32 27, i32 29, i32 31>601; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i16> [[TMP9]], [[TMP10]]602; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.phadd.sw(<16 x i16> [[A0:%.*]], <16 x i16> [[A1:%.*]])603; CHECK-NEXT: store <16 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8604; CHECK-NEXT: ret <16 x i16> [[RES]]605;606 %res = call <16 x i16> @llvm.x86.avx2.phadd.sw(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]607 ret <16 x i16> %res608}609declare <16 x i16> @llvm.x86.avx2.phadd.sw(<16 x i16>, <16 x i16>) nounwind readnone610 611 612define <16 x i16> @test_x86_avx2_phadd_w(<16 x i16> %a0, <16 x i16> %a1) #0 {613; CHECK-LABEL: @test_x86_avx2_phadd_w(614; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8615; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8616; CHECK-NEXT: call void @llvm.donothing()617; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <16 x i16> [[TMP1]], <16 x i16> [[TMP2]], <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 16, i32 18, i32 20, i32 22, i32 8, i32 10, i32 12, i32 14, i32 24, i32 26, i32 28, i32 30>618; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <16 x i16> [[TMP1]], <16 x i16> [[TMP2]], <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 17, i32 19, i32 21, i32 23, i32 9, i32 11, i32 13, i32 15, i32 25, i32 27, i32 29, i32 31>619; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i16> [[TMP9]], [[TMP10]]620; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.phadd.w(<16 x i16> [[A0:%.*]], <16 x i16> [[A1:%.*]])621; CHECK-NEXT: store <16 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8622; CHECK-NEXT: ret <16 x i16> [[RES]]623;624 %res = call <16 x i16> @llvm.x86.avx2.phadd.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]625 ret <16 x i16> %res626}627declare <16 x i16> @llvm.x86.avx2.phadd.w(<16 x i16>, <16 x i16>) nounwind readnone628 629 630define <8 x i32> @test_x86_avx2_phsub_d(<8 x i32> %a0, <8 x i32> %a1) #0 {631; CHECK-LABEL: @test_x86_avx2_phsub_d(632; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8633; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8634; CHECK-NEXT: call void @llvm.donothing()635; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> [[TMP2]], <8 x i32> <i32 0, i32 2, i32 8, i32 10, i32 4, i32 6, i32 12, i32 14>636; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> [[TMP2]], <8 x i32> <i32 1, i32 3, i32 9, i32 11, i32 5, i32 7, i32 13, i32 15>637; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> [[TMP9]], [[TMP10]]638; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx2.phsub.d(<8 x i32> [[A0:%.*]], <8 x i32> [[A1:%.*]])639; CHECK-NEXT: store <8 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8640; CHECK-NEXT: ret <8 x i32> [[RES]]641;642 %res = call <8 x i32> @llvm.x86.avx2.phsub.d(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1]643 ret <8 x i32> %res644}645declare <8 x i32> @llvm.x86.avx2.phsub.d(<8 x i32>, <8 x i32>) nounwind readnone646 647 648define <16 x i16> @test_x86_avx2_phsub_sw(<16 x i16> %a0, <16 x i16> %a1) #0 {649; CHECK-LABEL: @test_x86_avx2_phsub_sw(650; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8651; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8652; CHECK-NEXT: call void @llvm.donothing()653; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <16 x i16> [[TMP1]], <16 x i16> [[TMP2]], <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 16, i32 18, i32 20, i32 22, i32 8, i32 10, i32 12, i32 14, i32 24, i32 26, i32 28, i32 30>654; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <16 x i16> [[TMP1]], <16 x i16> [[TMP2]], <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 17, i32 19, i32 21, i32 23, i32 9, i32 11, i32 13, i32 15, i32 25, i32 27, i32 29, i32 31>655; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i16> [[TMP9]], [[TMP10]]656; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.phsub.sw(<16 x i16> [[A0:%.*]], <16 x i16> [[A1:%.*]])657; CHECK-NEXT: store <16 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8658; CHECK-NEXT: ret <16 x i16> [[RES]]659;660 %res = call <16 x i16> @llvm.x86.avx2.phsub.sw(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]661 ret <16 x i16> %res662}663declare <16 x i16> @llvm.x86.avx2.phsub.sw(<16 x i16>, <16 x i16>) nounwind readnone664 665 666define <16 x i16> @test_x86_avx2_phsub_w(<16 x i16> %a0, <16 x i16> %a1) #0 {667; CHECK-LABEL: @test_x86_avx2_phsub_w(668; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8669; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8670; CHECK-NEXT: call void @llvm.donothing()671; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <16 x i16> [[TMP1]], <16 x i16> [[TMP2]], <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 16, i32 18, i32 20, i32 22, i32 8, i32 10, i32 12, i32 14, i32 24, i32 26, i32 28, i32 30>672; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <16 x i16> [[TMP1]], <16 x i16> [[TMP2]], <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 17, i32 19, i32 21, i32 23, i32 9, i32 11, i32 13, i32 15, i32 25, i32 27, i32 29, i32 31>673; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i16> [[TMP9]], [[TMP10]]674; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.phsub.w(<16 x i16> [[A0:%.*]], <16 x i16> [[A1:%.*]])675; CHECK-NEXT: store <16 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8676; CHECK-NEXT: ret <16 x i16> [[RES]]677;678 %res = call <16 x i16> @llvm.x86.avx2.phsub.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]679 ret <16 x i16> %res680}681declare <16 x i16> @llvm.x86.avx2.phsub.w(<16 x i16>, <16 x i16>) nounwind readnone682 683 684define <16 x i16> @test_x86_avx2_pmadd_ub_sw(<32 x i8> %a0, <32 x i8> %a1) #0 {685; CHECK-LABEL: @test_x86_avx2_pmadd_ub_sw(686; CHECK-NEXT: [[TMP1:%.*]] = load <32 x i8>, ptr @__msan_param_tls, align 8687; CHECK-NEXT: [[TMP2:%.*]] = load <32 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8688; CHECK-NEXT: call void @llvm.donothing()689; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <32 x i8> [[TMP1]], zeroinitializer690; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <32 x i8> [[TMP2]], zeroinitializer691; CHECK-NEXT: [[TMP12:%.*]] = icmp ne <32 x i8> [[A0:%.*]], zeroinitializer692; CHECK-NEXT: [[TMP13:%.*]] = icmp ne <32 x i8> [[A1:%.*]], zeroinitializer693; CHECK-NEXT: [[TMP11:%.*]] = and <32 x i1> [[TMP4]], [[TMP5]]694; CHECK-NEXT: [[TMP14:%.*]] = and <32 x i1> [[TMP12]], [[TMP5]]695; CHECK-NEXT: [[TMP15:%.*]] = and <32 x i1> [[TMP4]], [[TMP13]]696; CHECK-NEXT: [[TMP16:%.*]] = or <32 x i1> [[TMP11]], [[TMP14]]697; CHECK-NEXT: [[TMP17:%.*]] = or <32 x i1> [[TMP16]], [[TMP15]]698; CHECK-NEXT: [[TMP7:%.*]] = sext <32 x i1> [[TMP17]] to <32 x i8>699; CHECK-NEXT: [[TMP18:%.*]] = bitcast <32 x i8> [[TMP7]] to <16 x i16>700; CHECK-NEXT: [[TMP19:%.*]] = icmp ne <16 x i16> [[TMP18]], zeroinitializer701; CHECK-NEXT: [[TMP6:%.*]] = sext <16 x i1> [[TMP19]] to <16 x i16>702; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.pmadd.ub.sw(<32 x i8> [[A0]], <32 x i8> [[A1]])703; CHECK-NEXT: store <16 x i16> [[TMP6]], ptr @__msan_retval_tls, align 8704; CHECK-NEXT: ret <16 x i16> [[RES]]705;706 %res = call <16 x i16> @llvm.x86.avx2.pmadd.ub.sw(<32 x i8> %a0, <32 x i8> %a1) ; <<16 x i16>> [#uses=1]707 ret <16 x i16> %res708}709declare <16 x i16> @llvm.x86.avx2.pmadd.ub.sw(<32 x i8>, <32 x i8>) nounwind readnone710 711define <16 x i16> @test_x86_avx2_pmadd_ub_sw_load_op0(ptr %ptr, <32 x i8> %a1) #0 {712; CHECK-LABEL: @test_x86_avx2_pmadd_ub_sw_load_op0(713; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8714; CHECK-NEXT: [[TMP2:%.*]] = load <32 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8715; CHECK-NEXT: call void @llvm.donothing()716; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0717; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]718; CHECK: 3:719; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]720; CHECK-NEXT: unreachable721; CHECK: 4:722; CHECK-NEXT: [[A0:%.*]] = load <32 x i8>, ptr [[PTR:%.*]], align 32723; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[PTR]] to i64724; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 87960930222080725; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr726; CHECK-NEXT: [[_MSLD:%.*]] = load <32 x i8>, ptr [[TMP7]], align 32727; CHECK-NEXT: [[TMP9:%.*]] = icmp ne <32 x i8> [[_MSLD]], zeroinitializer728; CHECK-NEXT: [[TMP10:%.*]] = icmp ne <32 x i8> [[TMP2]], zeroinitializer729; CHECK-NEXT: [[TMP17:%.*]] = icmp ne <32 x i8> [[A0]], zeroinitializer730; CHECK-NEXT: [[TMP18:%.*]] = icmp ne <32 x i8> [[A1:%.*]], zeroinitializer731; CHECK-NEXT: [[TMP16:%.*]] = and <32 x i1> [[TMP9]], [[TMP10]]732; CHECK-NEXT: [[TMP19:%.*]] = and <32 x i1> [[TMP17]], [[TMP10]]733; CHECK-NEXT: [[TMP20:%.*]] = and <32 x i1> [[TMP9]], [[TMP18]]734; CHECK-NEXT: [[TMP21:%.*]] = or <32 x i1> [[TMP16]], [[TMP19]]735; CHECK-NEXT: [[TMP22:%.*]] = or <32 x i1> [[TMP21]], [[TMP20]]736; CHECK-NEXT: [[TMP12:%.*]] = sext <32 x i1> [[TMP22]] to <32 x i8>737; CHECK-NEXT: [[TMP23:%.*]] = bitcast <32 x i8> [[TMP12]] to <16 x i16>738; CHECK-NEXT: [[TMP24:%.*]] = icmp ne <16 x i16> [[TMP23]], zeroinitializer739; CHECK-NEXT: [[TMP11:%.*]] = sext <16 x i1> [[TMP24]] to <16 x i16>740; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.pmadd.ub.sw(<32 x i8> [[A0]], <32 x i8> [[A1]])741; CHECK-NEXT: store <16 x i16> [[TMP11]], ptr @__msan_retval_tls, align 8742; CHECK-NEXT: ret <16 x i16> [[RES]]743;744 %a0 = load <32 x i8>, ptr %ptr745 %res = call <16 x i16> @llvm.x86.avx2.pmadd.ub.sw(<32 x i8> %a0, <32 x i8> %a1) ; <<16 x i16>> [#uses=1]746 ret <16 x i16> %res747}748 749define <16 x i16> @test_x86_avx2_pmul_hr_sw(<16 x i16> %a0, <16 x i16> %a1) #0 {750; CHECK-LABEL: @test_x86_avx2_pmul_hr_sw(751; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8752; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8753; CHECK-NEXT: call void @llvm.donothing()754; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i16> [[TMP1]], [[TMP2]]755; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.pmul.hr.sw(<16 x i16> [[A0:%.*]], <16 x i16> [[A1:%.*]])756; CHECK-NEXT: store <16 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8757; CHECK-NEXT: ret <16 x i16> [[RES]]758;759 %res = call <16 x i16> @llvm.x86.avx2.pmul.hr.sw(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]760 ret <16 x i16> %res761}762declare <16 x i16> @llvm.x86.avx2.pmul.hr.sw(<16 x i16>, <16 x i16>) nounwind readnone763 764 765define <32 x i8> @test_x86_avx2_pshuf_b(<32 x i8> %a0, <32 x i8> %a1) #0 {766; CHECK-LABEL: @test_x86_avx2_pshuf_b(767; CHECK-NEXT: [[TMP1:%.*]] = load <32 x i8>, ptr @__msan_param_tls, align 8768; CHECK-NEXT: [[TMP2:%.*]] = load <32 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8769; CHECK-NEXT: call void @llvm.donothing()770; CHECK-NEXT: [[TMP3:%.*]] = call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> [[TMP1]], <32 x i8> [[A1:%.*]])771; CHECK-NEXT: [[_MSPROP:%.*]] = or <32 x i8> [[TMP2]], [[TMP3]]772; CHECK-NEXT: [[RES:%.*]] = call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> [[A0:%.*]], <32 x i8> [[A1]])773; CHECK-NEXT: store <32 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 8774; CHECK-NEXT: ret <32 x i8> [[RES]]775;776 %res = call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %a0, <32 x i8> %a1) ; <<16 x i8>> [#uses=1]777 ret <32 x i8> %res778}779declare <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8>, <32 x i8>) nounwind readnone780 781 782define <32 x i8> @test_x86_avx2_psign_b(<32 x i8> %a0, <32 x i8> %a1) #0 {783; CHECK-LABEL: @test_x86_avx2_psign_b(784; CHECK-NEXT: [[TMP1:%.*]] = load <32 x i8>, ptr @__msan_param_tls, align 8785; CHECK-NEXT: [[TMP2:%.*]] = load <32 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8786; CHECK-NEXT: call void @llvm.donothing()787; CHECK-NEXT: [[_MSPROP:%.*]] = or <32 x i8> [[TMP1]], [[TMP2]]788; CHECK-NEXT: [[RES:%.*]] = call <32 x i8> @llvm.x86.avx2.psign.b(<32 x i8> [[A0:%.*]], <32 x i8> [[A1:%.*]])789; CHECK-NEXT: store <32 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 8790; CHECK-NEXT: ret <32 x i8> [[RES]]791;792 %res = call <32 x i8> @llvm.x86.avx2.psign.b(<32 x i8> %a0, <32 x i8> %a1) ; <<32 x i8>> [#uses=1]793 ret <32 x i8> %res794}795declare <32 x i8> @llvm.x86.avx2.psign.b(<32 x i8>, <32 x i8>) nounwind readnone796 797 798define <8 x i32> @test_x86_avx2_psign_d(<8 x i32> %a0, <8 x i32> %a1) #0 {799; CHECK-LABEL: @test_x86_avx2_psign_d(800; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8801; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8802; CHECK-NEXT: call void @llvm.donothing()803; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> [[TMP1]], [[TMP2]]804; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx2.psign.d(<8 x i32> [[A0:%.*]], <8 x i32> [[A1:%.*]])805; CHECK-NEXT: store <8 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8806; CHECK-NEXT: ret <8 x i32> [[RES]]807;808 %res = call <8 x i32> @llvm.x86.avx2.psign.d(<8 x i32> %a0, <8 x i32> %a1) ; <<4 x i32>> [#uses=1]809 ret <8 x i32> %res810}811declare <8 x i32> @llvm.x86.avx2.psign.d(<8 x i32>, <8 x i32>) nounwind readnone812 813 814define <16 x i16> @test_x86_avx2_psign_w(<16 x i16> %a0, <16 x i16> %a1) #0 {815; CHECK-LABEL: @test_x86_avx2_psign_w(816; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8817; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8818; CHECK-NEXT: call void @llvm.donothing()819; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i16> [[TMP1]], [[TMP2]]820; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.psign.w(<16 x i16> [[A0:%.*]], <16 x i16> [[A1:%.*]])821; CHECK-NEXT: store <16 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8822; CHECK-NEXT: ret <16 x i16> [[RES]]823;824 %res = call <16 x i16> @llvm.x86.avx2.psign.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]825 ret <16 x i16> %res826}827declare <16 x i16> @llvm.x86.avx2.psign.w(<16 x i16>, <16 x i16>) nounwind readnone828 829 830define <16 x i16> @test_x86_avx2_mpsadbw(<32 x i8> %a0, <32 x i8> %a1) #0 {831; CHECK-LABEL: @test_x86_avx2_mpsadbw(832; CHECK-NEXT: [[TMP1:%.*]] = load <32 x i8>, ptr @__msan_param_tls, align 8833; CHECK-NEXT: [[TMP2:%.*]] = load <32 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8834; CHECK-NEXT: call void @llvm.donothing()835; CHECK-NEXT: [[TMP3:%.*]] = bitcast <32 x i8> [[TMP1]] to i256836; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP3]], 0837; CHECK-NEXT: [[TMP4:%.*]] = bitcast <32 x i8> [[TMP2]] to i256838; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP4]], 0839; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]840; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]841; CHECK: 5:842; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]843; CHECK-NEXT: unreachable844; CHECK: 6:845; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.mpsadbw(<32 x i8> [[A0:%.*]], <32 x i8> [[A1:%.*]], i8 7)846; CHECK-NEXT: store <16 x i16> zeroinitializer, ptr @__msan_retval_tls, align 8847; CHECK-NEXT: ret <16 x i16> [[RES]]848;849 %res = call <16 x i16> @llvm.x86.avx2.mpsadbw(<32 x i8> %a0, <32 x i8> %a1, i8 7) ; <<16 x i16>> [#uses=1]850 ret <16 x i16> %res851}852declare <16 x i16> @llvm.x86.avx2.mpsadbw(<32 x i8>, <32 x i8>, i8) nounwind readnone853 854define <16 x i16> @test_x86_avx2_mpsadbw_load_op0(ptr %ptr, <32 x i8> %a1) #0 {855; CHECK-LABEL: @test_x86_avx2_mpsadbw_load_op0(856; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8857; CHECK-NEXT: [[TMP2:%.*]] = load <32 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8858; CHECK-NEXT: call void @llvm.donothing()859; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0860; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]861; CHECK: 3:862; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]863; CHECK-NEXT: unreachable864; CHECK: 4:865; CHECK-NEXT: [[A0:%.*]] = load <32 x i8>, ptr [[PTR:%.*]], align 32866; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[PTR]] to i64867; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 87960930222080868; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr869; CHECK-NEXT: [[_MSLD:%.*]] = load <32 x i8>, ptr [[TMP7]], align 32870; CHECK-NEXT: [[TMP8:%.*]] = bitcast <32 x i8> [[_MSLD]] to i256871; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP8]], 0872; CHECK-NEXT: [[TMP9:%.*]] = bitcast <32 x i8> [[TMP2]] to i256873; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i256 [[TMP9]], 0874; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP1]], [[_MSCMP2]]875; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP10:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]876; CHECK: 10:877; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]878; CHECK-NEXT: unreachable879; CHECK: 11:880; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.mpsadbw(<32 x i8> [[A0]], <32 x i8> [[A1:%.*]], i8 7)881; CHECK-NEXT: store <16 x i16> zeroinitializer, ptr @__msan_retval_tls, align 8882; CHECK-NEXT: ret <16 x i16> [[RES]]883;884 %a0 = load <32 x i8>, ptr %ptr885 %res = call <16 x i16> @llvm.x86.avx2.mpsadbw(<32 x i8> %a0, <32 x i8> %a1, i8 7) ; <<16 x i16>> [#uses=1]886 ret <16 x i16> %res887}888 889define <16 x i16> @test_x86_avx2_packusdw(<8 x i32> %a0, <8 x i32> %a1) #0 {890; CHECK-LABEL: @test_x86_avx2_packusdw(891; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8892; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8893; CHECK-NEXT: call void @llvm.donothing()894; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <8 x i32> [[TMP1]], zeroinitializer895; CHECK-NEXT: [[TMP4:%.*]] = sext <8 x i1> [[TMP3]] to <8 x i32>896; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <8 x i32> [[TMP2]], zeroinitializer897; CHECK-NEXT: [[TMP6:%.*]] = sext <8 x i1> [[TMP5]] to <8 x i32>898; CHECK-NEXT: [[_MSPROP_VECTOR_PACK:%.*]] = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> [[TMP4]], <8 x i32> [[TMP6]])899; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.packusdw(<8 x i32> [[A0:%.*]], <8 x i32> [[A1:%.*]])900; CHECK-NEXT: store <16 x i16> [[_MSPROP_VECTOR_PACK]], ptr @__msan_retval_tls, align 8901; CHECK-NEXT: ret <16 x i16> [[RES]]902;903 %res = call <16 x i16> @llvm.x86.avx2.packusdw(<8 x i32> %a0, <8 x i32> %a1) ; <<16 x i16>> [#uses=1]904 ret <16 x i16> %res905}906declare <16 x i16> @llvm.x86.avx2.packusdw(<8 x i32>, <8 x i32>) nounwind readnone907 908 909define <16 x i16> @test_x86_avx2_packusdw_fold() #0 {910; CHECK-LABEL: @test_x86_avx2_packusdw_fold(911; CHECK-NEXT: call void @llvm.donothing()912; CHECK-NEXT: [[_MSPROP_VECTOR_PACK:%.*]] = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> zeroinitializer, <8 x i32> zeroinitializer)913; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.packusdw(<8 x i32> zeroinitializer, <8 x i32> <i32 255, i32 32767, i32 65535, i32 -1, i32 -32767, i32 -65535, i32 0, i32 -256>)914; CHECK-NEXT: store <16 x i16> [[_MSPROP_VECTOR_PACK]], ptr @__msan_retval_tls, align 8915; CHECK-NEXT: ret <16 x i16> [[RES]]916;917 %res = call <16 x i16> @llvm.x86.avx2.packusdw(<8 x i32> zeroinitializer, <8 x i32> <i32 255, i32 32767, i32 65535, i32 -1, i32 -32767, i32 -65535, i32 0, i32 -256>)918 ret <16 x i16> %res919}920 921 922define <32 x i8> @test_x86_avx2_pblendvb(<32 x i8> %a0, <32 x i8> %a1, <32 x i8> %a2) #0 {923; CHECK-LABEL: @test_x86_avx2_pblendvb(924; CHECK-NEXT: [[TMP1:%.*]] = load <32 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 8925; CHECK-NEXT: [[TMP2:%.*]] = load <32 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8926; CHECK-NEXT: [[TMP3:%.*]] = load <32 x i8>, ptr @__msan_param_tls, align 8927; CHECK-NEXT: call void @llvm.donothing()928; CHECK-NEXT: [[TMP4:%.*]] = ashr <32 x i8> [[A2:%.*]], splat (i8 7)929; CHECK-NEXT: [[TMP5:%.*]] = trunc <32 x i8> [[TMP4]] to <32 x i1>930; CHECK-NEXT: [[TMP6:%.*]] = ashr <32 x i8> [[TMP1]], splat (i8 7)931; CHECK-NEXT: [[TMP7:%.*]] = trunc <32 x i8> [[TMP6]] to <32 x i1>932; CHECK-NEXT: [[TMP8:%.*]] = select <32 x i1> [[TMP5]], <32 x i8> [[TMP2]], <32 x i8> [[TMP3]]933; CHECK-NEXT: [[TMP9:%.*]] = xor <32 x i8> [[A1:%.*]], [[A0:%.*]]934; CHECK-NEXT: [[TMP10:%.*]] = or <32 x i8> [[TMP9]], [[TMP2]]935; CHECK-NEXT: [[TMP11:%.*]] = or <32 x i8> [[TMP10]], [[TMP3]]936; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <32 x i1> [[TMP7]], <32 x i8> [[TMP11]], <32 x i8> [[TMP8]]937; CHECK-NEXT: [[RES:%.*]] = call <32 x i8> @llvm.x86.avx2.pblendvb(<32 x i8> [[A0]], <32 x i8> [[A1]], <32 x i8> [[A2]])938; CHECK-NEXT: store <32 x i8> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 8939; CHECK-NEXT: ret <32 x i8> [[RES]]940;941 %res = call <32 x i8> @llvm.x86.avx2.pblendvb(<32 x i8> %a0, <32 x i8> %a1, <32 x i8> %a2) ; <<32 x i8>> [#uses=1]942 ret <32 x i8> %res943}944declare <32 x i8> @llvm.x86.avx2.pblendvb(<32 x i8>, <32 x i8>, <32 x i8>) nounwind readnone945 946 947define <16 x i16> @test_x86_avx2_pblendw(<16 x i16> %a0, <16 x i16> %a1) #0 {948; CHECK-LABEL: @test_x86_avx2_pblendw(949; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8950; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8951; CHECK-NEXT: call void @llvm.donothing()952; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <16 x i16> [[TMP1]], <16 x i16> [[TMP2]], <16 x i32> <i32 16, i32 17, i32 18, i32 3, i32 4, i32 5, i32 6, i32 7, i32 24, i32 25, i32 26, i32 11, i32 12, i32 13, i32 14, i32 15>953; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <16 x i16> [[A0:%.*]], <16 x i16> [[A1:%.*]], <16 x i32> <i32 16, i32 17, i32 18, i32 3, i32 4, i32 5, i32 6, i32 7, i32 24, i32 25, i32 26, i32 11, i32 12, i32 13, i32 14, i32 15>954; CHECK-NEXT: store <16 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8955; CHECK-NEXT: ret <16 x i16> [[TMP3]]956;957 %res = call <16 x i16> @llvm.x86.avx2.pblendw(<16 x i16> %a0, <16 x i16> %a1, i8 7) ; <<16 x i16>> [#uses=1]958 ret <16 x i16> %res959}960declare <16 x i16> @llvm.x86.avx2.pblendw(<16 x i16>, <16 x i16>, i8) nounwind readnone961 962 963define <4 x i32> @test_x86_avx2_pblendd_128(<4 x i32> %a0, <4 x i32> %a1) #0 {964; CHECK-LABEL: @test_x86_avx2_pblendd_128(965; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8966; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8967; CHECK-NEXT: call void @llvm.donothing()968; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> [[TMP2]], <4 x i32> <i32 4, i32 5, i32 6, i32 3>969; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i32> [[A0:%.*]], <4 x i32> [[A1:%.*]], <4 x i32> <i32 4, i32 5, i32 6, i32 3>970; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8971; CHECK-NEXT: ret <4 x i32> [[TMP3]]972;973 %res = call <4 x i32> @llvm.x86.avx2.pblendd.128(<4 x i32> %a0, <4 x i32> %a1, i8 7) ; <<4 x i32>> [#uses=1]974 ret <4 x i32> %res975}976declare <4 x i32> @llvm.x86.avx2.pblendd.128(<4 x i32>, <4 x i32>, i8) nounwind readnone977 978 979define <8 x i32> @test_x86_avx2_pblendd_256(<8 x i32> %a0, <8 x i32> %a1) #0 {980; CHECK-LABEL: @test_x86_avx2_pblendd_256(981; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8982; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8983; CHECK-NEXT: call void @llvm.donothing()984; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> [[TMP2]], <8 x i32> <i32 8, i32 9, i32 10, i32 3, i32 4, i32 5, i32 6, i32 7>985; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x i32> [[A0:%.*]], <8 x i32> [[A1:%.*]], <8 x i32> <i32 8, i32 9, i32 10, i32 3, i32 4, i32 5, i32 6, i32 7>986; CHECK-NEXT: store <8 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8987; CHECK-NEXT: ret <8 x i32> [[TMP3]]988;989 %res = call <8 x i32> @llvm.x86.avx2.pblendd.256(<8 x i32> %a0, <8 x i32> %a1, i8 7) ; <<8 x i32>> [#uses=1]990 ret <8 x i32> %res991}992declare <8 x i32> @llvm.x86.avx2.pblendd.256(<8 x i32>, <8 x i32>, i8) nounwind readnone993 994 995define <8 x i32> @test_x86_avx2_permd(<8 x i32> %a0, <8 x i32> %a1) #0 {996; CHECK-LABEL: @test_x86_avx2_permd(997; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8998; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8999; CHECK-NEXT: call void @llvm.donothing()1000; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> [[TMP1]], [[TMP2]]1001; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx2.permd(<8 x i32> [[A0:%.*]], <8 x i32> [[A1:%.*]])1002; CHECK-NEXT: store <8 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 81003; CHECK-NEXT: ret <8 x i32> [[RES]]1004;1005 %res = call <8 x i32> @llvm.x86.avx2.permd(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1]1006 ret <8 x i32> %res1007}1008declare <8 x i32> @llvm.x86.avx2.permd(<8 x i32>, <8 x i32>) nounwind readonly1009 1010 1011define <8 x float> @test_x86_avx2_permps(<8 x float> %a0, <8 x i32> %a1) #0 {1012; CHECK-LABEL: @test_x86_avx2_permps(1013; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 81014; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81015; CHECK-NEXT: call void @llvm.donothing()1016; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i32> [[TMP1]] to i2561017; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP3]], 01018; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i32> [[TMP2]] to i2561019; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP4]], 01020; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1021; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]1022; CHECK: 5:1023; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]1024; CHECK-NEXT: unreachable1025; CHECK: 6:1026; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx2.permps(<8 x float> [[A0:%.*]], <8 x i32> [[A1:%.*]])1027; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81028; CHECK-NEXT: ret <8 x float> [[RES]]1029;1030 %res = call <8 x float> @llvm.x86.avx2.permps(<8 x float> %a0, <8 x i32> %a1) ; <<8 x float>> [#uses=1]1031 ret <8 x float> %res1032}1033declare <8 x float> @llvm.x86.avx2.permps(<8 x float>, <8 x i32>) nounwind readonly1034 1035 1036define <2 x i64> @test_x86_avx2_maskload_q(ptr %a0, <2 x i64> %a1) #0 {1037; CHECK-LABEL: @test_x86_avx2_maskload_q(1038; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81039; CHECK-NEXT: call void @llvm.donothing()1040; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[A0:%.*]] to i641041; CHECK-NEXT: [[TMP9:%.*]] = xor i64 [[TMP6]], 879609302220801042; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP9]] to ptr1043; CHECK-NEXT: [[TMP5:%.*]] = call <2 x i64> @llvm.x86.avx2.maskload.q(ptr [[TMP4]], <2 x i64> [[A1:%.*]])1044; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP2]] to i1281045; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP3]], 01046; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]1047; CHECK: 7:1048; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]1049; CHECK-NEXT: unreachable1050; CHECK: 8:1051; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.avx2.maskload.q(ptr [[A0]], <2 x i64> [[A1]])1052; CHECK-NEXT: store <2 x i64> [[TMP5]], ptr @__msan_retval_tls, align 81053; CHECK-NEXT: ret <2 x i64> [[RES]]1054;1055 %res = call <2 x i64> @llvm.x86.avx2.maskload.q(ptr %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1]1056 ret <2 x i64> %res1057}1058declare <2 x i64> @llvm.x86.avx2.maskload.q(ptr, <2 x i64>) nounwind readonly1059 1060 1061define <4 x i64> @test_x86_avx2_maskload_q_256(ptr %a0, <4 x i64> %a1) #0 {1062; CHECK-LABEL: @test_x86_avx2_maskload_q_256(1063; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81064; CHECK-NEXT: call void @llvm.donothing()1065; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[A0:%.*]] to i641066; CHECK-NEXT: [[TMP9:%.*]] = xor i64 [[TMP6]], 879609302220801067; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP9]] to ptr1068; CHECK-NEXT: [[TMP5:%.*]] = call <4 x i64> @llvm.x86.avx2.maskload.q.256(ptr [[TMP4]], <4 x i64> [[A1:%.*]])1069; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i64> [[TMP2]] to i2561070; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP3]], 01071; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]1072; CHECK: 7:1073; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]1074; CHECK-NEXT: unreachable1075; CHECK: 8:1076; CHECK-NEXT: [[RES:%.*]] = call <4 x i64> @llvm.x86.avx2.maskload.q.256(ptr [[A0]], <4 x i64> [[A1]])1077; CHECK-NEXT: store <4 x i64> [[TMP5]], ptr @__msan_retval_tls, align 81078; CHECK-NEXT: ret <4 x i64> [[RES]]1079;1080 %res = call <4 x i64> @llvm.x86.avx2.maskload.q.256(ptr %a0, <4 x i64> %a1) ; <<4 x i64>> [#uses=1]1081 ret <4 x i64> %res1082}1083declare <4 x i64> @llvm.x86.avx2.maskload.q.256(ptr, <4 x i64>) nounwind readonly1084 1085 1086define <4 x i32> @test_x86_avx2_maskload_d(ptr %a0, <4 x i32> %a1) #0 {1087; CHECK-LABEL: @test_x86_avx2_maskload_d(1088; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81089; CHECK-NEXT: call void @llvm.donothing()1090; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[A0:%.*]] to i641091; CHECK-NEXT: [[TMP9:%.*]] = xor i64 [[TMP6]], 879609302220801092; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP9]] to ptr1093; CHECK-NEXT: [[TMP5:%.*]] = call <4 x i32> @llvm.x86.avx2.maskload.d(ptr [[TMP4]], <4 x i32> [[A1:%.*]])1094; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP2]] to i1281095; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP3]], 01096; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]1097; CHECK: 7:1098; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]1099; CHECK-NEXT: unreachable1100; CHECK: 8:1101; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx2.maskload.d(ptr [[A0]], <4 x i32> [[A1]])1102; CHECK-NEXT: store <4 x i32> [[TMP5]], ptr @__msan_retval_tls, align 81103; CHECK-NEXT: ret <4 x i32> [[RES]]1104;1105 %res = call <4 x i32> @llvm.x86.avx2.maskload.d(ptr %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]1106 ret <4 x i32> %res1107}1108declare <4 x i32> @llvm.x86.avx2.maskload.d(ptr, <4 x i32>) nounwind readonly1109 1110 1111define <8 x i32> @test_x86_avx2_maskload_d_256(ptr %a0, <8 x i32> %a1) #0 {1112; CHECK-LABEL: @test_x86_avx2_maskload_d_256(1113; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81114; CHECK-NEXT: call void @llvm.donothing()1115; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[A0:%.*]] to i641116; CHECK-NEXT: [[TMP9:%.*]] = xor i64 [[TMP6]], 879609302220801117; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP9]] to ptr1118; CHECK-NEXT: [[TMP5:%.*]] = call <8 x i32> @llvm.x86.avx2.maskload.d.256(ptr [[TMP4]], <8 x i32> [[A1:%.*]])1119; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i32> [[TMP2]] to i2561120; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP3]], 01121; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]1122; CHECK: 7:1123; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]1124; CHECK-NEXT: unreachable1125; CHECK: 8:1126; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx2.maskload.d.256(ptr [[A0]], <8 x i32> [[A1]])1127; CHECK-NEXT: store <8 x i32> [[TMP5]], ptr @__msan_retval_tls, align 81128; CHECK-NEXT: ret <8 x i32> [[RES]]1129;1130 %res = call <8 x i32> @llvm.x86.avx2.maskload.d.256(ptr %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1]1131 ret <8 x i32> %res1132}1133declare <8 x i32> @llvm.x86.avx2.maskload.d.256(ptr, <8 x i32>) nounwind readonly1134 1135 1136define void @test_x86_avx2_maskstore_q(ptr %a0, <2 x i64> %a1, <2 x i64> %a2) #0 {1137; CHECK-LABEL: @test_x86_avx2_maskstore_q(1138; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 81139; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81140; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81141; CHECK-NEXT: call void @llvm.donothing()1142; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A0:%.*]] to i641143; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP4]], 879609302220801144; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP7]] to ptr1145; CHECK-NEXT: call void @llvm.x86.avx2.maskstore.q(ptr [[TMP6]], <2 x i64> [[A1:%.*]], <2 x i64> [[TMP3]])1146; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01147; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP2]] to i1281148; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP5]], 01149; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP2]]1150; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]1151; CHECK: 8:1152; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]1153; CHECK-NEXT: unreachable1154; CHECK: 9:1155; CHECK-NEXT: call void @llvm.x86.avx2.maskstore.q(ptr [[A0]], <2 x i64> [[A1]], <2 x i64> [[A2:%.*]])1156; CHECK-NEXT: ret void1157;1158 call void @llvm.x86.avx2.maskstore.q(ptr %a0, <2 x i64> %a1, <2 x i64> %a2)1159 ret void1160}1161declare void @llvm.x86.avx2.maskstore.q(ptr, <2 x i64>, <2 x i64>) nounwind1162 1163 1164define void @test_x86_avx2_maskstore_q_256(ptr %a0, <4 x i64> %a1, <4 x i64> %a2) #0 {1165; CHECK-LABEL: @test_x86_avx2_maskstore_q_256(1166; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 81167; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81168; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81169; CHECK-NEXT: call void @llvm.donothing()1170; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A0:%.*]] to i641171; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP4]], 879609302220801172; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP7]] to ptr1173; CHECK-NEXT: call void @llvm.x86.avx2.maskstore.q.256(ptr [[TMP6]], <4 x i64> [[A1:%.*]], <4 x i64> [[TMP3]])1174; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01175; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i64> [[TMP2]] to i2561176; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i256 [[TMP5]], 01177; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP2]]1178; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]1179; CHECK: 8:1180; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]1181; CHECK-NEXT: unreachable1182; CHECK: 9:1183; CHECK-NEXT: call void @llvm.x86.avx2.maskstore.q.256(ptr [[A0]], <4 x i64> [[A1]], <4 x i64> [[A2:%.*]])1184; CHECK-NEXT: ret void1185;1186 call void @llvm.x86.avx2.maskstore.q.256(ptr %a0, <4 x i64> %a1, <4 x i64> %a2)1187 ret void1188}1189declare void @llvm.x86.avx2.maskstore.q.256(ptr, <4 x i64>, <4 x i64>) nounwind1190 1191 1192define void @test_x86_avx2_maskstore_d(ptr %a0, <4 x i32> %a1, <4 x i32> %a2) #0 {1193; CHECK-LABEL: @test_x86_avx2_maskstore_d(1194; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 81195; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81196; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81197; CHECK-NEXT: call void @llvm.donothing()1198; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A0:%.*]] to i641199; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP4]], 879609302220801200; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP7]] to ptr1201; CHECK-NEXT: call void @llvm.x86.avx2.maskstore.d(ptr [[TMP6]], <4 x i32> [[A1:%.*]], <4 x i32> [[TMP3]])1202; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01203; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP2]] to i1281204; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP5]], 01205; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP2]]1206; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]1207; CHECK: 8:1208; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]1209; CHECK-NEXT: unreachable1210; CHECK: 9:1211; CHECK-NEXT: call void @llvm.x86.avx2.maskstore.d(ptr [[A0]], <4 x i32> [[A1]], <4 x i32> [[A2:%.*]])1212; CHECK-NEXT: ret void1213;1214 call void @llvm.x86.avx2.maskstore.d(ptr %a0, <4 x i32> %a1, <4 x i32> %a2)1215 ret void1216}1217declare void @llvm.x86.avx2.maskstore.d(ptr, <4 x i32>, <4 x i32>) nounwind1218 1219 1220define void @test_x86_avx2_maskstore_d_256(ptr %a0, <8 x i32> %a1, <8 x i32> %a2) #0 {1221; CHECK-LABEL: @test_x86_avx2_maskstore_d_256(1222; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 81223; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81224; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81225; CHECK-NEXT: call void @llvm.donothing()1226; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A0:%.*]] to i641227; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP4]], 879609302220801228; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP7]] to ptr1229; CHECK-NEXT: call void @llvm.x86.avx2.maskstore.d.256(ptr [[TMP6]], <8 x i32> [[A1:%.*]], <8 x i32> [[TMP3]])1230; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01231; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i32> [[TMP2]] to i2561232; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i256 [[TMP5]], 01233; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP2]]1234; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]1235; CHECK: 8:1236; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]1237; CHECK-NEXT: unreachable1238; CHECK: 9:1239; CHECK-NEXT: call void @llvm.x86.avx2.maskstore.d.256(ptr [[A0]], <8 x i32> [[A1]], <8 x i32> [[A2:%.*]])1240; CHECK-NEXT: ret void1241;1242 call void @llvm.x86.avx2.maskstore.d.256(ptr %a0, <8 x i32> %a1, <8 x i32> %a2)1243 ret void1244}1245declare void @llvm.x86.avx2.maskstore.d.256(ptr, <8 x i32>, <8 x i32>) nounwind1246 1247 1248define <4 x i32> @test_x86_avx2_psllv_d(<4 x i32> %a0, <4 x i32> %a1) #0 {1249; CHECK-LABEL: @test_x86_avx2_psllv_d(1250; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 81251; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81252; CHECK-NEXT: call void @llvm.donothing()1253; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <4 x i32> [[TMP2]], zeroinitializer1254; CHECK-NEXT: [[TMP4:%.*]] = sext <4 x i1> [[TMP3]] to <4 x i32>1255; CHECK-NEXT: [[TMP5:%.*]] = call <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32> [[TMP1]], <4 x i32> [[A1:%.*]])1256; CHECK-NEXT: [[TMP6:%.*]] = or <4 x i32> [[TMP5]], [[TMP4]]1257; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32> [[A0:%.*]], <4 x i32> [[A1]])1258; CHECK-NEXT: store <4 x i32> [[TMP6]], ptr @__msan_retval_tls, align 81259; CHECK-NEXT: ret <4 x i32> [[RES]]1260;1261 %res = call <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]1262 ret <4 x i32> %res1263}1264 1265define <4 x i32> @test_x86_avx2_psllv_d_const() #0 {1266; CHECK-LABEL: @test_x86_avx2_psllv_d_const(1267; CHECK-NEXT: call void @llvm.donothing()1268; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32> zeroinitializer, <4 x i32> <i32 1, i32 0, i32 33, i32 -1>)1269; CHECK-NEXT: [[TMP2:%.*]] = or <4 x i32> [[TMP1]], zeroinitializer1270; CHECK-NEXT: [[RES0:%.*]] = call <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32> <i32 2, i32 9, i32 0, i32 -1>, <4 x i32> <i32 1, i32 0, i32 33, i32 -1>)1271; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32> zeroinitializer, <4 x i32> <i32 1, i32 1, i32 1, i32 -1>)1272; CHECK-NEXT: [[TMP4:%.*]] = or <4 x i32> [[TMP3]], zeroinitializer1273; CHECK-NEXT: [[RES1:%.*]] = call <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32> <i32 1, i32 1, i32 1, i32 -1>, <4 x i32> <i32 1, i32 1, i32 1, i32 -1>)1274; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP2]], [[TMP4]]1275; CHECK-NEXT: [[RES2:%.*]] = add <4 x i32> [[RES0]], [[RES1]]1276; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 81277; CHECK-NEXT: ret <4 x i32> [[RES2]]1278;1279 %res0 = call <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32> <i32 2, i32 9, i32 0, i32 -1>, <4 x i32> <i32 1, i32 0, i32 33, i32 -1>)1280 %res1 = call <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32> <i32 1, i32 1, i32 1, i32 -1>, <4 x i32> <i32 1, i32 1, i32 1, i32 -1>)1281 %res2 = add <4 x i32> %res0, %res11282 ret <4 x i32> %res21283}1284declare <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32>, <4 x i32>) nounwind readnone1285 1286 1287define <8 x i32> @test_x86_avx2_psllv_d_256(<8 x i32> %a0, <8 x i32> %a1) #0 {1288; CHECK-LABEL: @test_x86_avx2_psllv_d_256(1289; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 81290; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81291; CHECK-NEXT: call void @llvm.donothing()1292; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <8 x i32> [[TMP2]], zeroinitializer1293; CHECK-NEXT: [[TMP4:%.*]] = sext <8 x i1> [[TMP3]] to <8 x i32>1294; CHECK-NEXT: [[TMP5:%.*]] = call <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32> [[TMP1]], <8 x i32> [[A1:%.*]])1295; CHECK-NEXT: [[TMP6:%.*]] = or <8 x i32> [[TMP5]], [[TMP4]]1296; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32> [[A0:%.*]], <8 x i32> [[A1]])1297; CHECK-NEXT: store <8 x i32> [[TMP6]], ptr @__msan_retval_tls, align 81298; CHECK-NEXT: ret <8 x i32> [[RES]]1299;1300 %res = call <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1]1301 ret <8 x i32> %res1302}1303 1304define <8 x i32> @test_x86_avx2_psllv_d_256_const() #0 {1305; CHECK-LABEL: @test_x86_avx2_psllv_d_256_const(1306; CHECK-NEXT: call void @llvm.donothing()1307; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32> zeroinitializer, <8 x i32> <i32 1, i32 0, i32 33, i32 -1, i32 2, i32 0, i32 34, i32 -2>)1308; CHECK-NEXT: [[TMP2:%.*]] = or <8 x i32> [[TMP1]], zeroinitializer1309; CHECK-NEXT: [[RES0:%.*]] = call <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32> <i32 2, i32 9, i32 0, i32 -1, i32 3, i32 7, i32 -1, i32 0>, <8 x i32> <i32 1, i32 0, i32 33, i32 -1, i32 2, i32 0, i32 34, i32 -2>)1310; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32> zeroinitializer, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 -1>)1311; CHECK-NEXT: [[TMP4:%.*]] = or <8 x i32> [[TMP3]], zeroinitializer1312; CHECK-NEXT: [[RES1:%.*]] = call <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32> <i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 -1>, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 -1>)1313; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> [[TMP2]], [[TMP4]]1314; CHECK-NEXT: [[RES2:%.*]] = add <8 x i32> [[RES0]], [[RES1]]1315; CHECK-NEXT: store <8 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 81316; CHECK-NEXT: ret <8 x i32> [[RES2]]1317;1318 %res0 = call <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32> <i32 2, i32 9, i32 0, i32 -1, i32 3, i32 7, i32 -1, i32 0>, <8 x i32> <i32 1, i32 0, i32 33, i32 -1,i32 2, i32 0, i32 34, i32 -2>)1319 %res1 = call <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32> <i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 -1>, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 -1>)1320 %res2 = add <8 x i32> %res0, %res11321 ret <8 x i32> %res21322}1323declare <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32>, <8 x i32>) nounwind readnone1324 1325 1326define <2 x i64> @test_x86_avx2_psllv_q(<2 x i64> %a0, <2 x i64> %a1) #0 {1327; CHECK-LABEL: @test_x86_avx2_psllv_q(1328; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 81329; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81330; CHECK-NEXT: call void @llvm.donothing()1331; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <2 x i64> [[TMP2]], zeroinitializer1332; CHECK-NEXT: [[TMP4:%.*]] = sext <2 x i1> [[TMP3]] to <2 x i64>1333; CHECK-NEXT: [[TMP5:%.*]] = call <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64> [[TMP1]], <2 x i64> [[A1:%.*]])1334; CHECK-NEXT: [[TMP6:%.*]] = or <2 x i64> [[TMP5]], [[TMP4]]1335; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64> [[A0:%.*]], <2 x i64> [[A1]])1336; CHECK-NEXT: store <2 x i64> [[TMP6]], ptr @__msan_retval_tls, align 81337; CHECK-NEXT: ret <2 x i64> [[RES]]1338;1339 %res = call <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1]1340 ret <2 x i64> %res1341}1342define <2 x i64> @test_x86_avx2_psllv_q_const() #0 {1343; CHECK-LABEL: @test_x86_avx2_psllv_q_const(1344; CHECK-NEXT: call void @llvm.donothing()1345; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64> zeroinitializer, <2 x i64> <i64 1, i64 -1>)1346; CHECK-NEXT: [[TMP2:%.*]] = or <2 x i64> [[TMP1]], zeroinitializer1347; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64> <i64 4, i64 -1>, <2 x i64> <i64 1, i64 -1>)1348; CHECK-NEXT: store <2 x i64> [[TMP2]], ptr @__msan_retval_tls, align 81349; CHECK-NEXT: ret <2 x i64> [[RES]]1350;1351 %res = call <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64> <i64 4, i64 -1>, <2 x i64> <i64 1, i64 -1>)1352 ret <2 x i64> %res1353}1354declare <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64>, <2 x i64>) nounwind readnone1355 1356 1357define <4 x i64> @test_x86_avx2_psllv_q_256(<4 x i64> %a0, <4 x i64> %a1) #0 {1358; CHECK-LABEL: @test_x86_avx2_psllv_q_256(1359; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 81360; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81361; CHECK-NEXT: call void @llvm.donothing()1362; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <4 x i64> [[TMP2]], zeroinitializer1363; CHECK-NEXT: [[TMP4:%.*]] = sext <4 x i1> [[TMP3]] to <4 x i64>1364; CHECK-NEXT: [[TMP5:%.*]] = call <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64> [[TMP1]], <4 x i64> [[A1:%.*]])1365; CHECK-NEXT: [[TMP6:%.*]] = or <4 x i64> [[TMP5]], [[TMP4]]1366; CHECK-NEXT: [[RES:%.*]] = call <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64> [[A0:%.*]], <4 x i64> [[A1]])1367; CHECK-NEXT: store <4 x i64> [[TMP6]], ptr @__msan_retval_tls, align 81368; CHECK-NEXT: ret <4 x i64> [[RES]]1369;1370 %res = call <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64> %a0, <4 x i64> %a1) ; <<4 x i64>> [#uses=1]1371 ret <4 x i64> %res1372}1373 1374define <4 x i64> @test_x86_avx2_psllv_q_256_const() #0 {1375; CHECK-LABEL: @test_x86_avx2_psllv_q_256_const(1376; CHECK-NEXT: call void @llvm.donothing()1377; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64> zeroinitializer, <4 x i64> <i64 1, i64 1, i64 1, i64 -1>)1378; CHECK-NEXT: [[TMP2:%.*]] = or <4 x i64> [[TMP1]], zeroinitializer1379; CHECK-NEXT: [[RES:%.*]] = call <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64> <i64 4, i64 4, i64 4, i64 -1>, <4 x i64> <i64 1, i64 1, i64 1, i64 -1>)1380; CHECK-NEXT: store <4 x i64> [[TMP2]], ptr @__msan_retval_tls, align 81381; CHECK-NEXT: ret <4 x i64> [[RES]]1382;1383 %res = call <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64> <i64 4, i64 4, i64 4, i64 -1>, <4 x i64> <i64 1, i64 1, i64 1, i64 -1>)1384 ret <4 x i64> %res1385}1386declare <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64>, <4 x i64>) nounwind readnone1387 1388 1389define <4 x i32> @test_x86_avx2_psrlv_d(<4 x i32> %a0, <4 x i32> %a1) #0 {1390; CHECK-LABEL: @test_x86_avx2_psrlv_d(1391; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 81392; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81393; CHECK-NEXT: call void @llvm.donothing()1394; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <4 x i32> [[TMP2]], zeroinitializer1395; CHECK-NEXT: [[TMP4:%.*]] = sext <4 x i1> [[TMP3]] to <4 x i32>1396; CHECK-NEXT: [[TMP5:%.*]] = call <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32> [[TMP1]], <4 x i32> [[A1:%.*]])1397; CHECK-NEXT: [[TMP6:%.*]] = or <4 x i32> [[TMP5]], [[TMP4]]1398; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32> [[A0:%.*]], <4 x i32> [[A1]])1399; CHECK-NEXT: store <4 x i32> [[TMP6]], ptr @__msan_retval_tls, align 81400; CHECK-NEXT: ret <4 x i32> [[RES]]1401;1402 %res = call <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]1403 ret <4 x i32> %res1404}1405 1406define <4 x i32> @test_x86_avx2_psrlv_d_const() #0 {1407; CHECK-LABEL: @test_x86_avx2_psrlv_d_const(1408; CHECK-NEXT: call void @llvm.donothing()1409; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32> zeroinitializer, <4 x i32> <i32 1, i32 0, i32 33, i32 -1>)1410; CHECK-NEXT: [[TMP2:%.*]] = or <4 x i32> [[TMP1]], zeroinitializer1411; CHECK-NEXT: [[RES0:%.*]] = call <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32> <i32 2, i32 9, i32 0, i32 -1>, <4 x i32> <i32 1, i32 0, i32 33, i32 -1>)1412; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32> zeroinitializer, <4 x i32> <i32 1, i32 1, i32 1, i32 -1>)1413; CHECK-NEXT: [[TMP4:%.*]] = or <4 x i32> [[TMP3]], zeroinitializer1414; CHECK-NEXT: [[RES1:%.*]] = call <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32> <i32 4, i32 4, i32 4, i32 -1>, <4 x i32> <i32 1, i32 1, i32 1, i32 -1>)1415; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP2]], [[TMP4]]1416; CHECK-NEXT: [[RES2:%.*]] = add <4 x i32> [[RES0]], [[RES1]]1417; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 81418; CHECK-NEXT: ret <4 x i32> [[RES2]]1419;1420 %res0 = call <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32> <i32 2, i32 9, i32 0, i32 -1>, <4 x i32> <i32 1, i32 0, i32 33, i32 -1>)1421 %res1 = call <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32> <i32 4, i32 4, i32 4, i32 -1>, <4 x i32> <i32 1, i32 1, i32 1, i32 -1>)1422 %res2 = add <4 x i32> %res0, %res11423 ret <4 x i32> %res21424}1425declare <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32>, <4 x i32>) nounwind readnone1426 1427 1428define <8 x i32> @test_x86_avx2_psrlv_d_256(<8 x i32> %a0, <8 x i32> %a1) #0 {1429; CHECK-LABEL: @test_x86_avx2_psrlv_d_256(1430; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 81431; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81432; CHECK-NEXT: call void @llvm.donothing()1433; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <8 x i32> [[TMP2]], zeroinitializer1434; CHECK-NEXT: [[TMP4:%.*]] = sext <8 x i1> [[TMP3]] to <8 x i32>1435; CHECK-NEXT: [[TMP5:%.*]] = call <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32> [[TMP1]], <8 x i32> [[A1:%.*]])1436; CHECK-NEXT: [[TMP6:%.*]] = or <8 x i32> [[TMP5]], [[TMP4]]1437; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32> [[A0:%.*]], <8 x i32> [[A1]])1438; CHECK-NEXT: store <8 x i32> [[TMP6]], ptr @__msan_retval_tls, align 81439; CHECK-NEXT: ret <8 x i32> [[RES]]1440;1441 %res = call <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1]1442 ret <8 x i32> %res1443}1444 1445define <8 x i32> @test_x86_avx2_psrlv_d_256_const() #0 {1446; CHECK-LABEL: @test_x86_avx2_psrlv_d_256_const(1447; CHECK-NEXT: call void @llvm.donothing()1448; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32> zeroinitializer, <8 x i32> <i32 1, i32 0, i32 33, i32 -1, i32 2, i32 0, i32 34, i32 -2>)1449; CHECK-NEXT: [[TMP2:%.*]] = or <8 x i32> [[TMP1]], zeroinitializer1450; CHECK-NEXT: [[RES0:%.*]] = call <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32> <i32 2, i32 9, i32 0, i32 -1, i32 3, i32 7, i32 -1, i32 0>, <8 x i32> <i32 1, i32 0, i32 33, i32 -1, i32 2, i32 0, i32 34, i32 -2>)1451; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32> zeroinitializer, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 -1>)1452; CHECK-NEXT: [[TMP4:%.*]] = or <8 x i32> [[TMP3]], zeroinitializer1453; CHECK-NEXT: [[RES1:%.*]] = call <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32> <i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 -1>, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 -1>)1454; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> [[TMP2]], [[TMP4]]1455; CHECK-NEXT: [[RES2:%.*]] = add <8 x i32> [[RES0]], [[RES1]]1456; CHECK-NEXT: store <8 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 81457; CHECK-NEXT: ret <8 x i32> [[RES2]]1458;1459 %res0 = call <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32> <i32 2, i32 9, i32 0, i32 -1, i32 3, i32 7, i32 -1, i32 0>, <8 x i32> <i32 1, i32 0, i32 33, i32 -1,i32 2, i32 0, i32 34, i32 -2>)1460 %res1 = call <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32> <i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 -1>, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 -1>)1461 %res2 = add <8 x i32> %res0, %res11462 ret <8 x i32> %res21463}1464declare <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32>, <8 x i32>) nounwind readnone1465 1466 1467define <2 x i64> @test_x86_avx2_psrlv_q(<2 x i64> %a0, <2 x i64> %a1) #0 {1468; CHECK-LABEL: @test_x86_avx2_psrlv_q(1469; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 81470; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81471; CHECK-NEXT: call void @llvm.donothing()1472; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <2 x i64> [[TMP2]], zeroinitializer1473; CHECK-NEXT: [[TMP4:%.*]] = sext <2 x i1> [[TMP3]] to <2 x i64>1474; CHECK-NEXT: [[TMP5:%.*]] = call <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64> [[TMP1]], <2 x i64> [[A1:%.*]])1475; CHECK-NEXT: [[TMP6:%.*]] = or <2 x i64> [[TMP5]], [[TMP4]]1476; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64> [[A0:%.*]], <2 x i64> [[A1]])1477; CHECK-NEXT: store <2 x i64> [[TMP6]], ptr @__msan_retval_tls, align 81478; CHECK-NEXT: ret <2 x i64> [[RES]]1479;1480 %res = call <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1]1481 ret <2 x i64> %res1482}1483 1484define <2 x i64> @test_x86_avx2_psrlv_q_const() #0 {1485; CHECK-LABEL: @test_x86_avx2_psrlv_q_const(1486; CHECK-NEXT: call void @llvm.donothing()1487; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64> zeroinitializer, <2 x i64> <i64 1, i64 -1>)1488; CHECK-NEXT: [[TMP2:%.*]] = or <2 x i64> [[TMP1]], zeroinitializer1489; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64> splat (i64 4), <2 x i64> <i64 1, i64 -1>)1490; CHECK-NEXT: store <2 x i64> [[TMP2]], ptr @__msan_retval_tls, align 81491; CHECK-NEXT: ret <2 x i64> [[RES]]1492;1493 %res = call <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64> <i64 4, i64 4>, <2 x i64> <i64 1, i64 -1>)1494 ret <2 x i64> %res1495}1496declare <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64>, <2 x i64>) nounwind readnone1497 1498 1499define <4 x i64> @test_x86_avx2_psrlv_q_256(<4 x i64> %a0, <4 x i64> %a1) #0 {1500; CHECK-LABEL: @test_x86_avx2_psrlv_q_256(1501; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 81502; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81503; CHECK-NEXT: call void @llvm.donothing()1504; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <4 x i64> [[TMP2]], zeroinitializer1505; CHECK-NEXT: [[TMP4:%.*]] = sext <4 x i1> [[TMP3]] to <4 x i64>1506; CHECK-NEXT: [[TMP5:%.*]] = call <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64> [[TMP1]], <4 x i64> [[A1:%.*]])1507; CHECK-NEXT: [[TMP6:%.*]] = or <4 x i64> [[TMP5]], [[TMP4]]1508; CHECK-NEXT: [[RES:%.*]] = call <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64> [[A0:%.*]], <4 x i64> [[A1]])1509; CHECK-NEXT: store <4 x i64> [[TMP6]], ptr @__msan_retval_tls, align 81510; CHECK-NEXT: ret <4 x i64> [[RES]]1511;1512 %res = call <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64> %a0, <4 x i64> %a1) ; <<4 x i64>> [#uses=1]1513 ret <4 x i64> %res1514}1515 1516 1517define <4 x i64> @test_x86_avx2_psrlv_q_256_const() #0 {1518; CHECK-LABEL: @test_x86_avx2_psrlv_q_256_const(1519; CHECK-NEXT: call void @llvm.donothing()1520; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64> zeroinitializer, <4 x i64> <i64 1, i64 1, i64 1, i64 -1>)1521; CHECK-NEXT: [[TMP2:%.*]] = or <4 x i64> [[TMP1]], zeroinitializer1522; CHECK-NEXT: [[RES:%.*]] = call <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64> splat (i64 4), <4 x i64> <i64 1, i64 1, i64 1, i64 -1>)1523; CHECK-NEXT: store <4 x i64> [[TMP2]], ptr @__msan_retval_tls, align 81524; CHECK-NEXT: ret <4 x i64> [[RES]]1525;1526 %res = call <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64> <i64 4, i64 4, i64 4, i64 4>, <4 x i64> <i64 1, i64 1, i64 1, i64 -1>)1527 ret <4 x i64> %res1528}1529declare <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64>, <4 x i64>) nounwind readnone1530 1531 1532define <4 x i32> @test_x86_avx2_psrav_d(<4 x i32> %a0, <4 x i32> %a1) #0 {1533; CHECK-LABEL: @test_x86_avx2_psrav_d(1534; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 81535; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81536; CHECK-NEXT: call void @llvm.donothing()1537; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <4 x i32> [[TMP2]], zeroinitializer1538; CHECK-NEXT: [[TMP4:%.*]] = sext <4 x i1> [[TMP3]] to <4 x i32>1539; CHECK-NEXT: [[TMP5:%.*]] = call <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32> [[TMP1]], <4 x i32> [[A1:%.*]])1540; CHECK-NEXT: [[TMP6:%.*]] = or <4 x i32> [[TMP5]], [[TMP4]]1541; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32> [[A0:%.*]], <4 x i32> [[A1]])1542; CHECK-NEXT: store <4 x i32> [[TMP6]], ptr @__msan_retval_tls, align 81543; CHECK-NEXT: ret <4 x i32> [[RES]]1544;1545 %res = call <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]1546 ret <4 x i32> %res1547}1548 1549define <4 x i32> @test_x86_avx2_psrav_d_const() #0 {1550; CHECK-LABEL: @test_x86_avx2_psrav_d_const(1551; CHECK-NEXT: call void @llvm.donothing()1552; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32> zeroinitializer, <4 x i32> <i32 1, i32 18, i32 35, i32 52>)1553; CHECK-NEXT: [[TMP2:%.*]] = or <4 x i32> [[TMP1]], zeroinitializer1554; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32> <i32 2, i32 9, i32 -12, i32 23>, <4 x i32> <i32 1, i32 18, i32 35, i32 52>)1555; CHECK-NEXT: store <4 x i32> [[TMP2]], ptr @__msan_retval_tls, align 81556; CHECK-NEXT: ret <4 x i32> [[RES]]1557;1558 %res = call <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32> <i32 2, i32 9, i32 -12, i32 23>, <4 x i32> <i32 1, i32 18, i32 35, i32 52>)1559 ret <4 x i32> %res1560}1561declare <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32>, <4 x i32>) nounwind readnone1562 1563define <8 x i32> @test_x86_avx2_psrav_d_256(<8 x i32> %a0, <8 x i32> %a1) #0 {1564; CHECK-LABEL: @test_x86_avx2_psrav_d_256(1565; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 81566; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81567; CHECK-NEXT: call void @llvm.donothing()1568; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <8 x i32> [[TMP2]], zeroinitializer1569; CHECK-NEXT: [[TMP4:%.*]] = sext <8 x i1> [[TMP3]] to <8 x i32>1570; CHECK-NEXT: [[TMP5:%.*]] = call <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32> [[TMP1]], <8 x i32> [[A1:%.*]])1571; CHECK-NEXT: [[TMP6:%.*]] = or <8 x i32> [[TMP5]], [[TMP4]]1572; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32> [[A0:%.*]], <8 x i32> [[A1]])1573; CHECK-NEXT: store <8 x i32> [[TMP6]], ptr @__msan_retval_tls, align 81574; CHECK-NEXT: ret <8 x i32> [[RES]]1575;1576 %res = call <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1]1577 ret <8 x i32> %res1578}1579 1580define <8 x i32> @test_x86_avx2_psrav_d_256_const() #0 {1581; CHECK-LABEL: @test_x86_avx2_psrav_d_256_const(1582; CHECK-NEXT: call void @llvm.donothing()1583; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32> zeroinitializer, <8 x i32> <i32 1, i32 18, i32 35, i32 52, i32 69, i32 15, i32 32, i32 49>)1584; CHECK-NEXT: [[TMP2:%.*]] = or <8 x i32> [[TMP1]], zeroinitializer1585; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32> <i32 2, i32 9, i32 -12, i32 23, i32 -26, i32 37, i32 -40, i32 51>, <8 x i32> <i32 1, i32 18, i32 35, i32 52, i32 69, i32 15, i32 32, i32 49>)1586; CHECK-NEXT: store <8 x i32> [[TMP2]], ptr @__msan_retval_tls, align 81587; CHECK-NEXT: ret <8 x i32> [[RES]]1588;1589 %res = call <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32> <i32 2, i32 9, i32 -12, i32 23, i32 -26, i32 37, i32 -40, i32 51>, <8 x i32> <i32 1, i32 18, i32 35, i32 52, i32 69, i32 15, i32 32, i32 49>)1590 ret <8 x i32> %res1591}1592declare <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32>, <8 x i32>) nounwind readnone1593 1594define <2 x double> @test_x86_avx2_gather_d_pd(<2 x double> %a0, ptr %a1, <4 x i32> %idx, <2 x double> %mask) #0 {1595; CHECK-LABEL: @test_x86_avx2_gather_d_pd(1596; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 81597; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81598; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 81599; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 81600; CHECK-NEXT: call void @llvm.donothing()1601; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP1]] to i1281602; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 01603; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 01604; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1605; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i32> [[TMP3]] to i1281606; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP6]], 01607; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]1608; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i64> [[TMP4]] to i1281609; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i128 [[TMP7]], 01610; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]1611; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]1612; CHECK: 8:1613; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]1614; CHECK-NEXT: unreachable1615; CHECK: 9:1616; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx2.gather.d.pd(<2 x double> [[A0:%.*]], ptr [[A1:%.*]], <4 x i32> [[IDX:%.*]], <2 x double> [[MASK:%.*]], i8 2)1617; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 81618; CHECK-NEXT: ret <2 x double> [[RES]]1619;1620 %res = call <2 x double> @llvm.x86.avx2.gather.d.pd(<2 x double> %a0,1621 ptr %a1, <4 x i32> %idx, <2 x double> %mask, i8 2) ;1622 ret <2 x double> %res1623}1624declare <2 x double> @llvm.x86.avx2.gather.d.pd(<2 x double>, ptr,1625 <4 x i32>, <2 x double>, i8) nounwind readonly1626 1627define <4 x double> @test_x86_avx2_gather_d_pd_256(<4 x double> %a0, ptr %a1, <4 x i32> %idx, <4 x double> %mask) #0 {1628; CHECK-LABEL: @test_x86_avx2_gather_d_pd_256(1629; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 81630; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81631; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 81632; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 56), align 81633; CHECK-NEXT: call void @llvm.donothing()1634; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i64> [[TMP1]] to i2561635; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP5]], 01636; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 01637; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1638; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i32> [[TMP3]] to i1281639; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP6]], 01640; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]1641; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i64> [[TMP4]] to i2561642; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i256 [[TMP7]], 01643; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]1644; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]1645; CHECK: 8:1646; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]1647; CHECK-NEXT: unreachable1648; CHECK: 9:1649; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.x86.avx2.gather.d.pd.256(<4 x double> [[A0:%.*]], ptr [[A1:%.*]], <4 x i32> [[IDX:%.*]], <4 x double> [[MASK:%.*]], i8 2)1650; CHECK-NEXT: store <4 x i64> zeroinitializer, ptr @__msan_retval_tls, align 81651; CHECK-NEXT: ret <4 x double> [[RES]]1652;1653 %res = call <4 x double> @llvm.x86.avx2.gather.d.pd.256(<4 x double> %a0,1654 ptr %a1, <4 x i32> %idx, <4 x double> %mask, i8 2) ;1655 ret <4 x double> %res1656}1657declare <4 x double> @llvm.x86.avx2.gather.d.pd.256(<4 x double>, ptr,1658 <4 x i32>, <4 x double>, i8) nounwind readonly1659 1660define <2 x double> @test_x86_avx2_gather_q_pd(<2 x double> %a0, ptr %a1, <2 x i64> %idx, <2 x double> %mask) #0 {1661; CHECK-LABEL: @test_x86_avx2_gather_q_pd(1662; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 81663; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81664; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 81665; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 81666; CHECK-NEXT: call void @llvm.donothing()1667; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP1]] to i1281668; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 01669; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 01670; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1671; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i64> [[TMP3]] to i1281672; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP6]], 01673; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]1674; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i64> [[TMP4]] to i1281675; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i128 [[TMP7]], 01676; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]1677; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]1678; CHECK: 8:1679; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]1680; CHECK-NEXT: unreachable1681; CHECK: 9:1682; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx2.gather.q.pd(<2 x double> [[A0:%.*]], ptr [[A1:%.*]], <2 x i64> [[IDX:%.*]], <2 x double> [[MASK:%.*]], i8 2)1683; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 81684; CHECK-NEXT: ret <2 x double> [[RES]]1685;1686 %res = call <2 x double> @llvm.x86.avx2.gather.q.pd(<2 x double> %a0,1687 ptr %a1, <2 x i64> %idx, <2 x double> %mask, i8 2) ;1688 ret <2 x double> %res1689}1690declare <2 x double> @llvm.x86.avx2.gather.q.pd(<2 x double>, ptr,1691 <2 x i64>, <2 x double>, i8) nounwind readonly1692 1693define <4 x double> @test_x86_avx2_gather_q_pd_256(<4 x double> %a0, ptr %a1, <4 x i64> %idx, <4 x double> %mask) #0 {1694; CHECK-LABEL: @test_x86_avx2_gather_q_pd_256(1695; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 81696; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81697; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 81698; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 72), align 81699; CHECK-NEXT: call void @llvm.donothing()1700; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i64> [[TMP1]] to i2561701; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP5]], 01702; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 01703; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1704; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i64> [[TMP3]] to i2561705; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i256 [[TMP6]], 01706; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]1707; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i64> [[TMP4]] to i2561708; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i256 [[TMP7]], 01709; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]1710; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]1711; CHECK: 8:1712; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]1713; CHECK-NEXT: unreachable1714; CHECK: 9:1715; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.x86.avx2.gather.q.pd.256(<4 x double> [[A0:%.*]], ptr [[A1:%.*]], <4 x i64> [[IDX:%.*]], <4 x double> [[MASK:%.*]], i8 2)1716; CHECK-NEXT: store <4 x i64> zeroinitializer, ptr @__msan_retval_tls, align 81717; CHECK-NEXT: ret <4 x double> [[RES]]1718;1719 %res = call <4 x double> @llvm.x86.avx2.gather.q.pd.256(<4 x double> %a0,1720 ptr %a1, <4 x i64> %idx, <4 x double> %mask, i8 2) ;1721 ret <4 x double> %res1722}1723declare <4 x double> @llvm.x86.avx2.gather.q.pd.256(<4 x double>, ptr,1724 <4 x i64>, <4 x double>, i8) nounwind readonly1725 1726define <4 x float> @test_x86_avx2_gather_d_ps(<4 x float> %a0, ptr %a1, <4 x i32> %idx, <4 x float> %mask) #0 {1727; CHECK-LABEL: @test_x86_avx2_gather_d_ps(1728; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 81729; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81730; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 81731; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 81732; CHECK-NEXT: call void @llvm.donothing()1733; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP1]] to i1281734; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 01735; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 01736; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1737; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i32> [[TMP3]] to i1281738; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP6]], 01739; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]1740; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i32> [[TMP4]] to i1281741; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i128 [[TMP7]], 01742; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]1743; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]1744; CHECK: 8:1745; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]1746; CHECK-NEXT: unreachable1747; CHECK: 9:1748; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx2.gather.d.ps(<4 x float> [[A0:%.*]], ptr [[A1:%.*]], <4 x i32> [[IDX:%.*]], <4 x float> [[MASK:%.*]], i8 2)1749; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81750; CHECK-NEXT: ret <4 x float> [[RES]]1751;1752 %res = call <4 x float> @llvm.x86.avx2.gather.d.ps(<4 x float> %a0,1753 ptr %a1, <4 x i32> %idx, <4 x float> %mask, i8 2) ;1754 ret <4 x float> %res1755}1756declare <4 x float> @llvm.x86.avx2.gather.d.ps(<4 x float>, ptr,1757 <4 x i32>, <4 x float>, i8) nounwind readonly1758 1759define <8 x float> @test_x86_avx2_gather_d_ps_256(<8 x float> %a0, ptr %a1, <8 x i32> %idx, <8 x float> %mask) #0 {1760; CHECK-LABEL: @test_x86_avx2_gather_d_ps_256(1761; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 81762; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81763; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 81764; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 72), align 81765; CHECK-NEXT: call void @llvm.donothing()1766; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i32> [[TMP1]] to i2561767; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP5]], 01768; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 01769; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1770; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i32> [[TMP3]] to i2561771; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i256 [[TMP6]], 01772; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]1773; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i32> [[TMP4]] to i2561774; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i256 [[TMP7]], 01775; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]1776; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]1777; CHECK: 8:1778; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]1779; CHECK-NEXT: unreachable1780; CHECK: 9:1781; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float> [[A0:%.*]], ptr [[A1:%.*]], <8 x i32> [[IDX:%.*]], <8 x float> [[MASK:%.*]], i8 2)1782; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81783; CHECK-NEXT: ret <8 x float> [[RES]]1784;1785 %res = call <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float> %a0,1786 ptr %a1, <8 x i32> %idx, <8 x float> %mask, i8 2) ;1787 ret <8 x float> %res1788}1789declare <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float>, ptr,1790 <8 x i32>, <8 x float>, i8) nounwind readonly1791 1792define <4 x float> @test_x86_avx2_gather_q_ps(<4 x float> %a0, ptr %a1, <2 x i64> %idx, <4 x float> %mask) #0 {1793; CHECK-LABEL: @test_x86_avx2_gather_q_ps(1794; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 81795; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81796; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 81797; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 81798; CHECK-NEXT: call void @llvm.donothing()1799; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP1]] to i1281800; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 01801; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 01802; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1803; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i64> [[TMP3]] to i1281804; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP6]], 01805; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]1806; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i32> [[TMP4]] to i1281807; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i128 [[TMP7]], 01808; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]1809; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]1810; CHECK: 8:1811; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]1812; CHECK-NEXT: unreachable1813; CHECK: 9:1814; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx2.gather.q.ps(<4 x float> [[A0:%.*]], ptr [[A1:%.*]], <2 x i64> [[IDX:%.*]], <4 x float> [[MASK:%.*]], i8 2)1815; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81816; CHECK-NEXT: ret <4 x float> [[RES]]1817;1818 %res = call <4 x float> @llvm.x86.avx2.gather.q.ps(<4 x float> %a0,1819 ptr %a1, <2 x i64> %idx, <4 x float> %mask, i8 2) ;1820 ret <4 x float> %res1821}1822declare <4 x float> @llvm.x86.avx2.gather.q.ps(<4 x float>, ptr,1823 <2 x i64>, <4 x float>, i8) nounwind readonly1824 1825define <4 x float> @test_x86_avx2_gather_q_ps_256(<4 x float> %a0, ptr %a1, <4 x i64> %idx, <4 x float> %mask) #0 {1826; CHECK-LABEL: @test_x86_avx2_gather_q_ps_256(1827; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 81828; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81829; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 81830; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 56), align 81831; CHECK-NEXT: call void @llvm.donothing()1832; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP1]] to i1281833; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 01834; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 01835; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1836; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i64> [[TMP3]] to i2561837; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i256 [[TMP6]], 01838; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]1839; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i32> [[TMP4]] to i1281840; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i128 [[TMP7]], 01841; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]1842; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]1843; CHECK: 8:1844; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]1845; CHECK-NEXT: unreachable1846; CHECK: 9:1847; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx2.gather.q.ps.256(<4 x float> [[A0:%.*]], ptr [[A1:%.*]], <4 x i64> [[IDX:%.*]], <4 x float> [[MASK:%.*]], i8 2)1848; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81849; CHECK-NEXT: ret <4 x float> [[RES]]1850;1851 %res = call <4 x float> @llvm.x86.avx2.gather.q.ps.256(<4 x float> %a0,1852 ptr %a1, <4 x i64> %idx, <4 x float> %mask, i8 2) ;1853 ret <4 x float> %res1854}1855declare <4 x float> @llvm.x86.avx2.gather.q.ps.256(<4 x float>, ptr,1856 <4 x i64>, <4 x float>, i8) nounwind readonly1857 1858define <2 x i64> @test_x86_avx2_gather_d_q(<2 x i64> %a0, ptr %a1, <4 x i32> %idx, <2 x i64> %mask) #0 {1859; CHECK-LABEL: @test_x86_avx2_gather_d_q(1860; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 81861; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81862; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 81863; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 81864; CHECK-NEXT: call void @llvm.donothing()1865; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP1]] to i1281866; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 01867; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 01868; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1869; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i32> [[TMP3]] to i1281870; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP6]], 01871; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]1872; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i64> [[TMP4]] to i1281873; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i128 [[TMP7]], 01874; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]1875; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]1876; CHECK: 8:1877; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]1878; CHECK-NEXT: unreachable1879; CHECK: 9:1880; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.avx2.gather.d.q(<2 x i64> [[A0:%.*]], ptr [[A1:%.*]], <4 x i32> [[IDX:%.*]], <2 x i64> [[MASK:%.*]], i8 2)1881; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 81882; CHECK-NEXT: ret <2 x i64> [[RES]]1883;1884 %res = call <2 x i64> @llvm.x86.avx2.gather.d.q(<2 x i64> %a0,1885 ptr %a1, <4 x i32> %idx, <2 x i64> %mask, i8 2) ;1886 ret <2 x i64> %res1887}1888declare <2 x i64> @llvm.x86.avx2.gather.d.q(<2 x i64>, ptr,1889 <4 x i32>, <2 x i64>, i8) nounwind readonly1890 1891define <4 x i64> @test_x86_avx2_gather_d_q_256(<4 x i64> %a0, ptr %a1, <4 x i32> %idx, <4 x i64> %mask) #0 {1892; CHECK-LABEL: @test_x86_avx2_gather_d_q_256(1893; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 81894; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81895; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 81896; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 56), align 81897; CHECK-NEXT: call void @llvm.donothing()1898; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i64> [[TMP1]] to i2561899; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP5]], 01900; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 01901; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1902; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i32> [[TMP3]] to i1281903; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP6]], 01904; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]1905; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i64> [[TMP4]] to i2561906; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i256 [[TMP7]], 01907; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]1908; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]1909; CHECK: 8:1910; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]1911; CHECK-NEXT: unreachable1912; CHECK: 9:1913; CHECK-NEXT: [[RES:%.*]] = call <4 x i64> @llvm.x86.avx2.gather.d.q.256(<4 x i64> [[A0:%.*]], ptr [[A1:%.*]], <4 x i32> [[IDX:%.*]], <4 x i64> [[MASK:%.*]], i8 2)1914; CHECK-NEXT: store <4 x i64> zeroinitializer, ptr @__msan_retval_tls, align 81915; CHECK-NEXT: ret <4 x i64> [[RES]]1916;1917 %res = call <4 x i64> @llvm.x86.avx2.gather.d.q.256(<4 x i64> %a0,1918 ptr %a1, <4 x i32> %idx, <4 x i64> %mask, i8 2) ;1919 ret <4 x i64> %res1920}1921declare <4 x i64> @llvm.x86.avx2.gather.d.q.256(<4 x i64>, ptr,1922 <4 x i32>, <4 x i64>, i8) nounwind readonly1923 1924define <2 x i64> @test_x86_avx2_gather_q_q(<2 x i64> %a0, ptr %a1, <2 x i64> %idx, <2 x i64> %mask) #0 {1925; CHECK-LABEL: @test_x86_avx2_gather_q_q(1926; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 81927; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81928; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 81929; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 81930; CHECK-NEXT: call void @llvm.donothing()1931; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP1]] to i1281932; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 01933; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 01934; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1935; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i64> [[TMP3]] to i1281936; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP6]], 01937; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]1938; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i64> [[TMP4]] to i1281939; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i128 [[TMP7]], 01940; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]1941; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]1942; CHECK: 8:1943; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]1944; CHECK-NEXT: unreachable1945; CHECK: 9:1946; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.avx2.gather.q.q(<2 x i64> [[A0:%.*]], ptr [[A1:%.*]], <2 x i64> [[IDX:%.*]], <2 x i64> [[MASK:%.*]], i8 2)1947; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 81948; CHECK-NEXT: ret <2 x i64> [[RES]]1949;1950 %res = call <2 x i64> @llvm.x86.avx2.gather.q.q(<2 x i64> %a0,1951 ptr %a1, <2 x i64> %idx, <2 x i64> %mask, i8 2) ;1952 ret <2 x i64> %res1953}1954declare <2 x i64> @llvm.x86.avx2.gather.q.q(<2 x i64>, ptr,1955 <2 x i64>, <2 x i64>, i8) nounwind readonly1956 1957define <4 x i64> @test_x86_avx2_gather_q_q_256(<4 x i64> %a0, ptr %a1, <4 x i64> %idx, <4 x i64> %mask) #0 {1958; CHECK-LABEL: @test_x86_avx2_gather_q_q_256(1959; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 81960; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81961; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 81962; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 72), align 81963; CHECK-NEXT: call void @llvm.donothing()1964; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i64> [[TMP1]] to i2561965; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP5]], 01966; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 01967; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1968; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i64> [[TMP3]] to i2561969; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i256 [[TMP6]], 01970; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]1971; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i64> [[TMP4]] to i2561972; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i256 [[TMP7]], 01973; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]1974; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]1975; CHECK: 8:1976; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]1977; CHECK-NEXT: unreachable1978; CHECK: 9:1979; CHECK-NEXT: [[RES:%.*]] = call <4 x i64> @llvm.x86.avx2.gather.q.q.256(<4 x i64> [[A0:%.*]], ptr [[A1:%.*]], <4 x i64> [[IDX:%.*]], <4 x i64> [[MASK:%.*]], i8 2)1980; CHECK-NEXT: store <4 x i64> zeroinitializer, ptr @__msan_retval_tls, align 81981; CHECK-NEXT: ret <4 x i64> [[RES]]1982;1983 %res = call <4 x i64> @llvm.x86.avx2.gather.q.q.256(<4 x i64> %a0,1984 ptr %a1, <4 x i64> %idx, <4 x i64> %mask, i8 2) ;1985 ret <4 x i64> %res1986}1987declare <4 x i64> @llvm.x86.avx2.gather.q.q.256(<4 x i64>, ptr,1988 <4 x i64>, <4 x i64>, i8) nounwind readonly1989 1990define <4 x i32> @test_x86_avx2_gather_d_d(<4 x i32> %a0, ptr %a1, <4 x i32> %idx, <4 x i32> %mask) #0 {1991; CHECK-LABEL: @test_x86_avx2_gather_d_d(1992; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 81993; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81994; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 81995; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 81996; CHECK-NEXT: call void @llvm.donothing()1997; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP1]] to i1281998; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 01999; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 02000; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]2001; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i32> [[TMP3]] to i1282002; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP6]], 02003; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]2004; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i32> [[TMP4]] to i1282005; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i128 [[TMP7]], 02006; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]2007; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]2008; CHECK: 8:2009; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]2010; CHECK-NEXT: unreachable2011; CHECK: 9:2012; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx2.gather.d.d(<4 x i32> [[A0:%.*]], ptr [[A1:%.*]], <4 x i32> [[IDX:%.*]], <4 x i32> [[MASK:%.*]], i8 2)2013; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 82014; CHECK-NEXT: ret <4 x i32> [[RES]]2015;2016 %res = call <4 x i32> @llvm.x86.avx2.gather.d.d(<4 x i32> %a0,2017 ptr %a1, <4 x i32> %idx, <4 x i32> %mask, i8 2) ;2018 ret <4 x i32> %res2019}2020declare <4 x i32> @llvm.x86.avx2.gather.d.d(<4 x i32>, ptr,2021 <4 x i32>, <4 x i32>, i8) nounwind readonly2022 2023define <8 x i32> @test_x86_avx2_gather_d_d_256(<8 x i32> %a0, ptr %a1, <8 x i32> %idx, <8 x i32> %mask) #0 {2024; CHECK-LABEL: @test_x86_avx2_gather_d_d_256(2025; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 82026; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 82027; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 82028; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 72), align 82029; CHECK-NEXT: call void @llvm.donothing()2030; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i32> [[TMP1]] to i2562031; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP5]], 02032; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 02033; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]2034; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i32> [[TMP3]] to i2562035; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i256 [[TMP6]], 02036; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]2037; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i32> [[TMP4]] to i2562038; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i256 [[TMP7]], 02039; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]2040; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]2041; CHECK: 8:2042; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]2043; CHECK-NEXT: unreachable2044; CHECK: 9:2045; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx2.gather.d.d.256(<8 x i32> [[A0:%.*]], ptr [[A1:%.*]], <8 x i32> [[IDX:%.*]], <8 x i32> [[MASK:%.*]], i8 2)2046; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 82047; CHECK-NEXT: ret <8 x i32> [[RES]]2048;2049 %res = call <8 x i32> @llvm.x86.avx2.gather.d.d.256(<8 x i32> %a0,2050 ptr %a1, <8 x i32> %idx, <8 x i32> %mask, i8 2) ;2051 ret <8 x i32> %res2052}2053declare <8 x i32> @llvm.x86.avx2.gather.d.d.256(<8 x i32>, ptr,2054 <8 x i32>, <8 x i32>, i8) nounwind readonly2055 2056define <4 x i32> @test_x86_avx2_gather_q_d(<4 x i32> %a0, ptr %a1, <2 x i64> %idx, <4 x i32> %mask) #0 {2057; CHECK-LABEL: @test_x86_avx2_gather_q_d(2058; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 82059; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 82060; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 82061; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 82062; CHECK-NEXT: call void @llvm.donothing()2063; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP1]] to i1282064; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 02065; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 02066; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]2067; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i64> [[TMP3]] to i1282068; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP6]], 02069; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]2070; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i32> [[TMP4]] to i1282071; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i128 [[TMP7]], 02072; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]2073; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]2074; CHECK: 8:2075; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]2076; CHECK-NEXT: unreachable2077; CHECK: 9:2078; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx2.gather.q.d(<4 x i32> [[A0:%.*]], ptr [[A1:%.*]], <2 x i64> [[IDX:%.*]], <4 x i32> [[MASK:%.*]], i8 2)2079; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 82080; CHECK-NEXT: ret <4 x i32> [[RES]]2081;2082 %res = call <4 x i32> @llvm.x86.avx2.gather.q.d(<4 x i32> %a0,2083 ptr %a1, <2 x i64> %idx, <4 x i32> %mask, i8 2) ;2084 ret <4 x i32> %res2085}2086declare <4 x i32> @llvm.x86.avx2.gather.q.d(<4 x i32>, ptr,2087 <2 x i64>, <4 x i32>, i8) nounwind readonly2088 2089define <4 x i32> @test_x86_avx2_gather_q_d_256(<4 x i32> %a0, ptr %a1, <4 x i64> %idx, <4 x i32> %mask) #0 {2090; CHECK-LABEL: @test_x86_avx2_gather_q_d_256(2091; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 82092; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 82093; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 82094; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 56), align 82095; CHECK-NEXT: call void @llvm.donothing()2096; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP1]] to i1282097; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 02098; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 02099; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]2100; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i64> [[TMP3]] to i2562101; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i256 [[TMP6]], 02102; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]2103; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i32> [[TMP4]] to i1282104; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i128 [[TMP7]], 02105; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]2106; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]2107; CHECK: 8:2108; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]2109; CHECK-NEXT: unreachable2110; CHECK: 9:2111; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx2.gather.q.d.256(<4 x i32> [[A0:%.*]], ptr [[A1:%.*]], <4 x i64> [[IDX:%.*]], <4 x i32> [[MASK:%.*]], i8 2)2112; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 82113; CHECK-NEXT: ret <4 x i32> [[RES]]2114;2115 %res = call <4 x i32> @llvm.x86.avx2.gather.q.d.256(<4 x i32> %a0,2116 ptr %a1, <4 x i64> %idx, <4 x i32> %mask, i8 2) ;2117 ret <4 x i32> %res2118}2119declare <4 x i32> @llvm.x86.avx2.gather.q.d.256(<4 x i32>, ptr,2120 <4 x i64>, <4 x i32>, i8) nounwind readonly2121 2122define <8 x float> @test_gather_mask(<8 x float> %a0, ptr %a, <8 x i32> %idx, <8 x float> %mask, ptr nocapture %out) #0 {2123; CHECK-LABEL: @test_gather_mask(2124; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 82125; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 82126; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 82127; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 72), align 82128; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 104), align 82129; CHECK-NEXT: call void @llvm.donothing()2130; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i32> [[TMP1]] to i2562131; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP6]], 02132; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 02133; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]2134; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i32> [[TMP3]] to i2562135; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i256 [[TMP7]], 02136; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]2137; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i32> [[TMP4]] to i2562138; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i256 [[TMP8]], 02139; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]2140; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP9:%.*]], label [[TMP10:%.*]], !prof [[PROF1]]2141; CHECK: 9:2142; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]2143; CHECK-NEXT: unreachable2144; CHECK: 10:2145; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float> [[A0:%.*]], ptr [[A:%.*]], <8 x i32> [[IDX:%.*]], <8 x float> [[MASK:%.*]], i8 4)2146; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i64 [[TMP5]], 02147; CHECK-NEXT: br i1 [[_MSCMP6]], label [[TMP11:%.*]], label [[TMP12:%.*]], !prof [[PROF1]]2148; CHECK: 11:2149; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]2150; CHECK-NEXT: unreachable2151; CHECK: 12:2152; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[OUT:%.*]] to i642153; CHECK-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], 879609302220802154; CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP14]] to ptr2155; CHECK-NEXT: store <8 x i32> [[TMP4]], ptr [[TMP15]], align 42156; CHECK-NEXT: store <8 x float> [[MASK]], ptr [[OUT]], align 42157; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 82158; CHECK-NEXT: ret <8 x float> [[RES]]2159;2160 %res = call <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float> %a0,2161 ptr %a, <8 x i32> %idx, <8 x float> %mask, i8 4) ;2162 2163 store <8 x float> %mask, ptr %out, align 42164 2165 ret <8 x float> %res2166}2167 2168define <2 x i64> @test_mask_demanded_bits(<2 x i64> %a0, ptr %a1, <2 x i64> %idx, <2 x i1> %mask) #0 {2169; CHECK-LABEL: @test_mask_demanded_bits(2170; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i1>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 82171; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 82172; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 82173; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 82174; CHECK-NEXT: call void @llvm.donothing()2175; CHECK-NEXT: [[_MSPROP:%.*]] = sext <2 x i1> [[TMP1]] to <2 x i64>2176; CHECK-NEXT: [[MASK1:%.*]] = sext <2 x i1> [[MASK:%.*]] to <2 x i64>2177; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP2]] to i1282178; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 02179; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP3]], 02180; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]2181; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i64> [[TMP4]] to i1282182; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP6]], 02183; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]2184; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i64> [[_MSPROP]] to i1282185; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i128 [[TMP7]], 02186; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]2187; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]2188; CHECK: 8:2189; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]2190; CHECK-NEXT: unreachable2191; CHECK: 9:2192; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.avx2.gather.q.q(<2 x i64> [[A0:%.*]], ptr [[A1:%.*]], <2 x i64> [[IDX:%.*]], <2 x i64> [[MASK1]], i8 2)2193; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 82194; CHECK-NEXT: ret <2 x i64> [[RES]]2195;2196 %mask1 = sext <2 x i1> %mask to <2 x i64>2197 %res = call <2 x i64> @llvm.x86.avx2.gather.q.q(<2 x i64> %a0,2198 ptr %a1, <2 x i64> %idx, <2 x i64> %mask1, i8 2) ;2199 ret <2 x i64> %res2200}2201 2202attributes #0 = { sanitize_memory }2203