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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt %s -S -mattr=+avx512f -passes=msan 2>&1 | FileCheck %s3;4; Forked from llvm/test/CodeGen/X86/avx512-intrinsics.ll5;6; Strictly handled:7; - llvm.x86.avx512.add.ps.5128; - llvm.x86.avx512.cvtsi2ss32, llvm.x86.avx512.cvttsd2si, llvm.x86.avx512.cvttss2si9; - llvm.x86.avx512.div.ps.51210; - llvm.x86.avx512.mask.add.sd.round, llvm.x86.avx512.mask.add.ss.round11; - llvm.x86.avx512.mask.cmp.pd.512, llvm.x86.avx512.mask.cmp.ps.512, llvm.x86.avx512.mask.cmp.sd, llvm.x86.avx512.mask.cmp.ss12; - llvm.x86.avx512.mask.compress.v16f32, llvm.x86.avx512.mask.compress.v16i32llvm.x86.avx512.mask.compress.v8f64, llvm.x86.avx512.mask.compress.v8i6413; - llvm.x86.avx512.mask.cvtpd2dq.512, llvm.x86.avx512.mask.cvtpd2ps.512, llvm.x86.avx512.mask.cvtpd2udq.512, llvm.x86.avx512.mask.cvtps2pd.512, llvm.x86.avx512.mask.cvtps2udq.51214; - llvm.x86.avx512.mask.cvtsd2ss.round, llvm.x86.avx512.mask.cvtss2sd.round15; - llvm.x86.avx512.mask.cvttpd2dq.512, llvm.x86.avx512.mask.cvttpd2udq.512, llvm.x86.avx512.mask.cvttps2dq.512, llvm.x86.avx512.mask.cvttps2udq.51216; - llvm.x86.avx512.mask.expand.v16f32, llvm.x86.avx512.mask.expand.v16i32, llvm.x86.avx512.mask.expand.v8f64, llvm.x86.avx512.mask.expand.v8i6417; - llvm.x86.avx512.mask.fixupimm.pd.512, llvm.x86.avx512.mask.fixupimm.ps.512, llvm.x86.avx512.mask.fixupimm.sd, llvm.x86.avx512.mask.fixupimm.ss18; - llvm.x86.avx512.mask.getexp.pd.512, llvm.x86.avx512.mask.getexp.ps.512, llvm.x86.avx512.mask.getexp.sd, llvm.x86.avx512.mask.getexp.ss19; - llvm.x86.avx512.mask.getmant.pd.512, llvm.x86.avx512.mask.getmant.ps.512, llvm.x86.avx512.mask.getmant.sd, llvm.x86.avx512.mask.getmant.ss20; - llvm.x86.avx512.mask.max.sd.round, llvm.x86.avx512.mask.max.ss.round21; - llvm.x86.avx512.mask.pmov.db.mem.512, llvm.x86.avx512.mask.pmov.dw.mem.512, llvm.x86.avx512.mask.pmov.qb.mem.512, llvm.x86.avx512.mask.pmov.qd.mem.512llvm.x86.avx512.mask.pmov.qw.mem.51222; - llvm.x86.avx512.mask.pmovs.db.mem.512, llvm.x86.avx512.mask.pmovs.dw.mem.512, llvm.x86.avx512.mask.pmovs.qb.mem.512, llvm.x86.avx512.mask.pmovs.qd.mem.512, llvm.x86.avx512.mask.pmovs.qw.mem.51223; - llvm.x86.avx512.mask.pmovus.db.mem.512, llvm.x86.avx512.mask.pmovus.dw.mem.512, llvm.x86.avx512.mask.pmovus.qb.mem.512, llvm.x86.avx512.mask.pmovus.qd.mem.512, llvm.x86.avx512.mask.pmovus.qw.mem.51224; - llvm.x86.avx512.mask.rndscale.sd, llvm.x86.avx512.mask.rndscale.ss25; - llvm.x86.avx512.mask.scalef.pd.512, llvm.x86.avx512.mask.scalef.ps.51226; - llvm.x86.avx512.mask.sqrt.sd, llvm.x86.avx512.mask.sqrt.ss27; - llvm.x86.avx512.maskz.fixupimm.pd.512, llvm.x86.avx512.maskz.fixupimm.ps.512, llvm.x86.avx512.maskz.fixupimm.sd, llvm.x86.avx512.maskz.fixupimm.ss28; - llvm.x86.avx512.mul.pd.512, llvm.x86.avx512.mul.ps.51229; - llvm.x86.avx512.permvar.df.512, llvm.x86.avx512.permvar.sf.51230; - llvm.x86.avx512.pternlog.d.512, llvm.x86.avx512.pternlog.q.51231; - llvm.x86.avx512.sitofp.round.v16f32.v16i3232; - llvm.x86.avx512.sqrt.pd.512, llvm.x86.avx512.sqrt.ps.51233; - llvm.x86.avx512.sub.ps.51234; - llvm.x86.avx512.uitofp.round.v16f32.v16i3235; - llvm.x86.avx512.vcomi.sd, llvm.x86.avx512.vcomi.ss36; - llvm.x86.avx512.vcvtsd2si32, llvm.x86.avx512.vcvtss2si3237; - llvm.x86.avx512.vfmadd.f32, llvm.x86.avx512.vfmadd.f6438;39; Heuristically handled:40; - llvm.fma.f32, llvm.fma.f6441; - llvm.sqrt.v16f32, llvm.sqrt.v8f6442; - llvm.x86.avx512.permvar.di.512, llvm.x86.avx512.permvar.si.51243 44target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"45target triple = "x86_64-unknown-linux-gnu"46 47define <8 x double> @test_mask_compress_pd_512(<8 x double> %data, <8 x double> %passthru, i8 %mask) #0 {48; CHECK-LABEL: @test_mask_compress_pd_512(49; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 850; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 851; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 852; CHECK-NEXT: call void @llvm.donothing()53; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8 [[TMP1]] to <8 x i1>54; CHECK-NEXT: [[TMP5:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>55; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i64> [[TMP2]] to i51256; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP6]], 057; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i64> [[TMP3]] to i51258; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP7]], 059; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]60; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i1> [[TMP4]] to i861; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP8]], 062; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]63; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP9:%.*]], label [[TMP10:%.*]], !prof [[PROF1:![0-9]+]]64; CHECK: 9:65; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10:[0-9]+]]66; CHECK-NEXT: unreachable67; CHECK: 10:68; CHECK-NEXT: [[TMP11:%.*]] = call <8 x double> @llvm.x86.avx512.mask.compress.v8f64(<8 x double> [[DATA:%.*]], <8 x double> [[PASSTHRU:%.*]], <8 x i1> [[TMP5]])69; CHECK-NEXT: store <8 x i64> zeroinitializer, ptr @__msan_retval_tls, align 870; CHECK-NEXT: ret <8 x double> [[TMP11]]71;72 %1 = bitcast i8 %mask to <8 x i1>73 %2 = call <8 x double> @llvm.x86.avx512.mask.compress.v8f64(<8 x double> %data, <8 x double> %passthru, <8 x i1> %1)74 ret <8 x double> %275}76 77define <8 x double> @test_maskz_compress_pd_512(<8 x double> %data, i8 %mask) #0 {78; CHECK-LABEL: @test_maskz_compress_pd_512(79; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 880; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 881; CHECK-NEXT: call void @llvm.donothing()82; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8 [[TMP1]] to <8 x i1>83; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>84; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i64> [[TMP2]] to i51285; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP5]], 086; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i1> [[TMP3]] to i887; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i8 [[TMP6]], 088; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]89; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]90; CHECK: 7:91; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]92; CHECK-NEXT: unreachable93; CHECK: 8:94; CHECK-NEXT: [[TMP9:%.*]] = call <8 x double> @llvm.x86.avx512.mask.compress.v8f64(<8 x double> [[DATA:%.*]], <8 x double> zeroinitializer, <8 x i1> [[TMP4]])95; CHECK-NEXT: store <8 x i64> zeroinitializer, ptr @__msan_retval_tls, align 896; CHECK-NEXT: ret <8 x double> [[TMP9]]97;98 %1 = bitcast i8 %mask to <8 x i1>99 %2 = call <8 x double> @llvm.x86.avx512.mask.compress.v8f64(<8 x double> %data, <8 x double> zeroinitializer, <8 x i1> %1)100 ret <8 x double> %2101}102 103define <8 x double> @test_compress_pd_512(<8 x double> %data, <8 x double> %extra_param) #0 {104; CHECK-LABEL: @test_compress_pd_512(105; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 8106; CHECK-NEXT: [[TMP7:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 8107; CHECK-NEXT: call void @llvm.donothing()108; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i64> [[TMP1]] to i512109; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP3]], 0110; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i64> [[TMP7]] to i512111; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 0112; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]113; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]114; CHECK: 5:115; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]116; CHECK-NEXT: unreachable117; CHECK: 6:118; CHECK-NEXT: [[TMP2:%.*]] = call <8 x double> @llvm.x86.avx512.mask.compress.v8f64(<8 x double> [[DATA:%.*]], <8 x double> [[EXTRA_PARAM:%.*]], <8 x i1> splat (i1 true))119; CHECK-NEXT: store <8 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8120; CHECK-NEXT: ret <8 x double> [[TMP2]]121;122 %1 = call <8 x double> @llvm.x86.avx512.mask.compress.v8f64(<8 x double> %data, <8 x double> %extra_param, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)123 ret <8 x double> %1124}125 126define <16 x float> @test_mask_compress_ps_512(<16 x float> %data, <16 x float> %passthru, i16 %mask) #0 {127; CHECK-LABEL: @test_mask_compress_ps_512(128; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 8129; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 8130; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 8131; CHECK-NEXT: call void @llvm.donothing()132; CHECK-NEXT: [[TMP4:%.*]] = bitcast i16 [[TMP1]] to <16 x i1>133; CHECK-NEXT: [[TMP5:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>134; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i32> [[TMP2]] to i512135; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP6]], 0136; CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i32> [[TMP3]] to i512137; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP7]], 0138; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]139; CHECK-NEXT: [[TMP8:%.*]] = bitcast <16 x i1> [[TMP4]] to i16140; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i16 [[TMP8]], 0141; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]142; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP9:%.*]], label [[TMP10:%.*]], !prof [[PROF1]]143; CHECK: 9:144; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]145; CHECK-NEXT: unreachable146; CHECK: 10:147; CHECK-NEXT: [[TMP11:%.*]] = call <16 x float> @llvm.x86.avx512.mask.compress.v16f32(<16 x float> [[DATA:%.*]], <16 x float> [[PASSTHRU:%.*]], <16 x i1> [[TMP5]])148; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8149; CHECK-NEXT: ret <16 x float> [[TMP11]]150;151 %1 = bitcast i16 %mask to <16 x i1>152 %2 = call <16 x float> @llvm.x86.avx512.mask.compress.v16f32(<16 x float> %data, <16 x float> %passthru, <16 x i1> %1)153 ret <16 x float> %2154}155 156define <16 x float> @test_maskz_compress_ps_512(<16 x float> %data, i16 %mask) #0 {157; CHECK-LABEL: @test_maskz_compress_ps_512(158; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 8159; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 8160; CHECK-NEXT: call void @llvm.donothing()161; CHECK-NEXT: [[TMP3:%.*]] = bitcast i16 [[TMP1]] to <16 x i1>162; CHECK-NEXT: [[TMP4:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>163; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP2]] to i512164; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP5]], 0165; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i1> [[TMP3]] to i16166; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i16 [[TMP6]], 0167; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]168; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]169; CHECK: 7:170; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]171; CHECK-NEXT: unreachable172; CHECK: 8:173; CHECK-NEXT: [[TMP9:%.*]] = call <16 x float> @llvm.x86.avx512.mask.compress.v16f32(<16 x float> [[DATA:%.*]], <16 x float> zeroinitializer, <16 x i1> [[TMP4]])174; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8175; CHECK-NEXT: ret <16 x float> [[TMP9]]176;177 %1 = bitcast i16 %mask to <16 x i1>178 %2 = call <16 x float> @llvm.x86.avx512.mask.compress.v16f32(<16 x float> %data, <16 x float> zeroinitializer, <16 x i1> %1)179 ret <16 x float> %2180}181 182define <16 x float> @test_compress_ps_512(<16 x float> %data, <16 x float> %extra_param) #0 {183; CHECK-LABEL: @test_compress_ps_512(184; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 8185; CHECK-NEXT: [[TMP7:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 8186; CHECK-NEXT: call void @llvm.donothing()187; CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i32> [[TMP1]] to i512188; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP3]], 0189; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP7]] to i512190; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 0191; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]192; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]193; CHECK: 5:194; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]195; CHECK-NEXT: unreachable196; CHECK: 6:197; CHECK-NEXT: [[TMP2:%.*]] = call <16 x float> @llvm.x86.avx512.mask.compress.v16f32(<16 x float> [[DATA:%.*]], <16 x float> [[EXTRA_PARAM:%.*]], <16 x i1> splat (i1 true))198; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8199; CHECK-NEXT: ret <16 x float> [[TMP2]]200;201 %1 = call <16 x float> @llvm.x86.avx512.mask.compress.v16f32(<16 x float> %data, <16 x float> %extra_param, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)202 ret <16 x float> %1203}204 205define <8 x i64> @test_mask_compress_q_512(<8 x i64> %data, <8 x i64> %passthru, i8 %mask) #0 {206; CHECK-LABEL: @test_mask_compress_q_512(207; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 8208; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 8209; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 8210; CHECK-NEXT: call void @llvm.donothing()211; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8 [[TMP1]] to <8 x i1>212; CHECK-NEXT: [[TMP5:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>213; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i64> [[TMP2]] to i512214; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP6]], 0215; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i64> [[TMP3]] to i512216; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP7]], 0217; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]218; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i1> [[TMP4]] to i8219; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP8]], 0220; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]221; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP9:%.*]], label [[TMP10:%.*]], !prof [[PROF1]]222; CHECK: 9:223; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]224; CHECK-NEXT: unreachable225; CHECK: 10:226; CHECK-NEXT: [[TMP11:%.*]] = call <8 x i64> @llvm.x86.avx512.mask.compress.v8i64(<8 x i64> [[DATA:%.*]], <8 x i64> [[PASSTHRU:%.*]], <8 x i1> [[TMP5]])227; CHECK-NEXT: store <8 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8228; CHECK-NEXT: ret <8 x i64> [[TMP11]]229;230 %1 = bitcast i8 %mask to <8 x i1>231 %2 = call <8 x i64> @llvm.x86.avx512.mask.compress.v8i64(<8 x i64> %data, <8 x i64> %passthru, <8 x i1> %1)232 ret <8 x i64> %2233}234 235define <8 x i64> @test_maskz_compress_q_512(<8 x i64> %data, i8 %mask) #0 {236; CHECK-LABEL: @test_maskz_compress_q_512(237; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 8238; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 8239; CHECK-NEXT: call void @llvm.donothing()240; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8 [[TMP1]] to <8 x i1>241; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>242; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i64> [[TMP2]] to i512243; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP5]], 0244; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i1> [[TMP3]] to i8245; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i8 [[TMP6]], 0246; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]247; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]248; CHECK: 7:249; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]250; CHECK-NEXT: unreachable251; CHECK: 8:252; CHECK-NEXT: [[TMP9:%.*]] = call <8 x i64> @llvm.x86.avx512.mask.compress.v8i64(<8 x i64> [[DATA:%.*]], <8 x i64> zeroinitializer, <8 x i1> [[TMP4]])253; CHECK-NEXT: store <8 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8254; CHECK-NEXT: ret <8 x i64> [[TMP9]]255;256 %1 = bitcast i8 %mask to <8 x i1>257 %2 = call <8 x i64> @llvm.x86.avx512.mask.compress.v8i64(<8 x i64> %data, <8 x i64> zeroinitializer, <8 x i1> %1)258 ret <8 x i64> %2259}260 261define <8 x i64> @test_compress_q_512(<8 x i64> %data, <8 x i64> %extra_param) #0 {262; CHECK-LABEL: @test_compress_q_512(263; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 8264; CHECK-NEXT: [[TMP7:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 8265; CHECK-NEXT: call void @llvm.donothing()266; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i64> [[TMP1]] to i512267; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP3]], 0268; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i64> [[TMP7]] to i512269; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 0270; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]271; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]272; CHECK: 5:273; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]274; CHECK-NEXT: unreachable275; CHECK: 6:276; CHECK-NEXT: [[TMP2:%.*]] = call <8 x i64> @llvm.x86.avx512.mask.compress.v8i64(<8 x i64> [[DATA:%.*]], <8 x i64> [[EXTRA_PARAM:%.*]], <8 x i1> splat (i1 true))277; CHECK-NEXT: store <8 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8278; CHECK-NEXT: ret <8 x i64> [[TMP2]]279;280 %1 = call <8 x i64> @llvm.x86.avx512.mask.compress.v8i64(<8 x i64> %data, <8 x i64> %extra_param, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)281 ret <8 x i64> %1282}283 284define <16 x i32> @test_mask_compress_d_512(<16 x i32> %data, <16 x i32> %passthru, i16 %mask) #0 {285; CHECK-LABEL: @test_mask_compress_d_512(286; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 8287; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 8288; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 8289; CHECK-NEXT: call void @llvm.donothing()290; CHECK-NEXT: [[TMP4:%.*]] = bitcast i16 [[TMP1]] to <16 x i1>291; CHECK-NEXT: [[TMP5:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>292; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i32> [[TMP2]] to i512293; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP6]], 0294; CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i32> [[TMP3]] to i512295; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP7]], 0296; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]297; CHECK-NEXT: [[TMP8:%.*]] = bitcast <16 x i1> [[TMP4]] to i16298; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i16 [[TMP8]], 0299; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]300; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP9:%.*]], label [[TMP10:%.*]], !prof [[PROF1]]301; CHECK: 9:302; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]303; CHECK-NEXT: unreachable304; CHECK: 10:305; CHECK-NEXT: [[TMP11:%.*]] = call <16 x i32> @llvm.x86.avx512.mask.compress.v16i32(<16 x i32> [[DATA:%.*]], <16 x i32> [[PASSTHRU:%.*]], <16 x i1> [[TMP5]])306; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8307; CHECK-NEXT: ret <16 x i32> [[TMP11]]308;309 %1 = bitcast i16 %mask to <16 x i1>310 %2 = call <16 x i32> @llvm.x86.avx512.mask.compress.v16i32(<16 x i32> %data, <16 x i32> %passthru, <16 x i1> %1)311 ret <16 x i32> %2312}313 314define <16 x i32> @test_maskz_compress_d_512(<16 x i32> %data, i16 %mask) #0 {315; CHECK-LABEL: @test_maskz_compress_d_512(316; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 8317; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 8318; CHECK-NEXT: call void @llvm.donothing()319; CHECK-NEXT: [[TMP3:%.*]] = bitcast i16 [[TMP1]] to <16 x i1>320; CHECK-NEXT: [[TMP4:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>321; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP2]] to i512322; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP5]], 0323; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i1> [[TMP3]] to i16324; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i16 [[TMP6]], 0325; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]326; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]327; CHECK: 7:328; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]329; CHECK-NEXT: unreachable330; CHECK: 8:331; CHECK-NEXT: [[TMP9:%.*]] = call <16 x i32> @llvm.x86.avx512.mask.compress.v16i32(<16 x i32> [[DATA:%.*]], <16 x i32> zeroinitializer, <16 x i1> [[TMP4]])332; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8333; CHECK-NEXT: ret <16 x i32> [[TMP9]]334;335 %1 = bitcast i16 %mask to <16 x i1>336 %2 = call <16 x i32> @llvm.x86.avx512.mask.compress.v16i32(<16 x i32> %data, <16 x i32> zeroinitializer, <16 x i1> %1)337 ret <16 x i32> %2338}339 340define <16 x i32> @test_compress_d_512(<16 x i32> %data, <16 x i32> %extra_param) #0 {341; CHECK-LABEL: @test_compress_d_512(342; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 8343; CHECK-NEXT: [[TMP7:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 8344; CHECK-NEXT: call void @llvm.donothing()345; CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i32> [[TMP1]] to i512346; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP3]], 0347; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP7]] to i512348; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 0349; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]350; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]351; CHECK: 5:352; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]353; CHECK-NEXT: unreachable354; CHECK: 6:355; CHECK-NEXT: [[TMP2:%.*]] = call <16 x i32> @llvm.x86.avx512.mask.compress.v16i32(<16 x i32> [[DATA:%.*]], <16 x i32> [[EXTRA_PARAM:%.*]], <16 x i1> splat (i1 true))356; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8357; CHECK-NEXT: ret <16 x i32> [[TMP2]]358;359 %1 = call <16 x i32> @llvm.x86.avx512.mask.compress.v16i32(<16 x i32> %data, <16 x i32> %extra_param, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)360 ret <16 x i32> %1361}362 363define <8 x double> @test_expand_pd_512(<8 x double> %data, <8 x double> %extra_param) #0 {364; CHECK-LABEL: @test_expand_pd_512(365; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 8366; CHECK-NEXT: [[TMP7:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 8367; CHECK-NEXT: call void @llvm.donothing()368; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i64> [[TMP1]] to i512369; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP3]], 0370; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i64> [[TMP7]] to i512371; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 0372; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]373; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]374; CHECK: 5:375; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]376; CHECK-NEXT: unreachable377; CHECK: 6:378; CHECK-NEXT: [[TMP2:%.*]] = call <8 x double> @llvm.x86.avx512.mask.expand.v8f64(<8 x double> [[DATA:%.*]], <8 x double> [[EXTRA_PARAM:%.*]], <8 x i1> splat (i1 true))379; CHECK-NEXT: store <8 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8380; CHECK-NEXT: ret <8 x double> [[TMP2]]381;382 %1 = call <8 x double> @llvm.x86.avx512.mask.expand.v8f64(<8 x double> %data, <8 x double> %extra_param, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)383 ret <8 x double> %1384}385 386define <8 x double> @test_mask_expand_pd_512(<8 x double> %data, <8 x double> %passthru, i8 %mask) #0 {387; CHECK-LABEL: @test_mask_expand_pd_512(388; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 8389; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 8390; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 8391; CHECK-NEXT: call void @llvm.donothing()392; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8 [[TMP1]] to <8 x i1>393; CHECK-NEXT: [[TMP5:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>394; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i64> [[TMP2]] to i512395; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP6]], 0396; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i64> [[TMP3]] to i512397; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP7]], 0398; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]399; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i1> [[TMP4]] to i8400; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP8]], 0401; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]402; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP9:%.*]], label [[TMP10:%.*]], !prof [[PROF1]]403; CHECK: 9:404; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]405; CHECK-NEXT: unreachable406; CHECK: 10:407; CHECK-NEXT: [[TMP11:%.*]] = call <8 x double> @llvm.x86.avx512.mask.expand.v8f64(<8 x double> [[DATA:%.*]], <8 x double> [[PASSTHRU:%.*]], <8 x i1> [[TMP5]])408; CHECK-NEXT: store <8 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8409; CHECK-NEXT: ret <8 x double> [[TMP11]]410;411 %1 = bitcast i8 %mask to <8 x i1>412 %2 = call <8 x double> @llvm.x86.avx512.mask.expand.v8f64(<8 x double> %data, <8 x double> %passthru, <8 x i1> %1)413 ret <8 x double> %2414}415 416define <8 x double> @test_maskz_expand_pd_512(<8 x double> %data, i8 %mask) #0 {417; CHECK-LABEL: @test_maskz_expand_pd_512(418; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 8419; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 8420; CHECK-NEXT: call void @llvm.donothing()421; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8 [[TMP1]] to <8 x i1>422; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>423; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i64> [[TMP2]] to i512424; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP5]], 0425; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i1> [[TMP3]] to i8426; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i8 [[TMP6]], 0427; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]428; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]429; CHECK: 7:430; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]431; CHECK-NEXT: unreachable432; CHECK: 8:433; CHECK-NEXT: [[TMP9:%.*]] = call <8 x double> @llvm.x86.avx512.mask.expand.v8f64(<8 x double> [[DATA:%.*]], <8 x double> zeroinitializer, <8 x i1> [[TMP4]])434; CHECK-NEXT: store <8 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8435; CHECK-NEXT: ret <8 x double> [[TMP9]]436;437 %1 = bitcast i8 %mask to <8 x i1>438 %2 = call <8 x double> @llvm.x86.avx512.mask.expand.v8f64(<8 x double> %data, <8 x double> zeroinitializer, <8 x i1> %1)439 ret <8 x double> %2440}441 442define <16 x float> @test_expand_ps_512(<16 x float> %data, <16 x float> %extra_param) #0 {443; CHECK-LABEL: @test_expand_ps_512(444; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 8445; CHECK-NEXT: [[TMP7:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 8446; CHECK-NEXT: call void @llvm.donothing()447; CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i32> [[TMP1]] to i512448; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP3]], 0449; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP7]] to i512450; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 0451; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]452; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]453; CHECK: 5:454; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]455; CHECK-NEXT: unreachable456; CHECK: 6:457; CHECK-NEXT: [[TMP2:%.*]] = call <16 x float> @llvm.x86.avx512.mask.expand.v16f32(<16 x float> [[DATA:%.*]], <16 x float> [[EXTRA_PARAM:%.*]], <16 x i1> splat (i1 true))458; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8459; CHECK-NEXT: ret <16 x float> [[TMP2]]460;461 %1 = call <16 x float> @llvm.x86.avx512.mask.expand.v16f32(<16 x float> %data, <16 x float> %extra_param, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)462 ret <16 x float> %1463}464 465define <16 x float> @test_mask_expand_ps_512(<16 x float> %data, <16 x float> %passthru, i16 %mask) #0 {466; CHECK-LABEL: @test_mask_expand_ps_512(467; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 8468; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 8469; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 8470; CHECK-NEXT: call void @llvm.donothing()471; CHECK-NEXT: [[TMP4:%.*]] = bitcast i16 [[TMP1]] to <16 x i1>472; CHECK-NEXT: [[TMP5:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>473; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i32> [[TMP2]] to i512474; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP6]], 0475; CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i32> [[TMP3]] to i512476; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP7]], 0477; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]478; CHECK-NEXT: [[TMP8:%.*]] = bitcast <16 x i1> [[TMP4]] to i16479; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i16 [[TMP8]], 0480; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]481; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP9:%.*]], label [[TMP10:%.*]], !prof [[PROF1]]482; CHECK: 9:483; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]484; CHECK-NEXT: unreachable485; CHECK: 10:486; CHECK-NEXT: [[TMP11:%.*]] = call <16 x float> @llvm.x86.avx512.mask.expand.v16f32(<16 x float> [[DATA:%.*]], <16 x float> [[PASSTHRU:%.*]], <16 x i1> [[TMP5]])487; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8488; CHECK-NEXT: ret <16 x float> [[TMP11]]489;490 %1 = bitcast i16 %mask to <16 x i1>491 %2 = call <16 x float> @llvm.x86.avx512.mask.expand.v16f32(<16 x float> %data, <16 x float> %passthru, <16 x i1> %1)492 ret <16 x float> %2493}494 495define <16 x float> @test_maskz_expand_ps_512(<16 x float> %data, i16 %mask) #0 {496; CHECK-LABEL: @test_maskz_expand_ps_512(497; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 8498; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 8499; CHECK-NEXT: call void @llvm.donothing()500; CHECK-NEXT: [[TMP3:%.*]] = bitcast i16 [[TMP1]] to <16 x i1>501; CHECK-NEXT: [[TMP4:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>502; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP2]] to i512503; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP5]], 0504; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i1> [[TMP3]] to i16505; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i16 [[TMP6]], 0506; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]507; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]508; CHECK: 7:509; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]510; CHECK-NEXT: unreachable511; CHECK: 8:512; CHECK-NEXT: [[TMP9:%.*]] = call <16 x float> @llvm.x86.avx512.mask.expand.v16f32(<16 x float> [[DATA:%.*]], <16 x float> zeroinitializer, <16 x i1> [[TMP4]])513; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8514; CHECK-NEXT: ret <16 x float> [[TMP9]]515;516 %1 = bitcast i16 %mask to <16 x i1>517 %2 = call <16 x float> @llvm.x86.avx512.mask.expand.v16f32(<16 x float> %data, <16 x float> zeroinitializer, <16 x i1> %1)518 ret <16 x float> %2519}520 521define <8 x i64> @test_expand_q_512(<8 x i64> %data, <8 x i64> %extra_param) #0 {522; CHECK-LABEL: @test_expand_q_512(523; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 8524; CHECK-NEXT: [[TMP7:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 8525; CHECK-NEXT: call void @llvm.donothing()526; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i64> [[TMP1]] to i512527; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP3]], 0528; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i64> [[TMP7]] to i512529; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 0530; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]531; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]532; CHECK: 5:533; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]534; CHECK-NEXT: unreachable535; CHECK: 6:536; CHECK-NEXT: [[TMP2:%.*]] = call <8 x i64> @llvm.x86.avx512.mask.expand.v8i64(<8 x i64> [[DATA:%.*]], <8 x i64> [[EXTRA_PARAM:%.*]], <8 x i1> splat (i1 true))537; CHECK-NEXT: store <8 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8538; CHECK-NEXT: ret <8 x i64> [[TMP2]]539;540 %1 = call <8 x i64> @llvm.x86.avx512.mask.expand.v8i64(<8 x i64> %data, <8 x i64> %extra_param, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)541 ret <8 x i64> %1542}543 544define <8 x i64> @test_mask_expand_q_512(<8 x i64> %data, <8 x i64> %passthru, i8 %mask) #0 {545; CHECK-LABEL: @test_mask_expand_q_512(546; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 8547; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 8548; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 8549; CHECK-NEXT: call void @llvm.donothing()550; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8 [[TMP1]] to <8 x i1>551; CHECK-NEXT: [[TMP5:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>552; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i64> [[TMP2]] to i512553; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP6]], 0554; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i64> [[TMP3]] to i512555; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP7]], 0556; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]557; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i1> [[TMP4]] to i8558; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP8]], 0559; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]560; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP9:%.*]], label [[TMP10:%.*]], !prof [[PROF1]]561; CHECK: 9:562; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]563; CHECK-NEXT: unreachable564; CHECK: 10:565; CHECK-NEXT: [[TMP11:%.*]] = call <8 x i64> @llvm.x86.avx512.mask.expand.v8i64(<8 x i64> [[DATA:%.*]], <8 x i64> [[PASSTHRU:%.*]], <8 x i1> [[TMP5]])566; CHECK-NEXT: store <8 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8567; CHECK-NEXT: ret <8 x i64> [[TMP11]]568;569 %1 = bitcast i8 %mask to <8 x i1>570 %2 = call <8 x i64> @llvm.x86.avx512.mask.expand.v8i64(<8 x i64> %data, <8 x i64> %passthru, <8 x i1> %1)571 ret <8 x i64> %2572}573 574define <8 x i64> @test_maskz_expand_q_512(<8 x i64> %data, i8 %mask) #0 {575; CHECK-LABEL: @test_maskz_expand_q_512(576; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 8577; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 8578; CHECK-NEXT: call void @llvm.donothing()579; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8 [[TMP1]] to <8 x i1>580; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>581; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i64> [[TMP2]] to i512582; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP5]], 0583; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i1> [[TMP3]] to i8584; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i8 [[TMP6]], 0585; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]586; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]587; CHECK: 7:588; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]589; CHECK-NEXT: unreachable590; CHECK: 8:591; CHECK-NEXT: [[TMP9:%.*]] = call <8 x i64> @llvm.x86.avx512.mask.expand.v8i64(<8 x i64> [[DATA:%.*]], <8 x i64> zeroinitializer, <8 x i1> [[TMP4]])592; CHECK-NEXT: store <8 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8593; CHECK-NEXT: ret <8 x i64> [[TMP9]]594;595 %1 = bitcast i8 %mask to <8 x i1>596 %2 = call <8 x i64> @llvm.x86.avx512.mask.expand.v8i64(<8 x i64> %data, <8 x i64> zeroinitializer, <8 x i1> %1)597 ret <8 x i64> %2598}599 600define <16 x i32> @test_expand_d_512(<16 x i32> %data, <16 x i32> %extra_param) #0 {601; CHECK-LABEL: @test_expand_d_512(602; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 8603; CHECK-NEXT: [[TMP7:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 8604; CHECK-NEXT: call void @llvm.donothing()605; CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i32> [[TMP1]] to i512606; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP3]], 0607; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP7]] to i512608; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 0609; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]610; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]611; CHECK: 5:612; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]613; CHECK-NEXT: unreachable614; CHECK: 6:615; CHECK-NEXT: [[TMP2:%.*]] = call <16 x i32> @llvm.x86.avx512.mask.expand.v16i32(<16 x i32> [[DATA:%.*]], <16 x i32> [[EXTRA_PARAM:%.*]], <16 x i1> splat (i1 true))616; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8617; CHECK-NEXT: ret <16 x i32> [[TMP2]]618;619 %1 = call <16 x i32> @llvm.x86.avx512.mask.expand.v16i32(<16 x i32> %data, <16 x i32> %extra_param, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)620 ret <16 x i32> %1621}622 623define <16 x i32> @test_mask_expand_d_512(<16 x i32> %data, <16 x i32> %passthru, i16 %mask) #0 {624; CHECK-LABEL: @test_mask_expand_d_512(625; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 8626; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 8627; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 8628; CHECK-NEXT: call void @llvm.donothing()629; CHECK-NEXT: [[TMP4:%.*]] = bitcast i16 [[TMP1]] to <16 x i1>630; CHECK-NEXT: [[TMP5:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>631; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i32> [[TMP2]] to i512632; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP6]], 0633; CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i32> [[TMP3]] to i512634; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP7]], 0635; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]636; CHECK-NEXT: [[TMP8:%.*]] = bitcast <16 x i1> [[TMP4]] to i16637; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i16 [[TMP8]], 0638; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]639; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP9:%.*]], label [[TMP10:%.*]], !prof [[PROF1]]640; CHECK: 9:641; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]642; CHECK-NEXT: unreachable643; CHECK: 10:644; CHECK-NEXT: [[TMP11:%.*]] = call <16 x i32> @llvm.x86.avx512.mask.expand.v16i32(<16 x i32> [[DATA:%.*]], <16 x i32> [[PASSTHRU:%.*]], <16 x i1> [[TMP5]])645; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8646; CHECK-NEXT: ret <16 x i32> [[TMP11]]647;648 %1 = bitcast i16 %mask to <16 x i1>649 %2 = call <16 x i32> @llvm.x86.avx512.mask.expand.v16i32(<16 x i32> %data, <16 x i32> %passthru, <16 x i1> %1)650 ret <16 x i32> %2651}652 653define <16 x i32> @test_maskz_expand_d_512(<16 x i32> %data, i16 %mask) #0 {654; CHECK-LABEL: @test_maskz_expand_d_512(655; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 8656; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 8657; CHECK-NEXT: call void @llvm.donothing()658; CHECK-NEXT: [[TMP3:%.*]] = bitcast i16 [[TMP1]] to <16 x i1>659; CHECK-NEXT: [[TMP4:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>660; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP2]] to i512661; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP5]], 0662; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i1> [[TMP3]] to i16663; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i16 [[TMP6]], 0664; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]665; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]666; CHECK: 7:667; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]668; CHECK-NEXT: unreachable669; CHECK: 8:670; CHECK-NEXT: [[TMP9:%.*]] = call <16 x i32> @llvm.x86.avx512.mask.expand.v16i32(<16 x i32> [[DATA:%.*]], <16 x i32> zeroinitializer, <16 x i1> [[TMP4]])671; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8672; CHECK-NEXT: ret <16 x i32> [[TMP9]]673;674 %1 = bitcast i16 %mask to <16 x i1>675 %2 = call <16 x i32> @llvm.x86.avx512.mask.expand.v16i32(<16 x i32> %data, <16 x i32> zeroinitializer, <16 x i1> %1)676 ret <16 x i32> %2677}678 679define <16 x float> @test_rcp_ps_512(<16 x float> %a0) #0 {680; CHECK-LABEL: @test_rcp_ps_512(681; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 8682; CHECK-NEXT: call void @llvm.donothing()683; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <16 x i32> [[TMP1]], zeroinitializer684; CHECK-NEXT: [[TMP3:%.*]] = sext <16 x i1> [[TMP2]] to <16 x i32>685; CHECK-NEXT: [[TMP4:%.*]] = select <16 x i1> splat (i1 true), <16 x i32> [[TMP3]], <16 x i32> zeroinitializer686; CHECK-NEXT: [[RES:%.*]] = call <16 x float> @llvm.x86.avx512.rcp14.ps.512(<16 x float> [[A0:%.*]], <16 x float> zeroinitializer, i16 -1)687; CHECK-NEXT: store <16 x i32> [[TMP4]], ptr @__msan_retval_tls, align 8688; CHECK-NEXT: ret <16 x float> [[RES]]689;690 %res = call <16 x float> @llvm.x86.avx512.rcp14.ps.512(<16 x float> %a0, <16 x float> zeroinitializer, i16 -1) ; <<16 x float>> [#uses=1]691 ret <16 x float> %res692}693declare <16 x float> @llvm.x86.avx512.rcp14.ps.512(<16 x float>, <16 x float>, i16) nounwind readnone694 695define <8 x double> @test_rcp_pd_512(<8 x double> %a0) #0 {696; CHECK-LABEL: @test_rcp_pd_512(697; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 8698; CHECK-NEXT: call void @llvm.donothing()699; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <8 x i64> [[TMP1]], zeroinitializer700; CHECK-NEXT: [[TMP3:%.*]] = sext <8 x i1> [[TMP2]] to <8 x i64>701; CHECK-NEXT: [[TMP4:%.*]] = select <8 x i1> splat (i1 true), <8 x i64> [[TMP3]], <8 x i64> zeroinitializer702; CHECK-NEXT: [[RES:%.*]] = call <8 x double> @llvm.x86.avx512.rcp14.pd.512(<8 x double> [[A0:%.*]], <8 x double> zeroinitializer, i8 -1)703; CHECK-NEXT: store <8 x i64> [[TMP4]], ptr @__msan_retval_tls, align 8704; CHECK-NEXT: ret <8 x double> [[RES]]705;706 %res = call <8 x double> @llvm.x86.avx512.rcp14.pd.512(<8 x double> %a0, <8 x double> zeroinitializer, i8 -1) ; <<8 x double>> [#uses=1]707 ret <8 x double> %res708}709declare <8 x double> @llvm.x86.avx512.rcp14.pd.512(<8 x double>, <8 x double>, i8) nounwind readnone710 711declare <2 x double> @llvm.x86.avx512.mask.rndscale.sd(<2 x double>, <2 x double>, <2 x double>, i8, i32, i32)712 713define <2 x double> @test_rndscale_sd(<2 x double> %a, <2 x double> %b, <2 x double> %extra_param) #0 {714; CHECK-LABEL: @test_rndscale_sd(715; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8716; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8717; CHECK-NEXT: [[TMP5:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8718; CHECK-NEXT: call void @llvm.donothing()719; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP1]] to i128720; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 0721; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP2]] to i128722; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 0723; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]724; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i64> [[TMP5]] to i128725; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP6]], 0726; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]727; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]728; CHECK: 7:729; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]730; CHECK-NEXT: unreachable731; CHECK: 8:732; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx512.mask.rndscale.sd(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> [[EXTRA_PARAM:%.*]], i8 -1, i32 11, i32 4)733; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8734; CHECK-NEXT: ret <2 x double> [[RES]]735;736 %res = call <2 x double> @llvm.x86.avx512.mask.rndscale.sd(<2 x double> %a, <2 x double> %b, <2 x double> %extra_param, i8 -1, i32 11, i32 4)737 ret <2 x double>%res738}739 740define <2 x double> @test_rndscale_sd_mask(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) #0 {741; CHECK-LABEL: @test_rndscale_sd_mask(742; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8743; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8744; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8745; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 8746; CHECK-NEXT: call void @llvm.donothing()747; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP1]] to i128748; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 0749; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i64> [[TMP2]] to i128750; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP6]], 0751; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]752; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i64> [[TMP3]] to i128753; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 0754; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]755; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 0756; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]757; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]758; CHECK: 8:759; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]760; CHECK-NEXT: unreachable761; CHECK: 9:762; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx512.mask.rndscale.sd(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> [[C:%.*]], i8 [[MASK:%.*]], i32 11, i32 4)763; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8764; CHECK-NEXT: ret <2 x double> [[RES]]765;766 %res = call <2 x double> @llvm.x86.avx512.mask.rndscale.sd(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask, i32 11, i32 4)767 ret <2 x double>%res768}769 770define <2 x double> @test_rndscale_sd_mask_load(<2 x double> %a, ptr %bptr, <2 x double> %c, i8 %mask) #0 {771; CHECK-LABEL: @test_rndscale_sd_mask_load(772; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8773; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8774; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 8775; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 8776; CHECK-NEXT: call void @llvm.donothing()777; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0778; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]779; CHECK: 5:780; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]781; CHECK-NEXT: unreachable782; CHECK: 6:783; CHECK-NEXT: [[B:%.*]] = load <2 x double>, ptr [[BPTR:%.*]], align 16784; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[BPTR]] to i64785; CHECK-NEXT: [[TMP8:%.*]] = xor i64 [[TMP7]], 87960930222080786; CHECK-NEXT: [[TMP9:%.*]] = inttoptr i64 [[TMP8]] to ptr787; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP9]], align 16788; CHECK-NEXT: [[TMP10:%.*]] = bitcast <2 x i64> [[TMP2]] to i128789; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP10]], 0790; CHECK-NEXT: [[TMP11:%.*]] = bitcast <2 x i64> [[_MSLD]] to i128791; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP11]], 0792; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP1]], [[_MSCMP2]]793; CHECK-NEXT: [[TMP12:%.*]] = bitcast <2 x i64> [[TMP3]] to i128794; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP12]], 0795; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSOR]], [[_MSCMP3]]796; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP4]], 0797; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]798; CHECK-NEXT: br i1 [[_MSOR6]], label [[TMP13:%.*]], label [[TMP14:%.*]], !prof [[PROF1]]799; CHECK: 13:800; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]801; CHECK-NEXT: unreachable802; CHECK: 14:803; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx512.mask.rndscale.sd(<2 x double> [[A:%.*]], <2 x double> [[B]], <2 x double> [[C:%.*]], i8 [[MASK:%.*]], i32 11, i32 4)804; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8805; CHECK-NEXT: ret <2 x double> [[RES]]806;807 %b = load <2 x double>, ptr %bptr808 %res = call <2 x double> @llvm.x86.avx512.mask.rndscale.sd(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask, i32 11, i32 4)809 ret <2 x double>%res810}811 812define <2 x double> @test_rndscale_sd_maskz(<2 x double> %a, <2 x double> %b, i8 %mask) #0 {813; CHECK-LABEL: @test_rndscale_sd_maskz(814; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8815; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8816; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8817; CHECK-NEXT: call void @llvm.donothing()818; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP1]] to i128819; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 0820; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP2]] to i128821; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 0822; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]823; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 0824; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]825; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]826; CHECK: 6:827; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]828; CHECK-NEXT: unreachable829; CHECK: 7:830; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx512.mask.rndscale.sd(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> zeroinitializer, i8 [[MASK:%.*]], i32 11, i32 4)831; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8832; CHECK-NEXT: ret <2 x double> [[RES]]833;834 %res = call <2 x double> @llvm.x86.avx512.mask.rndscale.sd(<2 x double> %a, <2 x double> %b, <2 x double> zeroinitializer, i8 %mask, i32 11, i32 4)835 ret <2 x double>%res836}837 838declare <4 x float> @llvm.x86.avx512.mask.rndscale.ss(<4 x float>, <4 x float>, <4 x float>, i8, i32, i32)839 840define <4 x float> @test_rndscale_ss(<4 x float> %a, <4 x float> %b, <4 x float> %extra_param) #0 {841; CHECK-LABEL: @test_rndscale_ss(842; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8843; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8844; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8845; CHECK-NEXT: call void @llvm.donothing()846; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP1]] to i128847; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 0848; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i128849; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 0850; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]851; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i32> [[TMP5]] to i128852; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP6]], 0853; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]854; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]855; CHECK: 7:856; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]857; CHECK-NEXT: unreachable858; CHECK: 8:859; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.mask.rndscale.ss(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> [[EXTRA_PARAM:%.*]], i8 -1, i32 11, i32 4)860; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8861; CHECK-NEXT: ret <4 x float> [[RES]]862;863 %res = call <4 x float> @llvm.x86.avx512.mask.rndscale.ss(<4 x float> %a, <4 x float> %b, <4 x float> %extra_param, i8 -1, i32 11, i32 4)864 ret <4 x float>%res865}866 867define <4 x float> @test_rndscale_ss_load(<4 x float> %a, ptr %bptr, <4 x float> %extra_param) #0 {868; CHECK-LABEL: @test_rndscale_ss_load(869; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8870; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8871; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 8872; CHECK-NEXT: call void @llvm.donothing()873; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0874; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP4:%.*]], label [[TMP10:%.*]], !prof [[PROF1]]875; CHECK: 4:876; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]877; CHECK-NEXT: unreachable878; CHECK: 5:879; CHECK-NEXT: [[B:%.*]] = load <4 x float>, ptr [[BPTR:%.*]], align 16880; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[BPTR]] to i64881; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 87960930222080882; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr883; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 16884; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x i32> [[TMP2]] to i128885; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP8]], 0886; CHECK-NEXT: [[TMP9:%.*]] = bitcast <4 x i32> [[_MSLD]] to i128887; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP9]], 0888; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP1]], [[_MSCMP2]]889; CHECK-NEXT: [[TMP11:%.*]] = bitcast <4 x i32> [[TMP3]] to i128890; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP11]], 0891; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSOR]], [[_MSCMP3]]892; CHECK-NEXT: br i1 [[_MSOR4]], label [[TMP12:%.*]], label [[TMP13:%.*]], !prof [[PROF1]]893; CHECK: 12:894; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]895; CHECK-NEXT: unreachable896; CHECK: 13:897; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.mask.rndscale.ss(<4 x float> [[A:%.*]], <4 x float> [[B]], <4 x float> [[EXTRA_PARAM:%.*]], i8 -1, i32 11, i32 4)898; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8899; CHECK-NEXT: ret <4 x float> [[RES]]900;901 %b = load <4 x float>, ptr %bptr902 %res = call <4 x float> @llvm.x86.avx512.mask.rndscale.ss(<4 x float> %a, <4 x float> %b, <4 x float> %extra_param, i8 -1, i32 11, i32 4)903 ret <4 x float>%res904}905 906define <4 x float> @test_rndscale_ss_mask(<4 x float> %a, <4 x float> %b, <4 x float> %c, i8 %mask) #0 {907; CHECK-LABEL: @test_rndscale_ss_mask(908; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8909; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8910; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8911; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 8912; CHECK-NEXT: call void @llvm.donothing()913; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP1]] to i128914; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 0915; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i32> [[TMP2]] to i128916; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP6]], 0917; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]918; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i32> [[TMP3]] to i128919; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 0920; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]921; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 0922; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]923; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]924; CHECK: 8:925; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]926; CHECK-NEXT: unreachable927; CHECK: 9:928; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.mask.rndscale.ss(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> [[C:%.*]], i8 [[MASK:%.*]], i32 11, i32 4)929; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8930; CHECK-NEXT: ret <4 x float> [[RES]]931;932 %res = call <4 x float> @llvm.x86.avx512.mask.rndscale.ss(<4 x float> %a, <4 x float> %b, <4 x float> %c, i8 %mask, i32 11, i32 4)933 ret <4 x float>%res934}935 936define <4 x float> @test_rndscale_ss_maskz(<4 x float> %a, <4 x float> %b, i8 %mask) #0 {937; CHECK-LABEL: @test_rndscale_ss_maskz(938; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8939; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8940; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8941; CHECK-NEXT: call void @llvm.donothing()942; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP1]] to i128943; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 0944; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP2]] to i128945; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 0946; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]947; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 0948; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]949; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]950; CHECK: 6:951; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]952; CHECK-NEXT: unreachable953; CHECK: 7:954; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.mask.rndscale.ss(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> zeroinitializer, i8 [[MASK:%.*]], i32 11, i32 4)955; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8956; CHECK-NEXT: ret <4 x float> [[RES]]957;958 %res = call <4 x float> @llvm.x86.avx512.mask.rndscale.ss(<4 x float> %a, <4 x float> %b, <4 x float> zeroinitializer, i8 %mask, i32 11, i32 4)959 ret <4 x float>%res960}961 962declare <8 x double> @llvm.x86.avx512.mask.rndscale.pd.512(<8 x double>, i32, <8 x double>, i8, i32)963 964define <8 x double> @test7(<8 x double> %a) #0 {965; CHECK-LABEL: @test7(966; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 8967; CHECK-NEXT: call void @llvm.donothing()968; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <8 x i64> [[TMP1]], zeroinitializer969; CHECK-NEXT: [[TMP3:%.*]] = sext <8 x i1> [[TMP2]] to <8 x i64>970; CHECK-NEXT: [[TMP4:%.*]] = select <8 x i1> splat (i1 true), <8 x i64> [[TMP3]], <8 x i64> [[TMP1]]971; CHECK-NEXT: [[RES:%.*]] = call <8 x double> @llvm.x86.avx512.mask.rndscale.pd.512(<8 x double> [[A:%.*]], i32 11, <8 x double> [[A]], i8 -1, i32 4)972; CHECK-NEXT: store <8 x i64> [[TMP4]], ptr @__msan_retval_tls, align 8973; CHECK-NEXT: ret <8 x double> [[RES]]974;975 %res = call <8 x double> @llvm.x86.avx512.mask.rndscale.pd.512(<8 x double> %a, i32 11, <8 x double> %a, i8 -1, i32 4)976 ret <8 x double>%res977}978 979declare <16 x float> @llvm.x86.avx512.mask.rndscale.ps.512(<16 x float>, i32, <16 x float>, i16, i32)980 981define <16 x float> @test8(<16 x float> %a) #0 {982; CHECK-LABEL: @test8(983; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 8984; CHECK-NEXT: call void @llvm.donothing()985; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <16 x i32> [[TMP1]], zeroinitializer986; CHECK-NEXT: [[TMP3:%.*]] = sext <16 x i1> [[TMP2]] to <16 x i32>987; CHECK-NEXT: [[TMP4:%.*]] = select <16 x i1> splat (i1 true), <16 x i32> [[TMP3]], <16 x i32> [[TMP1]]988; CHECK-NEXT: [[RES:%.*]] = call <16 x float> @llvm.x86.avx512.mask.rndscale.ps.512(<16 x float> [[A:%.*]], i32 11, <16 x float> [[A]], i16 -1, i32 4)989; CHECK-NEXT: store <16 x i32> [[TMP4]], ptr @__msan_retval_tls, align 8990; CHECK-NEXT: ret <16 x float> [[RES]]991;992 %res = call <16 x float> @llvm.x86.avx512.mask.rndscale.ps.512(<16 x float> %a, i32 11, <16 x float> %a, i16 -1, i32 4)993 ret <16 x float>%res994}995 996define <16 x float> @test_rsqrt_ps_512(<16 x float> %a0) #0 {997; CHECK-LABEL: @test_rsqrt_ps_512(998; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 8999; CHECK-NEXT: call void @llvm.donothing()1000; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <16 x i32> [[TMP1]], zeroinitializer1001; CHECK-NEXT: [[TMP3:%.*]] = sext <16 x i1> [[TMP2]] to <16 x i32>1002; CHECK-NEXT: [[TMP4:%.*]] = select <16 x i1> splat (i1 true), <16 x i32> [[TMP3]], <16 x i32> zeroinitializer1003; CHECK-NEXT: [[RES:%.*]] = call <16 x float> @llvm.x86.avx512.rsqrt14.ps.512(<16 x float> [[A0:%.*]], <16 x float> zeroinitializer, i16 -1)1004; CHECK-NEXT: store <16 x i32> [[TMP4]], ptr @__msan_retval_tls, align 81005; CHECK-NEXT: ret <16 x float> [[RES]]1006;1007 %res = call <16 x float> @llvm.x86.avx512.rsqrt14.ps.512(<16 x float> %a0, <16 x float> zeroinitializer, i16 -1) ; <<16 x float>> [#uses=1]1008 ret <16 x float> %res1009}1010declare <16 x float> @llvm.x86.avx512.rsqrt14.ps.512(<16 x float>, <16 x float>, i16) nounwind readnone1011 1012define <8 x double> @test_sqrt_pd_512(<8 x double> %a0) #0 {1013; CHECK-LABEL: @test_sqrt_pd_512(1014; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 81015; CHECK-NEXT: call void @llvm.donothing()1016; CHECK-NEXT: [[TMP2:%.*]] = call <8 x double> @llvm.sqrt.v8f64(<8 x double> [[A0:%.*]])1017; CHECK-NEXT: store <8 x i64> [[TMP1]], ptr @__msan_retval_tls, align 81018; CHECK-NEXT: ret <8 x double> [[TMP2]]1019;1020 %1 = call <8 x double> @llvm.sqrt.v8f64(<8 x double> %a0)1021 ret <8 x double> %11022}1023 1024define <8 x double> @test_mask_sqrt_pd_512(<8 x double> %a0, <8 x double> %passthru, i8 %mask) #0 {1025; CHECK-LABEL: @test_mask_sqrt_pd_512(1026; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 81027; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 81028; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 81029; CHECK-NEXT: call void @llvm.donothing()1030; CHECK-NEXT: [[TMP4:%.*]] = call <8 x double> @llvm.sqrt.v8f64(<8 x double> [[A0:%.*]])1031; CHECK-NEXT: [[TMP5:%.*]] = bitcast i8 [[TMP2]] to <8 x i1>1032; CHECK-NEXT: [[TMP6:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>1033; CHECK-NEXT: [[TMP7:%.*]] = select <8 x i1> [[TMP6]], <8 x i64> [[TMP1]], <8 x i64> [[TMP3]]1034; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x double> [[TMP4]] to <8 x i64>1035; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x double> [[PASSTHRU:%.*]] to <8 x i64>1036; CHECK-NEXT: [[TMP10:%.*]] = xor <8 x i64> [[TMP8]], [[TMP9]]1037; CHECK-NEXT: [[TMP11:%.*]] = or <8 x i64> [[TMP10]], [[TMP1]]1038; CHECK-NEXT: [[TMP12:%.*]] = or <8 x i64> [[TMP11]], [[TMP3]]1039; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP5]], <8 x i64> [[TMP12]], <8 x i64> [[TMP7]]1040; CHECK-NEXT: [[TMP13:%.*]] = select <8 x i1> [[TMP6]], <8 x double> [[TMP4]], <8 x double> [[PASSTHRU]]1041; CHECK-NEXT: store <8 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 81042; CHECK-NEXT: ret <8 x double> [[TMP13]]1043;1044 %1 = call <8 x double> @llvm.sqrt.v8f64(<8 x double> %a0)1045 %2 = bitcast i8 %mask to <8 x i1>1046 %3 = select <8 x i1> %2, <8 x double> %1, <8 x double> %passthru1047 ret <8 x double> %31048}1049 1050define <8 x double> @test_maskz_sqrt_pd_512(<8 x double> %a0, i8 %mask) #0 {1051; CHECK-LABEL: @test_maskz_sqrt_pd_512(1052; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 81053; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 81054; CHECK-NEXT: call void @llvm.donothing()1055; CHECK-NEXT: [[TMP3:%.*]] = call <8 x double> @llvm.sqrt.v8f64(<8 x double> [[A0:%.*]])1056; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8 [[TMP2]] to <8 x i1>1057; CHECK-NEXT: [[TMP5:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>1058; CHECK-NEXT: [[TMP6:%.*]] = select <8 x i1> [[TMP5]], <8 x i64> [[TMP1]], <8 x i64> zeroinitializer1059; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x double> [[TMP3]] to <8 x i64>1060; CHECK-NEXT: [[TMP8:%.*]] = xor <8 x i64> [[TMP7]], zeroinitializer1061; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i64> [[TMP8]], [[TMP1]]1062; CHECK-NEXT: [[TMP10:%.*]] = or <8 x i64> [[TMP9]], zeroinitializer1063; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP4]], <8 x i64> [[TMP10]], <8 x i64> [[TMP6]]1064; CHECK-NEXT: [[TMP11:%.*]] = select <8 x i1> [[TMP5]], <8 x double> [[TMP3]], <8 x double> zeroinitializer1065; CHECK-NEXT: store <8 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 81066; CHECK-NEXT: ret <8 x double> [[TMP11]]1067;1068 %1 = call <8 x double> @llvm.sqrt.v8f64(<8 x double> %a0)1069 %2 = bitcast i8 %mask to <8 x i1>1070 %3 = select <8 x i1> %2, <8 x double> %1, <8 x double> zeroinitializer1071 ret <8 x double> %31072}1073declare <8 x double> @llvm.sqrt.v8f64(<8 x double>)1074 1075define <8 x double> @test_sqrt_round_pd_512(<8 x double> %a0) #0 {1076; CHECK-LABEL: @test_sqrt_round_pd_512(1077; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 81078; CHECK-NEXT: call void @llvm.donothing()1079; CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i64> [[TMP1]] to i5121080; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP2]], 01081; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]1082; CHECK: 3:1083; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]1084; CHECK-NEXT: unreachable1085; CHECK: 4:1086; CHECK-NEXT: [[TMP5:%.*]] = call <8 x double> @llvm.x86.avx512.sqrt.pd.512(<8 x double> [[A0:%.*]], i32 11)1087; CHECK-NEXT: store <8 x i64> zeroinitializer, ptr @__msan_retval_tls, align 81088; CHECK-NEXT: ret <8 x double> [[TMP5]]1089;1090 %1 = call <8 x double> @llvm.x86.avx512.sqrt.pd.512(<8 x double> %a0, i32 11)1091 ret <8 x double> %11092}1093 1094define <8 x double> @test_mask_sqrt_round_pd_512(<8 x double> %a0, <8 x double> %passthru, i8 %mask) #0 {1095; CHECK-LABEL: @test_mask_sqrt_round_pd_512(1096; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 81097; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 81098; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 81099; CHECK-NEXT: call void @llvm.donothing()1100; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i64> [[TMP1]] to i5121101; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP4]], 01102; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]1103; CHECK: 5:1104; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]1105; CHECK-NEXT: unreachable1106; CHECK: 6:1107; CHECK-NEXT: [[TMP7:%.*]] = call <8 x double> @llvm.x86.avx512.sqrt.pd.512(<8 x double> [[A0:%.*]], i32 11)1108; CHECK-NEXT: [[TMP8:%.*]] = bitcast i8 [[TMP2]] to <8 x i1>1109; CHECK-NEXT: [[TMP9:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>1110; CHECK-NEXT: [[TMP10:%.*]] = select <8 x i1> [[TMP9]], <8 x i64> zeroinitializer, <8 x i64> [[TMP3]]1111; CHECK-NEXT: [[TMP11:%.*]] = bitcast <8 x double> [[TMP7]] to <8 x i64>1112; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x double> [[PASSTHRU:%.*]] to <8 x i64>1113; CHECK-NEXT: [[TMP13:%.*]] = xor <8 x i64> [[TMP11]], [[TMP12]]1114; CHECK-NEXT: [[TMP14:%.*]] = or <8 x i64> [[TMP13]], zeroinitializer1115; CHECK-NEXT: [[TMP15:%.*]] = or <8 x i64> [[TMP14]], [[TMP3]]1116; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP8]], <8 x i64> [[TMP15]], <8 x i64> [[TMP10]]1117; CHECK-NEXT: [[TMP16:%.*]] = select <8 x i1> [[TMP9]], <8 x double> [[TMP7]], <8 x double> [[PASSTHRU]]1118; CHECK-NEXT: store <8 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 81119; CHECK-NEXT: ret <8 x double> [[TMP16]]1120;1121 %1 = call <8 x double> @llvm.x86.avx512.sqrt.pd.512(<8 x double> %a0, i32 11)1122 %2 = bitcast i8 %mask to <8 x i1>1123 %3 = select <8 x i1> %2, <8 x double> %1, <8 x double> %passthru1124 ret <8 x double> %31125}1126 1127define <8 x double> @test_maskz_sqrt_round_pd_512(<8 x double> %a0, i8 %mask) #0 {1128; CHECK-LABEL: @test_maskz_sqrt_round_pd_512(1129; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 81130; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 81131; CHECK-NEXT: call void @llvm.donothing()1132; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i64> [[TMP1]] to i5121133; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP3]], 01134; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF1]]1135; CHECK: 4:1136; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]1137; CHECK-NEXT: unreachable1138; CHECK: 5:1139; CHECK-NEXT: [[TMP6:%.*]] = call <8 x double> @llvm.x86.avx512.sqrt.pd.512(<8 x double> [[A0:%.*]], i32 11)1140; CHECK-NEXT: [[TMP7:%.*]] = bitcast i8 [[TMP2]] to <8 x i1>1141; CHECK-NEXT: [[TMP8:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>1142; CHECK-NEXT: [[TMP9:%.*]] = select <8 x i1> [[TMP8]], <8 x i64> zeroinitializer, <8 x i64> zeroinitializer1143; CHECK-NEXT: [[TMP10:%.*]] = bitcast <8 x double> [[TMP6]] to <8 x i64>1144; CHECK-NEXT: [[TMP11:%.*]] = xor <8 x i64> [[TMP10]], zeroinitializer1145; CHECK-NEXT: [[TMP12:%.*]] = or <8 x i64> [[TMP11]], zeroinitializer1146; CHECK-NEXT: [[TMP13:%.*]] = or <8 x i64> [[TMP12]], zeroinitializer1147; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP7]], <8 x i64> [[TMP13]], <8 x i64> [[TMP9]]1148; CHECK-NEXT: [[TMP14:%.*]] = select <8 x i1> [[TMP8]], <8 x double> [[TMP6]], <8 x double> zeroinitializer1149; CHECK-NEXT: store <8 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 81150; CHECK-NEXT: ret <8 x double> [[TMP14]]1151;1152 %1 = call <8 x double> @llvm.x86.avx512.sqrt.pd.512(<8 x double> %a0, i32 11)1153 %2 = bitcast i8 %mask to <8 x i1>1154 %3 = select <8 x i1> %2, <8 x double> %1, <8 x double> zeroinitializer1155 ret <8 x double> %31156}1157declare <8 x double> @llvm.x86.avx512.sqrt.pd.512(<8 x double>, i32) nounwind readnone1158 1159define <16 x float> @test_sqrt_ps_512(<16 x float> %a0) #0 {1160; CHECK-LABEL: @test_sqrt_ps_512(1161; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 81162; CHECK-NEXT: call void @llvm.donothing()1163; CHECK-NEXT: [[TMP2:%.*]] = call <16 x float> @llvm.sqrt.v16f32(<16 x float> [[A0:%.*]])1164; CHECK-NEXT: store <16 x i32> [[TMP1]], ptr @__msan_retval_tls, align 81165; CHECK-NEXT: ret <16 x float> [[TMP2]]1166;1167 %1 = call <16 x float> @llvm.sqrt.v16f32(<16 x float> %a0)1168 ret <16 x float> %11169}1170 1171define <16 x float> @test_mask_sqrt_ps_512(<16 x float> %a0, <16 x float> %passthru, i16 %mask) #0 {1172; CHECK-LABEL: @test_mask_sqrt_ps_512(1173; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 81174; CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 81175; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 81176; CHECK-NEXT: call void @llvm.donothing()1177; CHECK-NEXT: [[TMP4:%.*]] = call <16 x float> @llvm.sqrt.v16f32(<16 x float> [[A0:%.*]])1178; CHECK-NEXT: [[TMP5:%.*]] = bitcast i16 [[TMP2]] to <16 x i1>1179; CHECK-NEXT: [[TMP6:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>1180; CHECK-NEXT: [[TMP7:%.*]] = select <16 x i1> [[TMP6]], <16 x i32> [[TMP1]], <16 x i32> [[TMP3]]1181; CHECK-NEXT: [[TMP8:%.*]] = bitcast <16 x float> [[TMP4]] to <16 x i32>1182; CHECK-NEXT: [[TMP9:%.*]] = bitcast <16 x float> [[PASSTHRU:%.*]] to <16 x i32>1183; CHECK-NEXT: [[TMP10:%.*]] = xor <16 x i32> [[TMP8]], [[TMP9]]1184; CHECK-NEXT: [[TMP11:%.*]] = or <16 x i32> [[TMP10]], [[TMP1]]1185; CHECK-NEXT: [[TMP12:%.*]] = or <16 x i32> [[TMP11]], [[TMP3]]1186; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP5]], <16 x i32> [[TMP12]], <16 x i32> [[TMP7]]1187; CHECK-NEXT: [[TMP13:%.*]] = select <16 x i1> [[TMP6]], <16 x float> [[TMP4]], <16 x float> [[PASSTHRU]]1188; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 81189; CHECK-NEXT: ret <16 x float> [[TMP13]]1190;1191 %1 = call <16 x float> @llvm.sqrt.v16f32(<16 x float> %a0)1192 %2 = bitcast i16 %mask to <16 x i1>1193 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> %passthru1194 ret <16 x float> %31195}1196 1197define <16 x float> @test_maskz_sqrt_ps_512(<16 x float> %a0, i16 %mask) #0 {1198; CHECK-LABEL: @test_maskz_sqrt_ps_512(1199; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 81200; CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 81201; CHECK-NEXT: call void @llvm.donothing()1202; CHECK-NEXT: [[TMP3:%.*]] = call <16 x float> @llvm.sqrt.v16f32(<16 x float> [[A0:%.*]])1203; CHECK-NEXT: [[TMP4:%.*]] = bitcast i16 [[TMP2]] to <16 x i1>1204; CHECK-NEXT: [[TMP5:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>1205; CHECK-NEXT: [[TMP6:%.*]] = select <16 x i1> [[TMP5]], <16 x i32> [[TMP1]], <16 x i32> zeroinitializer1206; CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x float> [[TMP3]] to <16 x i32>1207; CHECK-NEXT: [[TMP8:%.*]] = xor <16 x i32> [[TMP7]], zeroinitializer1208; CHECK-NEXT: [[TMP9:%.*]] = or <16 x i32> [[TMP8]], [[TMP1]]1209; CHECK-NEXT: [[TMP10:%.*]] = or <16 x i32> [[TMP9]], zeroinitializer1210; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP4]], <16 x i32> [[TMP10]], <16 x i32> [[TMP6]]1211; CHECK-NEXT: [[TMP11:%.*]] = select <16 x i1> [[TMP5]], <16 x float> [[TMP3]], <16 x float> zeroinitializer1212; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 81213; CHECK-NEXT: ret <16 x float> [[TMP11]]1214;1215 %1 = call <16 x float> @llvm.sqrt.v16f32(<16 x float> %a0)1216 %2 = bitcast i16 %mask to <16 x i1>1217 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> zeroinitializer1218 ret <16 x float> %31219}1220declare <16 x float> @llvm.sqrt.v16f32(<16 x float>)1221 1222define <16 x float> @test_sqrt_round_ps_512(<16 x float> %a0) #0 {1223; CHECK-LABEL: @test_sqrt_round_ps_512(1224; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 81225; CHECK-NEXT: call void @llvm.donothing()1226; CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i32> [[TMP1]] to i5121227; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP2]], 01228; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]1229; CHECK: 3:1230; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]1231; CHECK-NEXT: unreachable1232; CHECK: 4:1233; CHECK-NEXT: [[TMP5:%.*]] = call <16 x float> @llvm.x86.avx512.sqrt.ps.512(<16 x float> [[A0:%.*]], i32 11)1234; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81235; CHECK-NEXT: ret <16 x float> [[TMP5]]1236;1237 %1 = call <16 x float> @llvm.x86.avx512.sqrt.ps.512(<16 x float> %a0, i32 11)1238 ret <16 x float> %11239}1240 1241define <16 x float> @test_mask_sqrt_round_ps_512(<16 x float> %a0, <16 x float> %passthru, i16 %mask) #0 {1242; CHECK-LABEL: @test_mask_sqrt_round_ps_512(1243; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 81244; CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 81245; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 81246; CHECK-NEXT: call void @llvm.donothing()1247; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP1]] to i5121248; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP4]], 01249; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]1250; CHECK: 5:1251; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]1252; CHECK-NEXT: unreachable1253; CHECK: 6:1254; CHECK-NEXT: [[TMP7:%.*]] = call <16 x float> @llvm.x86.avx512.sqrt.ps.512(<16 x float> [[A0:%.*]], i32 11)1255; CHECK-NEXT: [[TMP8:%.*]] = bitcast i16 [[TMP2]] to <16 x i1>1256; CHECK-NEXT: [[TMP9:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>1257; CHECK-NEXT: [[TMP10:%.*]] = select <16 x i1> [[TMP9]], <16 x i32> zeroinitializer, <16 x i32> [[TMP3]]1258; CHECK-NEXT: [[TMP11:%.*]] = bitcast <16 x float> [[TMP7]] to <16 x i32>1259; CHECK-NEXT: [[TMP12:%.*]] = bitcast <16 x float> [[PASSTHRU:%.*]] to <16 x i32>1260; CHECK-NEXT: [[TMP13:%.*]] = xor <16 x i32> [[TMP11]], [[TMP12]]1261; CHECK-NEXT: [[TMP14:%.*]] = or <16 x i32> [[TMP13]], zeroinitializer1262; CHECK-NEXT: [[TMP15:%.*]] = or <16 x i32> [[TMP14]], [[TMP3]]1263; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP8]], <16 x i32> [[TMP15]], <16 x i32> [[TMP10]]1264; CHECK-NEXT: [[TMP16:%.*]] = select <16 x i1> [[TMP9]], <16 x float> [[TMP7]], <16 x float> [[PASSTHRU]]1265; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 81266; CHECK-NEXT: ret <16 x float> [[TMP16]]1267;1268 %1 = call <16 x float> @llvm.x86.avx512.sqrt.ps.512(<16 x float> %a0, i32 11)1269 %2 = bitcast i16 %mask to <16 x i1>1270 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> %passthru1271 ret <16 x float> %31272}1273 1274define <16 x float> @test_maskz_sqrt_round_ps_512(<16 x float> %a0, i16 %mask) #0 {1275; CHECK-LABEL: @test_maskz_sqrt_round_ps_512(1276; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 81277; CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 81278; CHECK-NEXT: call void @llvm.donothing()1279; CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i32> [[TMP1]] to i5121280; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP3]], 01281; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF1]]1282; CHECK: 4:1283; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]1284; CHECK-NEXT: unreachable1285; CHECK: 5:1286; CHECK-NEXT: [[TMP6:%.*]] = call <16 x float> @llvm.x86.avx512.sqrt.ps.512(<16 x float> [[A0:%.*]], i32 11)1287; CHECK-NEXT: [[TMP7:%.*]] = bitcast i16 [[TMP2]] to <16 x i1>1288; CHECK-NEXT: [[TMP8:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>1289; CHECK-NEXT: [[TMP9:%.*]] = select <16 x i1> [[TMP8]], <16 x i32> zeroinitializer, <16 x i32> zeroinitializer1290; CHECK-NEXT: [[TMP10:%.*]] = bitcast <16 x float> [[TMP6]] to <16 x i32>1291; CHECK-NEXT: [[TMP11:%.*]] = xor <16 x i32> [[TMP10]], zeroinitializer1292; CHECK-NEXT: [[TMP12:%.*]] = or <16 x i32> [[TMP11]], zeroinitializer1293; CHECK-NEXT: [[TMP13:%.*]] = or <16 x i32> [[TMP12]], zeroinitializer1294; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP7]], <16 x i32> [[TMP13]], <16 x i32> [[TMP9]]1295; CHECK-NEXT: [[TMP14:%.*]] = select <16 x i1> [[TMP8]], <16 x float> [[TMP6]], <16 x float> zeroinitializer1296; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 81297; CHECK-NEXT: ret <16 x float> [[TMP14]]1298;1299 %1 = call <16 x float> @llvm.x86.avx512.sqrt.ps.512(<16 x float> %a0, i32 11)1300 %2 = bitcast i16 %mask to <16 x i1>1301 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> zeroinitializer1302 ret <16 x float> %31303}1304declare <16 x float> @llvm.x86.avx512.sqrt.ps.512(<16 x float>, i32) nounwind readnone1305 1306define <8 x double> @test_getexp_pd_512(<8 x double> %a0) #0 {1307; CHECK-LABEL: @test_getexp_pd_512(1308; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 81309; CHECK-NEXT: call void @llvm.donothing()1310; CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i64> [[TMP1]] to i5121311; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP2]], 01312; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]1313; CHECK: 3:1314; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]1315; CHECK-NEXT: unreachable1316; CHECK: 4:1317; CHECK-NEXT: [[RES:%.*]] = call <8 x double> @llvm.x86.avx512.mask.getexp.pd.512(<8 x double> [[A0:%.*]], <8 x double> zeroinitializer, i8 -1, i32 4)1318; CHECK-NEXT: store <8 x i64> zeroinitializer, ptr @__msan_retval_tls, align 81319; CHECK-NEXT: ret <8 x double> [[RES]]1320;1321 %res = call <8 x double> @llvm.x86.avx512.mask.getexp.pd.512(<8 x double> %a0, <8 x double> zeroinitializer, i8 -1, i32 4)1322 ret <8 x double> %res1323}1324define <8 x double> @test_getexp_round_pd_512(<8 x double> %a0) #0 {1325; CHECK-LABEL: @test_getexp_round_pd_512(1326; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 81327; CHECK-NEXT: call void @llvm.donothing()1328; CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i64> [[TMP1]] to i5121329; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP2]], 01330; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]1331; CHECK: 3:1332; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]1333; CHECK-NEXT: unreachable1334; CHECK: 4:1335; CHECK-NEXT: [[RES:%.*]] = call <8 x double> @llvm.x86.avx512.mask.getexp.pd.512(<8 x double> [[A0:%.*]], <8 x double> zeroinitializer, i8 -1, i32 12)1336; CHECK-NEXT: store <8 x i64> zeroinitializer, ptr @__msan_retval_tls, align 81337; CHECK-NEXT: ret <8 x double> [[RES]]1338;1339 %res = call <8 x double> @llvm.x86.avx512.mask.getexp.pd.512(<8 x double> %a0, <8 x double> zeroinitializer, i8 -1, i32 12)1340 ret <8 x double> %res1341}1342declare <8 x double> @llvm.x86.avx512.mask.getexp.pd.512(<8 x double>, <8 x double>, i8, i32) nounwind readnone1343 1344define <16 x float> @test_getexp_ps_512(<16 x float> %a0) #0 {1345; CHECK-LABEL: @test_getexp_ps_512(1346; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 81347; CHECK-NEXT: call void @llvm.donothing()1348; CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i32> [[TMP1]] to i5121349; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP2]], 01350; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]1351; CHECK: 3:1352; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]1353; CHECK-NEXT: unreachable1354; CHECK: 4:1355; CHECK-NEXT: [[RES:%.*]] = call <16 x float> @llvm.x86.avx512.mask.getexp.ps.512(<16 x float> [[A0:%.*]], <16 x float> zeroinitializer, i16 -1, i32 4)1356; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81357; CHECK-NEXT: ret <16 x float> [[RES]]1358;1359 %res = call <16 x float> @llvm.x86.avx512.mask.getexp.ps.512(<16 x float> %a0, <16 x float> zeroinitializer, i16 -1, i32 4)1360 ret <16 x float> %res1361}1362 1363define <16 x float> @test_getexp_round_ps_512(<16 x float> %a0) #0 {1364; CHECK-LABEL: @test_getexp_round_ps_512(1365; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 81366; CHECK-NEXT: call void @llvm.donothing()1367; CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i32> [[TMP1]] to i5121368; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP2]], 01369; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]1370; CHECK: 3:1371; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]1372; CHECK-NEXT: unreachable1373; CHECK: 4:1374; CHECK-NEXT: [[RES:%.*]] = call <16 x float> @llvm.x86.avx512.mask.getexp.ps.512(<16 x float> [[A0:%.*]], <16 x float> zeroinitializer, i16 -1, i32 8)1375; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81376; CHECK-NEXT: ret <16 x float> [[RES]]1377;1378 %res = call <16 x float> @llvm.x86.avx512.mask.getexp.ps.512(<16 x float> %a0, <16 x float> zeroinitializer, i16 -1, i32 8)1379 ret <16 x float> %res1380}1381declare <16 x float> @llvm.x86.avx512.mask.getexp.ps.512(<16 x float>, <16 x float>, i16, i32) nounwind readnone1382 1383declare <4 x float> @llvm.x86.avx512.mask.sqrt.ss(<4 x float>, <4 x float>, <4 x float>, i8, i32) nounwind readnone1384 1385define <4 x float> @test_sqrt_ss(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) #0 {1386; CHECK-LABEL: @test_sqrt_ss(1387; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 81388; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81389; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81390; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 81391; CHECK-NEXT: call void @llvm.donothing()1392; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP1]] to i1281393; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 01394; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i32> [[TMP2]] to i1281395; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP6]], 01396; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1397; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i32> [[TMP3]] to i1281398; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 01399; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]1400; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 01401; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]1402; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]1403; CHECK: 8:1404; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]1405; CHECK-NEXT: unreachable1406; CHECK: 9:1407; CHECK-NEXT: [[RES0:%.*]] = call <4 x float> @llvm.x86.avx512.mask.sqrt.ss(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], <4 x float> [[A2:%.*]], i8 [[MASK:%.*]], i32 4)1408; CHECK-NEXT: [[TMP10:%.*]] = bitcast <4 x i32> [[TMP1]] to i1281409; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i128 [[TMP10]], 01410; CHECK-NEXT: [[TMP11:%.*]] = bitcast <4 x i32> [[TMP2]] to i1281411; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i128 [[TMP11]], 01412; CHECK-NEXT: [[_MSOR8:%.*]] = or i1 [[_MSCMP6]], [[_MSCMP7]]1413; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i32> [[TMP3]] to i1281414; CHECK-NEXT: [[_MSCMP9:%.*]] = icmp ne i128 [[TMP12]], 01415; CHECK-NEXT: [[_MSOR10:%.*]] = or i1 [[_MSOR8]], [[_MSCMP9]]1416; CHECK-NEXT: [[_MSCMP11:%.*]] = icmp ne i8 [[TMP4]], 01417; CHECK-NEXT: [[_MSOR12:%.*]] = or i1 [[_MSOR10]], [[_MSCMP11]]1418; CHECK-NEXT: br i1 [[_MSOR12]], label [[TMP13:%.*]], label [[TMP14:%.*]], !prof [[PROF1]]1419; CHECK: 13:1420; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]1421; CHECK-NEXT: unreachable1422; CHECK: 14:1423; CHECK-NEXT: [[RES1:%.*]] = call <4 x float> @llvm.x86.avx512.mask.sqrt.ss(<4 x float> [[A0]], <4 x float> [[A1]], <4 x float> [[A2]], i8 [[MASK]], i32 9)1424; CHECK-NEXT: [[TMP15:%.*]] = bitcast <4 x i32> [[TMP1]] to i1281425; CHECK-NEXT: [[_MSCMP13:%.*]] = icmp ne i128 [[TMP15]], 01426; CHECK-NEXT: [[TMP16:%.*]] = bitcast <4 x i32> [[TMP2]] to i1281427; CHECK-NEXT: [[_MSCMP14:%.*]] = icmp ne i128 [[TMP16]], 01428; CHECK-NEXT: [[_MSOR15:%.*]] = or i1 [[_MSCMP13]], [[_MSCMP14]]1429; CHECK-NEXT: [[_MSCMP16:%.*]] = icmp ne i8 [[TMP4]], 01430; CHECK-NEXT: [[_MSOR17:%.*]] = or i1 [[_MSOR15]], [[_MSCMP16]]1431; CHECK-NEXT: br i1 [[_MSOR17]], label [[TMP17:%.*]], label [[TMP18:%.*]], !prof [[PROF1]]1432; CHECK: 17:1433; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]1434; CHECK-NEXT: unreachable1435; CHECK: 18:1436; CHECK-NEXT: [[RES2:%.*]] = call <4 x float> @llvm.x86.avx512.mask.sqrt.ss(<4 x float> [[A0]], <4 x float> [[A1]], <4 x float> zeroinitializer, i8 [[MASK]], i32 10)1437; CHECK-NEXT: [[TMP19:%.*]] = bitcast <4 x i32> [[TMP1]] to i1281438; CHECK-NEXT: [[_MSCMP18:%.*]] = icmp ne i128 [[TMP19]], 01439; CHECK-NEXT: [[TMP20:%.*]] = bitcast <4 x i32> [[TMP2]] to i1281440; CHECK-NEXT: [[_MSCMP19:%.*]] = icmp ne i128 [[TMP20]], 01441; CHECK-NEXT: [[_MSOR20:%.*]] = or i1 [[_MSCMP18]], [[_MSCMP19]]1442; CHECK-NEXT: br i1 [[_MSOR20]], label [[TMP21:%.*]], label [[TMP22:%.*]], !prof [[PROF1]]1443; CHECK: 21:1444; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]1445; CHECK-NEXT: unreachable1446; CHECK: 22:1447; CHECK-NEXT: [[RES3:%.*]] = call <4 x float> @llvm.x86.avx512.mask.sqrt.ss(<4 x float> [[A0]], <4 x float> [[A1]], <4 x float> zeroinitializer, i8 -1, i32 11)1448; CHECK-NEXT: [[RES_1:%.*]] = fadd <4 x float> [[RES0]], [[RES1]]1449; CHECK-NEXT: [[RES_2:%.*]] = fadd <4 x float> [[RES2]], [[RES3]]1450; CHECK-NEXT: [[RES:%.*]] = fadd <4 x float> [[RES_1]], [[RES_2]]1451; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81452; CHECK-NEXT: ret <4 x float> [[RES]]1453;1454 %res0 = call <4 x float> @llvm.x86.avx512.mask.sqrt.ss(<4 x float>%a0, <4 x float> %a1, <4 x float> %a2, i8 %mask, i32 4)1455 %res1 = call <4 x float> @llvm.x86.avx512.mask.sqrt.ss(<4 x float>%a0, <4 x float> %a1, <4 x float> %a2, i8 %mask, i32 9)1456 %res2 = call <4 x float> @llvm.x86.avx512.mask.sqrt.ss(<4 x float>%a0, <4 x float> %a1, <4 x float> zeroinitializer, i8 %mask, i32 10)1457 %res3 = call <4 x float> @llvm.x86.avx512.mask.sqrt.ss(<4 x float>%a0, <4 x float> %a1, <4 x float> zeroinitializer, i8 -1, i32 11)1458 1459 %res.1 = fadd <4 x float> %res0, %res11460 %res.2 = fadd <4 x float> %res2, %res31461 %res = fadd <4 x float> %res.1, %res.21462 ret <4 x float> %res1463}1464 1465declare <2 x double> @llvm.x86.avx512.mask.sqrt.sd(<2 x double>, <2 x double>, <2 x double>, i8, i32) nounwind readnone1466 1467define <2 x double> @test_sqrt_sd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) #0 {1468; CHECK-LABEL: @test_sqrt_sd(1469; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 81470; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81471; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81472; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 81473; CHECK-NEXT: call void @llvm.donothing()1474; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP1]] to i1281475; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 01476; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i64> [[TMP2]] to i1281477; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP6]], 01478; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1479; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i64> [[TMP3]] to i1281480; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 01481; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]1482; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 01483; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]1484; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]1485; CHECK: 8:1486; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]1487; CHECK-NEXT: unreachable1488; CHECK: 9:1489; CHECK-NEXT: [[RES0:%.*]] = call <2 x double> @llvm.x86.avx512.mask.sqrt.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]], <2 x double> [[A2:%.*]], i8 [[MASK:%.*]], i32 4)1490; CHECK-NEXT: [[TMP10:%.*]] = bitcast <2 x i64> [[TMP1]] to i1281491; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i128 [[TMP10]], 01492; CHECK-NEXT: [[TMP11:%.*]] = bitcast <2 x i64> [[TMP2]] to i1281493; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i128 [[TMP11]], 01494; CHECK-NEXT: [[_MSOR8:%.*]] = or i1 [[_MSCMP6]], [[_MSCMP7]]1495; CHECK-NEXT: [[TMP12:%.*]] = bitcast <2 x i64> [[TMP3]] to i1281496; CHECK-NEXT: [[_MSCMP9:%.*]] = icmp ne i128 [[TMP12]], 01497; CHECK-NEXT: [[_MSOR10:%.*]] = or i1 [[_MSOR8]], [[_MSCMP9]]1498; CHECK-NEXT: [[_MSCMP11:%.*]] = icmp ne i8 [[TMP4]], 01499; CHECK-NEXT: [[_MSOR12:%.*]] = or i1 [[_MSOR10]], [[_MSCMP11]]1500; CHECK-NEXT: br i1 [[_MSOR12]], label [[TMP13:%.*]], label [[TMP14:%.*]], !prof [[PROF1]]1501; CHECK: 13:1502; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]1503; CHECK-NEXT: unreachable1504; CHECK: 14:1505; CHECK-NEXT: [[RES1:%.*]] = call <2 x double> @llvm.x86.avx512.mask.sqrt.sd(<2 x double> [[A0]], <2 x double> [[A1]], <2 x double> [[A2]], i8 [[MASK]], i32 9)1506; CHECK-NEXT: [[TMP15:%.*]] = bitcast <2 x i64> [[TMP1]] to i1281507; CHECK-NEXT: [[_MSCMP13:%.*]] = icmp ne i128 [[TMP15]], 01508; CHECK-NEXT: [[TMP16:%.*]] = bitcast <2 x i64> [[TMP2]] to i1281509; CHECK-NEXT: [[_MSCMP14:%.*]] = icmp ne i128 [[TMP16]], 01510; CHECK-NEXT: [[_MSOR15:%.*]] = or i1 [[_MSCMP13]], [[_MSCMP14]]1511; CHECK-NEXT: [[_MSCMP16:%.*]] = icmp ne i8 [[TMP4]], 01512; CHECK-NEXT: [[_MSOR17:%.*]] = or i1 [[_MSOR15]], [[_MSCMP16]]1513; CHECK-NEXT: br i1 [[_MSOR17]], label [[TMP17:%.*]], label [[TMP18:%.*]], !prof [[PROF1]]1514; CHECK: 17:1515; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]1516; CHECK-NEXT: unreachable1517; CHECK: 18:1518; CHECK-NEXT: [[RES2:%.*]] = call <2 x double> @llvm.x86.avx512.mask.sqrt.sd(<2 x double> [[A0]], <2 x double> [[A1]], <2 x double> zeroinitializer, i8 [[MASK]], i32 10)1519; CHECK-NEXT: [[TMP19:%.*]] = bitcast <2 x i64> [[TMP1]] to i1281520; CHECK-NEXT: [[_MSCMP18:%.*]] = icmp ne i128 [[TMP19]], 01521; CHECK-NEXT: [[TMP20:%.*]] = bitcast <2 x i64> [[TMP2]] to i1281522; CHECK-NEXT: [[_MSCMP19:%.*]] = icmp ne i128 [[TMP20]], 01523; CHECK-NEXT: [[_MSOR20:%.*]] = or i1 [[_MSCMP18]], [[_MSCMP19]]1524; CHECK-NEXT: br i1 [[_MSOR20]], label [[TMP21:%.*]], label [[TMP22:%.*]], !prof [[PROF1]]1525; CHECK: 21:1526; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]1527; CHECK-NEXT: unreachable1528; CHECK: 22:1529; CHECK-NEXT: [[RES3:%.*]] = call <2 x double> @llvm.x86.avx512.mask.sqrt.sd(<2 x double> [[A0]], <2 x double> [[A1]], <2 x double> zeroinitializer, i8 -1, i32 11)1530; CHECK-NEXT: [[RES_1:%.*]] = fadd <2 x double> [[RES0]], [[RES1]]1531; CHECK-NEXT: [[RES_2:%.*]] = fadd <2 x double> [[RES2]], [[RES3]]1532; CHECK-NEXT: [[RES:%.*]] = fadd <2 x double> [[RES_1]], [[RES_2]]1533; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 81534; CHECK-NEXT: ret <2 x double> [[RES]]1535;1536 %res0 = call <2 x double> @llvm.x86.avx512.mask.sqrt.sd(<2 x double>%a0, <2 x double> %a1, <2 x double> %a2, i8 %mask, i32 4)1537 %res1 = call <2 x double> @llvm.x86.avx512.mask.sqrt.sd(<2 x double>%a0, <2 x double> %a1, <2 x double> %a2, i8 %mask, i32 9)1538 %res2 = call <2 x double> @llvm.x86.avx512.mask.sqrt.sd(<2 x double>%a0, <2 x double> %a1, <2 x double> zeroinitializer, i8 %mask, i32 10)1539 %res3 = call <2 x double> @llvm.x86.avx512.mask.sqrt.sd(<2 x double>%a0, <2 x double> %a1, <2 x double> zeroinitializer, i8 -1, i32 11)1540 1541 %res.1 = fadd <2 x double> %res0, %res11542 %res.2 = fadd <2 x double> %res2, %res31543 %res = fadd <2 x double> %res.1, %res.21544 ret <2 x double> %res1545}1546 1547define i32 @test_x86_avx512_cvttsd2usi(<2 x double> %a0) #0 {1548; CHECK-LABEL: @test_x86_avx512_cvttsd2usi(1549; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 81550; CHECK-NEXT: call void @llvm.donothing()1551; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i64> [[TMP1]], i32 01552; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 01553; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]1554; CHECK: 3:1555; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]1556; CHECK-NEXT: unreachable1557; CHECK: 4:1558; CHECK-NEXT: [[RES0:%.*]] = call i32 @llvm.x86.avx512.cvttsd2usi(<2 x double> [[A0:%.*]], i32 4)1559; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i64> [[TMP1]], i32 01560; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP5]], 01561; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]1562; CHECK: 6:1563; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]1564; CHECK-NEXT: unreachable1565; CHECK: 7:1566; CHECK-NEXT: [[RES1:%.*]] = call i32 @llvm.x86.avx512.cvttsd2usi(<2 x double> [[A0]], i32 8)1567; CHECK-NEXT: [[RES2:%.*]] = add i32 [[RES0]], [[RES1]]1568; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 81569; CHECK-NEXT: ret i32 [[RES2]]1570;1571 %res0 = call i32 @llvm.x86.avx512.cvttsd2usi(<2 x double> %a0, i32 4) ;1572 %res1 = call i32 @llvm.x86.avx512.cvttsd2usi(<2 x double> %a0, i32 8) ;1573 %res2 = add i32 %res0, %res11574 ret i32 %res21575}1576declare i32 @llvm.x86.avx512.cvttsd2usi(<2 x double>, i32) nounwind readnone1577 1578define i32 @test_x86_avx512_cvttsd2si(<2 x double> %a0) #0 {1579; CHECK-LABEL: @test_x86_avx512_cvttsd2si(1580; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 81581; CHECK-NEXT: call void @llvm.donothing()1582; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to i1281583; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 01584; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]1585; CHECK: 3:1586; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]1587; CHECK-NEXT: unreachable1588; CHECK: 4:1589; CHECK-NEXT: [[RES0:%.*]] = call i32 @llvm.x86.avx512.cvttsd2si(<2 x double> [[A0:%.*]], i32 4)1590; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP1]] to i1281591; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 01592; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]1593; CHECK: 6:1594; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]1595; CHECK-NEXT: unreachable1596; CHECK: 7:1597; CHECK-NEXT: [[RES1:%.*]] = call i32 @llvm.x86.avx512.cvttsd2si(<2 x double> [[A0]], i32 8)1598; CHECK-NEXT: [[RES2:%.*]] = add i32 [[RES0]], [[RES1]]1599; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 81600; CHECK-NEXT: ret i32 [[RES2]]1601;1602 %res0 = call i32 @llvm.x86.avx512.cvttsd2si(<2 x double> %a0, i32 4) ;1603 %res1 = call i32 @llvm.x86.avx512.cvttsd2si(<2 x double> %a0, i32 8) ;1604 %res2 = add i32 %res0, %res11605 ret i32 %res21606}1607declare i32 @llvm.x86.avx512.cvttsd2si(<2 x double>, i32) nounwind readnone1608 1609define i32 @test_x86_avx512_cvttss2si(<4 x float> %a0) #0 {1610; CHECK-LABEL: @test_x86_avx512_cvttss2si(1611; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 81612; CHECK-NEXT: call void @llvm.donothing()1613; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[TMP1]] to i1281614; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 01615; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]1616; CHECK: 3:1617; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]1618; CHECK-NEXT: unreachable1619; CHECK: 4:1620; CHECK-NEXT: [[RES0:%.*]] = call i32 @llvm.x86.avx512.cvttss2si(<4 x float> [[A0:%.*]], i32 8)1621; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP1]] to i1281622; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 01623; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]1624; CHECK: 6:1625; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]1626; CHECK-NEXT: unreachable1627; CHECK: 7:1628; CHECK-NEXT: [[RES1:%.*]] = call i32 @llvm.x86.avx512.cvttss2si(<4 x float> [[A0]], i32 4)1629; CHECK-NEXT: [[RES2:%.*]] = add i32 [[RES0]], [[RES1]]1630; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 81631; CHECK-NEXT: ret i32 [[RES2]]1632;1633 %res0 = call i32 @llvm.x86.avx512.cvttss2si(<4 x float> %a0, i32 8) ;1634 %res1 = call i32 @llvm.x86.avx512.cvttss2si(<4 x float> %a0, i32 4) ;1635 %res2 = add i32 %res0, %res11636 ret i32 %res21637}1638declare i32 @llvm.x86.avx512.cvttss2si(<4 x float>, i32) nounwind readnone1639 1640define i32 @test_x86_avx512_cvttss2si_load(ptr %a0) #0 {1641; CHECK-LABEL: @test_x86_avx512_cvttss2si_load(1642; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81643; CHECK-NEXT: call void @llvm.donothing()1644; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01645; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]1646; CHECK: 2:1647; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]1648; CHECK-NEXT: unreachable1649; CHECK: 3:1650; CHECK-NEXT: [[A1:%.*]] = load <4 x float>, ptr [[A0:%.*]], align 161651; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A0]] to i641652; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 879609302220801653; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr1654; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP6]], align 161655; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i32> [[_MSLD]] to i1281656; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP7]], 01657; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]1658; CHECK: 8:1659; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]1660; CHECK-NEXT: unreachable1661; CHECK: 9:1662; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx512.cvttss2si(<4 x float> [[A1]], i32 4)1663; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 81664; CHECK-NEXT: ret i32 [[RES]]1665;1666 %a1 = load <4 x float>, ptr %a01667 %res = call i32 @llvm.x86.avx512.cvttss2si(<4 x float> %a1, i32 4) ;1668 ret i32 %res1669}1670 1671define i32 @test_x86_avx512_cvttss2usi(<4 x float> %a0) #0 {1672; CHECK-LABEL: @test_x86_avx512_cvttss2usi(1673; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 81674; CHECK-NEXT: call void @llvm.donothing()1675; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[TMP1]], i32 01676; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP2]], 01677; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]1678; CHECK: 3:1679; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]1680; CHECK-NEXT: unreachable1681; CHECK: 4:1682; CHECK-NEXT: [[RES0:%.*]] = call i32 @llvm.x86.avx512.cvttss2usi(<4 x float> [[A0:%.*]], i32 8)1683; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i32> [[TMP1]], i32 01684; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i32 [[TMP5]], 01685; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]1686; CHECK: 6:1687; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]1688; CHECK-NEXT: unreachable1689; CHECK: 7:1690; CHECK-NEXT: [[RES1:%.*]] = call i32 @llvm.x86.avx512.cvttss2usi(<4 x float> [[A0]], i32 4)1691; CHECK-NEXT: [[RES2:%.*]] = add i32 [[RES0]], [[RES1]]1692; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 81693; CHECK-NEXT: ret i32 [[RES2]]1694;1695 %res0 = call i32 @llvm.x86.avx512.cvttss2usi(<4 x float> %a0, i32 8) ;1696 %res1 = call i32 @llvm.x86.avx512.cvttss2usi(<4 x float> %a0, i32 4) ;1697 %res2 = add i32 %res0, %res11698 ret i32 %res21699}1700declare i32 @llvm.x86.avx512.cvttss2usi(<4 x float>, i32) nounwind readnone1701 1702define i32 @test_x86_avx512_cvtsd2usi32(<2 x double> %a0) #0 {1703; CHECK-LABEL: @test_x86_avx512_cvtsd2usi32(1704; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 81705; CHECK-NEXT: call void @llvm.donothing()1706; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i64> [[TMP1]], i32 01707; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 01708; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]1709; CHECK: 3:1710; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]1711; CHECK-NEXT: unreachable1712; CHECK: 4:1713; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx512.vcvtsd2usi32(<2 x double> [[A0:%.*]], i32 4)1714; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i64> [[TMP1]], i32 01715; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP5]], 01716; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]1717; CHECK: 6:1718; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]1719; CHECK-NEXT: unreachable1720; CHECK: 7:1721; CHECK-NEXT: [[RES1:%.*]] = call i32 @llvm.x86.avx512.vcvtsd2usi32(<2 x double> [[A0]], i32 11)1722; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i64> [[TMP1]], i32 01723; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP8]], 01724; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP9:%.*]], label [[TMP10:%.*]], !prof [[PROF1]]1725; CHECK: 9:1726; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]1727; CHECK-NEXT: unreachable1728; CHECK: 10:1729; CHECK-NEXT: [[RES2:%.*]] = call i32 @llvm.x86.avx512.vcvtsd2usi32(<2 x double> [[A0]], i32 9)1730; CHECK-NEXT: [[RES3:%.*]] = add i32 [[RES]], [[RES1]]1731; CHECK-NEXT: [[RES4:%.*]] = add i32 [[RES3]], [[RES2]]1732; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 81733; CHECK-NEXT: ret i32 [[RES4]]1734;1735 %res = call i32 @llvm.x86.avx512.vcvtsd2usi32(<2 x double> %a0, i32 4)1736 %res1 = call i32 @llvm.x86.avx512.vcvtsd2usi32(<2 x double> %a0, i32 11)1737 %res2 = call i32 @llvm.x86.avx512.vcvtsd2usi32(<2 x double> %a0, i32 9)1738 %res3 = add i32 %res, %res11739 %res4 = add i32 %res3, %res21740 ret i32 %res41741}1742declare i32 @llvm.x86.avx512.vcvtsd2usi32(<2 x double>, i32) nounwind readnone1743 1744define i32 @test_x86_avx512_cvtsd2si32(<2 x double> %a0) #0 {1745; CHECK-LABEL: @test_x86_avx512_cvtsd2si32(1746; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 81747; CHECK-NEXT: call void @llvm.donothing()1748; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to i1281749; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 01750; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]1751; CHECK: 3:1752; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]1753; CHECK-NEXT: unreachable1754; CHECK: 4:1755; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx512.vcvtsd2si32(<2 x double> [[A0:%.*]], i32 4)1756; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP1]] to i1281757; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 01758; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]1759; CHECK: 6:1760; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]1761; CHECK-NEXT: unreachable1762; CHECK: 7:1763; CHECK-NEXT: [[RES1:%.*]] = call i32 @llvm.x86.avx512.vcvtsd2si32(<2 x double> [[A0]], i32 11)1764; CHECK-NEXT: [[TMP8:%.*]] = bitcast <2 x i64> [[TMP1]] to i1281765; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP8]], 01766; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP9:%.*]], label [[TMP10:%.*]], !prof [[PROF1]]1767; CHECK: 9:1768; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]1769; CHECK-NEXT: unreachable1770; CHECK: 10:1771; CHECK-NEXT: [[RES2:%.*]] = call i32 @llvm.x86.avx512.vcvtsd2si32(<2 x double> [[A0]], i32 9)1772; CHECK-NEXT: [[RES3:%.*]] = add i32 [[RES]], [[RES1]]1773; CHECK-NEXT: [[RES4:%.*]] = add i32 [[RES3]], [[RES2]]1774; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 81775; CHECK-NEXT: ret i32 [[RES4]]1776;1777 %res = call i32 @llvm.x86.avx512.vcvtsd2si32(<2 x double> %a0, i32 4)1778 %res1 = call i32 @llvm.x86.avx512.vcvtsd2si32(<2 x double> %a0, i32 11)1779 %res2 = call i32 @llvm.x86.avx512.vcvtsd2si32(<2 x double> %a0, i32 9)1780 %res3 = add i32 %res, %res11781 %res4 = add i32 %res3, %res21782 ret i32 %res41783}1784declare i32 @llvm.x86.avx512.vcvtsd2si32(<2 x double>, i32) nounwind readnone1785 1786define i32 @test_x86_avx512_cvtss2usi32(<4 x float> %a0) #0 {1787; CHECK-LABEL: @test_x86_avx512_cvtss2usi32(1788; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 81789; CHECK-NEXT: call void @llvm.donothing()1790; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[TMP1]], i32 01791; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP2]], 01792; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]1793; CHECK: 3:1794; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]1795; CHECK-NEXT: unreachable1796; CHECK: 4:1797; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx512.vcvtss2usi32(<4 x float> [[A0:%.*]], i32 4)1798; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i32> [[TMP1]], i32 01799; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i32 [[TMP5]], 01800; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]1801; CHECK: 6:1802; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]1803; CHECK-NEXT: unreachable1804; CHECK: 7:1805; CHECK-NEXT: [[RES1:%.*]] = call i32 @llvm.x86.avx512.vcvtss2usi32(<4 x float> [[A0]], i32 11)1806; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x i32> [[TMP1]], i32 01807; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i32 [[TMP8]], 01808; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP9:%.*]], label [[TMP10:%.*]], !prof [[PROF1]]1809; CHECK: 9:1810; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]1811; CHECK-NEXT: unreachable1812; CHECK: 10:1813; CHECK-NEXT: [[RES2:%.*]] = call i32 @llvm.x86.avx512.vcvtss2usi32(<4 x float> [[A0]], i32 9)1814; CHECK-NEXT: [[RES3:%.*]] = add i32 [[RES]], [[RES1]]1815; CHECK-NEXT: [[RES4:%.*]] = add i32 [[RES3]], [[RES2]]1816; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 81817; CHECK-NEXT: ret i32 [[RES4]]1818;1819 %res = call i32 @llvm.x86.avx512.vcvtss2usi32(<4 x float> %a0, i32 4)1820 %res1 = call i32 @llvm.x86.avx512.vcvtss2usi32(<4 x float> %a0, i32 11)1821 %res2 = call i32 @llvm.x86.avx512.vcvtss2usi32(<4 x float> %a0, i32 9)1822 %res3 = add i32 %res, %res11823 %res4 = add i32 %res3, %res21824 ret i32 %res41825}1826declare i32 @llvm.x86.avx512.vcvtss2usi32(<4 x float>, i32) nounwind readnone1827 1828define i32 @test_x86_avx512_cvtss2si32(<4 x float> %a0) #0 {1829; CHECK-LABEL: @test_x86_avx512_cvtss2si32(1830; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 81831; CHECK-NEXT: call void @llvm.donothing()1832; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[TMP1]] to i1281833; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 01834; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]1835; CHECK: 3:1836; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]1837; CHECK-NEXT: unreachable1838; CHECK: 4:1839; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx512.vcvtss2si32(<4 x float> [[A0:%.*]], i32 4)1840; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP1]] to i1281841; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 01842; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]1843; CHECK: 6:1844; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]1845; CHECK-NEXT: unreachable1846; CHECK: 7:1847; CHECK-NEXT: [[RES1:%.*]] = call i32 @llvm.x86.avx512.vcvtss2si32(<4 x float> [[A0]], i32 11)1848; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x i32> [[TMP1]] to i1281849; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP8]], 01850; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP9:%.*]], label [[TMP10:%.*]], !prof [[PROF1]]1851; CHECK: 9:1852; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]1853; CHECK-NEXT: unreachable1854; CHECK: 10:1855; CHECK-NEXT: [[RES2:%.*]] = call i32 @llvm.x86.avx512.vcvtss2si32(<4 x float> [[A0]], i32 9)1856; CHECK-NEXT: [[RES3:%.*]] = add i32 [[RES]], [[RES1]]1857; CHECK-NEXT: [[RES4:%.*]] = add i32 [[RES3]], [[RES2]]1858; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 81859; CHECK-NEXT: ret i32 [[RES4]]1860;1861 %res = call i32 @llvm.x86.avx512.vcvtss2si32(<4 x float> %a0, i32 4)1862 %res1 = call i32 @llvm.x86.avx512.vcvtss2si32(<4 x float> %a0, i32 11)1863 %res2 = call i32 @llvm.x86.avx512.vcvtss2si32(<4 x float> %a0, i32 9)1864 %res3 = add i32 %res, %res11865 %res4 = add i32 %res3, %res21866 ret i32 %res41867}1868declare i32 @llvm.x86.avx512.vcvtss2si32(<4 x float>, i32) nounwind readnone1869 1870define <16 x i16> @test_x86_vcvtps2ph_256(<16 x float> %a0, <16 x i16> %src, i16 %mask, ptr %dst) #0 {1871; CHECK-LABEL: @test_x86_vcvtps2ph_256(1872; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 81873; CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 81874; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 81875; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 104), align 81876; CHECK-NEXT: call void @llvm.donothing()1877; CHECK-NEXT: [[TMP6:%.*]] = icmp ne <16 x i32> [[TMP1]], zeroinitializer1878; CHECK-NEXT: [[TMP7:%.*]] = sext <16 x i1> [[TMP6]] to <16 x i16>1879; CHECK-NEXT: [[TMP8:%.*]] = select <16 x i1> splat (i1 true), <16 x i16> [[TMP7]], <16 x i16> zeroinitializer1880; CHECK-NEXT: [[RES1:%.*]] = call <16 x i16> @llvm.x86.avx512.mask.vcvtps2ph.512(<16 x float> [[A0:%.*]], i32 2, <16 x i16> zeroinitializer, i16 -1)1881; CHECK-NEXT: [[TMP10:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>1882; CHECK-NEXT: [[TMP11:%.*]] = icmp ne <16 x i32> [[TMP1]], zeroinitializer1883; CHECK-NEXT: [[TMP12:%.*]] = sext <16 x i1> [[TMP11]] to <16 x i16>1884; CHECK-NEXT: [[TMP13:%.*]] = select <16 x i1> [[TMP10]], <16 x i16> [[TMP12]], <16 x i16> zeroinitializer1885; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i16 [[TMP2]], 01886; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP9:%.*]], label [[TMP14:%.*]], !prof [[PROF1]]1887; CHECK: 7:1888; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]1889; CHECK-NEXT: unreachable1890; CHECK: 8:1891; CHECK-NEXT: [[RES2:%.*]] = call <16 x i16> @llvm.x86.avx512.mask.vcvtps2ph.512(<16 x float> [[A0]], i32 11, <16 x i16> zeroinitializer, i16 [[MASK]])1892; CHECK-NEXT: [[TMP25:%.*]] = bitcast i16 [[MASK]] to <16 x i1>1893; CHECK-NEXT: [[TMP26:%.*]] = icmp ne <16 x i32> [[TMP1]], zeroinitializer1894; CHECK-NEXT: [[TMP27:%.*]] = sext <16 x i1> [[TMP26]] to <16 x i16>1895; CHECK-NEXT: [[TMP20:%.*]] = select <16 x i1> [[TMP25]], <16 x i16> [[TMP27]], <16 x i16> [[TMP3]]1896; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i16 [[TMP2]], 01897; CHECK-NEXT: br i1 [[_MSCMP6]], label [[TMP15:%.*]], label [[TMP16:%.*]], !prof [[PROF1]]1898; CHECK: 10:1899; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]1900; CHECK-NEXT: unreachable1901; CHECK: 11:1902; CHECK-NEXT: [[RES3:%.*]] = call <16 x i16> @llvm.x86.avx512.mask.vcvtps2ph.512(<16 x float> [[A0]], i32 12, <16 x i16> [[SRC:%.*]], i16 [[MASK]])1903; CHECK-NEXT: [[_MSCMP8:%.*]] = icmp ne i64 [[TMP4]], 01904; CHECK-NEXT: br i1 [[_MSCMP8]], label [[TMP21:%.*]], label [[TMP22:%.*]], !prof [[PROF1]]1905; CHECK: 12:1906; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]1907; CHECK-NEXT: unreachable1908; CHECK: 13:1909; CHECK-NEXT: [[TMP17:%.*]] = ptrtoint ptr [[DST:%.*]] to i641910; CHECK-NEXT: [[TMP18:%.*]] = xor i64 [[TMP17]], 879609302220801911; CHECK-NEXT: [[TMP19:%.*]] = inttoptr i64 [[TMP18]] to ptr1912; CHECK-NEXT: store <16 x i16> [[TMP8]], ptr [[TMP19]], align 321913; CHECK-NEXT: store <16 x i16> [[RES1]], ptr [[DST]], align 321914; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i16> [[TMP13]], [[TMP20]]1915; CHECK-NEXT: [[RES:%.*]] = add <16 x i16> [[RES2]], [[RES3]]1916; CHECK-NEXT: store <16 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 81917; CHECK-NEXT: ret <16 x i16> [[RES]]1918;1919 %res1 = call <16 x i16> @llvm.x86.avx512.mask.vcvtps2ph.512(<16 x float> %a0, i32 2, <16 x i16> zeroinitializer, i16 -1)1920 %res2 = call <16 x i16> @llvm.x86.avx512.mask.vcvtps2ph.512(<16 x float> %a0, i32 11, <16 x i16> zeroinitializer, i16 %mask)1921 %res3 = call <16 x i16> @llvm.x86.avx512.mask.vcvtps2ph.512(<16 x float> %a0, i32 12, <16 x i16> %src, i16 %mask)1922 store <16 x i16> %res1, ptr %dst1923 %res = add <16 x i16> %res2, %res31924 ret <16 x i16> %res1925}1926 1927declare <16 x i16> @llvm.x86.avx512.mask.vcvtps2ph.512(<16 x float>, i32, <16 x i16>, i16) nounwind readonly1928 1929define i16 @test_cmpps(<16 x float> %a, <16 x float> %b) #0 {1930; CHECK-LABEL: @test_cmpps(1931; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 81932; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 81933; CHECK-NEXT: call void @llvm.donothing()1934; CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i32> [[TMP1]] to i5121935; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP3]], 01936; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP2]] to i5121937; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 01938; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1939; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]1940; CHECK: 5:1941; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]1942; CHECK-NEXT: unreachable1943; CHECK: 6:1944; CHECK-NEXT: [[RES:%.*]] = call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> [[A:%.*]], <16 x float> [[B:%.*]], i32 2, <16 x i1> splat (i1 true), i32 8)1945; CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i1> [[RES]] to i161946; CHECK-NEXT: store i16 0, ptr @__msan_retval_tls, align 81947; CHECK-NEXT: ret i16 [[TMP7]]1948;1949 %res = call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %a, <16 x float> %b, i32 2, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i32 8)1950 %1 = bitcast <16 x i1> %res to i161951 ret i16 %11952}1953declare <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float>, <16 x float>, i32, <16 x i1>, i32)1954 1955define i8 @test_cmppd(<8 x double> %a, <8 x double> %b) #0 {1956; CHECK-LABEL: @test_cmppd(1957; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 81958; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 81959; CHECK-NEXT: call void @llvm.donothing()1960; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i64> [[TMP1]] to i5121961; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP3]], 01962; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i64> [[TMP2]] to i5121963; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 01964; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1965; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]1966; CHECK: 5:1967; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]1968; CHECK-NEXT: unreachable1969; CHECK: 6:1970; CHECK-NEXT: [[RES:%.*]] = call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> [[A:%.*]], <8 x double> [[B:%.*]], i32 4, <8 x i1> splat (i1 true), i32 4)1971; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i1> [[RES]] to i81972; CHECK-NEXT: store i8 0, ptr @__msan_retval_tls, align 81973; CHECK-NEXT: ret i8 [[TMP7]]1974;1975 %res = call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %a, <8 x double> %b, i32 4, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i32 4)1976 %1 = bitcast <8 x i1> %res to i81977 ret i8 %11978}1979declare <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double>, <8 x double>, i32, <8 x i1>, i32)1980 1981 1982 ; fp min - max1983define <8 x double> @test_vmaxpd(<8 x double> %a0, <8 x double> %a1) #0 {1984; CHECK-LABEL: @test_vmaxpd(1985; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 81986; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 81987; CHECK-NEXT: call void @llvm.donothing()1988; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i64> [[TMP1]], [[TMP2]]1989; CHECK-NEXT: [[_MSPROP1:%.*]] = or <8 x i64> [[_MSPROP]], zeroinitializer1990; CHECK-NEXT: [[TMP7:%.*]] = call <8 x double> @llvm.x86.avx512.max.pd.512(<8 x double> [[A0:%.*]], <8 x double> [[A1:%.*]], i32 4)1991; CHECK-NEXT: store <8 x i64> [[_MSPROP1]], ptr @__msan_retval_tls, align 81992; CHECK-NEXT: ret <8 x double> [[TMP7]]1993;1994 %1 = call <8 x double> @llvm.x86.avx512.max.pd.512(<8 x double> %a0, <8 x double> %a1, i32 4)1995 ret <8 x double> %11996}1997declare <8 x double> @llvm.x86.avx512.max.pd.512(<8 x double>, <8 x double>, i32)1998 1999define <8 x double> @test_vminpd(<8 x double> %a0, <8 x double> %a1) #0 {2000; CHECK-LABEL: @test_vminpd(2001; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 82002; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82003; CHECK-NEXT: call void @llvm.donothing()2004; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i64> [[TMP1]], [[TMP2]]2005; CHECK-NEXT: [[_MSPROP1:%.*]] = or <8 x i64> [[_MSPROP]], zeroinitializer2006; CHECK-NEXT: [[TMP7:%.*]] = call <8 x double> @llvm.x86.avx512.min.pd.512(<8 x double> [[A0:%.*]], <8 x double> [[A1:%.*]], i32 4)2007; CHECK-NEXT: store <8 x i64> [[_MSPROP1]], ptr @__msan_retval_tls, align 82008; CHECK-NEXT: ret <8 x double> [[TMP7]]2009;2010 %1 = call <8 x double> @llvm.x86.avx512.min.pd.512(<8 x double> %a0, <8 x double> %a1, i32 4)2011 ret <8 x double> %12012}2013declare <8 x double> @llvm.x86.avx512.min.pd.512(<8 x double>, <8 x double>, i32)2014 2015define void @test_mask_store_ss(ptr %ptr, <4 x float> %data, i8 %mask) #0 {2016; CHECK-LABEL: @test_mask_store_ss(2017; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 82018; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82019; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr @__msan_param_tls, align 82020; CHECK-NEXT: call void @llvm.donothing()2021; CHECK-NEXT: [[TMP4:%.*]] = and i8 [[TMP1]], 02022; CHECK-NEXT: [[TMP5:%.*]] = and i8 [[MASK:%.*]], 02023; CHECK-NEXT: [[TMP6:%.*]] = and i8 [[TMP1]], 12024; CHECK-NEXT: [[TMP7:%.*]] = or i8 [[TMP4]], [[TMP5]]2025; CHECK-NEXT: [[TMP8:%.*]] = or i8 [[TMP7]], [[TMP6]]2026; CHECK-NEXT: [[TMP9:%.*]] = and i8 [[MASK]], 12027; CHECK-NEXT: [[TMP10:%.*]] = bitcast i8 [[TMP8]] to <8 x i1>2028; CHECK-NEXT: [[TMP11:%.*]] = bitcast i8 [[TMP9]] to <8 x i1>2029; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP10]], <8 x i1> [[TMP10]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>2030; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP11]], <8 x i1> [[TMP11]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>2031; CHECK-NEXT: [[TMP12:%.*]] = ptrtoint ptr [[PTR:%.*]] to i642032; CHECK-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], 879609302220802033; CHECK-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP13]] to ptr2034; CHECK-NEXT: call void @llvm.masked.store.v4i32.p0(<4 x i32> [[TMP2]], ptr align 1 [[TMP14]], <4 x i1> [[EXTRACT]])2035; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP3]], 02036; CHECK-NEXT: [[TMP15:%.*]] = bitcast <4 x i1> [[_MSPROP]] to i42037; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i4 [[TMP15]], 02038; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]2039; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP16:%.*]], label [[TMP17:%.*]], !prof [[PROF1]]2040; CHECK: 16:2041; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]2042; CHECK-NEXT: unreachable2043; CHECK: 17:2044; CHECK-NEXT: call void @llvm.masked.store.v4f32.p0(<4 x float> [[DATA:%.*]], ptr align 1 [[PTR]], <4 x i1> [[EXTRACT]])2045; CHECK-NEXT: ret void2046;2047 %1 = and i8 %mask, 12048 %2 = bitcast i8 %1 to <8 x i1>2049 %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>2050 call void @llvm.masked.store.v4f32.p0(<4 x float> %data, ptr %ptr, i32 1, <4 x i1> %extract)2051 ret void2052}2053declare void @llvm.masked.store.v4f32.p0(<4 x float>, ptr, i32, <4 x i1>) #12054 2055 2056declare <16 x float> @llvm.x86.avx512.sub.ps.512(<16 x float>, <16 x float>, i32)2057declare <16 x float> @llvm.x86.avx512.mul.ps.512(<16 x float>, <16 x float>, i32)2058declare <8 x double> @llvm.x86.avx512.mul.pd.512(<8 x double>, <8 x double>, i32)2059 2060define <16 x float> @test_vsubps_rn(<16 x float> %a0, <16 x float> %a1) #0 {2061; CHECK-LABEL: @test_vsubps_rn(2062; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 82063; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82064; CHECK-NEXT: call void @llvm.donothing()2065; CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i32> [[TMP1]] to i5122066; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP3]], 02067; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP2]] to i5122068; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 02069; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]2070; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]2071; CHECK: 5:2072; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]2073; CHECK-NEXT: unreachable2074; CHECK: 6:2075; CHECK-NEXT: [[TMP7:%.*]] = call <16 x float> @llvm.x86.avx512.sub.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 8)2076; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 82077; CHECK-NEXT: ret <16 x float> [[TMP7]]2078;2079 %1 = call <16 x float> @llvm.x86.avx512.sub.ps.512(<16 x float> %a0, <16 x float> %a1, i32 8)2080 ret <16 x float> %12081}2082 2083define <16 x float> @test_vsubps_rd(<16 x float> %a0, <16 x float> %a1) #0 {2084; CHECK-LABEL: @test_vsubps_rd(2085; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 82086; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82087; CHECK-NEXT: call void @llvm.donothing()2088; CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i32> [[TMP1]] to i5122089; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP3]], 02090; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP2]] to i5122091; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 02092; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]2093; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]2094; CHECK: 5:2095; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]2096; CHECK-NEXT: unreachable2097; CHECK: 6:2098; CHECK-NEXT: [[TMP7:%.*]] = call <16 x float> @llvm.x86.avx512.sub.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 9)2099; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 82100; CHECK-NEXT: ret <16 x float> [[TMP7]]2101;2102 %1 = call <16 x float> @llvm.x86.avx512.sub.ps.512(<16 x float> %a0, <16 x float> %a1, i32 9)2103 ret <16 x float> %12104}2105 2106define <16 x float> @test_vsubps_ru(<16 x float> %a0, <16 x float> %a1) #0 {2107; CHECK-LABEL: @test_vsubps_ru(2108; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 82109; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82110; CHECK-NEXT: call void @llvm.donothing()2111; CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i32> [[TMP1]] to i5122112; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP3]], 02113; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP2]] to i5122114; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 02115; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]2116; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]2117; CHECK: 5:2118; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]2119; CHECK-NEXT: unreachable2120; CHECK: 6:2121; CHECK-NEXT: [[TMP7:%.*]] = call <16 x float> @llvm.x86.avx512.sub.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 10)2122; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 82123; CHECK-NEXT: ret <16 x float> [[TMP7]]2124;2125 %1 = call <16 x float> @llvm.x86.avx512.sub.ps.512(<16 x float> %a0, <16 x float> %a1, i32 10)2126 ret <16 x float> %12127}2128 2129define <16 x float> @test_vsubps_rz(<16 x float> %a0, <16 x float> %a1) #0 {2130; CHECK-LABEL: @test_vsubps_rz(2131; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 82132; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82133; CHECK-NEXT: call void @llvm.donothing()2134; CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i32> [[TMP1]] to i5122135; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP3]], 02136; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP2]] to i5122137; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 02138; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]2139; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]2140; CHECK: 5:2141; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]2142; CHECK-NEXT: unreachable2143; CHECK: 6:2144; CHECK-NEXT: [[TMP7:%.*]] = call <16 x float> @llvm.x86.avx512.sub.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 11)2145; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 82146; CHECK-NEXT: ret <16 x float> [[TMP7]]2147;2148 %1 = call <16 x float> @llvm.x86.avx512.sub.ps.512(<16 x float> %a0, <16 x float> %a1, i32 11)2149 ret <16 x float> %12150}2151 2152define <16 x float> @test_vmulps_rn(<16 x float> %a0, <16 x float> %a1) #0 {2153; CHECK-LABEL: @test_vmulps_rn(2154; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 82155; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82156; CHECK-NEXT: call void @llvm.donothing()2157; CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i32> [[TMP1]] to i5122158; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP3]], 02159; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP2]] to i5122160; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 02161; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]2162; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]2163; CHECK: 5:2164; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]2165; CHECK-NEXT: unreachable2166; CHECK: 6:2167; CHECK-NEXT: [[TMP7:%.*]] = call <16 x float> @llvm.x86.avx512.mul.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 8)2168; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 82169; CHECK-NEXT: ret <16 x float> [[TMP7]]2170;2171 %1 = call <16 x float> @llvm.x86.avx512.mul.ps.512(<16 x float> %a0, <16 x float> %a1, i32 8)2172 ret <16 x float> %12173}2174 2175define <16 x float> @test_vmulps_rd(<16 x float> %a0, <16 x float> %a1) #0 {2176; CHECK-LABEL: @test_vmulps_rd(2177; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 82178; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82179; CHECK-NEXT: call void @llvm.donothing()2180; CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i32> [[TMP1]] to i5122181; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP3]], 02182; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP2]] to i5122183; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 02184; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]2185; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]2186; CHECK: 5:2187; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]2188; CHECK-NEXT: unreachable2189; CHECK: 6:2190; CHECK-NEXT: [[TMP7:%.*]] = call <16 x float> @llvm.x86.avx512.mul.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 9)2191; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 82192; CHECK-NEXT: ret <16 x float> [[TMP7]]2193;2194 %1 = call <16 x float> @llvm.x86.avx512.mul.ps.512(<16 x float> %a0, <16 x float> %a1, i32 9)2195 ret <16 x float> %12196}2197 2198define <16 x float> @test_vmulps_ru(<16 x float> %a0, <16 x float> %a1) #0 {2199; CHECK-LABEL: @test_vmulps_ru(2200; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 82201; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82202; CHECK-NEXT: call void @llvm.donothing()2203; CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i32> [[TMP1]] to i5122204; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP3]], 02205; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP2]] to i5122206; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 02207; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]2208; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]2209; CHECK: 5:2210; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]2211; CHECK-NEXT: unreachable2212; CHECK: 6:2213; CHECK-NEXT: [[TMP7:%.*]] = call <16 x float> @llvm.x86.avx512.mul.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 10)2214; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 82215; CHECK-NEXT: ret <16 x float> [[TMP7]]2216;2217 %1 = call <16 x float> @llvm.x86.avx512.mul.ps.512(<16 x float> %a0, <16 x float> %a1, i32 10)2218 ret <16 x float> %12219}2220 2221define <16 x float> @test_vmulps_rz(<16 x float> %a0, <16 x float> %a1) #0 {2222; CHECK-LABEL: @test_vmulps_rz(2223; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 82224; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82225; CHECK-NEXT: call void @llvm.donothing()2226; CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i32> [[TMP1]] to i5122227; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP3]], 02228; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP2]] to i5122229; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 02230; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]2231; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]2232; CHECK: 5:2233; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]2234; CHECK-NEXT: unreachable2235; CHECK: 6:2236; CHECK-NEXT: [[TMP7:%.*]] = call <16 x float> @llvm.x86.avx512.mul.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 11)2237; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 82238; CHECK-NEXT: ret <16 x float> [[TMP7]]2239;2240 %1 = call <16 x float> @llvm.x86.avx512.mul.ps.512(<16 x float> %a0, <16 x float> %a1, i32 11)2241 ret <16 x float> %12242}2243 2244define <16 x float> @test_vmulps_mask_rn(<16 x float> %a0, <16 x float> %a1, i16 %mask) #0 {2245; CHECK-LABEL: @test_vmulps_mask_rn(2246; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 82247; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82248; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 82249; CHECK-NEXT: call void @llvm.donothing()2250; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP1]] to i5122251; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP4]], 02252; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP2]] to i5122253; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP5]], 02254; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]2255; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]2256; CHECK: 6:2257; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]2258; CHECK-NEXT: unreachable2259; CHECK: 7:2260; CHECK-NEXT: [[TMP8:%.*]] = call <16 x float> @llvm.x86.avx512.mul.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 8)2261; CHECK-NEXT: [[TMP9:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>2262; CHECK-NEXT: [[TMP10:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>2263; CHECK-NEXT: [[TMP11:%.*]] = select <16 x i1> [[TMP10]], <16 x i32> zeroinitializer, <16 x i32> zeroinitializer2264; CHECK-NEXT: [[TMP12:%.*]] = bitcast <16 x float> [[TMP8]] to <16 x i32>2265; CHECK-NEXT: [[TMP13:%.*]] = xor <16 x i32> [[TMP12]], zeroinitializer2266; CHECK-NEXT: [[TMP14:%.*]] = or <16 x i32> [[TMP13]], zeroinitializer2267; CHECK-NEXT: [[TMP15:%.*]] = or <16 x i32> [[TMP14]], zeroinitializer2268; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP9]], <16 x i32> [[TMP15]], <16 x i32> [[TMP11]]2269; CHECK-NEXT: [[TMP16:%.*]] = select <16 x i1> [[TMP10]], <16 x float> [[TMP8]], <16 x float> zeroinitializer2270; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82271; CHECK-NEXT: ret <16 x float> [[TMP16]]2272;2273 %1 = call <16 x float> @llvm.x86.avx512.mul.ps.512(<16 x float> %a0, <16 x float> %a1, i32 8)2274 %2 = bitcast i16 %mask to <16 x i1>2275 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> zeroinitializer2276 ret <16 x float> %32277}2278 2279define <16 x float> @test_vmulps_mask_rd(<16 x float> %a0, <16 x float> %a1, i16 %mask) #0 {2280; CHECK-LABEL: @test_vmulps_mask_rd(2281; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 82282; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82283; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 82284; CHECK-NEXT: call void @llvm.donothing()2285; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP1]] to i5122286; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP4]], 02287; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP2]] to i5122288; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP5]], 02289; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]2290; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]2291; CHECK: 6:2292; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]2293; CHECK-NEXT: unreachable2294; CHECK: 7:2295; CHECK-NEXT: [[TMP8:%.*]] = call <16 x float> @llvm.x86.avx512.mul.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 9)2296; CHECK-NEXT: [[TMP9:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>2297; CHECK-NEXT: [[TMP10:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>2298; CHECK-NEXT: [[TMP11:%.*]] = select <16 x i1> [[TMP10]], <16 x i32> zeroinitializer, <16 x i32> zeroinitializer2299; CHECK-NEXT: [[TMP12:%.*]] = bitcast <16 x float> [[TMP8]] to <16 x i32>2300; CHECK-NEXT: [[TMP13:%.*]] = xor <16 x i32> [[TMP12]], zeroinitializer2301; CHECK-NEXT: [[TMP14:%.*]] = or <16 x i32> [[TMP13]], zeroinitializer2302; CHECK-NEXT: [[TMP15:%.*]] = or <16 x i32> [[TMP14]], zeroinitializer2303; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP9]], <16 x i32> [[TMP15]], <16 x i32> [[TMP11]]2304; CHECK-NEXT: [[TMP16:%.*]] = select <16 x i1> [[TMP10]], <16 x float> [[TMP8]], <16 x float> zeroinitializer2305; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82306; CHECK-NEXT: ret <16 x float> [[TMP16]]2307;2308 %1 = call <16 x float> @llvm.x86.avx512.mul.ps.512(<16 x float> %a0, <16 x float> %a1, i32 9)2309 %2 = bitcast i16 %mask to <16 x i1>2310 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> zeroinitializer2311 ret <16 x float> %32312}2313 2314define <16 x float> @test_vmulps_mask_ru(<16 x float> %a0, <16 x float> %a1, i16 %mask) #0 {2315; CHECK-LABEL: @test_vmulps_mask_ru(2316; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 82317; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82318; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 82319; CHECK-NEXT: call void @llvm.donothing()2320; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP1]] to i5122321; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP4]], 02322; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP2]] to i5122323; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP5]], 02324; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]2325; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]2326; CHECK: 6:2327; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]2328; CHECK-NEXT: unreachable2329; CHECK: 7:2330; CHECK-NEXT: [[TMP8:%.*]] = call <16 x float> @llvm.x86.avx512.mul.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 10)2331; CHECK-NEXT: [[TMP9:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>2332; CHECK-NEXT: [[TMP10:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>2333; CHECK-NEXT: [[TMP11:%.*]] = select <16 x i1> [[TMP10]], <16 x i32> zeroinitializer, <16 x i32> zeroinitializer2334; CHECK-NEXT: [[TMP12:%.*]] = bitcast <16 x float> [[TMP8]] to <16 x i32>2335; CHECK-NEXT: [[TMP13:%.*]] = xor <16 x i32> [[TMP12]], zeroinitializer2336; CHECK-NEXT: [[TMP14:%.*]] = or <16 x i32> [[TMP13]], zeroinitializer2337; CHECK-NEXT: [[TMP15:%.*]] = or <16 x i32> [[TMP14]], zeroinitializer2338; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP9]], <16 x i32> [[TMP15]], <16 x i32> [[TMP11]]2339; CHECK-NEXT: [[TMP16:%.*]] = select <16 x i1> [[TMP10]], <16 x float> [[TMP8]], <16 x float> zeroinitializer2340; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82341; CHECK-NEXT: ret <16 x float> [[TMP16]]2342;2343 %1 = call <16 x float> @llvm.x86.avx512.mul.ps.512(<16 x float> %a0, <16 x float> %a1, i32 10)2344 %2 = bitcast i16 %mask to <16 x i1>2345 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> zeroinitializer2346 ret <16 x float> %32347}2348 2349define <16 x float> @test_vmulps_mask_rz(<16 x float> %a0, <16 x float> %a1, i16 %mask) #0 {2350; CHECK-LABEL: @test_vmulps_mask_rz(2351; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 82352; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82353; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 82354; CHECK-NEXT: call void @llvm.donothing()2355; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP1]] to i5122356; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP4]], 02357; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP2]] to i5122358; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP5]], 02359; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]2360; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]2361; CHECK: 6:2362; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]2363; CHECK-NEXT: unreachable2364; CHECK: 7:2365; CHECK-NEXT: [[TMP8:%.*]] = call <16 x float> @llvm.x86.avx512.mul.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 11)2366; CHECK-NEXT: [[TMP9:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>2367; CHECK-NEXT: [[TMP10:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>2368; CHECK-NEXT: [[TMP11:%.*]] = select <16 x i1> [[TMP10]], <16 x i32> zeroinitializer, <16 x i32> zeroinitializer2369; CHECK-NEXT: [[TMP12:%.*]] = bitcast <16 x float> [[TMP8]] to <16 x i32>2370; CHECK-NEXT: [[TMP13:%.*]] = xor <16 x i32> [[TMP12]], zeroinitializer2371; CHECK-NEXT: [[TMP14:%.*]] = or <16 x i32> [[TMP13]], zeroinitializer2372; CHECK-NEXT: [[TMP15:%.*]] = or <16 x i32> [[TMP14]], zeroinitializer2373; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP9]], <16 x i32> [[TMP15]], <16 x i32> [[TMP11]]2374; CHECK-NEXT: [[TMP16:%.*]] = select <16 x i1> [[TMP10]], <16 x float> [[TMP8]], <16 x float> zeroinitializer2375; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82376; CHECK-NEXT: ret <16 x float> [[TMP16]]2377;2378 %1 = call <16 x float> @llvm.x86.avx512.mul.ps.512(<16 x float> %a0, <16 x float> %a1, i32 11)2379 %2 = bitcast i16 %mask to <16 x i1>2380 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> zeroinitializer2381 ret <16 x float> %32382}2383 2384define <16 x float> @test_vmulps_mask_passthru_rn(<16 x float> %a0, <16 x float> %a1, <16 x float> %passthru, i16 %mask) #0 {2385; CHECK-LABEL: @test_vmulps_mask_passthru_rn(2386; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 82387; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82388; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 82389; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 82390; CHECK-NEXT: call void @llvm.donothing()2391; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP1]] to i5122392; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP5]], 02393; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i32> [[TMP2]] to i5122394; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP6]], 02395; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]2396; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]2397; CHECK: 7:2398; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]2399; CHECK-NEXT: unreachable2400; CHECK: 8:2401; CHECK-NEXT: [[TMP9:%.*]] = call <16 x float> @llvm.x86.avx512.mul.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 8)2402; CHECK-NEXT: [[TMP10:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>2403; CHECK-NEXT: [[TMP11:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>2404; CHECK-NEXT: [[TMP12:%.*]] = select <16 x i1> [[TMP11]], <16 x i32> zeroinitializer, <16 x i32> [[TMP4]]2405; CHECK-NEXT: [[TMP13:%.*]] = bitcast <16 x float> [[TMP9]] to <16 x i32>2406; CHECK-NEXT: [[TMP14:%.*]] = bitcast <16 x float> [[PASSTHRU:%.*]] to <16 x i32>2407; CHECK-NEXT: [[TMP15:%.*]] = xor <16 x i32> [[TMP13]], [[TMP14]]2408; CHECK-NEXT: [[TMP16:%.*]] = or <16 x i32> [[TMP15]], zeroinitializer2409; CHECK-NEXT: [[TMP17:%.*]] = or <16 x i32> [[TMP16]], [[TMP4]]2410; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP10]], <16 x i32> [[TMP17]], <16 x i32> [[TMP12]]2411; CHECK-NEXT: [[TMP18:%.*]] = select <16 x i1> [[TMP11]], <16 x float> [[TMP9]], <16 x float> [[PASSTHRU]]2412; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82413; CHECK-NEXT: ret <16 x float> [[TMP18]]2414;2415 %1 = call <16 x float> @llvm.x86.avx512.mul.ps.512(<16 x float> %a0, <16 x float> %a1, i32 8)2416 %2 = bitcast i16 %mask to <16 x i1>2417 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> %passthru2418 ret <16 x float> %32419}2420 2421define <16 x float> @test_vmulps_mask_passthru_rd(<16 x float> %a0, <16 x float> %a1, <16 x float> %passthru, i16 %mask) #0 {2422; CHECK-LABEL: @test_vmulps_mask_passthru_rd(2423; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 82424; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82425; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 82426; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 82427; CHECK-NEXT: call void @llvm.donothing()2428; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP1]] to i5122429; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP5]], 02430; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i32> [[TMP2]] to i5122431; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP6]], 02432; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]2433; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]2434; CHECK: 7:2435; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]2436; CHECK-NEXT: unreachable2437; CHECK: 8:2438; CHECK-NEXT: [[TMP9:%.*]] = call <16 x float> @llvm.x86.avx512.mul.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 9)2439; CHECK-NEXT: [[TMP10:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>2440; CHECK-NEXT: [[TMP11:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>2441; CHECK-NEXT: [[TMP12:%.*]] = select <16 x i1> [[TMP11]], <16 x i32> zeroinitializer, <16 x i32> [[TMP4]]2442; CHECK-NEXT: [[TMP13:%.*]] = bitcast <16 x float> [[TMP9]] to <16 x i32>2443; CHECK-NEXT: [[TMP14:%.*]] = bitcast <16 x float> [[PASSTHRU:%.*]] to <16 x i32>2444; CHECK-NEXT: [[TMP15:%.*]] = xor <16 x i32> [[TMP13]], [[TMP14]]2445; CHECK-NEXT: [[TMP16:%.*]] = or <16 x i32> [[TMP15]], zeroinitializer2446; CHECK-NEXT: [[TMP17:%.*]] = or <16 x i32> [[TMP16]], [[TMP4]]2447; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP10]], <16 x i32> [[TMP17]], <16 x i32> [[TMP12]]2448; CHECK-NEXT: [[TMP18:%.*]] = select <16 x i1> [[TMP11]], <16 x float> [[TMP9]], <16 x float> [[PASSTHRU]]2449; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82450; CHECK-NEXT: ret <16 x float> [[TMP18]]2451;2452 %1 = call <16 x float> @llvm.x86.avx512.mul.ps.512(<16 x float> %a0, <16 x float> %a1, i32 9)2453 %2 = bitcast i16 %mask to <16 x i1>2454 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> %passthru2455 ret <16 x float> %32456}2457 2458define <16 x float> @test_vmulps_mask_passthru_ru(<16 x float> %a0, <16 x float> %a1, <16 x float> %passthru, i16 %mask) #0 {2459; CHECK-LABEL: @test_vmulps_mask_passthru_ru(2460; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 82461; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82462; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 82463; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 82464; CHECK-NEXT: call void @llvm.donothing()2465; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP1]] to i5122466; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP5]], 02467; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i32> [[TMP2]] to i5122468; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP6]], 02469; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]2470; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]2471; CHECK: 7:2472; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]2473; CHECK-NEXT: unreachable2474; CHECK: 8:2475; CHECK-NEXT: [[TMP9:%.*]] = call <16 x float> @llvm.x86.avx512.mul.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 10)2476; CHECK-NEXT: [[TMP10:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>2477; CHECK-NEXT: [[TMP11:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>2478; CHECK-NEXT: [[TMP12:%.*]] = select <16 x i1> [[TMP11]], <16 x i32> zeroinitializer, <16 x i32> [[TMP4]]2479; CHECK-NEXT: [[TMP13:%.*]] = bitcast <16 x float> [[TMP9]] to <16 x i32>2480; CHECK-NEXT: [[TMP14:%.*]] = bitcast <16 x float> [[PASSTHRU:%.*]] to <16 x i32>2481; CHECK-NEXT: [[TMP15:%.*]] = xor <16 x i32> [[TMP13]], [[TMP14]]2482; CHECK-NEXT: [[TMP16:%.*]] = or <16 x i32> [[TMP15]], zeroinitializer2483; CHECK-NEXT: [[TMP17:%.*]] = or <16 x i32> [[TMP16]], [[TMP4]]2484; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP10]], <16 x i32> [[TMP17]], <16 x i32> [[TMP12]]2485; CHECK-NEXT: [[TMP18:%.*]] = select <16 x i1> [[TMP11]], <16 x float> [[TMP9]], <16 x float> [[PASSTHRU]]2486; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82487; CHECK-NEXT: ret <16 x float> [[TMP18]]2488;2489 %1 = call <16 x float> @llvm.x86.avx512.mul.ps.512(<16 x float> %a0, <16 x float> %a1, i32 10)2490 %2 = bitcast i16 %mask to <16 x i1>2491 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> %passthru2492 ret <16 x float> %32493}2494 2495define <16 x float> @test_vmulps_mask_passthru_rz(<16 x float> %a0, <16 x float> %a1, <16 x float> %passthru, i16 %mask) #0 {2496; CHECK-LABEL: @test_vmulps_mask_passthru_rz(2497; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 82498; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82499; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 82500; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 82501; CHECK-NEXT: call void @llvm.donothing()2502; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP1]] to i5122503; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP5]], 02504; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i32> [[TMP2]] to i5122505; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP6]], 02506; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]2507; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]2508; CHECK: 7:2509; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]2510; CHECK-NEXT: unreachable2511; CHECK: 8:2512; CHECK-NEXT: [[TMP9:%.*]] = call <16 x float> @llvm.x86.avx512.mul.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 11)2513; CHECK-NEXT: [[TMP10:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>2514; CHECK-NEXT: [[TMP11:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>2515; CHECK-NEXT: [[TMP12:%.*]] = select <16 x i1> [[TMP11]], <16 x i32> zeroinitializer, <16 x i32> [[TMP4]]2516; CHECK-NEXT: [[TMP13:%.*]] = bitcast <16 x float> [[TMP9]] to <16 x i32>2517; CHECK-NEXT: [[TMP14:%.*]] = bitcast <16 x float> [[PASSTHRU:%.*]] to <16 x i32>2518; CHECK-NEXT: [[TMP15:%.*]] = xor <16 x i32> [[TMP13]], [[TMP14]]2519; CHECK-NEXT: [[TMP16:%.*]] = or <16 x i32> [[TMP15]], zeroinitializer2520; CHECK-NEXT: [[TMP17:%.*]] = or <16 x i32> [[TMP16]], [[TMP4]]2521; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP10]], <16 x i32> [[TMP17]], <16 x i32> [[TMP12]]2522; CHECK-NEXT: [[TMP18:%.*]] = select <16 x i1> [[TMP11]], <16 x float> [[TMP9]], <16 x float> [[PASSTHRU]]2523; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82524; CHECK-NEXT: ret <16 x float> [[TMP18]]2525;2526 %1 = call <16 x float> @llvm.x86.avx512.mul.ps.512(<16 x float> %a0, <16 x float> %a1, i32 11)2527 %2 = bitcast i16 %mask to <16 x i1>2528 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> %passthru2529 ret <16 x float> %32530}2531 2532define <8 x double> @test_vmulpd_mask_rn(<8 x double> %a0, <8 x double> %a1, i8 %mask) #0 {2533; CHECK-LABEL: @test_vmulpd_mask_rn(2534; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 82535; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82536; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 82537; CHECK-NEXT: call void @llvm.donothing()2538; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i64> [[TMP1]] to i5122539; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP4]], 02540; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i64> [[TMP2]] to i5122541; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP5]], 02542; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]2543; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]2544; CHECK: 6:2545; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]2546; CHECK-NEXT: unreachable2547; CHECK: 7:2548; CHECK-NEXT: [[TMP8:%.*]] = call <8 x double> @llvm.x86.avx512.mul.pd.512(<8 x double> [[A0:%.*]], <8 x double> [[A1:%.*]], i32 8)2549; CHECK-NEXT: [[TMP9:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>2550; CHECK-NEXT: [[TMP10:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>2551; CHECK-NEXT: [[TMP11:%.*]] = select <8 x i1> [[TMP10]], <8 x i64> zeroinitializer, <8 x i64> zeroinitializer2552; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x double> [[TMP8]] to <8 x i64>2553; CHECK-NEXT: [[TMP13:%.*]] = xor <8 x i64> [[TMP12]], zeroinitializer2554; CHECK-NEXT: [[TMP14:%.*]] = or <8 x i64> [[TMP13]], zeroinitializer2555; CHECK-NEXT: [[TMP15:%.*]] = or <8 x i64> [[TMP14]], zeroinitializer2556; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP9]], <8 x i64> [[TMP15]], <8 x i64> [[TMP11]]2557; CHECK-NEXT: [[TMP16:%.*]] = select <8 x i1> [[TMP10]], <8 x double> [[TMP8]], <8 x double> zeroinitializer2558; CHECK-NEXT: store <8 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82559; CHECK-NEXT: ret <8 x double> [[TMP16]]2560;2561 %1 = call <8 x double> @llvm.x86.avx512.mul.pd.512(<8 x double> %a0, <8 x double> %a1, i32 8)2562 %2 = bitcast i8 %mask to <8 x i1>2563 %3 = select <8 x i1> %2, <8 x double> %1, <8 x double> zeroinitializer2564 ret <8 x double> %32565}2566 2567define <8 x double> @test_vmulpd_mask_rd(<8 x double> %a0, <8 x double> %a1, i8 %mask) #0 {2568; CHECK-LABEL: @test_vmulpd_mask_rd(2569; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 82570; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82571; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 82572; CHECK-NEXT: call void @llvm.donothing()2573; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i64> [[TMP1]] to i5122574; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP4]], 02575; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i64> [[TMP2]] to i5122576; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP5]], 02577; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]2578; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]2579; CHECK: 6:2580; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]2581; CHECK-NEXT: unreachable2582; CHECK: 7:2583; CHECK-NEXT: [[TMP8:%.*]] = call <8 x double> @llvm.x86.avx512.mul.pd.512(<8 x double> [[A0:%.*]], <8 x double> [[A1:%.*]], i32 9)2584; CHECK-NEXT: [[TMP9:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>2585; CHECK-NEXT: [[TMP10:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>2586; CHECK-NEXT: [[TMP11:%.*]] = select <8 x i1> [[TMP10]], <8 x i64> zeroinitializer, <8 x i64> zeroinitializer2587; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x double> [[TMP8]] to <8 x i64>2588; CHECK-NEXT: [[TMP13:%.*]] = xor <8 x i64> [[TMP12]], zeroinitializer2589; CHECK-NEXT: [[TMP14:%.*]] = or <8 x i64> [[TMP13]], zeroinitializer2590; CHECK-NEXT: [[TMP15:%.*]] = or <8 x i64> [[TMP14]], zeroinitializer2591; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP9]], <8 x i64> [[TMP15]], <8 x i64> [[TMP11]]2592; CHECK-NEXT: [[TMP16:%.*]] = select <8 x i1> [[TMP10]], <8 x double> [[TMP8]], <8 x double> zeroinitializer2593; CHECK-NEXT: store <8 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82594; CHECK-NEXT: ret <8 x double> [[TMP16]]2595;2596 %1 = call <8 x double> @llvm.x86.avx512.mul.pd.512(<8 x double> %a0, <8 x double> %a1, i32 9)2597 %2 = bitcast i8 %mask to <8 x i1>2598 %3 = select <8 x i1> %2, <8 x double> %1, <8 x double> zeroinitializer2599 ret <8 x double> %32600}2601 2602define <8 x double> @test_vmulpd_mask_ru(<8 x double> %a0, <8 x double> %a1, i8 %mask) #0 {2603; CHECK-LABEL: @test_vmulpd_mask_ru(2604; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 82605; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82606; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 82607; CHECK-NEXT: call void @llvm.donothing()2608; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i64> [[TMP1]] to i5122609; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP4]], 02610; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i64> [[TMP2]] to i5122611; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP5]], 02612; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]2613; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]2614; CHECK: 6:2615; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]2616; CHECK-NEXT: unreachable2617; CHECK: 7:2618; CHECK-NEXT: [[TMP8:%.*]] = call <8 x double> @llvm.x86.avx512.mul.pd.512(<8 x double> [[A0:%.*]], <8 x double> [[A1:%.*]], i32 10)2619; CHECK-NEXT: [[TMP9:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>2620; CHECK-NEXT: [[TMP10:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>2621; CHECK-NEXT: [[TMP11:%.*]] = select <8 x i1> [[TMP10]], <8 x i64> zeroinitializer, <8 x i64> zeroinitializer2622; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x double> [[TMP8]] to <8 x i64>2623; CHECK-NEXT: [[TMP13:%.*]] = xor <8 x i64> [[TMP12]], zeroinitializer2624; CHECK-NEXT: [[TMP14:%.*]] = or <8 x i64> [[TMP13]], zeroinitializer2625; CHECK-NEXT: [[TMP15:%.*]] = or <8 x i64> [[TMP14]], zeroinitializer2626; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP9]], <8 x i64> [[TMP15]], <8 x i64> [[TMP11]]2627; CHECK-NEXT: [[TMP16:%.*]] = select <8 x i1> [[TMP10]], <8 x double> [[TMP8]], <8 x double> zeroinitializer2628; CHECK-NEXT: store <8 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82629; CHECK-NEXT: ret <8 x double> [[TMP16]]2630;2631 %1 = call <8 x double> @llvm.x86.avx512.mul.pd.512(<8 x double> %a0, <8 x double> %a1, i32 10)2632 %2 = bitcast i8 %mask to <8 x i1>2633 %3 = select <8 x i1> %2, <8 x double> %1, <8 x double> zeroinitializer2634 ret <8 x double> %32635}2636 2637define <8 x double> @test_vmulpd_mask_rz(<8 x double> %a0, <8 x double> %a1, i8 %mask) #0 {2638; CHECK-LABEL: @test_vmulpd_mask_rz(2639; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 82640; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82641; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 82642; CHECK-NEXT: call void @llvm.donothing()2643; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i64> [[TMP1]] to i5122644; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP4]], 02645; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i64> [[TMP2]] to i5122646; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP5]], 02647; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]2648; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]2649; CHECK: 6:2650; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]2651; CHECK-NEXT: unreachable2652; CHECK: 7:2653; CHECK-NEXT: [[TMP8:%.*]] = call <8 x double> @llvm.x86.avx512.mul.pd.512(<8 x double> [[A0:%.*]], <8 x double> [[A1:%.*]], i32 11)2654; CHECK-NEXT: [[TMP9:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>2655; CHECK-NEXT: [[TMP10:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>2656; CHECK-NEXT: [[TMP11:%.*]] = select <8 x i1> [[TMP10]], <8 x i64> zeroinitializer, <8 x i64> zeroinitializer2657; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x double> [[TMP8]] to <8 x i64>2658; CHECK-NEXT: [[TMP13:%.*]] = xor <8 x i64> [[TMP12]], zeroinitializer2659; CHECK-NEXT: [[TMP14:%.*]] = or <8 x i64> [[TMP13]], zeroinitializer2660; CHECK-NEXT: [[TMP15:%.*]] = or <8 x i64> [[TMP14]], zeroinitializer2661; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP9]], <8 x i64> [[TMP15]], <8 x i64> [[TMP11]]2662; CHECK-NEXT: [[TMP16:%.*]] = select <8 x i1> [[TMP10]], <8 x double> [[TMP8]], <8 x double> zeroinitializer2663; CHECK-NEXT: store <8 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82664; CHECK-NEXT: ret <8 x double> [[TMP16]]2665;2666 %1 = call <8 x double> @llvm.x86.avx512.mul.pd.512(<8 x double> %a0, <8 x double> %a1, i32 11)2667 %2 = bitcast i8 %mask to <8 x i1>2668 %3 = select <8 x i1> %2, <8 x double> %1, <8 x double> zeroinitializer2669 ret <8 x double> %32670}2671 2672define <16 x float> @test_mm512_maskz_add_round_ps_rn_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) #0 {2673; CHECK-LABEL: @test_mm512_maskz_add_round_ps_rn_sae(2674; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 82675; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82676; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 82677; CHECK-NEXT: call void @llvm.donothing()2678; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP1]] to i5122679; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP4]], 02680; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP2]] to i5122681; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP5]], 02682; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]2683; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]2684; CHECK: 6:2685; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]2686; CHECK-NEXT: unreachable2687; CHECK: 7:2688; CHECK-NEXT: [[TMP8:%.*]] = call <16 x float> @llvm.x86.avx512.add.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 8)2689; CHECK-NEXT: [[TMP9:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>2690; CHECK-NEXT: [[TMP10:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>2691; CHECK-NEXT: [[TMP11:%.*]] = select <16 x i1> [[TMP10]], <16 x i32> zeroinitializer, <16 x i32> zeroinitializer2692; CHECK-NEXT: [[TMP12:%.*]] = bitcast <16 x float> [[TMP8]] to <16 x i32>2693; CHECK-NEXT: [[TMP13:%.*]] = xor <16 x i32> [[TMP12]], zeroinitializer2694; CHECK-NEXT: [[TMP14:%.*]] = or <16 x i32> [[TMP13]], zeroinitializer2695; CHECK-NEXT: [[TMP15:%.*]] = or <16 x i32> [[TMP14]], zeroinitializer2696; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP9]], <16 x i32> [[TMP15]], <16 x i32> [[TMP11]]2697; CHECK-NEXT: [[TMP16:%.*]] = select <16 x i1> [[TMP10]], <16 x float> [[TMP8]], <16 x float> zeroinitializer2698; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82699; CHECK-NEXT: ret <16 x float> [[TMP16]]2700;2701 %1 = call <16 x float> @llvm.x86.avx512.add.ps.512(<16 x float> %a0, <16 x float> %a1, i32 8)2702 %2 = bitcast i16 %mask to <16 x i1>2703 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> zeroinitializer2704 ret <16 x float> %32705}2706 2707define <16 x float> @test_mm512_maskz_add_round_ps_rd_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) #0 {2708; CHECK-LABEL: @test_mm512_maskz_add_round_ps_rd_sae(2709; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 82710; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82711; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 82712; CHECK-NEXT: call void @llvm.donothing()2713; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP1]] to i5122714; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP4]], 02715; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP2]] to i5122716; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP5]], 02717; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]2718; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]2719; CHECK: 6:2720; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]2721; CHECK-NEXT: unreachable2722; CHECK: 7:2723; CHECK-NEXT: [[TMP8:%.*]] = call <16 x float> @llvm.x86.avx512.add.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 9)2724; CHECK-NEXT: [[TMP9:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>2725; CHECK-NEXT: [[TMP10:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>2726; CHECK-NEXT: [[TMP11:%.*]] = select <16 x i1> [[TMP10]], <16 x i32> zeroinitializer, <16 x i32> zeroinitializer2727; CHECK-NEXT: [[TMP12:%.*]] = bitcast <16 x float> [[TMP8]] to <16 x i32>2728; CHECK-NEXT: [[TMP13:%.*]] = xor <16 x i32> [[TMP12]], zeroinitializer2729; CHECK-NEXT: [[TMP14:%.*]] = or <16 x i32> [[TMP13]], zeroinitializer2730; CHECK-NEXT: [[TMP15:%.*]] = or <16 x i32> [[TMP14]], zeroinitializer2731; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP9]], <16 x i32> [[TMP15]], <16 x i32> [[TMP11]]2732; CHECK-NEXT: [[TMP16:%.*]] = select <16 x i1> [[TMP10]], <16 x float> [[TMP8]], <16 x float> zeroinitializer2733; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82734; CHECK-NEXT: ret <16 x float> [[TMP16]]2735;2736 %1 = call <16 x float> @llvm.x86.avx512.add.ps.512(<16 x float> %a0, <16 x float> %a1, i32 9)2737 %2 = bitcast i16 %mask to <16 x i1>2738 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> zeroinitializer2739 ret <16 x float> %32740}2741 2742define <16 x float> @test_mm512_maskz_add_round_ps_ru_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) #0 {2743; CHECK-LABEL: @test_mm512_maskz_add_round_ps_ru_sae(2744; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 82745; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82746; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 82747; CHECK-NEXT: call void @llvm.donothing()2748; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP1]] to i5122749; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP4]], 02750; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP2]] to i5122751; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP5]], 02752; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]2753; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]2754; CHECK: 6:2755; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]2756; CHECK-NEXT: unreachable2757; CHECK: 7:2758; CHECK-NEXT: [[TMP8:%.*]] = call <16 x float> @llvm.x86.avx512.add.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 10)2759; CHECK-NEXT: [[TMP9:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>2760; CHECK-NEXT: [[TMP10:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>2761; CHECK-NEXT: [[TMP11:%.*]] = select <16 x i1> [[TMP10]], <16 x i32> zeroinitializer, <16 x i32> zeroinitializer2762; CHECK-NEXT: [[TMP12:%.*]] = bitcast <16 x float> [[TMP8]] to <16 x i32>2763; CHECK-NEXT: [[TMP13:%.*]] = xor <16 x i32> [[TMP12]], zeroinitializer2764; CHECK-NEXT: [[TMP14:%.*]] = or <16 x i32> [[TMP13]], zeroinitializer2765; CHECK-NEXT: [[TMP15:%.*]] = or <16 x i32> [[TMP14]], zeroinitializer2766; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP9]], <16 x i32> [[TMP15]], <16 x i32> [[TMP11]]2767; CHECK-NEXT: [[TMP16:%.*]] = select <16 x i1> [[TMP10]], <16 x float> [[TMP8]], <16 x float> zeroinitializer2768; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82769; CHECK-NEXT: ret <16 x float> [[TMP16]]2770;2771 %1 = call <16 x float> @llvm.x86.avx512.add.ps.512(<16 x float> %a0, <16 x float> %a1, i32 10)2772 %2 = bitcast i16 %mask to <16 x i1>2773 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> zeroinitializer2774 ret <16 x float> %32775}2776 2777define <16 x float> @test_mm512_maskz_add_round_ps_rz_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) #0 {2778; CHECK-LABEL: @test_mm512_maskz_add_round_ps_rz_sae(2779; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 82780; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82781; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 82782; CHECK-NEXT: call void @llvm.donothing()2783; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP1]] to i5122784; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP4]], 02785; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP2]] to i5122786; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP5]], 02787; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]2788; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]2789; CHECK: 6:2790; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]2791; CHECK-NEXT: unreachable2792; CHECK: 7:2793; CHECK-NEXT: [[TMP8:%.*]] = call <16 x float> @llvm.x86.avx512.add.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 11)2794; CHECK-NEXT: [[TMP9:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>2795; CHECK-NEXT: [[TMP10:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>2796; CHECK-NEXT: [[TMP11:%.*]] = select <16 x i1> [[TMP10]], <16 x i32> zeroinitializer, <16 x i32> zeroinitializer2797; CHECK-NEXT: [[TMP12:%.*]] = bitcast <16 x float> [[TMP8]] to <16 x i32>2798; CHECK-NEXT: [[TMP13:%.*]] = xor <16 x i32> [[TMP12]], zeroinitializer2799; CHECK-NEXT: [[TMP14:%.*]] = or <16 x i32> [[TMP13]], zeroinitializer2800; CHECK-NEXT: [[TMP15:%.*]] = or <16 x i32> [[TMP14]], zeroinitializer2801; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP9]], <16 x i32> [[TMP15]], <16 x i32> [[TMP11]]2802; CHECK-NEXT: [[TMP16:%.*]] = select <16 x i1> [[TMP10]], <16 x float> [[TMP8]], <16 x float> zeroinitializer2803; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82804; CHECK-NEXT: ret <16 x float> [[TMP16]]2805;2806 %1 = call <16 x float> @llvm.x86.avx512.add.ps.512(<16 x float> %a0, <16 x float> %a1, i32 11)2807 %2 = bitcast i16 %mask to <16 x i1>2808 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> zeroinitializer2809 ret <16 x float> %32810}2811 2812define <16 x float> @test_mm512_maskz_add_round_ps_current(<16 x float> %a0, <16 x float> %a1, i16 %mask) #0 {2813; CHECK-LABEL: @test_mm512_maskz_add_round_ps_current(2814; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 82815; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82816; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 82817; CHECK-NEXT: call void @llvm.donothing()2818; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP1]] to i5122819; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP4]], 02820; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP2]] to i5122821; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP5]], 02822; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]2823; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]2824; CHECK: 6:2825; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]2826; CHECK-NEXT: unreachable2827; CHECK: 7:2828; CHECK-NEXT: [[TMP8:%.*]] = call <16 x float> @llvm.x86.avx512.add.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 4)2829; CHECK-NEXT: [[TMP9:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>2830; CHECK-NEXT: [[TMP10:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>2831; CHECK-NEXT: [[TMP11:%.*]] = select <16 x i1> [[TMP10]], <16 x i32> zeroinitializer, <16 x i32> zeroinitializer2832; CHECK-NEXT: [[TMP12:%.*]] = bitcast <16 x float> [[TMP8]] to <16 x i32>2833; CHECK-NEXT: [[TMP13:%.*]] = xor <16 x i32> [[TMP12]], zeroinitializer2834; CHECK-NEXT: [[TMP14:%.*]] = or <16 x i32> [[TMP13]], zeroinitializer2835; CHECK-NEXT: [[TMP15:%.*]] = or <16 x i32> [[TMP14]], zeroinitializer2836; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP9]], <16 x i32> [[TMP15]], <16 x i32> [[TMP11]]2837; CHECK-NEXT: [[TMP16:%.*]] = select <16 x i1> [[TMP10]], <16 x float> [[TMP8]], <16 x float> zeroinitializer2838; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82839; CHECK-NEXT: ret <16 x float> [[TMP16]]2840;2841 %1 = call <16 x float> @llvm.x86.avx512.add.ps.512(<16 x float> %a0, <16 x float> %a1, i32 4)2842 %2 = bitcast i16 %mask to <16 x i1>2843 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> zeroinitializer2844 ret <16 x float> %32845}2846 2847define <16 x float> @test_mm512_mask_add_round_ps_rn_sae(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) #0 {2848; CHECK-LABEL: @test_mm512_mask_add_round_ps_rn_sae(2849; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 82850; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82851; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 82852; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 82853; CHECK-NEXT: call void @llvm.donothing()2854; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP1]] to i5122855; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP5]], 02856; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i32> [[TMP2]] to i5122857; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP6]], 02858; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]2859; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]2860; CHECK: 7:2861; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]2862; CHECK-NEXT: unreachable2863; CHECK: 8:2864; CHECK-NEXT: [[TMP9:%.*]] = call <16 x float> @llvm.x86.avx512.add.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 8)2865; CHECK-NEXT: [[TMP10:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>2866; CHECK-NEXT: [[TMP11:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>2867; CHECK-NEXT: [[TMP12:%.*]] = select <16 x i1> [[TMP11]], <16 x i32> zeroinitializer, <16 x i32> [[TMP4]]2868; CHECK-NEXT: [[TMP13:%.*]] = bitcast <16 x float> [[TMP9]] to <16 x i32>2869; CHECK-NEXT: [[TMP14:%.*]] = bitcast <16 x float> [[SRC:%.*]] to <16 x i32>2870; CHECK-NEXT: [[TMP15:%.*]] = xor <16 x i32> [[TMP13]], [[TMP14]]2871; CHECK-NEXT: [[TMP16:%.*]] = or <16 x i32> [[TMP15]], zeroinitializer2872; CHECK-NEXT: [[TMP17:%.*]] = or <16 x i32> [[TMP16]], [[TMP4]]2873; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP10]], <16 x i32> [[TMP17]], <16 x i32> [[TMP12]]2874; CHECK-NEXT: [[TMP18:%.*]] = select <16 x i1> [[TMP11]], <16 x float> [[TMP9]], <16 x float> [[SRC]]2875; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82876; CHECK-NEXT: ret <16 x float> [[TMP18]]2877;2878 %1 = call <16 x float> @llvm.x86.avx512.add.ps.512(<16 x float> %a0, <16 x float> %a1, i32 8)2879 %2 = bitcast i16 %mask to <16 x i1>2880 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> %src2881 ret <16 x float> %32882}2883 2884define <16 x float> @test_mm512_mask_add_round_ps_rd_sae(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) #0 {2885; CHECK-LABEL: @test_mm512_mask_add_round_ps_rd_sae(2886; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 82887; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82888; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 82889; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 82890; CHECK-NEXT: call void @llvm.donothing()2891; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP1]] to i5122892; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP5]], 02893; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i32> [[TMP2]] to i5122894; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP6]], 02895; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]2896; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]2897; CHECK: 7:2898; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]2899; CHECK-NEXT: unreachable2900; CHECK: 8:2901; CHECK-NEXT: [[TMP9:%.*]] = call <16 x float> @llvm.x86.avx512.add.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 9)2902; CHECK-NEXT: [[TMP10:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>2903; CHECK-NEXT: [[TMP11:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>2904; CHECK-NEXT: [[TMP12:%.*]] = select <16 x i1> [[TMP11]], <16 x i32> zeroinitializer, <16 x i32> [[TMP4]]2905; CHECK-NEXT: [[TMP13:%.*]] = bitcast <16 x float> [[TMP9]] to <16 x i32>2906; CHECK-NEXT: [[TMP14:%.*]] = bitcast <16 x float> [[SRC:%.*]] to <16 x i32>2907; CHECK-NEXT: [[TMP15:%.*]] = xor <16 x i32> [[TMP13]], [[TMP14]]2908; CHECK-NEXT: [[TMP16:%.*]] = or <16 x i32> [[TMP15]], zeroinitializer2909; CHECK-NEXT: [[TMP17:%.*]] = or <16 x i32> [[TMP16]], [[TMP4]]2910; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP10]], <16 x i32> [[TMP17]], <16 x i32> [[TMP12]]2911; CHECK-NEXT: [[TMP18:%.*]] = select <16 x i1> [[TMP11]], <16 x float> [[TMP9]], <16 x float> [[SRC]]2912; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82913; CHECK-NEXT: ret <16 x float> [[TMP18]]2914;2915 %1 = call <16 x float> @llvm.x86.avx512.add.ps.512(<16 x float> %a0, <16 x float> %a1, i32 9)2916 %2 = bitcast i16 %mask to <16 x i1>2917 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> %src2918 ret <16 x float> %32919}2920 2921define <16 x float> @test_mm512_mask_add_round_ps_ru_sae(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) #0 {2922; CHECK-LABEL: @test_mm512_mask_add_round_ps_ru_sae(2923; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 82924; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82925; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 82926; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 82927; CHECK-NEXT: call void @llvm.donothing()2928; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP1]] to i5122929; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP5]], 02930; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i32> [[TMP2]] to i5122931; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP6]], 02932; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]2933; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]2934; CHECK: 7:2935; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]2936; CHECK-NEXT: unreachable2937; CHECK: 8:2938; CHECK-NEXT: [[TMP9:%.*]] = call <16 x float> @llvm.x86.avx512.add.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 10)2939; CHECK-NEXT: [[TMP10:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>2940; CHECK-NEXT: [[TMP11:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>2941; CHECK-NEXT: [[TMP12:%.*]] = select <16 x i1> [[TMP11]], <16 x i32> zeroinitializer, <16 x i32> [[TMP4]]2942; CHECK-NEXT: [[TMP13:%.*]] = bitcast <16 x float> [[TMP9]] to <16 x i32>2943; CHECK-NEXT: [[TMP14:%.*]] = bitcast <16 x float> [[SRC:%.*]] to <16 x i32>2944; CHECK-NEXT: [[TMP15:%.*]] = xor <16 x i32> [[TMP13]], [[TMP14]]2945; CHECK-NEXT: [[TMP16:%.*]] = or <16 x i32> [[TMP15]], zeroinitializer2946; CHECK-NEXT: [[TMP17:%.*]] = or <16 x i32> [[TMP16]], [[TMP4]]2947; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP10]], <16 x i32> [[TMP17]], <16 x i32> [[TMP12]]2948; CHECK-NEXT: [[TMP18:%.*]] = select <16 x i1> [[TMP11]], <16 x float> [[TMP9]], <16 x float> [[SRC]]2949; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82950; CHECK-NEXT: ret <16 x float> [[TMP18]]2951;2952 %1 = call <16 x float> @llvm.x86.avx512.add.ps.512(<16 x float> %a0, <16 x float> %a1, i32 10)2953 %2 = bitcast i16 %mask to <16 x i1>2954 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> %src2955 ret <16 x float> %32956}2957 2958define <16 x float> @test_mm512_mask_add_round_ps_rz_sae(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) #0 {2959; CHECK-LABEL: @test_mm512_mask_add_round_ps_rz_sae(2960; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 82961; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82962; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 82963; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 82964; CHECK-NEXT: call void @llvm.donothing()2965; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP1]] to i5122966; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP5]], 02967; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i32> [[TMP2]] to i5122968; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP6]], 02969; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]2970; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]2971; CHECK: 7:2972; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]2973; CHECK-NEXT: unreachable2974; CHECK: 8:2975; CHECK-NEXT: [[TMP9:%.*]] = call <16 x float> @llvm.x86.avx512.add.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 11)2976; CHECK-NEXT: [[TMP10:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>2977; CHECK-NEXT: [[TMP11:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>2978; CHECK-NEXT: [[TMP12:%.*]] = select <16 x i1> [[TMP11]], <16 x i32> zeroinitializer, <16 x i32> [[TMP4]]2979; CHECK-NEXT: [[TMP13:%.*]] = bitcast <16 x float> [[TMP9]] to <16 x i32>2980; CHECK-NEXT: [[TMP14:%.*]] = bitcast <16 x float> [[SRC:%.*]] to <16 x i32>2981; CHECK-NEXT: [[TMP15:%.*]] = xor <16 x i32> [[TMP13]], [[TMP14]]2982; CHECK-NEXT: [[TMP16:%.*]] = or <16 x i32> [[TMP15]], zeroinitializer2983; CHECK-NEXT: [[TMP17:%.*]] = or <16 x i32> [[TMP16]], [[TMP4]]2984; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP10]], <16 x i32> [[TMP17]], <16 x i32> [[TMP12]]2985; CHECK-NEXT: [[TMP18:%.*]] = select <16 x i1> [[TMP11]], <16 x float> [[TMP9]], <16 x float> [[SRC]]2986; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82987; CHECK-NEXT: ret <16 x float> [[TMP18]]2988;2989 %1 = call <16 x float> @llvm.x86.avx512.add.ps.512(<16 x float> %a0, <16 x float> %a1, i32 11)2990 %2 = bitcast i16 %mask to <16 x i1>2991 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> %src2992 ret <16 x float> %32993}2994 2995define <16 x float> @test_mm512_mask_add_round_ps_current(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) #0 {2996; CHECK-LABEL: @test_mm512_mask_add_round_ps_current(2997; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 82998; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82999; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 83000; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 83001; CHECK-NEXT: call void @llvm.donothing()3002; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP1]] to i5123003; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP5]], 03004; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i32> [[TMP2]] to i5123005; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP6]], 03006; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3007; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]3008; CHECK: 7:3009; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]3010; CHECK-NEXT: unreachable3011; CHECK: 8:3012; CHECK-NEXT: [[TMP9:%.*]] = call <16 x float> @llvm.x86.avx512.add.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 4)3013; CHECK-NEXT: [[TMP10:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>3014; CHECK-NEXT: [[TMP11:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>3015; CHECK-NEXT: [[TMP12:%.*]] = select <16 x i1> [[TMP11]], <16 x i32> zeroinitializer, <16 x i32> [[TMP4]]3016; CHECK-NEXT: [[TMP13:%.*]] = bitcast <16 x float> [[TMP9]] to <16 x i32>3017; CHECK-NEXT: [[TMP14:%.*]] = bitcast <16 x float> [[SRC:%.*]] to <16 x i32>3018; CHECK-NEXT: [[TMP15:%.*]] = xor <16 x i32> [[TMP13]], [[TMP14]]3019; CHECK-NEXT: [[TMP16:%.*]] = or <16 x i32> [[TMP15]], zeroinitializer3020; CHECK-NEXT: [[TMP17:%.*]] = or <16 x i32> [[TMP16]], [[TMP4]]3021; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP10]], <16 x i32> [[TMP17]], <16 x i32> [[TMP12]]3022; CHECK-NEXT: [[TMP18:%.*]] = select <16 x i1> [[TMP11]], <16 x float> [[TMP9]], <16 x float> [[SRC]]3023; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 83024; CHECK-NEXT: ret <16 x float> [[TMP18]]3025;3026 %1 = call <16 x float> @llvm.x86.avx512.add.ps.512(<16 x float> %a0, <16 x float> %a1, i32 4)3027 %2 = bitcast i16 %mask to <16 x i1>3028 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> %src3029 ret <16 x float> %33030}3031 3032define <16 x float> @test_mm512_add_round_ps_rn_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) #0 {3033; CHECK-LABEL: @test_mm512_add_round_ps_rn_sae(3034; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 83035; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 83036; CHECK-NEXT: call void @llvm.donothing()3037; CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i32> [[TMP1]] to i5123038; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP3]], 03039; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP2]] to i5123040; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 03041; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3042; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]3043; CHECK: 5:3044; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]3045; CHECK-NEXT: unreachable3046; CHECK: 6:3047; CHECK-NEXT: [[TMP7:%.*]] = call <16 x float> @llvm.x86.avx512.add.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 8)3048; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 83049; CHECK-NEXT: ret <16 x float> [[TMP7]]3050;3051 %1 = call <16 x float> @llvm.x86.avx512.add.ps.512(<16 x float> %a0, <16 x float> %a1, i32 8)3052 ret <16 x float> %13053}3054 3055define <16 x float> @test_mm512_add_round_ps_rd_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) #0 {3056; CHECK-LABEL: @test_mm512_add_round_ps_rd_sae(3057; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 83058; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 83059; CHECK-NEXT: call void @llvm.donothing()3060; CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i32> [[TMP1]] to i5123061; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP3]], 03062; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP2]] to i5123063; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 03064; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3065; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]3066; CHECK: 5:3067; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]3068; CHECK-NEXT: unreachable3069; CHECK: 6:3070; CHECK-NEXT: [[TMP7:%.*]] = call <16 x float> @llvm.x86.avx512.add.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 9)3071; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 83072; CHECK-NEXT: ret <16 x float> [[TMP7]]3073;3074 %1 = call <16 x float> @llvm.x86.avx512.add.ps.512(<16 x float> %a0, <16 x float> %a1, i32 9)3075 ret <16 x float> %13076}3077 3078define <16 x float> @test_mm512_add_round_ps_ru_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) #0 {3079; CHECK-LABEL: @test_mm512_add_round_ps_ru_sae(3080; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 83081; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 83082; CHECK-NEXT: call void @llvm.donothing()3083; CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i32> [[TMP1]] to i5123084; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP3]], 03085; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP2]] to i5123086; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 03087; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3088; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]3089; CHECK: 5:3090; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]3091; CHECK-NEXT: unreachable3092; CHECK: 6:3093; CHECK-NEXT: [[TMP7:%.*]] = call <16 x float> @llvm.x86.avx512.add.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 10)3094; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 83095; CHECK-NEXT: ret <16 x float> [[TMP7]]3096;3097 %1 = call <16 x float> @llvm.x86.avx512.add.ps.512(<16 x float> %a0, <16 x float> %a1, i32 10)3098 ret <16 x float> %13099}3100 3101define <16 x float> @test_mm512_add_round_ps_rz_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) #0 {3102; CHECK-LABEL: @test_mm512_add_round_ps_rz_sae(3103; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 83104; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 83105; CHECK-NEXT: call void @llvm.donothing()3106; CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i32> [[TMP1]] to i5123107; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP3]], 03108; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP2]] to i5123109; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 03110; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3111; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]3112; CHECK: 5:3113; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]3114; CHECK-NEXT: unreachable3115; CHECK: 6:3116; CHECK-NEXT: [[TMP7:%.*]] = call <16 x float> @llvm.x86.avx512.add.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 11)3117; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 83118; CHECK-NEXT: ret <16 x float> [[TMP7]]3119;3120 %1 = call <16 x float> @llvm.x86.avx512.add.ps.512(<16 x float> %a0, <16 x float> %a1, i32 11)3121 ret <16 x float> %13122}3123 3124define <16 x float> @test_mm512_add_round_ps_current(<16 x float> %a0, <16 x float> %a1, i16 %mask) #0 {3125; CHECK-LABEL: @test_mm512_add_round_ps_current(3126; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 83127; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 83128; CHECK-NEXT: call void @llvm.donothing()3129; CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i32> [[TMP1]] to i5123130; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP3]], 03131; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP2]] to i5123132; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 03133; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3134; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]3135; CHECK: 5:3136; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]3137; CHECK-NEXT: unreachable3138; CHECK: 6:3139; CHECK-NEXT: [[TMP7:%.*]] = call <16 x float> @llvm.x86.avx512.add.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 4)3140; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 83141; CHECK-NEXT: ret <16 x float> [[TMP7]]3142;3143 %1 = call <16 x float> @llvm.x86.avx512.add.ps.512(<16 x float> %a0, <16 x float> %a1, i32 4)3144 ret <16 x float> %13145}3146declare <16 x float> @llvm.x86.avx512.add.ps.512(<16 x float>, <16 x float>, i32)3147 3148define <16 x float> @test_mm512_mask_sub_round_ps_rn_sae(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) #0 {3149; CHECK-LABEL: @test_mm512_mask_sub_round_ps_rn_sae(3150; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 83151; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 83152; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 83153; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 83154; CHECK-NEXT: call void @llvm.donothing()3155; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP1]] to i5123156; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP5]], 03157; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i32> [[TMP2]] to i5123158; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP6]], 03159; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3160; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]3161; CHECK: 7:3162; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]3163; CHECK-NEXT: unreachable3164; CHECK: 8:3165; CHECK-NEXT: [[TMP9:%.*]] = call <16 x float> @llvm.x86.avx512.sub.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 8)3166; CHECK-NEXT: [[TMP10:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>3167; CHECK-NEXT: [[TMP11:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>3168; CHECK-NEXT: [[TMP12:%.*]] = select <16 x i1> [[TMP11]], <16 x i32> zeroinitializer, <16 x i32> [[TMP4]]3169; CHECK-NEXT: [[TMP13:%.*]] = bitcast <16 x float> [[TMP9]] to <16 x i32>3170; CHECK-NEXT: [[TMP14:%.*]] = bitcast <16 x float> [[SRC:%.*]] to <16 x i32>3171; CHECK-NEXT: [[TMP15:%.*]] = xor <16 x i32> [[TMP13]], [[TMP14]]3172; CHECK-NEXT: [[TMP16:%.*]] = or <16 x i32> [[TMP15]], zeroinitializer3173; CHECK-NEXT: [[TMP17:%.*]] = or <16 x i32> [[TMP16]], [[TMP4]]3174; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP10]], <16 x i32> [[TMP17]], <16 x i32> [[TMP12]]3175; CHECK-NEXT: [[TMP18:%.*]] = select <16 x i1> [[TMP11]], <16 x float> [[TMP9]], <16 x float> [[SRC]]3176; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 83177; CHECK-NEXT: ret <16 x float> [[TMP18]]3178;3179 %1 = call <16 x float> @llvm.x86.avx512.sub.ps.512(<16 x float> %a0, <16 x float> %a1, i32 8)3180 %2 = bitcast i16 %mask to <16 x i1>3181 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> %src3182 ret <16 x float> %33183}3184 3185define <16 x float> @test_mm512_mask_sub_round_ps_rd_sae(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) #0 {3186; CHECK-LABEL: @test_mm512_mask_sub_round_ps_rd_sae(3187; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 83188; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 83189; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 83190; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 83191; CHECK-NEXT: call void @llvm.donothing()3192; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP1]] to i5123193; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP5]], 03194; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i32> [[TMP2]] to i5123195; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP6]], 03196; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3197; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]3198; CHECK: 7:3199; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]3200; CHECK-NEXT: unreachable3201; CHECK: 8:3202; CHECK-NEXT: [[TMP9:%.*]] = call <16 x float> @llvm.x86.avx512.sub.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 9)3203; CHECK-NEXT: [[TMP10:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>3204; CHECK-NEXT: [[TMP11:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>3205; CHECK-NEXT: [[TMP12:%.*]] = select <16 x i1> [[TMP11]], <16 x i32> zeroinitializer, <16 x i32> [[TMP4]]3206; CHECK-NEXT: [[TMP13:%.*]] = bitcast <16 x float> [[TMP9]] to <16 x i32>3207; CHECK-NEXT: [[TMP14:%.*]] = bitcast <16 x float> [[SRC:%.*]] to <16 x i32>3208; CHECK-NEXT: [[TMP15:%.*]] = xor <16 x i32> [[TMP13]], [[TMP14]]3209; CHECK-NEXT: [[TMP16:%.*]] = or <16 x i32> [[TMP15]], zeroinitializer3210; CHECK-NEXT: [[TMP17:%.*]] = or <16 x i32> [[TMP16]], [[TMP4]]3211; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP10]], <16 x i32> [[TMP17]], <16 x i32> [[TMP12]]3212; CHECK-NEXT: [[TMP18:%.*]] = select <16 x i1> [[TMP11]], <16 x float> [[TMP9]], <16 x float> [[SRC]]3213; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 83214; CHECK-NEXT: ret <16 x float> [[TMP18]]3215;3216 %1 = call <16 x float> @llvm.x86.avx512.sub.ps.512(<16 x float> %a0, <16 x float> %a1, i32 9)3217 %2 = bitcast i16 %mask to <16 x i1>3218 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> %src3219 ret <16 x float> %33220}3221 3222define <16 x float> @test_mm512_mask_sub_round_ps_ru_sae(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) #0 {3223; CHECK-LABEL: @test_mm512_mask_sub_round_ps_ru_sae(3224; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 83225; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 83226; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 83227; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 83228; CHECK-NEXT: call void @llvm.donothing()3229; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP1]] to i5123230; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP5]], 03231; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i32> [[TMP2]] to i5123232; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP6]], 03233; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3234; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]3235; CHECK: 7:3236; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]3237; CHECK-NEXT: unreachable3238; CHECK: 8:3239; CHECK-NEXT: [[TMP9:%.*]] = call <16 x float> @llvm.x86.avx512.sub.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 10)3240; CHECK-NEXT: [[TMP10:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>3241; CHECK-NEXT: [[TMP11:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>3242; CHECK-NEXT: [[TMP12:%.*]] = select <16 x i1> [[TMP11]], <16 x i32> zeroinitializer, <16 x i32> [[TMP4]]3243; CHECK-NEXT: [[TMP13:%.*]] = bitcast <16 x float> [[TMP9]] to <16 x i32>3244; CHECK-NEXT: [[TMP14:%.*]] = bitcast <16 x float> [[SRC:%.*]] to <16 x i32>3245; CHECK-NEXT: [[TMP15:%.*]] = xor <16 x i32> [[TMP13]], [[TMP14]]3246; CHECK-NEXT: [[TMP16:%.*]] = or <16 x i32> [[TMP15]], zeroinitializer3247; CHECK-NEXT: [[TMP17:%.*]] = or <16 x i32> [[TMP16]], [[TMP4]]3248; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP10]], <16 x i32> [[TMP17]], <16 x i32> [[TMP12]]3249; CHECK-NEXT: [[TMP18:%.*]] = select <16 x i1> [[TMP11]], <16 x float> [[TMP9]], <16 x float> [[SRC]]3250; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 83251; CHECK-NEXT: ret <16 x float> [[TMP18]]3252;3253 %1 = call <16 x float> @llvm.x86.avx512.sub.ps.512(<16 x float> %a0, <16 x float> %a1, i32 10)3254 %2 = bitcast i16 %mask to <16 x i1>3255 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> %src3256 ret <16 x float> %33257}3258 3259define <16 x float> @test_mm512_mask_sub_round_ps_rz_sae(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) #0 {3260; CHECK-LABEL: @test_mm512_mask_sub_round_ps_rz_sae(3261; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 83262; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 83263; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 83264; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 83265; CHECK-NEXT: call void @llvm.donothing()3266; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP1]] to i5123267; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP5]], 03268; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i32> [[TMP2]] to i5123269; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP6]], 03270; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3271; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]3272; CHECK: 7:3273; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]3274; CHECK-NEXT: unreachable3275; CHECK: 8:3276; CHECK-NEXT: [[TMP9:%.*]] = call <16 x float> @llvm.x86.avx512.sub.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 11)3277; CHECK-NEXT: [[TMP10:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>3278; CHECK-NEXT: [[TMP11:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>3279; CHECK-NEXT: [[TMP12:%.*]] = select <16 x i1> [[TMP11]], <16 x i32> zeroinitializer, <16 x i32> [[TMP4]]3280; CHECK-NEXT: [[TMP13:%.*]] = bitcast <16 x float> [[TMP9]] to <16 x i32>3281; CHECK-NEXT: [[TMP14:%.*]] = bitcast <16 x float> [[SRC:%.*]] to <16 x i32>3282; CHECK-NEXT: [[TMP15:%.*]] = xor <16 x i32> [[TMP13]], [[TMP14]]3283; CHECK-NEXT: [[TMP16:%.*]] = or <16 x i32> [[TMP15]], zeroinitializer3284; CHECK-NEXT: [[TMP17:%.*]] = or <16 x i32> [[TMP16]], [[TMP4]]3285; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP10]], <16 x i32> [[TMP17]], <16 x i32> [[TMP12]]3286; CHECK-NEXT: [[TMP18:%.*]] = select <16 x i1> [[TMP11]], <16 x float> [[TMP9]], <16 x float> [[SRC]]3287; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 83288; CHECK-NEXT: ret <16 x float> [[TMP18]]3289;3290 %1 = call <16 x float> @llvm.x86.avx512.sub.ps.512(<16 x float> %a0, <16 x float> %a1, i32 11)3291 %2 = bitcast i16 %mask to <16 x i1>3292 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> %src3293 ret <16 x float> %33294}3295 3296define <16 x float> @test_mm512_mask_sub_round_ps_current(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) #0 {3297; CHECK-LABEL: @test_mm512_mask_sub_round_ps_current(3298; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 83299; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 83300; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 83301; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 83302; CHECK-NEXT: call void @llvm.donothing()3303; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP1]] to i5123304; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP5]], 03305; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i32> [[TMP2]] to i5123306; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP6]], 03307; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3308; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]3309; CHECK: 7:3310; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]3311; CHECK-NEXT: unreachable3312; CHECK: 8:3313; CHECK-NEXT: [[TMP9:%.*]] = call <16 x float> @llvm.x86.avx512.sub.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 4)3314; CHECK-NEXT: [[TMP10:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>3315; CHECK-NEXT: [[TMP11:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>3316; CHECK-NEXT: [[TMP12:%.*]] = select <16 x i1> [[TMP11]], <16 x i32> zeroinitializer, <16 x i32> [[TMP4]]3317; CHECK-NEXT: [[TMP13:%.*]] = bitcast <16 x float> [[TMP9]] to <16 x i32>3318; CHECK-NEXT: [[TMP14:%.*]] = bitcast <16 x float> [[SRC:%.*]] to <16 x i32>3319; CHECK-NEXT: [[TMP15:%.*]] = xor <16 x i32> [[TMP13]], [[TMP14]]3320; CHECK-NEXT: [[TMP16:%.*]] = or <16 x i32> [[TMP15]], zeroinitializer3321; CHECK-NEXT: [[TMP17:%.*]] = or <16 x i32> [[TMP16]], [[TMP4]]3322; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP10]], <16 x i32> [[TMP17]], <16 x i32> [[TMP12]]3323; CHECK-NEXT: [[TMP18:%.*]] = select <16 x i1> [[TMP11]], <16 x float> [[TMP9]], <16 x float> [[SRC]]3324; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 83325; CHECK-NEXT: ret <16 x float> [[TMP18]]3326;3327 %1 = call <16 x float> @llvm.x86.avx512.sub.ps.512(<16 x float> %a0, <16 x float> %a1, i32 4)3328 %2 = bitcast i16 %mask to <16 x i1>3329 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> %src3330 ret <16 x float> %33331}3332 3333define <16 x float> @test_mm512_sub_round_ps_rn_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) #0 {3334; CHECK-LABEL: @test_mm512_sub_round_ps_rn_sae(3335; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 83336; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 83337; CHECK-NEXT: call void @llvm.donothing()3338; CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i32> [[TMP1]] to i5123339; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP3]], 03340; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP2]] to i5123341; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 03342; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3343; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]3344; CHECK: 5:3345; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]3346; CHECK-NEXT: unreachable3347; CHECK: 6:3348; CHECK-NEXT: [[TMP7:%.*]] = call <16 x float> @llvm.x86.avx512.sub.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 8)3349; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 83350; CHECK-NEXT: ret <16 x float> [[TMP7]]3351;3352 %1 = call <16 x float> @llvm.x86.avx512.sub.ps.512(<16 x float> %a0, <16 x float> %a1, i32 8)3353 ret <16 x float> %13354}3355 3356define <16 x float> @test_mm512_sub_round_ps_rd_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) #0 {3357; CHECK-LABEL: @test_mm512_sub_round_ps_rd_sae(3358; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 83359; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 83360; CHECK-NEXT: call void @llvm.donothing()3361; CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i32> [[TMP1]] to i5123362; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP3]], 03363; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP2]] to i5123364; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 03365; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3366; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]3367; CHECK: 5:3368; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]3369; CHECK-NEXT: unreachable3370; CHECK: 6:3371; CHECK-NEXT: [[TMP7:%.*]] = call <16 x float> @llvm.x86.avx512.sub.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 9)3372; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 83373; CHECK-NEXT: ret <16 x float> [[TMP7]]3374;3375 %1 = call <16 x float> @llvm.x86.avx512.sub.ps.512(<16 x float> %a0, <16 x float> %a1, i32 9)3376 ret <16 x float> %13377}3378 3379define <16 x float> @test_mm512_sub_round_ps_ru_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) #0 {3380; CHECK-LABEL: @test_mm512_sub_round_ps_ru_sae(3381; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 83382; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 83383; CHECK-NEXT: call void @llvm.donothing()3384; CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i32> [[TMP1]] to i5123385; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP3]], 03386; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP2]] to i5123387; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 03388; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3389; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]3390; CHECK: 5:3391; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]3392; CHECK-NEXT: unreachable3393; CHECK: 6:3394; CHECK-NEXT: [[TMP7:%.*]] = call <16 x float> @llvm.x86.avx512.sub.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 10)3395; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 83396; CHECK-NEXT: ret <16 x float> [[TMP7]]3397;3398 %1 = call <16 x float> @llvm.x86.avx512.sub.ps.512(<16 x float> %a0, <16 x float> %a1, i32 10)3399 ret <16 x float> %13400}3401 3402define <16 x float> @test_mm512_sub_round_ps_rz_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) #0 {3403; CHECK-LABEL: @test_mm512_sub_round_ps_rz_sae(3404; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 83405; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 83406; CHECK-NEXT: call void @llvm.donothing()3407; CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i32> [[TMP1]] to i5123408; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP3]], 03409; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP2]] to i5123410; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 03411; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3412; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]3413; CHECK: 5:3414; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]3415; CHECK-NEXT: unreachable3416; CHECK: 6:3417; CHECK-NEXT: [[TMP7:%.*]] = call <16 x float> @llvm.x86.avx512.sub.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 11)3418; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 83419; CHECK-NEXT: ret <16 x float> [[TMP7]]3420;3421 %1 = call <16 x float> @llvm.x86.avx512.sub.ps.512(<16 x float> %a0, <16 x float> %a1, i32 11)3422 ret <16 x float> %13423}3424 3425define <16 x float> @test_mm512_sub_round_ps_current(<16 x float> %a0, <16 x float> %a1, i16 %mask) #0 {3426; CHECK-LABEL: @test_mm512_sub_round_ps_current(3427; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 83428; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 83429; CHECK-NEXT: call void @llvm.donothing()3430; CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i32> [[TMP1]] to i5123431; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP3]], 03432; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP2]] to i5123433; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 03434; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3435; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]3436; CHECK: 5:3437; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]3438; CHECK-NEXT: unreachable3439; CHECK: 6:3440; CHECK-NEXT: [[TMP7:%.*]] = call <16 x float> @llvm.x86.avx512.sub.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 4)3441; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 83442; CHECK-NEXT: ret <16 x float> [[TMP7]]3443;3444 %1 = call <16 x float> @llvm.x86.avx512.sub.ps.512(<16 x float> %a0, <16 x float> %a1, i32 4)3445 ret <16 x float> %13446}3447 3448define <16 x float> @test_mm512_maskz_div_round_ps_rn_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) #0 {3449; CHECK-LABEL: @test_mm512_maskz_div_round_ps_rn_sae(3450; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 83451; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 83452; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 83453; CHECK-NEXT: call void @llvm.donothing()3454; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP1]] to i5123455; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP4]], 03456; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP2]] to i5123457; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP5]], 03458; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3459; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]3460; CHECK: 6:3461; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]3462; CHECK-NEXT: unreachable3463; CHECK: 7:3464; CHECK-NEXT: [[TMP8:%.*]] = call <16 x float> @llvm.x86.avx512.div.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 8)3465; CHECK-NEXT: [[TMP9:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>3466; CHECK-NEXT: [[TMP10:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>3467; CHECK-NEXT: [[TMP11:%.*]] = select <16 x i1> [[TMP10]], <16 x i32> zeroinitializer, <16 x i32> zeroinitializer3468; CHECK-NEXT: [[TMP12:%.*]] = bitcast <16 x float> [[TMP8]] to <16 x i32>3469; CHECK-NEXT: [[TMP13:%.*]] = xor <16 x i32> [[TMP12]], zeroinitializer3470; CHECK-NEXT: [[TMP14:%.*]] = or <16 x i32> [[TMP13]], zeroinitializer3471; CHECK-NEXT: [[TMP15:%.*]] = or <16 x i32> [[TMP14]], zeroinitializer3472; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP9]], <16 x i32> [[TMP15]], <16 x i32> [[TMP11]]3473; CHECK-NEXT: [[TMP16:%.*]] = select <16 x i1> [[TMP10]], <16 x float> [[TMP8]], <16 x float> zeroinitializer3474; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 83475; CHECK-NEXT: ret <16 x float> [[TMP16]]3476;3477 %1 = call <16 x float> @llvm.x86.avx512.div.ps.512(<16 x float> %a0, <16 x float> %a1, i32 8)3478 %2 = bitcast i16 %mask to <16 x i1>3479 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> zeroinitializer3480 ret <16 x float> %33481}3482 3483define <16 x float> @test_mm512_maskz_div_round_ps_rd_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) #0 {3484; CHECK-LABEL: @test_mm512_maskz_div_round_ps_rd_sae(3485; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 83486; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 83487; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 83488; CHECK-NEXT: call void @llvm.donothing()3489; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP1]] to i5123490; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP4]], 03491; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP2]] to i5123492; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP5]], 03493; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3494; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]3495; CHECK: 6:3496; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]3497; CHECK-NEXT: unreachable3498; CHECK: 7:3499; CHECK-NEXT: [[TMP8:%.*]] = call <16 x float> @llvm.x86.avx512.div.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 9)3500; CHECK-NEXT: [[TMP9:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>3501; CHECK-NEXT: [[TMP10:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>3502; CHECK-NEXT: [[TMP11:%.*]] = select <16 x i1> [[TMP10]], <16 x i32> zeroinitializer, <16 x i32> zeroinitializer3503; CHECK-NEXT: [[TMP12:%.*]] = bitcast <16 x float> [[TMP8]] to <16 x i32>3504; CHECK-NEXT: [[TMP13:%.*]] = xor <16 x i32> [[TMP12]], zeroinitializer3505; CHECK-NEXT: [[TMP14:%.*]] = or <16 x i32> [[TMP13]], zeroinitializer3506; CHECK-NEXT: [[TMP15:%.*]] = or <16 x i32> [[TMP14]], zeroinitializer3507; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP9]], <16 x i32> [[TMP15]], <16 x i32> [[TMP11]]3508; CHECK-NEXT: [[TMP16:%.*]] = select <16 x i1> [[TMP10]], <16 x float> [[TMP8]], <16 x float> zeroinitializer3509; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 83510; CHECK-NEXT: ret <16 x float> [[TMP16]]3511;3512 %1 = call <16 x float> @llvm.x86.avx512.div.ps.512(<16 x float> %a0, <16 x float> %a1, i32 9)3513 %2 = bitcast i16 %mask to <16 x i1>3514 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> zeroinitializer3515 ret <16 x float> %33516}3517 3518define <16 x float> @test_mm512_maskz_div_round_ps_ru_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) #0 {3519; CHECK-LABEL: @test_mm512_maskz_div_round_ps_ru_sae(3520; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 83521; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 83522; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 83523; CHECK-NEXT: call void @llvm.donothing()3524; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP1]] to i5123525; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP4]], 03526; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP2]] to i5123527; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP5]], 03528; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3529; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]3530; CHECK: 6:3531; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]3532; CHECK-NEXT: unreachable3533; CHECK: 7:3534; CHECK-NEXT: [[TMP8:%.*]] = call <16 x float> @llvm.x86.avx512.div.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 10)3535; CHECK-NEXT: [[TMP9:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>3536; CHECK-NEXT: [[TMP10:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>3537; CHECK-NEXT: [[TMP11:%.*]] = select <16 x i1> [[TMP10]], <16 x i32> zeroinitializer, <16 x i32> zeroinitializer3538; CHECK-NEXT: [[TMP12:%.*]] = bitcast <16 x float> [[TMP8]] to <16 x i32>3539; CHECK-NEXT: [[TMP13:%.*]] = xor <16 x i32> [[TMP12]], zeroinitializer3540; CHECK-NEXT: [[TMP14:%.*]] = or <16 x i32> [[TMP13]], zeroinitializer3541; CHECK-NEXT: [[TMP15:%.*]] = or <16 x i32> [[TMP14]], zeroinitializer3542; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP9]], <16 x i32> [[TMP15]], <16 x i32> [[TMP11]]3543; CHECK-NEXT: [[TMP16:%.*]] = select <16 x i1> [[TMP10]], <16 x float> [[TMP8]], <16 x float> zeroinitializer3544; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 83545; CHECK-NEXT: ret <16 x float> [[TMP16]]3546;3547 %1 = call <16 x float> @llvm.x86.avx512.div.ps.512(<16 x float> %a0, <16 x float> %a1, i32 10)3548 %2 = bitcast i16 %mask to <16 x i1>3549 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> zeroinitializer3550 ret <16 x float> %33551}3552 3553define <16 x float> @test_mm512_maskz_div_round_ps_rz_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) #0 {3554; CHECK-LABEL: @test_mm512_maskz_div_round_ps_rz_sae(3555; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 83556; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 83557; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 83558; CHECK-NEXT: call void @llvm.donothing()3559; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP1]] to i5123560; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP4]], 03561; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP2]] to i5123562; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP5]], 03563; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3564; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]3565; CHECK: 6:3566; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]3567; CHECK-NEXT: unreachable3568; CHECK: 7:3569; CHECK-NEXT: [[TMP8:%.*]] = call <16 x float> @llvm.x86.avx512.div.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 11)3570; CHECK-NEXT: [[TMP9:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>3571; CHECK-NEXT: [[TMP10:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>3572; CHECK-NEXT: [[TMP11:%.*]] = select <16 x i1> [[TMP10]], <16 x i32> zeroinitializer, <16 x i32> zeroinitializer3573; CHECK-NEXT: [[TMP12:%.*]] = bitcast <16 x float> [[TMP8]] to <16 x i32>3574; CHECK-NEXT: [[TMP13:%.*]] = xor <16 x i32> [[TMP12]], zeroinitializer3575; CHECK-NEXT: [[TMP14:%.*]] = or <16 x i32> [[TMP13]], zeroinitializer3576; CHECK-NEXT: [[TMP15:%.*]] = or <16 x i32> [[TMP14]], zeroinitializer3577; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP9]], <16 x i32> [[TMP15]], <16 x i32> [[TMP11]]3578; CHECK-NEXT: [[TMP16:%.*]] = select <16 x i1> [[TMP10]], <16 x float> [[TMP8]], <16 x float> zeroinitializer3579; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 83580; CHECK-NEXT: ret <16 x float> [[TMP16]]3581;3582 %1 = call <16 x float> @llvm.x86.avx512.div.ps.512(<16 x float> %a0, <16 x float> %a1, i32 11)3583 %2 = bitcast i16 %mask to <16 x i1>3584 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> zeroinitializer3585 ret <16 x float> %33586}3587 3588define <16 x float> @test_mm512_maskz_div_round_ps_current(<16 x float> %a0, <16 x float> %a1, i16 %mask) #0 {3589; CHECK-LABEL: @test_mm512_maskz_div_round_ps_current(3590; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 83591; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 83592; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 83593; CHECK-NEXT: call void @llvm.donothing()3594; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP1]] to i5123595; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP4]], 03596; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP2]] to i5123597; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP5]], 03598; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3599; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]3600; CHECK: 6:3601; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]3602; CHECK-NEXT: unreachable3603; CHECK: 7:3604; CHECK-NEXT: [[TMP8:%.*]] = call <16 x float> @llvm.x86.avx512.div.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 4)3605; CHECK-NEXT: [[TMP9:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>3606; CHECK-NEXT: [[TMP10:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>3607; CHECK-NEXT: [[TMP11:%.*]] = select <16 x i1> [[TMP10]], <16 x i32> zeroinitializer, <16 x i32> zeroinitializer3608; CHECK-NEXT: [[TMP12:%.*]] = bitcast <16 x float> [[TMP8]] to <16 x i32>3609; CHECK-NEXT: [[TMP13:%.*]] = xor <16 x i32> [[TMP12]], zeroinitializer3610; CHECK-NEXT: [[TMP14:%.*]] = or <16 x i32> [[TMP13]], zeroinitializer3611; CHECK-NEXT: [[TMP15:%.*]] = or <16 x i32> [[TMP14]], zeroinitializer3612; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP9]], <16 x i32> [[TMP15]], <16 x i32> [[TMP11]]3613; CHECK-NEXT: [[TMP16:%.*]] = select <16 x i1> [[TMP10]], <16 x float> [[TMP8]], <16 x float> zeroinitializer3614; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 83615; CHECK-NEXT: ret <16 x float> [[TMP16]]3616;3617 %1 = call <16 x float> @llvm.x86.avx512.div.ps.512(<16 x float> %a0, <16 x float> %a1, i32 4)3618 %2 = bitcast i16 %mask to <16 x i1>3619 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> zeroinitializer3620 ret <16 x float> %33621}3622 3623define <16 x float> @test_mm512_mask_div_round_ps_rn_sae(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) #0 {3624; CHECK-LABEL: @test_mm512_mask_div_round_ps_rn_sae(3625; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 83626; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 83627; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 83628; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 83629; CHECK-NEXT: call void @llvm.donothing()3630; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP1]] to i5123631; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP5]], 03632; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i32> [[TMP2]] to i5123633; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP6]], 03634; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3635; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]3636; CHECK: 7:3637; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]3638; CHECK-NEXT: unreachable3639; CHECK: 8:3640; CHECK-NEXT: [[TMP9:%.*]] = call <16 x float> @llvm.x86.avx512.div.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 8)3641; CHECK-NEXT: [[TMP10:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>3642; CHECK-NEXT: [[TMP11:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>3643; CHECK-NEXT: [[TMP12:%.*]] = select <16 x i1> [[TMP11]], <16 x i32> zeroinitializer, <16 x i32> [[TMP4]]3644; CHECK-NEXT: [[TMP13:%.*]] = bitcast <16 x float> [[TMP9]] to <16 x i32>3645; CHECK-NEXT: [[TMP14:%.*]] = bitcast <16 x float> [[SRC:%.*]] to <16 x i32>3646; CHECK-NEXT: [[TMP15:%.*]] = xor <16 x i32> [[TMP13]], [[TMP14]]3647; CHECK-NEXT: [[TMP16:%.*]] = or <16 x i32> [[TMP15]], zeroinitializer3648; CHECK-NEXT: [[TMP17:%.*]] = or <16 x i32> [[TMP16]], [[TMP4]]3649; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP10]], <16 x i32> [[TMP17]], <16 x i32> [[TMP12]]3650; CHECK-NEXT: [[TMP18:%.*]] = select <16 x i1> [[TMP11]], <16 x float> [[TMP9]], <16 x float> [[SRC]]3651; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 83652; CHECK-NEXT: ret <16 x float> [[TMP18]]3653;3654 %1 = call <16 x float> @llvm.x86.avx512.div.ps.512(<16 x float> %a0, <16 x float> %a1, i32 8)3655 %2 = bitcast i16 %mask to <16 x i1>3656 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> %src3657 ret <16 x float> %33658}3659 3660define <16 x float> @test_mm512_mask_div_round_ps_rd_sae(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) #0 {3661; CHECK-LABEL: @test_mm512_mask_div_round_ps_rd_sae(3662; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 83663; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 83664; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 83665; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 83666; CHECK-NEXT: call void @llvm.donothing()3667; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP1]] to i5123668; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP5]], 03669; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i32> [[TMP2]] to i5123670; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP6]], 03671; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3672; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]3673; CHECK: 7:3674; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]3675; CHECK-NEXT: unreachable3676; CHECK: 8:3677; CHECK-NEXT: [[TMP9:%.*]] = call <16 x float> @llvm.x86.avx512.div.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 9)3678; CHECK-NEXT: [[TMP10:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>3679; CHECK-NEXT: [[TMP11:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>3680; CHECK-NEXT: [[TMP12:%.*]] = select <16 x i1> [[TMP11]], <16 x i32> zeroinitializer, <16 x i32> [[TMP4]]3681; CHECK-NEXT: [[TMP13:%.*]] = bitcast <16 x float> [[TMP9]] to <16 x i32>3682; CHECK-NEXT: [[TMP14:%.*]] = bitcast <16 x float> [[SRC:%.*]] to <16 x i32>3683; CHECK-NEXT: [[TMP15:%.*]] = xor <16 x i32> [[TMP13]], [[TMP14]]3684; CHECK-NEXT: [[TMP16:%.*]] = or <16 x i32> [[TMP15]], zeroinitializer3685; CHECK-NEXT: [[TMP17:%.*]] = or <16 x i32> [[TMP16]], [[TMP4]]3686; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP10]], <16 x i32> [[TMP17]], <16 x i32> [[TMP12]]3687; CHECK-NEXT: [[TMP18:%.*]] = select <16 x i1> [[TMP11]], <16 x float> [[TMP9]], <16 x float> [[SRC]]3688; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 83689; CHECK-NEXT: ret <16 x float> [[TMP18]]3690;3691 %1 = call <16 x float> @llvm.x86.avx512.div.ps.512(<16 x float> %a0, <16 x float> %a1, i32 9)3692 %2 = bitcast i16 %mask to <16 x i1>3693 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> %src3694 ret <16 x float> %33695}3696 3697define <16 x float> @test_mm512_mask_div_round_ps_ru_sae(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) #0 {3698; CHECK-LABEL: @test_mm512_mask_div_round_ps_ru_sae(3699; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 83700; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 83701; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 83702; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 83703; CHECK-NEXT: call void @llvm.donothing()3704; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP1]] to i5123705; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP5]], 03706; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i32> [[TMP2]] to i5123707; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP6]], 03708; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3709; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]3710; CHECK: 7:3711; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]3712; CHECK-NEXT: unreachable3713; CHECK: 8:3714; CHECK-NEXT: [[TMP9:%.*]] = call <16 x float> @llvm.x86.avx512.div.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 10)3715; CHECK-NEXT: [[TMP10:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>3716; CHECK-NEXT: [[TMP11:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>3717; CHECK-NEXT: [[TMP12:%.*]] = select <16 x i1> [[TMP11]], <16 x i32> zeroinitializer, <16 x i32> [[TMP4]]3718; CHECK-NEXT: [[TMP13:%.*]] = bitcast <16 x float> [[TMP9]] to <16 x i32>3719; CHECK-NEXT: [[TMP14:%.*]] = bitcast <16 x float> [[SRC:%.*]] to <16 x i32>3720; CHECK-NEXT: [[TMP15:%.*]] = xor <16 x i32> [[TMP13]], [[TMP14]]3721; CHECK-NEXT: [[TMP16:%.*]] = or <16 x i32> [[TMP15]], zeroinitializer3722; CHECK-NEXT: [[TMP17:%.*]] = or <16 x i32> [[TMP16]], [[TMP4]]3723; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP10]], <16 x i32> [[TMP17]], <16 x i32> [[TMP12]]3724; CHECK-NEXT: [[TMP18:%.*]] = select <16 x i1> [[TMP11]], <16 x float> [[TMP9]], <16 x float> [[SRC]]3725; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 83726; CHECK-NEXT: ret <16 x float> [[TMP18]]3727;3728 %1 = call <16 x float> @llvm.x86.avx512.div.ps.512(<16 x float> %a0, <16 x float> %a1, i32 10)3729 %2 = bitcast i16 %mask to <16 x i1>3730 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> %src3731 ret <16 x float> %33732}3733 3734define <16 x float> @test_mm512_mask_div_round_ps_rz_sae(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) #0 {3735; CHECK-LABEL: @test_mm512_mask_div_round_ps_rz_sae(3736; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 83737; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 83738; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 83739; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 83740; CHECK-NEXT: call void @llvm.donothing()3741; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP1]] to i5123742; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP5]], 03743; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i32> [[TMP2]] to i5123744; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP6]], 03745; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3746; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]3747; CHECK: 7:3748; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]3749; CHECK-NEXT: unreachable3750; CHECK: 8:3751; CHECK-NEXT: [[TMP9:%.*]] = call <16 x float> @llvm.x86.avx512.div.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 11)3752; CHECK-NEXT: [[TMP10:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>3753; CHECK-NEXT: [[TMP11:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>3754; CHECK-NEXT: [[TMP12:%.*]] = select <16 x i1> [[TMP11]], <16 x i32> zeroinitializer, <16 x i32> [[TMP4]]3755; CHECK-NEXT: [[TMP13:%.*]] = bitcast <16 x float> [[TMP9]] to <16 x i32>3756; CHECK-NEXT: [[TMP14:%.*]] = bitcast <16 x float> [[SRC:%.*]] to <16 x i32>3757; CHECK-NEXT: [[TMP15:%.*]] = xor <16 x i32> [[TMP13]], [[TMP14]]3758; CHECK-NEXT: [[TMP16:%.*]] = or <16 x i32> [[TMP15]], zeroinitializer3759; CHECK-NEXT: [[TMP17:%.*]] = or <16 x i32> [[TMP16]], [[TMP4]]3760; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP10]], <16 x i32> [[TMP17]], <16 x i32> [[TMP12]]3761; CHECK-NEXT: [[TMP18:%.*]] = select <16 x i1> [[TMP11]], <16 x float> [[TMP9]], <16 x float> [[SRC]]3762; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 83763; CHECK-NEXT: ret <16 x float> [[TMP18]]3764;3765 %1 = call <16 x float> @llvm.x86.avx512.div.ps.512(<16 x float> %a0, <16 x float> %a1, i32 11)3766 %2 = bitcast i16 %mask to <16 x i1>3767 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> %src3768 ret <16 x float> %33769}3770 3771define <16 x float> @test_mm512_mask_div_round_ps_current(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) #0 {3772; CHECK-LABEL: @test_mm512_mask_div_round_ps_current(3773; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 83774; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 83775; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 83776; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 83777; CHECK-NEXT: call void @llvm.donothing()3778; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP1]] to i5123779; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP5]], 03780; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i32> [[TMP2]] to i5123781; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP6]], 03782; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3783; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]3784; CHECK: 7:3785; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]3786; CHECK-NEXT: unreachable3787; CHECK: 8:3788; CHECK-NEXT: [[TMP9:%.*]] = call <16 x float> @llvm.x86.avx512.div.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 4)3789; CHECK-NEXT: [[TMP10:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>3790; CHECK-NEXT: [[TMP11:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>3791; CHECK-NEXT: [[TMP12:%.*]] = select <16 x i1> [[TMP11]], <16 x i32> zeroinitializer, <16 x i32> [[TMP4]]3792; CHECK-NEXT: [[TMP13:%.*]] = bitcast <16 x float> [[TMP9]] to <16 x i32>3793; CHECK-NEXT: [[TMP14:%.*]] = bitcast <16 x float> [[SRC:%.*]] to <16 x i32>3794; CHECK-NEXT: [[TMP15:%.*]] = xor <16 x i32> [[TMP13]], [[TMP14]]3795; CHECK-NEXT: [[TMP16:%.*]] = or <16 x i32> [[TMP15]], zeroinitializer3796; CHECK-NEXT: [[TMP17:%.*]] = or <16 x i32> [[TMP16]], [[TMP4]]3797; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP10]], <16 x i32> [[TMP17]], <16 x i32> [[TMP12]]3798; CHECK-NEXT: [[TMP18:%.*]] = select <16 x i1> [[TMP11]], <16 x float> [[TMP9]], <16 x float> [[SRC]]3799; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 83800; CHECK-NEXT: ret <16 x float> [[TMP18]]3801;3802 %1 = call <16 x float> @llvm.x86.avx512.div.ps.512(<16 x float> %a0, <16 x float> %a1, i32 4)3803 %2 = bitcast i16 %mask to <16 x i1>3804 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> %src3805 ret <16 x float> %33806}3807 3808define <16 x float> @test_mm512_div_round_ps_rn_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) #0 {3809; CHECK-LABEL: @test_mm512_div_round_ps_rn_sae(3810; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 83811; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 83812; CHECK-NEXT: call void @llvm.donothing()3813; CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i32> [[TMP1]] to i5123814; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP3]], 03815; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP2]] to i5123816; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 03817; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3818; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]3819; CHECK: 5:3820; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]3821; CHECK-NEXT: unreachable3822; CHECK: 6:3823; CHECK-NEXT: [[TMP7:%.*]] = call <16 x float> @llvm.x86.avx512.div.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 8)3824; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 83825; CHECK-NEXT: ret <16 x float> [[TMP7]]3826;3827 %1 = call <16 x float> @llvm.x86.avx512.div.ps.512(<16 x float> %a0, <16 x float> %a1, i32 8)3828 ret <16 x float> %13829}3830 3831define <16 x float> @test_mm512_div_round_ps_rd_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) #0 {3832; CHECK-LABEL: @test_mm512_div_round_ps_rd_sae(3833; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 83834; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 83835; CHECK-NEXT: call void @llvm.donothing()3836; CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i32> [[TMP1]] to i5123837; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP3]], 03838; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP2]] to i5123839; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 03840; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3841; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]3842; CHECK: 5:3843; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]3844; CHECK-NEXT: unreachable3845; CHECK: 6:3846; CHECK-NEXT: [[TMP7:%.*]] = call <16 x float> @llvm.x86.avx512.div.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 9)3847; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 83848; CHECK-NEXT: ret <16 x float> [[TMP7]]3849;3850 %1 = call <16 x float> @llvm.x86.avx512.div.ps.512(<16 x float> %a0, <16 x float> %a1, i32 9)3851 ret <16 x float> %13852}3853 3854define <16 x float> @test_mm512_div_round_ps_ru_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) #0 {3855; CHECK-LABEL: @test_mm512_div_round_ps_ru_sae(3856; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 83857; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 83858; CHECK-NEXT: call void @llvm.donothing()3859; CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i32> [[TMP1]] to i5123860; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP3]], 03861; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP2]] to i5123862; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 03863; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3864; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]3865; CHECK: 5:3866; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]3867; CHECK-NEXT: unreachable3868; CHECK: 6:3869; CHECK-NEXT: [[TMP7:%.*]] = call <16 x float> @llvm.x86.avx512.div.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 10)3870; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 83871; CHECK-NEXT: ret <16 x float> [[TMP7]]3872;3873 %1 = call <16 x float> @llvm.x86.avx512.div.ps.512(<16 x float> %a0, <16 x float> %a1, i32 10)3874 ret <16 x float> %13875}3876 3877define <16 x float> @test_mm512_div_round_ps_rz_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) #0 {3878; CHECK-LABEL: @test_mm512_div_round_ps_rz_sae(3879; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 83880; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 83881; CHECK-NEXT: call void @llvm.donothing()3882; CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i32> [[TMP1]] to i5123883; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP3]], 03884; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP2]] to i5123885; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 03886; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3887; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]3888; CHECK: 5:3889; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]3890; CHECK-NEXT: unreachable3891; CHECK: 6:3892; CHECK-NEXT: [[TMP7:%.*]] = call <16 x float> @llvm.x86.avx512.div.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 11)3893; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 83894; CHECK-NEXT: ret <16 x float> [[TMP7]]3895;3896 %1 = call <16 x float> @llvm.x86.avx512.div.ps.512(<16 x float> %a0, <16 x float> %a1, i32 11)3897 ret <16 x float> %13898}3899 3900define <16 x float> @test_mm512_div_round_ps_current(<16 x float> %a0, <16 x float> %a1, i16 %mask) #0 {3901; CHECK-LABEL: @test_mm512_div_round_ps_current(3902; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 83903; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 83904; CHECK-NEXT: call void @llvm.donothing()3905; CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i32> [[TMP1]] to i5123906; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP3]], 03907; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP2]] to i5123908; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 03909; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3910; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]3911; CHECK: 5:3912; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]3913; CHECK-NEXT: unreachable3914; CHECK: 6:3915; CHECK-NEXT: [[TMP7:%.*]] = call <16 x float> @llvm.x86.avx512.div.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 4)3916; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 83917; CHECK-NEXT: ret <16 x float> [[TMP7]]3918;3919 %1 = call <16 x float> @llvm.x86.avx512.div.ps.512(<16 x float> %a0, <16 x float> %a1, i32 4)3920 ret <16 x float> %13921}3922declare <16 x float> @llvm.x86.avx512.div.ps.512(<16 x float>, <16 x float>, i32)3923 3924define <16 x float> @test_mm512_maskz_min_round_ps_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) #0 {3925; CHECK-LABEL: @test_mm512_maskz_min_round_ps_sae(3926; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 83927; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 83928; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 83929; CHECK-NEXT: call void @llvm.donothing()3930; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i32> [[TMP1]], [[TMP2]]3931; CHECK-NEXT: [[_MSPROP1:%.*]] = or <16 x i32> [[_MSPROP]], zeroinitializer3932; CHECK-NEXT: [[TMP8:%.*]] = call <16 x float> @llvm.x86.avx512.min.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 8)3933; CHECK-NEXT: [[TMP9:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>3934; CHECK-NEXT: [[TMP10:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>3935; CHECK-NEXT: [[TMP11:%.*]] = select <16 x i1> [[TMP10]], <16 x i32> [[_MSPROP1]], <16 x i32> zeroinitializer3936; CHECK-NEXT: [[TMP12:%.*]] = bitcast <16 x float> [[TMP8]] to <16 x i32>3937; CHECK-NEXT: [[TMP13:%.*]] = xor <16 x i32> [[TMP12]], zeroinitializer3938; CHECK-NEXT: [[TMP14:%.*]] = or <16 x i32> [[TMP13]], [[_MSPROP1]]3939; CHECK-NEXT: [[TMP15:%.*]] = or <16 x i32> [[TMP14]], zeroinitializer3940; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP9]], <16 x i32> [[TMP15]], <16 x i32> [[TMP11]]3941; CHECK-NEXT: [[TMP16:%.*]] = select <16 x i1> [[TMP10]], <16 x float> [[TMP8]], <16 x float> zeroinitializer3942; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 83943; CHECK-NEXT: ret <16 x float> [[TMP16]]3944;3945 %1 = call <16 x float> @llvm.x86.avx512.min.ps.512(<16 x float> %a0, <16 x float> %a1, i32 8)3946 %2 = bitcast i16 %mask to <16 x i1>3947 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> zeroinitializer3948 ret <16 x float> %33949}3950 3951define <16 x float> @test_mm512_maskz_min_round_ps_current(<16 x float> %a0, <16 x float> %a1, i16 %mask) #0 {3952; CHECK-LABEL: @test_mm512_maskz_min_round_ps_current(3953; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 83954; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 83955; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 83956; CHECK-NEXT: call void @llvm.donothing()3957; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i32> [[TMP1]], [[TMP2]]3958; CHECK-NEXT: [[_MSPROP1:%.*]] = or <16 x i32> [[_MSPROP]], zeroinitializer3959; CHECK-NEXT: [[TMP8:%.*]] = call <16 x float> @llvm.x86.avx512.min.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 4)3960; CHECK-NEXT: [[TMP9:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>3961; CHECK-NEXT: [[TMP10:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>3962; CHECK-NEXT: [[TMP11:%.*]] = select <16 x i1> [[TMP10]], <16 x i32> [[_MSPROP1]], <16 x i32> zeroinitializer3963; CHECK-NEXT: [[TMP12:%.*]] = bitcast <16 x float> [[TMP8]] to <16 x i32>3964; CHECK-NEXT: [[TMP13:%.*]] = xor <16 x i32> [[TMP12]], zeroinitializer3965; CHECK-NEXT: [[TMP14:%.*]] = or <16 x i32> [[TMP13]], [[_MSPROP1]]3966; CHECK-NEXT: [[TMP15:%.*]] = or <16 x i32> [[TMP14]], zeroinitializer3967; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP9]], <16 x i32> [[TMP15]], <16 x i32> [[TMP11]]3968; CHECK-NEXT: [[TMP16:%.*]] = select <16 x i1> [[TMP10]], <16 x float> [[TMP8]], <16 x float> zeroinitializer3969; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 83970; CHECK-NEXT: ret <16 x float> [[TMP16]]3971;3972 %1 = call <16 x float> @llvm.x86.avx512.min.ps.512(<16 x float> %a0, <16 x float> %a1, i32 4)3973 %2 = bitcast i16 %mask to <16 x i1>3974 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> zeroinitializer3975 ret <16 x float> %33976}3977 3978define <16 x float> @test_mm512_mask_min_round_ps_sae(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) #0 {3979; CHECK-LABEL: @test_mm512_mask_min_round_ps_sae(3980; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 83981; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 83982; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 83983; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 83984; CHECK-NEXT: call void @llvm.donothing()3985; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i32> [[TMP1]], [[TMP2]]3986; CHECK-NEXT: [[_MSPROP1:%.*]] = or <16 x i32> [[_MSPROP]], zeroinitializer3987; CHECK-NEXT: [[TMP9:%.*]] = call <16 x float> @llvm.x86.avx512.min.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 8)3988; CHECK-NEXT: [[TMP10:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>3989; CHECK-NEXT: [[TMP11:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>3990; CHECK-NEXT: [[TMP12:%.*]] = select <16 x i1> [[TMP11]], <16 x i32> [[_MSPROP1]], <16 x i32> [[TMP4]]3991; CHECK-NEXT: [[TMP13:%.*]] = bitcast <16 x float> [[TMP9]] to <16 x i32>3992; CHECK-NEXT: [[TMP14:%.*]] = bitcast <16 x float> [[SRC:%.*]] to <16 x i32>3993; CHECK-NEXT: [[TMP15:%.*]] = xor <16 x i32> [[TMP13]], [[TMP14]]3994; CHECK-NEXT: [[TMP16:%.*]] = or <16 x i32> [[TMP15]], [[_MSPROP1]]3995; CHECK-NEXT: [[TMP17:%.*]] = or <16 x i32> [[TMP16]], [[TMP4]]3996; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP10]], <16 x i32> [[TMP17]], <16 x i32> [[TMP12]]3997; CHECK-NEXT: [[TMP18:%.*]] = select <16 x i1> [[TMP11]], <16 x float> [[TMP9]], <16 x float> [[SRC]]3998; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 83999; CHECK-NEXT: ret <16 x float> [[TMP18]]4000;4001 %1 = call <16 x float> @llvm.x86.avx512.min.ps.512(<16 x float> %a0, <16 x float> %a1, i32 8)4002 %2 = bitcast i16 %mask to <16 x i1>4003 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> %src4004 ret <16 x float> %34005}4006 4007define <16 x float> @test_mm512_mask_min_round_ps_current(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) #0 {4008; CHECK-LABEL: @test_mm512_mask_min_round_ps_current(4009; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 84010; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 84011; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 84012; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 84013; CHECK-NEXT: call void @llvm.donothing()4014; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i32> [[TMP1]], [[TMP2]]4015; CHECK-NEXT: [[_MSPROP1:%.*]] = or <16 x i32> [[_MSPROP]], zeroinitializer4016; CHECK-NEXT: [[TMP9:%.*]] = call <16 x float> @llvm.x86.avx512.min.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 4)4017; CHECK-NEXT: [[TMP10:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>4018; CHECK-NEXT: [[TMP11:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>4019; CHECK-NEXT: [[TMP12:%.*]] = select <16 x i1> [[TMP11]], <16 x i32> [[_MSPROP1]], <16 x i32> [[TMP4]]4020; CHECK-NEXT: [[TMP13:%.*]] = bitcast <16 x float> [[TMP9]] to <16 x i32>4021; CHECK-NEXT: [[TMP14:%.*]] = bitcast <16 x float> [[SRC:%.*]] to <16 x i32>4022; CHECK-NEXT: [[TMP15:%.*]] = xor <16 x i32> [[TMP13]], [[TMP14]]4023; CHECK-NEXT: [[TMP16:%.*]] = or <16 x i32> [[TMP15]], [[_MSPROP1]]4024; CHECK-NEXT: [[TMP17:%.*]] = or <16 x i32> [[TMP16]], [[TMP4]]4025; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP10]], <16 x i32> [[TMP17]], <16 x i32> [[TMP12]]4026; CHECK-NEXT: [[TMP18:%.*]] = select <16 x i1> [[TMP11]], <16 x float> [[TMP9]], <16 x float> [[SRC]]4027; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 84028; CHECK-NEXT: ret <16 x float> [[TMP18]]4029;4030 %1 = call <16 x float> @llvm.x86.avx512.min.ps.512(<16 x float> %a0, <16 x float> %a1, i32 4)4031 %2 = bitcast i16 %mask to <16 x i1>4032 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> %src4033 ret <16 x float> %34034}4035 4036define <16 x float> @test_mm512_min_round_ps_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) #0 {4037; CHECK-LABEL: @test_mm512_min_round_ps_sae(4038; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 84039; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 84040; CHECK-NEXT: call void @llvm.donothing()4041; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i32> [[TMP1]], [[TMP2]]4042; CHECK-NEXT: [[_MSPROP1:%.*]] = or <16 x i32> [[_MSPROP]], zeroinitializer4043; CHECK-NEXT: [[TMP7:%.*]] = call <16 x float> @llvm.x86.avx512.min.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 8)4044; CHECK-NEXT: store <16 x i32> [[_MSPROP1]], ptr @__msan_retval_tls, align 84045; CHECK-NEXT: ret <16 x float> [[TMP7]]4046;4047 %1 = call <16 x float> @llvm.x86.avx512.min.ps.512(<16 x float> %a0, <16 x float> %a1, i32 8)4048 ret <16 x float> %14049}4050 4051define <16 x float> @test_mm512_min_round_ps_current(<16 x float> %a0, <16 x float> %a1, i16 %mask) #0 {4052; CHECK-LABEL: @test_mm512_min_round_ps_current(4053; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 84054; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 84055; CHECK-NEXT: call void @llvm.donothing()4056; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i32> [[TMP1]], [[TMP2]]4057; CHECK-NEXT: [[_MSPROP1:%.*]] = or <16 x i32> [[_MSPROP]], zeroinitializer4058; CHECK-NEXT: [[TMP7:%.*]] = call <16 x float> @llvm.x86.avx512.min.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 4)4059; CHECK-NEXT: store <16 x i32> [[_MSPROP1]], ptr @__msan_retval_tls, align 84060; CHECK-NEXT: ret <16 x float> [[TMP7]]4061;4062 %1 = call <16 x float> @llvm.x86.avx512.min.ps.512(<16 x float> %a0, <16 x float> %a1, i32 4)4063 ret <16 x float> %14064}4065declare <16 x float> @llvm.x86.avx512.min.ps.512(<16 x float>, <16 x float>, i32)4066 4067define <16 x float> @test_mm512_maskz_max_round_ps_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) #0 {4068; CHECK-LABEL: @test_mm512_maskz_max_round_ps_sae(4069; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 84070; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 84071; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 84072; CHECK-NEXT: call void @llvm.donothing()4073; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i32> [[TMP1]], [[TMP2]]4074; CHECK-NEXT: [[_MSPROP1:%.*]] = or <16 x i32> [[_MSPROP]], zeroinitializer4075; CHECK-NEXT: [[TMP8:%.*]] = call <16 x float> @llvm.x86.avx512.max.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 8)4076; CHECK-NEXT: [[TMP9:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>4077; CHECK-NEXT: [[TMP10:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>4078; CHECK-NEXT: [[TMP11:%.*]] = select <16 x i1> [[TMP10]], <16 x i32> [[_MSPROP1]], <16 x i32> zeroinitializer4079; CHECK-NEXT: [[TMP12:%.*]] = bitcast <16 x float> [[TMP8]] to <16 x i32>4080; CHECK-NEXT: [[TMP13:%.*]] = xor <16 x i32> [[TMP12]], zeroinitializer4081; CHECK-NEXT: [[TMP14:%.*]] = or <16 x i32> [[TMP13]], [[_MSPROP1]]4082; CHECK-NEXT: [[TMP15:%.*]] = or <16 x i32> [[TMP14]], zeroinitializer4083; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP9]], <16 x i32> [[TMP15]], <16 x i32> [[TMP11]]4084; CHECK-NEXT: [[TMP16:%.*]] = select <16 x i1> [[TMP10]], <16 x float> [[TMP8]], <16 x float> zeroinitializer4085; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 84086; CHECK-NEXT: ret <16 x float> [[TMP16]]4087;4088 %1 = call <16 x float> @llvm.x86.avx512.max.ps.512(<16 x float> %a0, <16 x float> %a1, i32 8)4089 %2 = bitcast i16 %mask to <16 x i1>4090 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> zeroinitializer4091 ret <16 x float> %34092}4093 4094define <16 x float> @test_mm512_maskz_max_round_ps_current(<16 x float> %a0, <16 x float> %a1, i16 %mask) #0 {4095; CHECK-LABEL: @test_mm512_maskz_max_round_ps_current(4096; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 84097; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 84098; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 84099; CHECK-NEXT: call void @llvm.donothing()4100; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i32> [[TMP1]], [[TMP2]]4101; CHECK-NEXT: [[_MSPROP1:%.*]] = or <16 x i32> [[_MSPROP]], zeroinitializer4102; CHECK-NEXT: [[TMP8:%.*]] = call <16 x float> @llvm.x86.avx512.max.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 4)4103; CHECK-NEXT: [[TMP9:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>4104; CHECK-NEXT: [[TMP10:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>4105; CHECK-NEXT: [[TMP11:%.*]] = select <16 x i1> [[TMP10]], <16 x i32> [[_MSPROP1]], <16 x i32> zeroinitializer4106; CHECK-NEXT: [[TMP12:%.*]] = bitcast <16 x float> [[TMP8]] to <16 x i32>4107; CHECK-NEXT: [[TMP13:%.*]] = xor <16 x i32> [[TMP12]], zeroinitializer4108; CHECK-NEXT: [[TMP14:%.*]] = or <16 x i32> [[TMP13]], [[_MSPROP1]]4109; CHECK-NEXT: [[TMP15:%.*]] = or <16 x i32> [[TMP14]], zeroinitializer4110; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP9]], <16 x i32> [[TMP15]], <16 x i32> [[TMP11]]4111; CHECK-NEXT: [[TMP16:%.*]] = select <16 x i1> [[TMP10]], <16 x float> [[TMP8]], <16 x float> zeroinitializer4112; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 84113; CHECK-NEXT: ret <16 x float> [[TMP16]]4114;4115 %1 = call <16 x float> @llvm.x86.avx512.max.ps.512(<16 x float> %a0, <16 x float> %a1, i32 4)4116 %2 = bitcast i16 %mask to <16 x i1>4117 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> zeroinitializer4118 ret <16 x float> %34119}4120 4121define <16 x float> @test_mm512_mask_max_round_ps_sae(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) #0 {4122; CHECK-LABEL: @test_mm512_mask_max_round_ps_sae(4123; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 84124; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 84125; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 84126; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 84127; CHECK-NEXT: call void @llvm.donothing()4128; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i32> [[TMP1]], [[TMP2]]4129; CHECK-NEXT: [[_MSPROP1:%.*]] = or <16 x i32> [[_MSPROP]], zeroinitializer4130; CHECK-NEXT: [[TMP9:%.*]] = call <16 x float> @llvm.x86.avx512.max.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 8)4131; CHECK-NEXT: [[TMP10:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>4132; CHECK-NEXT: [[TMP11:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>4133; CHECK-NEXT: [[TMP12:%.*]] = select <16 x i1> [[TMP11]], <16 x i32> [[_MSPROP1]], <16 x i32> [[TMP4]]4134; CHECK-NEXT: [[TMP13:%.*]] = bitcast <16 x float> [[TMP9]] to <16 x i32>4135; CHECK-NEXT: [[TMP14:%.*]] = bitcast <16 x float> [[SRC:%.*]] to <16 x i32>4136; CHECK-NEXT: [[TMP15:%.*]] = xor <16 x i32> [[TMP13]], [[TMP14]]4137; CHECK-NEXT: [[TMP16:%.*]] = or <16 x i32> [[TMP15]], [[_MSPROP1]]4138; CHECK-NEXT: [[TMP17:%.*]] = or <16 x i32> [[TMP16]], [[TMP4]]4139; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP10]], <16 x i32> [[TMP17]], <16 x i32> [[TMP12]]4140; CHECK-NEXT: [[TMP18:%.*]] = select <16 x i1> [[TMP11]], <16 x float> [[TMP9]], <16 x float> [[SRC]]4141; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 84142; CHECK-NEXT: ret <16 x float> [[TMP18]]4143;4144 %1 = call <16 x float> @llvm.x86.avx512.max.ps.512(<16 x float> %a0, <16 x float> %a1, i32 8)4145 %2 = bitcast i16 %mask to <16 x i1>4146 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> %src4147 ret <16 x float> %34148}4149 4150define <16 x float> @test_mm512_mask_max_round_ps_current(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) #0 {4151; CHECK-LABEL: @test_mm512_mask_max_round_ps_current(4152; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 84153; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 84154; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 84155; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 84156; CHECK-NEXT: call void @llvm.donothing()4157; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i32> [[TMP1]], [[TMP2]]4158; CHECK-NEXT: [[_MSPROP1:%.*]] = or <16 x i32> [[_MSPROP]], zeroinitializer4159; CHECK-NEXT: [[TMP9:%.*]] = call <16 x float> @llvm.x86.avx512.max.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 4)4160; CHECK-NEXT: [[TMP10:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>4161; CHECK-NEXT: [[TMP11:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>4162; CHECK-NEXT: [[TMP12:%.*]] = select <16 x i1> [[TMP11]], <16 x i32> [[_MSPROP1]], <16 x i32> [[TMP4]]4163; CHECK-NEXT: [[TMP13:%.*]] = bitcast <16 x float> [[TMP9]] to <16 x i32>4164; CHECK-NEXT: [[TMP14:%.*]] = bitcast <16 x float> [[SRC:%.*]] to <16 x i32>4165; CHECK-NEXT: [[TMP15:%.*]] = xor <16 x i32> [[TMP13]], [[TMP14]]4166; CHECK-NEXT: [[TMP16:%.*]] = or <16 x i32> [[TMP15]], [[_MSPROP1]]4167; CHECK-NEXT: [[TMP17:%.*]] = or <16 x i32> [[TMP16]], [[TMP4]]4168; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP10]], <16 x i32> [[TMP17]], <16 x i32> [[TMP12]]4169; CHECK-NEXT: [[TMP18:%.*]] = select <16 x i1> [[TMP11]], <16 x float> [[TMP9]], <16 x float> [[SRC]]4170; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 84171; CHECK-NEXT: ret <16 x float> [[TMP18]]4172;4173 %1 = call <16 x float> @llvm.x86.avx512.max.ps.512(<16 x float> %a0, <16 x float> %a1, i32 4)4174 %2 = bitcast i16 %mask to <16 x i1>4175 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> %src4176 ret <16 x float> %34177}4178 4179define <16 x float> @test_mm512_max_round_ps_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) #0 {4180; CHECK-LABEL: @test_mm512_max_round_ps_sae(4181; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 84182; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 84183; CHECK-NEXT: call void @llvm.donothing()4184; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i32> [[TMP1]], [[TMP2]]4185; CHECK-NEXT: [[_MSPROP1:%.*]] = or <16 x i32> [[_MSPROP]], zeroinitializer4186; CHECK-NEXT: [[TMP7:%.*]] = call <16 x float> @llvm.x86.avx512.max.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 8)4187; CHECK-NEXT: store <16 x i32> [[_MSPROP1]], ptr @__msan_retval_tls, align 84188; CHECK-NEXT: ret <16 x float> [[TMP7]]4189;4190 %1 = call <16 x float> @llvm.x86.avx512.max.ps.512(<16 x float> %a0, <16 x float> %a1, i32 8)4191 ret <16 x float> %14192}4193 4194define <16 x float> @test_mm512_max_round_ps_current(<16 x float> %a0, <16 x float> %a1, i16 %mask) #0 {4195; CHECK-LABEL: @test_mm512_max_round_ps_current(4196; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 84197; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 84198; CHECK-NEXT: call void @llvm.donothing()4199; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i32> [[TMP1]], [[TMP2]]4200; CHECK-NEXT: [[_MSPROP1:%.*]] = or <16 x i32> [[_MSPROP]], zeroinitializer4201; CHECK-NEXT: [[TMP7:%.*]] = call <16 x float> @llvm.x86.avx512.max.ps.512(<16 x float> [[A0:%.*]], <16 x float> [[A1:%.*]], i32 4)4202; CHECK-NEXT: store <16 x i32> [[_MSPROP1]], ptr @__msan_retval_tls, align 84203; CHECK-NEXT: ret <16 x float> [[TMP7]]4204;4205 %1 = call <16 x float> @llvm.x86.avx512.max.ps.512(<16 x float> %a0, <16 x float> %a1, i32 4)4206 ret <16 x float> %14207}4208declare <16 x float> @llvm.x86.avx512.max.ps.512(<16 x float>, <16 x float>, i32)4209 4210declare <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>, <4 x float>, <4 x float>, i8, i32) nounwind readnone4211 4212define <4 x float> @test_mask_add_ss_rn(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) #0 {4213; CHECK-LABEL: @test_mask_add_ss_rn(4214; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 84215; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84216; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 84217; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 84218; CHECK-NEXT: call void @llvm.donothing()4219; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP1]] to i1284220; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 04221; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i32> [[TMP2]] to i1284222; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP6]], 04223; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]4224; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i32> [[TMP3]] to i1284225; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 04226; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]4227; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 04228; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]4229; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]4230; CHECK: 8:4231; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]4232; CHECK-NEXT: unreachable4233; CHECK: 9:4234; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], <4 x float> [[A2:%.*]], i8 [[MASK:%.*]], i32 8)4235; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 84236; CHECK-NEXT: ret <4 x float> [[RES]]4237;4238 %res = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> %a2, i8 %mask, i32 8)4239 ret <4 x float> %res4240}4241 4242define <4 x float> @test_mask_add_ss_rd(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) #0 {4243; CHECK-LABEL: @test_mask_add_ss_rd(4244; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 84245; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84246; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 84247; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 84248; CHECK-NEXT: call void @llvm.donothing()4249; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP1]] to i1284250; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 04251; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i32> [[TMP2]] to i1284252; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP6]], 04253; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]4254; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i32> [[TMP3]] to i1284255; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 04256; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]4257; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 04258; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]4259; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]4260; CHECK: 8:4261; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]4262; CHECK-NEXT: unreachable4263; CHECK: 9:4264; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], <4 x float> [[A2:%.*]], i8 [[MASK:%.*]], i32 9)4265; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 84266; CHECK-NEXT: ret <4 x float> [[RES]]4267;4268 %res = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> %a2, i8 %mask, i32 9)4269 ret <4 x float> %res4270}4271 4272define <4 x float> @test_mask_add_ss_ru(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) #0 {4273; CHECK-LABEL: @test_mask_add_ss_ru(4274; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 84275; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84276; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 84277; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 84278; CHECK-NEXT: call void @llvm.donothing()4279; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP1]] to i1284280; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 04281; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i32> [[TMP2]] to i1284282; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP6]], 04283; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]4284; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i32> [[TMP3]] to i1284285; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 04286; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]4287; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 04288; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]4289; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]4290; CHECK: 8:4291; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]4292; CHECK-NEXT: unreachable4293; CHECK: 9:4294; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], <4 x float> [[A2:%.*]], i8 [[MASK:%.*]], i32 10)4295; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 84296; CHECK-NEXT: ret <4 x float> [[RES]]4297;4298 %res = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> %a2, i8 %mask, i32 10)4299 ret <4 x float> %res4300}4301 4302define <4 x float> @test_mask_add_ss_rz(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) #0 {4303; CHECK-LABEL: @test_mask_add_ss_rz(4304; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 84305; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84306; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 84307; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 84308; CHECK-NEXT: call void @llvm.donothing()4309; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP1]] to i1284310; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 04311; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i32> [[TMP2]] to i1284312; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP6]], 04313; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]4314; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i32> [[TMP3]] to i1284315; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 04316; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]4317; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 04318; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]4319; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]4320; CHECK: 8:4321; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]4322; CHECK-NEXT: unreachable4323; CHECK: 9:4324; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], <4 x float> [[A2:%.*]], i8 [[MASK:%.*]], i32 11)4325; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 84326; CHECK-NEXT: ret <4 x float> [[RES]]4327;4328 %res = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> %a2, i8 %mask, i32 11)4329 ret <4 x float> %res4330}4331 4332define <4 x float> @test_mask_add_ss_current(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) #0 {4333; CHECK-LABEL: @test_mask_add_ss_current(4334; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 84335; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84336; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 84337; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 84338; CHECK-NEXT: call void @llvm.donothing()4339; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP1]] to i1284340; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 04341; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i32> [[TMP2]] to i1284342; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP6]], 04343; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]4344; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i32> [[TMP3]] to i1284345; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 04346; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]4347; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 04348; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]4349; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]4350; CHECK: 8:4351; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]4352; CHECK-NEXT: unreachable4353; CHECK: 9:4354; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], <4 x float> [[A2:%.*]], i8 [[MASK:%.*]], i32 4)4355; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 84356; CHECK-NEXT: ret <4 x float> [[RES]]4357;4358 %res = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> %a2, i8 %mask, i32 4)4359 ret <4 x float> %res4360}4361 4362define <4 x float> @test_maskz_add_ss_rn(<4 x float> %a0, <4 x float> %a1, i8 %mask) #0 {4363; CHECK-LABEL: @test_maskz_add_ss_rn(4364; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 84365; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84366; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 84367; CHECK-NEXT: call void @llvm.donothing()4368; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP1]] to i1284369; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 04370; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP2]] to i1284371; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 04372; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]4373; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 04374; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]4375; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]4376; CHECK: 6:4377; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]4378; CHECK-NEXT: unreachable4379; CHECK: 7:4380; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], <4 x float> zeroinitializer, i8 [[MASK:%.*]], i32 8)4381; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 84382; CHECK-NEXT: ret <4 x float> [[RES]]4383;4384 %res = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> zeroinitializer, i8 %mask, i32 8)4385 ret <4 x float> %res4386}4387 4388define <4 x float> @test_add_ss_rn(<4 x float> %a0, <4 x float> %a1) #0 {4389; CHECK-LABEL: @test_add_ss_rn(4390; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 84391; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84392; CHECK-NEXT: call void @llvm.donothing()4393; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP1]] to i1284394; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 04395; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i1284396; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 04397; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]4398; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]4399; CHECK: 5:4400; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]4401; CHECK-NEXT: unreachable4402; CHECK: 6:4403; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], <4 x float> zeroinitializer, i8 -1, i32 8)4404; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 84405; CHECK-NEXT: ret <4 x float> [[RES]]4406;4407 %res = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> zeroinitializer, i8 -1, i32 8)4408 ret <4 x float> %res4409}4410 4411define <4 x float> @test_mask_add_ss_current_memfold(<4 x float> %a0, ptr %a1, <4 x float> %a2, i8 %mask, <4 x float> %extra_param) #0 {4412; CHECK-LABEL: @test_mask_add_ss_current_memfold(4413; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84414; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 84415; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 84416; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 84417; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 84418; CHECK-NEXT: call void @llvm.donothing()4419; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 04420; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP6:%.*]], label [[TMP13:%.*]], !prof [[PROF1]]4421; CHECK: 6:4422; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]4423; CHECK-NEXT: unreachable4424; CHECK: 7:4425; CHECK-NEXT: [[A1_VAL:%.*]] = load float, ptr [[A1:%.*]], align 44426; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[A1]] to i644427; CHECK-NEXT: [[TMP8:%.*]] = xor i64 [[TMP7]], 879609302220804428; CHECK-NEXT: [[TMP9:%.*]] = inttoptr i64 [[TMP8]] to ptr4429; CHECK-NEXT: [[_MSLD:%.*]] = load i32, ptr [[TMP9]], align 44430; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <4 x i32> [[TMP5]], i32 [[_MSLD]], i32 04431; CHECK-NEXT: [[A1V0:%.*]] = insertelement <4 x float> [[EXTRA_PARAM:%.*]], float [[A1_VAL]], i32 04432; CHECK-NEXT: [[_MSPROP1:%.*]] = insertelement <4 x i32> [[_MSPROP]], i32 0, i32 14433; CHECK-NEXT: [[A1V1:%.*]] = insertelement <4 x float> [[A1V0]], float 0.000000e+00, i32 14434; CHECK-NEXT: [[_MSPROP2:%.*]] = insertelement <4 x i32> [[_MSPROP1]], i32 0, i32 24435; CHECK-NEXT: [[A1V2:%.*]] = insertelement <4 x float> [[A1V1]], float 0.000000e+00, i32 24436; CHECK-NEXT: [[_MSPROP3:%.*]] = insertelement <4 x i32> [[_MSPROP2]], i32 0, i32 34437; CHECK-NEXT: [[A1V:%.*]] = insertelement <4 x float> [[A1V2]], float 0.000000e+00, i32 34438; CHECK-NEXT: [[TMP10:%.*]] = bitcast <4 x i32> [[TMP2]] to i1284439; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i128 [[TMP10]], 04440; CHECK-NEXT: [[TMP11:%.*]] = bitcast <4 x i32> [[_MSPROP3]] to i1284441; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i128 [[TMP11]], 04442; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP4]], [[_MSCMP5]]4443; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i32> [[TMP3]] to i1284444; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i128 [[TMP12]], 04445; CHECK-NEXT: [[_MSOR7:%.*]] = or i1 [[_MSOR]], [[_MSCMP6]]4446; CHECK-NEXT: [[_MSCMP8:%.*]] = icmp ne i8 [[TMP4]], 04447; CHECK-NEXT: [[_MSOR9:%.*]] = or i1 [[_MSOR7]], [[_MSCMP8]]4448; CHECK-NEXT: br i1 [[_MSOR9]], label [[TMP14:%.*]], label [[TMP15:%.*]], !prof [[PROF1]]4449; CHECK: 14:4450; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]4451; CHECK-NEXT: unreachable4452; CHECK: 15:4453; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float> [[A0:%.*]], <4 x float> [[A1V]], <4 x float> [[A2:%.*]], i8 [[MASK:%.*]], i32 4)4454; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 84455; CHECK-NEXT: ret <4 x float> [[RES]]4456;4457 %a1.val = load float, ptr %a14458 %a1v0 = insertelement <4 x float> %extra_param, float %a1.val, i32 04459 %a1v1 = insertelement <4 x float> %a1v0, float 0.000000e+00, i32 14460 %a1v2 = insertelement <4 x float> %a1v1, float 0.000000e+00, i32 24461 %a1v = insertelement <4 x float> %a1v2, float 0.000000e+00, i32 34462 %res = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>%a0, <4 x float> %a1v, <4 x float> %a2, i8 %mask, i32 4)4463 ret <4 x float> %res4464}4465 4466define <4 x float> @test_maskz_add_ss_current_memfold(<4 x float> %a0, ptr %a1, i8 %mask, <4 x float> %extra_param) #0 {4467; CHECK-LABEL: @test_maskz_add_ss_current_memfold(4468; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84469; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 84470; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 84471; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 84472; CHECK-NEXT: call void @llvm.donothing()4473; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 04474; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP5:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]4475; CHECK: 5:4476; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]4477; CHECK-NEXT: unreachable4478; CHECK: 6:4479; CHECK-NEXT: [[A1_VAL:%.*]] = load float, ptr [[A1:%.*]], align 44480; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[A1]] to i644481; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 879609302220804482; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr4483; CHECK-NEXT: [[_MSLD:%.*]] = load i32, ptr [[TMP8]], align 44484; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <4 x i32> [[TMP4]], i32 [[_MSLD]], i32 04485; CHECK-NEXT: [[A1V0:%.*]] = insertelement <4 x float> [[EXTRA_PARAM:%.*]], float [[A1_VAL]], i32 04486; CHECK-NEXT: [[_MSPROP1:%.*]] = insertelement <4 x i32> [[_MSPROP]], i32 0, i32 14487; CHECK-NEXT: [[A1V1:%.*]] = insertelement <4 x float> [[A1V0]], float 0.000000e+00, i32 14488; CHECK-NEXT: [[_MSPROP2:%.*]] = insertelement <4 x i32> [[_MSPROP1]], i32 0, i32 24489; CHECK-NEXT: [[A1V2:%.*]] = insertelement <4 x float> [[A1V1]], float 0.000000e+00, i32 24490; CHECK-NEXT: [[_MSPROP3:%.*]] = insertelement <4 x i32> [[_MSPROP2]], i32 0, i32 34491; CHECK-NEXT: [[A1V:%.*]] = insertelement <4 x float> [[A1V2]], float 0.000000e+00, i32 34492; CHECK-NEXT: [[TMP9:%.*]] = bitcast <4 x i32> [[TMP2]] to i1284493; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i128 [[TMP9]], 04494; CHECK-NEXT: [[TMP10:%.*]] = bitcast <4 x i32> [[_MSPROP3]] to i1284495; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i128 [[TMP10]], 04496; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP4]], [[_MSCMP5]]4497; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i8 [[TMP3]], 04498; CHECK-NEXT: [[_MSOR7:%.*]] = or i1 [[_MSOR]], [[_MSCMP6]]4499; CHECK-NEXT: br i1 [[_MSOR7]], label [[TMP12:%.*]], label [[TMP13:%.*]], !prof [[PROF1]]4500; CHECK: 12:4501; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]4502; CHECK-NEXT: unreachable4503; CHECK: 13:4504; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float> [[A0:%.*]], <4 x float> [[A1V]], <4 x float> zeroinitializer, i8 [[MASK:%.*]], i32 4)4505; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 84506; CHECK-NEXT: ret <4 x float> [[RES]]4507;4508 %a1.val = load float, ptr %a14509 %a1v0 = insertelement <4 x float> %extra_param, float %a1.val, i32 04510 %a1v1 = insertelement <4 x float> %a1v0, float 0.000000e+00, i32 14511 %a1v2 = insertelement <4 x float> %a1v1, float 0.000000e+00, i32 24512 %a1v = insertelement <4 x float> %a1v2, float 0.000000e+00, i32 34513 %res = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>%a0, <4 x float> %a1v, <4 x float> zeroinitializer, i8 %mask, i32 4)4514 ret <4 x float> %res4515}4516 4517declare <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>, <2 x double>, <2 x double>, i8, i32) nounwind readnone4518 4519define <2 x double> @test_mask_add_sd_rn(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) #0 {4520; CHECK-LABEL: @test_mask_add_sd_rn(4521; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 84522; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84523; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 84524; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 84525; CHECK-NEXT: call void @llvm.donothing()4526; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP1]] to i1284527; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 04528; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i64> [[TMP2]] to i1284529; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP6]], 04530; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]4531; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i64> [[TMP3]] to i1284532; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 04533; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]4534; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 04535; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]4536; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]4537; CHECK: 8:4538; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]4539; CHECK-NEXT: unreachable4540; CHECK: 9:4541; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]], <2 x double> [[A2:%.*]], i8 [[MASK:%.*]], i32 8)4542; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 84543; CHECK-NEXT: ret <2 x double> [[RES]]4544;4545 %res = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> %a2, i8 %mask, i32 8)4546 ret <2 x double> %res4547}4548 4549define <2 x double> @test_mask_add_sd_rd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) #0 {4550; CHECK-LABEL: @test_mask_add_sd_rd(4551; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 84552; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84553; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 84554; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 84555; CHECK-NEXT: call void @llvm.donothing()4556; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP1]] to i1284557; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 04558; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i64> [[TMP2]] to i1284559; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP6]], 04560; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]4561; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i64> [[TMP3]] to i1284562; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 04563; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]4564; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 04565; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]4566; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]4567; CHECK: 8:4568; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]4569; CHECK-NEXT: unreachable4570; CHECK: 9:4571; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]], <2 x double> [[A2:%.*]], i8 [[MASK:%.*]], i32 9)4572; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 84573; CHECK-NEXT: ret <2 x double> [[RES]]4574;4575 %res = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> %a2, i8 %mask, i32 9)4576 ret <2 x double> %res4577}4578 4579define <2 x double> @test_mask_add_sd_ru(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) #0 {4580; CHECK-LABEL: @test_mask_add_sd_ru(4581; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 84582; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84583; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 84584; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 84585; CHECK-NEXT: call void @llvm.donothing()4586; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP1]] to i1284587; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 04588; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i64> [[TMP2]] to i1284589; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP6]], 04590; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]4591; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i64> [[TMP3]] to i1284592; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 04593; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]4594; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 04595; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]4596; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]4597; CHECK: 8:4598; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]4599; CHECK-NEXT: unreachable4600; CHECK: 9:4601; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]], <2 x double> [[A2:%.*]], i8 [[MASK:%.*]], i32 10)4602; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 84603; CHECK-NEXT: ret <2 x double> [[RES]]4604;4605 %res = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> %a2, i8 %mask, i32 10)4606 ret <2 x double> %res4607}4608 4609define <2 x double> @test_mask_add_sd_rz(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) #0 {4610; CHECK-LABEL: @test_mask_add_sd_rz(4611; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 84612; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84613; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 84614; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 84615; CHECK-NEXT: call void @llvm.donothing()4616; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP1]] to i1284617; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 04618; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i64> [[TMP2]] to i1284619; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP6]], 04620; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]4621; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i64> [[TMP3]] to i1284622; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 04623; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]4624; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 04625; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]4626; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]4627; CHECK: 8:4628; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]4629; CHECK-NEXT: unreachable4630; CHECK: 9:4631; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]], <2 x double> [[A2:%.*]], i8 [[MASK:%.*]], i32 11)4632; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 84633; CHECK-NEXT: ret <2 x double> [[RES]]4634;4635 %res = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> %a2, i8 %mask, i32 11)4636 ret <2 x double> %res4637}4638 4639define <2 x double> @test_mask_add_sd_current(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) #0 {4640; CHECK-LABEL: @test_mask_add_sd_current(4641; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 84642; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84643; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 84644; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 84645; CHECK-NEXT: call void @llvm.donothing()4646; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP1]] to i1284647; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 04648; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i64> [[TMP2]] to i1284649; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP6]], 04650; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]4651; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i64> [[TMP3]] to i1284652; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 04653; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]4654; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 04655; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]4656; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]4657; CHECK: 8:4658; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]4659; CHECK-NEXT: unreachable4660; CHECK: 9:4661; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]], <2 x double> [[A2:%.*]], i8 [[MASK:%.*]], i32 4)4662; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 84663; CHECK-NEXT: ret <2 x double> [[RES]]4664;4665 %res = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> %a2, i8 %mask, i32 4)4666 ret <2 x double> %res4667}4668 4669define <2 x double> @test_maskz_add_sd_rn(<2 x double> %a0, <2 x double> %a1, i8 %mask) #0 {4670; CHECK-LABEL: @test_maskz_add_sd_rn(4671; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 84672; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84673; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 84674; CHECK-NEXT: call void @llvm.donothing()4675; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP1]] to i1284676; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 04677; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP2]] to i1284678; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 04679; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]4680; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 04681; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]4682; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]4683; CHECK: 6:4684; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]4685; CHECK-NEXT: unreachable4686; CHECK: 7:4687; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]], <2 x double> zeroinitializer, i8 [[MASK:%.*]], i32 8)4688; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 84689; CHECK-NEXT: ret <2 x double> [[RES]]4690;4691 %res = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> zeroinitializer, i8 %mask, i32 8)4692 ret <2 x double> %res4693}4694 4695define <2 x double> @test_add_sd_rn(<2 x double> %a0, <2 x double> %a1) #0 {4696; CHECK-LABEL: @test_add_sd_rn(4697; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 84698; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84699; CHECK-NEXT: call void @llvm.donothing()4700; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP1]] to i1284701; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 04702; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP2]] to i1284703; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 04704; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]4705; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]4706; CHECK: 5:4707; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]4708; CHECK-NEXT: unreachable4709; CHECK: 6:4710; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]], <2 x double> zeroinitializer, i8 -1, i32 8)4711; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 84712; CHECK-NEXT: ret <2 x double> [[RES]]4713;4714 %res = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> zeroinitializer, i8 -1, i32 8)4715 ret <2 x double> %res4716}4717 4718define <2 x double> @test_mask_add_sd_current_memfold(<2 x double> %a0, ptr %a1, <2 x double> %a2, i8 %mask, <2 x double> %extra_param) #0 {4719; CHECK-LABEL: @test_mask_add_sd_current_memfold(4720; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84721; CHECK-NEXT: [[TMP5:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 84722; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 84723; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 84724; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 84725; CHECK-NEXT: call void @llvm.donothing()4726; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 04727; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP6:%.*]], label [[TMP13:%.*]], !prof [[PROF1]]4728; CHECK: 6:4729; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]4730; CHECK-NEXT: unreachable4731; CHECK: 7:4732; CHECK-NEXT: [[A1_VAL:%.*]] = load double, ptr [[A1:%.*]], align 84733; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[A1]] to i644734; CHECK-NEXT: [[TMP8:%.*]] = xor i64 [[TMP7]], 879609302220804735; CHECK-NEXT: [[TMP9:%.*]] = inttoptr i64 [[TMP8]] to ptr4736; CHECK-NEXT: [[_MSLD:%.*]] = load i64, ptr [[TMP9]], align 84737; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <2 x i64> [[TMP5]], i64 [[_MSLD]], i32 04738; CHECK-NEXT: [[A1V0:%.*]] = insertelement <2 x double> [[EXTRA_PARAM:%.*]], double [[A1_VAL]], i32 04739; CHECK-NEXT: [[_MSPROP1:%.*]] = insertelement <2 x i64> [[_MSPROP]], i64 0, i32 14740; CHECK-NEXT: [[A1V:%.*]] = insertelement <2 x double> [[A1V0]], double 0.000000e+00, i32 14741; CHECK-NEXT: [[TMP10:%.*]] = bitcast <2 x i64> [[TMP2]] to i1284742; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP10]], 04743; CHECK-NEXT: [[TMP11:%.*]] = bitcast <2 x i64> [[_MSPROP1]] to i1284744; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP11]], 04745; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]4746; CHECK-NEXT: [[TMP12:%.*]] = bitcast <2 x i64> [[TMP3]] to i1284747; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i128 [[TMP12]], 04748; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR]], [[_MSCMP4]]4749; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i8 [[TMP4]], 04750; CHECK-NEXT: [[_MSOR7:%.*]] = or i1 [[_MSOR5]], [[_MSCMP6]]4751; CHECK-NEXT: br i1 [[_MSOR7]], label [[TMP14:%.*]], label [[TMP15:%.*]], !prof [[PROF1]]4752; CHECK: 14:4753; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]4754; CHECK-NEXT: unreachable4755; CHECK: 15:4756; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double> [[A0:%.*]], <2 x double> [[A1V]], <2 x double> [[A2:%.*]], i8 [[MASK:%.*]], i32 4)4757; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 84758; CHECK-NEXT: ret <2 x double> [[RES]]4759;4760 %a1.val = load double, ptr %a14761 %a1v0 = insertelement <2 x double> %extra_param, double %a1.val, i32 04762 %a1v = insertelement <2 x double> %a1v0, double 0.000000e+00, i32 14763 %res = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>%a0, <2 x double> %a1v, <2 x double> %a2, i8 %mask, i32 4)4764 ret <2 x double> %res4765}4766 4767define <2 x double> @test_maskz_add_sd_current_memfold(<2 x double> %a0, ptr %a1, i8 %mask, <2 x double> %extra_param) #0 {4768; CHECK-LABEL: @test_maskz_add_sd_current_memfold(4769; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84770; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 84771; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 84772; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 84773; CHECK-NEXT: call void @llvm.donothing()4774; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 04775; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP5:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]4776; CHECK: 5:4777; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]4778; CHECK-NEXT: unreachable4779; CHECK: 6:4780; CHECK-NEXT: [[A1_VAL:%.*]] = load double, ptr [[A1:%.*]], align 84781; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[A1]] to i644782; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 879609302220804783; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr4784; CHECK-NEXT: [[_MSLD:%.*]] = load i64, ptr [[TMP8]], align 84785; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <2 x i64> [[TMP4]], i64 [[_MSLD]], i32 04786; CHECK-NEXT: [[A1V0:%.*]] = insertelement <2 x double> [[EXTRA_PARAM:%.*]], double [[A1_VAL]], i32 04787; CHECK-NEXT: [[_MSPROP1:%.*]] = insertelement <2 x i64> [[_MSPROP]], i64 0, i32 14788; CHECK-NEXT: [[A1V:%.*]] = insertelement <2 x double> [[A1V0]], double 0.000000e+00, i32 14789; CHECK-NEXT: [[TMP9:%.*]] = bitcast <2 x i64> [[TMP2]] to i1284790; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP9]], 04791; CHECK-NEXT: [[TMP10:%.*]] = bitcast <2 x i64> [[_MSPROP1]] to i1284792; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP10]], 04793; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]4794; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP3]], 04795; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR]], [[_MSCMP4]]4796; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP12:%.*]], label [[TMP13:%.*]], !prof [[PROF1]]4797; CHECK: 12:4798; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]4799; CHECK-NEXT: unreachable4800; CHECK: 13:4801; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double> [[A0:%.*]], <2 x double> [[A1V]], <2 x double> zeroinitializer, i8 [[MASK:%.*]], i32 4)4802; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 84803; CHECK-NEXT: ret <2 x double> [[RES]]4804;4805 %a1.val = load double, ptr %a14806 %a1v0 = insertelement <2 x double> %extra_param, double %a1.val, i32 04807 %a1v = insertelement <2 x double> %a1v0, double 0.000000e+00, i32 14808 %res = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>%a0, <2 x double> %a1v, <2 x double> zeroinitializer, i8 %mask, i32 4)4809 ret <2 x double> %res4810}4811 4812declare <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>, <4 x float>, <4 x float>, i8, i32) nounwind readnone4813 4814define <4 x float> @test_mask_max_ss_sae(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) #0 {4815; CHECK-LABEL: @test_mask_max_ss_sae(4816; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 84817; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84818; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 84819; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 84820; CHECK-NEXT: call void @llvm.donothing()4821; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP1]] to i1284822; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 04823; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i32> [[TMP2]] to i1284824; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP6]], 04825; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]4826; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i32> [[TMP3]] to i1284827; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 04828; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]4829; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 04830; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]4831; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]4832; CHECK: 8:4833; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]4834; CHECK-NEXT: unreachable4835; CHECK: 9:4836; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], <4 x float> [[A2:%.*]], i8 [[MASK:%.*]], i32 8)4837; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 84838; CHECK-NEXT: ret <4 x float> [[RES]]4839;4840 %res = call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> %a2, i8 %mask, i32 8)4841 ret <4 x float> %res4842}4843 4844define <4 x float> @test_maskz_max_ss_sae(<4 x float> %a0, <4 x float> %a1, i8 %mask) #0 {4845; CHECK-LABEL: @test_maskz_max_ss_sae(4846; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 84847; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84848; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 84849; CHECK-NEXT: call void @llvm.donothing()4850; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP1]] to i1284851; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 04852; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP2]] to i1284853; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 04854; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]4855; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 04856; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]4857; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]4858; CHECK: 6:4859; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]4860; CHECK-NEXT: unreachable4861; CHECK: 7:4862; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], <4 x float> zeroinitializer, i8 [[MASK:%.*]], i32 8)4863; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 84864; CHECK-NEXT: ret <4 x float> [[RES]]4865;4866 %res = call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> zeroinitializer, i8 %mask, i32 8)4867 ret <4 x float> %res4868}4869 4870define <4 x float> @test_max_ss_sae(<4 x float> %a0, <4 x float> %a1) #0 {4871; CHECK-LABEL: @test_max_ss_sae(4872; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 84873; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84874; CHECK-NEXT: call void @llvm.donothing()4875; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP1]] to i1284876; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 04877; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i1284878; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 04879; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]4880; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]4881; CHECK: 5:4882; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]4883; CHECK-NEXT: unreachable4884; CHECK: 6:4885; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], <4 x float> zeroinitializer, i8 -1, i32 8)4886; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 84887; CHECK-NEXT: ret <4 x float> [[RES]]4888;4889 %res = call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> zeroinitializer, i8 -1, i32 8)4890 ret <4 x float> %res4891}4892 4893define <4 x float> @test_mask_max_ss(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) #0 {4894; CHECK-LABEL: @test_mask_max_ss(4895; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 84896; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84897; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 84898; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 84899; CHECK-NEXT: call void @llvm.donothing()4900; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP1]] to i1284901; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 04902; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i32> [[TMP2]] to i1284903; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP6]], 04904; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]4905; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i32> [[TMP3]] to i1284906; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 04907; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]4908; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 04909; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]4910; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]4911; CHECK: 8:4912; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]4913; CHECK-NEXT: unreachable4914; CHECK: 9:4915; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], <4 x float> [[A2:%.*]], i8 [[MASK:%.*]], i32 4)4916; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 84917; CHECK-NEXT: ret <4 x float> [[RES]]4918;4919 %res = call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> %a2, i8 %mask, i32 4)4920 ret <4 x float> %res4921}4922 4923define <4 x float> @test_maskz_max_ss(<4 x float> %a0, <4 x float> %a1, i8 %mask) #0 {4924; CHECK-LABEL: @test_maskz_max_ss(4925; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 84926; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84927; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 84928; CHECK-NEXT: call void @llvm.donothing()4929; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP1]] to i1284930; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 04931; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP2]] to i1284932; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 04933; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]4934; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 04935; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]4936; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]4937; CHECK: 6:4938; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]4939; CHECK-NEXT: unreachable4940; CHECK: 7:4941; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], <4 x float> zeroinitializer, i8 [[MASK:%.*]], i32 4)4942; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 84943; CHECK-NEXT: ret <4 x float> [[RES]]4944;4945 %res = call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> zeroinitializer, i8 %mask, i32 4)4946 ret <4 x float> %res4947}4948 4949define <4 x float> @test_max_ss(<4 x float> %a0, <4 x float> %a1) #0 {4950; CHECK-LABEL: @test_max_ss(4951; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 84952; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84953; CHECK-NEXT: call void @llvm.donothing()4954; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP1]] to i1284955; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 04956; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i1284957; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 04958; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]4959; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]4960; CHECK: 5:4961; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]4962; CHECK-NEXT: unreachable4963; CHECK: 6:4964; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], <4 x float> zeroinitializer, i8 -1, i32 4)4965; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 84966; CHECK-NEXT: ret <4 x float> [[RES]]4967;4968 %res = call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> zeroinitializer, i8 -1, i32 4)4969 ret <4 x float> %res4970}4971 4972define <4 x float> @test_mask_max_ss_memfold(<4 x float> %a0, ptr %a1, <4 x float> %a2, i8 %mask, <4 x float> %extra_param) #0 {4973; CHECK-LABEL: @test_mask_max_ss_memfold(4974; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84975; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 84976; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 84977; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 84978; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 84979; CHECK-NEXT: call void @llvm.donothing()4980; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 04981; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP6:%.*]], label [[TMP13:%.*]], !prof [[PROF1]]4982; CHECK: 6:4983; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]4984; CHECK-NEXT: unreachable4985; CHECK: 7:4986; CHECK-NEXT: [[A1_VAL:%.*]] = load float, ptr [[A1:%.*]], align 44987; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[A1]] to i644988; CHECK-NEXT: [[TMP8:%.*]] = xor i64 [[TMP7]], 879609302220804989; CHECK-NEXT: [[TMP9:%.*]] = inttoptr i64 [[TMP8]] to ptr4990; CHECK-NEXT: [[_MSLD:%.*]] = load i32, ptr [[TMP9]], align 44991; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <4 x i32> [[TMP5]], i32 [[_MSLD]], i32 04992; CHECK-NEXT: [[A1V0:%.*]] = insertelement <4 x float> [[EXTRA_PARAM:%.*]], float [[A1_VAL]], i32 04993; CHECK-NEXT: [[_MSPROP1:%.*]] = insertelement <4 x i32> [[_MSPROP]], i32 0, i32 14994; CHECK-NEXT: [[A1V1:%.*]] = insertelement <4 x float> [[A1V0]], float 0.000000e+00, i32 14995; CHECK-NEXT: [[_MSPROP2:%.*]] = insertelement <4 x i32> [[_MSPROP1]], i32 0, i32 24996; CHECK-NEXT: [[A1V2:%.*]] = insertelement <4 x float> [[A1V1]], float 0.000000e+00, i32 24997; CHECK-NEXT: [[_MSPROP3:%.*]] = insertelement <4 x i32> [[_MSPROP2]], i32 0, i32 34998; CHECK-NEXT: [[A1V:%.*]] = insertelement <4 x float> [[A1V2]], float 0.000000e+00, i32 34999; CHECK-NEXT: [[TMP10:%.*]] = bitcast <4 x i32> [[TMP2]] to i1285000; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i128 [[TMP10]], 05001; CHECK-NEXT: [[TMP11:%.*]] = bitcast <4 x i32> [[_MSPROP3]] to i1285002; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i128 [[TMP11]], 05003; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP4]], [[_MSCMP5]]5004; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i32> [[TMP3]] to i1285005; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i128 [[TMP12]], 05006; CHECK-NEXT: [[_MSOR7:%.*]] = or i1 [[_MSOR]], [[_MSCMP6]]5007; CHECK-NEXT: [[_MSCMP8:%.*]] = icmp ne i8 [[TMP4]], 05008; CHECK-NEXT: [[_MSOR9:%.*]] = or i1 [[_MSOR7]], [[_MSCMP8]]5009; CHECK-NEXT: br i1 [[_MSOR9]], label [[TMP14:%.*]], label [[TMP15:%.*]], !prof [[PROF1]]5010; CHECK: 14:5011; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]5012; CHECK-NEXT: unreachable5013; CHECK: 15:5014; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float> [[A0:%.*]], <4 x float> [[A1V]], <4 x float> [[A2:%.*]], i8 [[MASK:%.*]], i32 4)5015; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 85016; CHECK-NEXT: ret <4 x float> [[RES]]5017;5018 %a1.val = load float, ptr %a15019 %a1v0 = insertelement <4 x float> %extra_param, float %a1.val, i32 05020 %a1v1 = insertelement <4 x float> %a1v0, float 0.000000e+00, i32 15021 %a1v2 = insertelement <4 x float> %a1v1, float 0.000000e+00, i32 25022 %a1v = insertelement <4 x float> %a1v2, float 0.000000e+00, i32 35023 %res = call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>%a0, <4 x float> %a1v, <4 x float> %a2, i8 %mask, i32 4)5024 ret <4 x float> %res5025}5026 5027define <4 x float> @test_maskz_max_ss_memfold(<4 x float> %a0, ptr %a1, i8 %mask, <4 x float> %extra_param) #0 {5028; CHECK-LABEL: @test_maskz_max_ss_memfold(5029; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 85030; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 85031; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 85032; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 85033; CHECK-NEXT: call void @llvm.donothing()5034; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05035; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP5:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]5036; CHECK: 5:5037; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]5038; CHECK-NEXT: unreachable5039; CHECK: 6:5040; CHECK-NEXT: [[A1_VAL:%.*]] = load float, ptr [[A1:%.*]], align 45041; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[A1]] to i645042; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 879609302220805043; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr5044; CHECK-NEXT: [[_MSLD:%.*]] = load i32, ptr [[TMP8]], align 45045; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <4 x i32> [[TMP4]], i32 [[_MSLD]], i32 05046; CHECK-NEXT: [[A1V0:%.*]] = insertelement <4 x float> [[EXTRA_PARAM:%.*]], float [[A1_VAL]], i32 05047; CHECK-NEXT: [[_MSPROP1:%.*]] = insertelement <4 x i32> [[_MSPROP]], i32 0, i32 15048; CHECK-NEXT: [[A1V1:%.*]] = insertelement <4 x float> [[A1V0]], float 0.000000e+00, i32 15049; CHECK-NEXT: [[_MSPROP2:%.*]] = insertelement <4 x i32> [[_MSPROP1]], i32 0, i32 25050; CHECK-NEXT: [[A1V2:%.*]] = insertelement <4 x float> [[A1V1]], float 0.000000e+00, i32 25051; CHECK-NEXT: [[_MSPROP3:%.*]] = insertelement <4 x i32> [[_MSPROP2]], i32 0, i32 35052; CHECK-NEXT: [[A1V:%.*]] = insertelement <4 x float> [[A1V2]], float 0.000000e+00, i32 35053; CHECK-NEXT: [[TMP9:%.*]] = bitcast <4 x i32> [[TMP2]] to i1285054; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i128 [[TMP9]], 05055; CHECK-NEXT: [[TMP10:%.*]] = bitcast <4 x i32> [[_MSPROP3]] to i1285056; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i128 [[TMP10]], 05057; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP4]], [[_MSCMP5]]5058; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i8 [[TMP3]], 05059; CHECK-NEXT: [[_MSOR7:%.*]] = or i1 [[_MSOR]], [[_MSCMP6]]5060; CHECK-NEXT: br i1 [[_MSOR7]], label [[TMP12:%.*]], label [[TMP13:%.*]], !prof [[PROF1]]5061; CHECK: 12:5062; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]5063; CHECK-NEXT: unreachable5064; CHECK: 13:5065; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float> [[A0:%.*]], <4 x float> [[A1V]], <4 x float> zeroinitializer, i8 [[MASK:%.*]], i32 4)5066; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 85067; CHECK-NEXT: ret <4 x float> [[RES]]5068;5069 %a1.val = load float, ptr %a15070 %a1v0 = insertelement <4 x float> %extra_param, float %a1.val, i32 05071 %a1v1 = insertelement <4 x float> %a1v0, float 0.000000e+00, i32 15072 %a1v2 = insertelement <4 x float> %a1v1, float 0.000000e+00, i32 25073 %a1v = insertelement <4 x float> %a1v2, float 0.000000e+00, i32 35074 %res = call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>%a0, <4 x float> %a1v, <4 x float> zeroinitializer, i8 %mask, i32 4)5075 ret <4 x float> %res5076}5077declare <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>, <2 x double>, <2 x double>, i8, i32) nounwind readnone5078 5079define <2 x double> @test_mask_max_sd_sae(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) #0 {5080; CHECK-LABEL: @test_mask_max_sd_sae(5081; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 85082; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 85083; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 85084; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 85085; CHECK-NEXT: call void @llvm.donothing()5086; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP1]] to i1285087; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 05088; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i64> [[TMP2]] to i1285089; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP6]], 05090; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]5091; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i64> [[TMP3]] to i1285092; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 05093; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]5094; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 05095; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]5096; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]5097; CHECK: 8:5098; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]5099; CHECK-NEXT: unreachable5100; CHECK: 9:5101; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]], <2 x double> [[A2:%.*]], i8 [[MASK:%.*]], i32 8)5102; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 85103; CHECK-NEXT: ret <2 x double> [[RES]]5104;5105 %res = call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> %a2, i8 %mask, i32 8)5106 ret <2 x double> %res5107}5108 5109define <2 x double> @test_maskz_max_sd_sae(<2 x double> %a0, <2 x double> %a1, i8 %mask) #0 {5110; CHECK-LABEL: @test_maskz_max_sd_sae(5111; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 85112; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 85113; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 85114; CHECK-NEXT: call void @llvm.donothing()5115; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP1]] to i1285116; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 05117; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP2]] to i1285118; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 05119; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]5120; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 05121; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]5122; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]5123; CHECK: 6:5124; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]5125; CHECK-NEXT: unreachable5126; CHECK: 7:5127; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]], <2 x double> zeroinitializer, i8 [[MASK:%.*]], i32 8)5128; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 85129; CHECK-NEXT: ret <2 x double> [[RES]]5130;5131 %res = call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> zeroinitializer, i8 %mask, i32 8)5132 ret <2 x double> %res5133}5134 5135define <2 x double> @test_max_sd_sae(<2 x double> %a0, <2 x double> %a1) #0 {5136; CHECK-LABEL: @test_max_sd_sae(5137; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 85138; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 85139; CHECK-NEXT: call void @llvm.donothing()5140; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP1]] to i1285141; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 05142; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP2]] to i1285143; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 05144; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]5145; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]5146; CHECK: 5:5147; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]5148; CHECK-NEXT: unreachable5149; CHECK: 6:5150; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]], <2 x double> zeroinitializer, i8 -1, i32 8)5151; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 85152; CHECK-NEXT: ret <2 x double> [[RES]]5153;5154 %res = call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> zeroinitializer, i8 -1, i32 8)5155 ret <2 x double> %res5156}5157 5158define <2 x double> @test_mask_max_sd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) #0 {5159; CHECK-LABEL: @test_mask_max_sd(5160; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 85161; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 85162; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 85163; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 85164; CHECK-NEXT: call void @llvm.donothing()5165; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP1]] to i1285166; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 05167; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i64> [[TMP2]] to i1285168; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP6]], 05169; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]5170; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i64> [[TMP3]] to i1285171; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 05172; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]5173; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 05174; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]5175; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]5176; CHECK: 8:5177; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]5178; CHECK-NEXT: unreachable5179; CHECK: 9:5180; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]], <2 x double> [[A2:%.*]], i8 [[MASK:%.*]], i32 4)5181; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 85182; CHECK-NEXT: ret <2 x double> [[RES]]5183;5184 %res = call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> %a2, i8 %mask, i32 4)5185 ret <2 x double> %res5186}5187 5188define <2 x double> @test_maskz_max_sd(<2 x double> %a0, <2 x double> %a1, i8 %mask) #0 {5189; CHECK-LABEL: @test_maskz_max_sd(5190; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 85191; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 85192; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 85193; CHECK-NEXT: call void @llvm.donothing()5194; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP1]] to i1285195; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 05196; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP2]] to i1285197; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 05198; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]5199; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 05200; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]5201; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]5202; CHECK: 6:5203; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]5204; CHECK-NEXT: unreachable5205; CHECK: 7:5206; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]], <2 x double> zeroinitializer, i8 [[MASK:%.*]], i32 4)5207; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 85208; CHECK-NEXT: ret <2 x double> [[RES]]5209;5210 %res = call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> zeroinitializer, i8 %mask, i32 4)5211 ret <2 x double> %res5212}5213 5214define <2 x double> @test_max_sd(<2 x double> %a0, <2 x double> %a1) #0 {5215; CHECK-LABEL: @test_max_sd(5216; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 85217; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 85218; CHECK-NEXT: call void @llvm.donothing()5219; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP1]] to i1285220; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 05221; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP2]] to i1285222; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 05223; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]5224; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]5225; CHECK: 5:5226; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]5227; CHECK-NEXT: unreachable5228; CHECK: 6:5229; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]], <2 x double> zeroinitializer, i8 -1, i32 4)5230; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 85231; CHECK-NEXT: ret <2 x double> [[RES]]5232;5233 %res = call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> zeroinitializer, i8 -1, i32 4)5234 ret <2 x double> %res5235}5236 5237define <2 x double> @test_mask_max_sd_memfold(<2 x double> %a0, ptr %a1, <2 x double> %a2, i8 %mask, <2 x double> %extra_param) #0 {5238; CHECK-LABEL: @test_mask_max_sd_memfold(5239; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 85240; CHECK-NEXT: [[TMP5:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 85241; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 85242; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 85243; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 85244; CHECK-NEXT: call void @llvm.donothing()5245; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05246; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP6:%.*]], label [[TMP13:%.*]], !prof [[PROF1]]5247; CHECK: 6:5248; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]5249; CHECK-NEXT: unreachable5250; CHECK: 7:5251; CHECK-NEXT: [[A1_VAL:%.*]] = load double, ptr [[A1:%.*]], align 85252; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[A1]] to i645253; CHECK-NEXT: [[TMP8:%.*]] = xor i64 [[TMP7]], 879609302220805254; CHECK-NEXT: [[TMP9:%.*]] = inttoptr i64 [[TMP8]] to ptr5255; CHECK-NEXT: [[_MSLD:%.*]] = load i64, ptr [[TMP9]], align 85256; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <2 x i64> [[TMP5]], i64 [[_MSLD]], i32 05257; CHECK-NEXT: [[A1V0:%.*]] = insertelement <2 x double> [[EXTRA_PARAM:%.*]], double [[A1_VAL]], i32 05258; CHECK-NEXT: [[_MSPROP1:%.*]] = insertelement <2 x i64> [[_MSPROP]], i64 0, i32 15259; CHECK-NEXT: [[A1V:%.*]] = insertelement <2 x double> [[A1V0]], double 0.000000e+00, i32 15260; CHECK-NEXT: [[TMP10:%.*]] = bitcast <2 x i64> [[TMP2]] to i1285261; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP10]], 05262; CHECK-NEXT: [[TMP11:%.*]] = bitcast <2 x i64> [[_MSPROP1]] to i1285263; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP11]], 05264; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]5265; CHECK-NEXT: [[TMP12:%.*]] = bitcast <2 x i64> [[TMP3]] to i1285266; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i128 [[TMP12]], 05267; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR]], [[_MSCMP4]]5268; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i8 [[TMP4]], 05269; CHECK-NEXT: [[_MSOR7:%.*]] = or i1 [[_MSOR5]], [[_MSCMP6]]5270; CHECK-NEXT: br i1 [[_MSOR7]], label [[TMP14:%.*]], label [[TMP15:%.*]], !prof [[PROF1]]5271; CHECK: 14:5272; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]5273; CHECK-NEXT: unreachable5274; CHECK: 15:5275; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double> [[A0:%.*]], <2 x double> [[A1V]], <2 x double> [[A2:%.*]], i8 [[MASK:%.*]], i32 4)5276; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 85277; CHECK-NEXT: ret <2 x double> [[RES]]5278;5279 %a1.val = load double, ptr %a15280 %a1v0 = insertelement <2 x double> %extra_param, double %a1.val, i32 05281 %a1v = insertelement <2 x double> %a1v0, double 0.000000e+00, i32 15282 %res = call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>%a0, <2 x double> %a1v, <2 x double> %a2, i8 %mask, i32 4)5283 ret <2 x double> %res5284}5285 5286define <2 x double> @test_maskz_max_sd_memfold(<2 x double> %a0, ptr %a1, i8 %mask, <2 x double> %extra_param) #0 {5287; CHECK-LABEL: @test_maskz_max_sd_memfold(5288; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 85289; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 85290; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 85291; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 85292; CHECK-NEXT: call void @llvm.donothing()5293; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05294; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP5:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]5295; CHECK: 5:5296; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]5297; CHECK-NEXT: unreachable5298; CHECK: 6:5299; CHECK-NEXT: [[A1_VAL:%.*]] = load double, ptr [[A1:%.*]], align 85300; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[A1]] to i645301; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 879609302220805302; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr5303; CHECK-NEXT: [[_MSLD:%.*]] = load i64, ptr [[TMP8]], align 85304; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <2 x i64> [[TMP4]], i64 [[_MSLD]], i32 05305; CHECK-NEXT: [[A1V0:%.*]] = insertelement <2 x double> [[EXTRA_PARAM:%.*]], double [[A1_VAL]], i32 05306; CHECK-NEXT: [[_MSPROP1:%.*]] = insertelement <2 x i64> [[_MSPROP]], i64 0, i32 15307; CHECK-NEXT: [[A1V:%.*]] = insertelement <2 x double> [[A1V0]], double 0.000000e+00, i32 15308; CHECK-NEXT: [[TMP9:%.*]] = bitcast <2 x i64> [[TMP2]] to i1285309; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP9]], 05310; CHECK-NEXT: [[TMP10:%.*]] = bitcast <2 x i64> [[_MSPROP1]] to i1285311; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP10]], 05312; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]5313; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP3]], 05314; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR]], [[_MSCMP4]]5315; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP12:%.*]], label [[TMP13:%.*]], !prof [[PROF1]]5316; CHECK: 12:5317; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]5318; CHECK-NEXT: unreachable5319; CHECK: 13:5320; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double> [[A0:%.*]], <2 x double> [[A1V]], <2 x double> zeroinitializer, i8 [[MASK:%.*]], i32 4)5321; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 85322; CHECK-NEXT: ret <2 x double> [[RES]]5323;5324 %a1.val = load double, ptr %a15325 %a1v0 = insertelement <2 x double> %extra_param, double %a1.val, i32 05326 %a1v = insertelement <2 x double> %a1v0, double 0.000000e+00, i32 15327 %res = call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>%a0, <2 x double> %a1v, <2 x double> zeroinitializer, i8 %mask, i32 4)5328 ret <2 x double> %res5329}5330 5331define <4 x float> @test_x86_avx512_cvtsi2ss32(<4 x float> %a, i32 %b) #0 {5332; CHECK-LABEL: @test_x86_avx512_cvtsi2ss32(5333; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 85334; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 85335; CHECK-NEXT: call void @llvm.donothing()5336; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP1]] to i1285337; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 05338; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i32 [[TMP2]], 05339; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]5340; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF1]]5341; CHECK: 4:5342; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]5343; CHECK-NEXT: unreachable5344; CHECK: 5:5345; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.cvtsi2ss32(<4 x float> [[A:%.*]], i32 [[B:%.*]], i32 11)5346; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 85347; CHECK-NEXT: ret <4 x float> [[RES]]5348;5349 %res = call <4 x float> @llvm.x86.avx512.cvtsi2ss32(<4 x float> %a, i32 %b, i32 11) ; <<<4 x float>> [#uses=1]5350 ret <4 x float> %res5351}5352declare <4 x float> @llvm.x86.avx512.cvtsi2ss32(<4 x float>, i32, i32) nounwind readnone5353 5354define <4 x float> @test_x86_avx512__mm_cvt_roundu32_ss (<4 x float> %a, i32 %b) #0 {5355; CHECK-LABEL: @test_x86_avx512__mm_cvt_roundu32_ss(5356; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 85357; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 85358; CHECK-NEXT: call void @llvm.donothing()5359; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 0, i32 05360; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP1]], 05361; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF1]]5362; CHECK: 4:5363; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]5364; CHECK-NEXT: unreachable5365; CHECK: 5:5366; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.cvtusi2ss(<4 x float> [[A:%.*]], i32 [[B:%.*]], i32 9)5367; CHECK-NEXT: store <4 x i32> [[TMP3]], ptr @__msan_retval_tls, align 85368; CHECK-NEXT: ret <4 x float> [[RES]]5369;5370 %res = call <4 x float> @llvm.x86.avx512.cvtusi2ss(<4 x float> %a, i32 %b, i32 9) ; <<<4 x float>> [#uses=1]5371 ret <4 x float> %res5372}5373 5374define <4 x float> @test_x86_avx512__mm_cvt_roundu32_ss_mem(<4 x float> %a, ptr %ptr) #0 {5375; CHECK-LABEL: @test_x86_avx512__mm_cvt_roundu32_ss_mem(5376; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 85377; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 85378; CHECK-NEXT: call void @llvm.donothing()5379; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05380; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]5381; CHECK: 3:5382; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]5383; CHECK-NEXT: unreachable5384; CHECK: 4:5385; CHECK-NEXT: [[B:%.*]] = load i32, ptr [[PTR:%.*]], align 45386; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[PTR]] to i645387; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 879609302220805388; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr5389; CHECK-NEXT: [[_MSLD:%.*]] = load i32, ptr [[TMP7]], align 45390; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x i32> [[TMP2]], i32 0, i32 05391; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i32 [[_MSLD]], 05392; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP9:%.*]], label [[TMP10:%.*]], !prof [[PROF1]]5393; CHECK: 9:5394; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]5395; CHECK-NEXT: unreachable5396; CHECK: 10:5397; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.cvtusi2ss(<4 x float> [[A:%.*]], i32 [[B]], i32 9)5398; CHECK-NEXT: store <4 x i32> [[TMP8]], ptr @__msan_retval_tls, align 85399; CHECK-NEXT: ret <4 x float> [[RES]]5400;5401 %b = load i32, ptr %ptr5402 %res = call <4 x float> @llvm.x86.avx512.cvtusi2ss(<4 x float> %a, i32 %b, i32 9) ; <<<4 x float>> [#uses=1]5403 ret <4 x float> %res5404}5405 5406define <4 x float> @test_x86_avx512__mm_cvtu32_ss(<4 x float> %a, i32 %b) #0 {5407; CHECK-LABEL: @test_x86_avx512__mm_cvtu32_ss(5408; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 85409; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 85410; CHECK-NEXT: call void @llvm.donothing()5411; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 0, i32 05412; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP1]], 05413; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF1]]5414; CHECK: 4:5415; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]5416; CHECK-NEXT: unreachable5417; CHECK: 5:5418; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.cvtusi2ss(<4 x float> [[A:%.*]], i32 [[B:%.*]], i32 4)5419; CHECK-NEXT: store <4 x i32> [[TMP3]], ptr @__msan_retval_tls, align 85420; CHECK-NEXT: ret <4 x float> [[RES]]5421;5422 %res = call <4 x float> @llvm.x86.avx512.cvtusi2ss(<4 x float> %a, i32 %b, i32 4) ; <<<4 x float>> [#uses=1]5423 ret <4 x float> %res5424}5425 5426define <4 x float> @test_x86_avx512__mm_cvtu32_ss_mem(<4 x float> %a, ptr %ptr) #0 {5427; CHECK-LABEL: @test_x86_avx512__mm_cvtu32_ss_mem(5428; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 85429; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 85430; CHECK-NEXT: call void @llvm.donothing()5431; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05432; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]5433; CHECK: 3:5434; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]5435; CHECK-NEXT: unreachable5436; CHECK: 4:5437; CHECK-NEXT: [[B:%.*]] = load i32, ptr [[PTR:%.*]], align 45438; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[PTR]] to i645439; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 879609302220805440; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr5441; CHECK-NEXT: [[_MSLD:%.*]] = load i32, ptr [[TMP7]], align 45442; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x i32> [[TMP2]], i32 0, i32 05443; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i32 [[_MSLD]], 05444; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP9:%.*]], label [[TMP10:%.*]], !prof [[PROF1]]5445; CHECK: 9:5446; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]5447; CHECK-NEXT: unreachable5448; CHECK: 10:5449; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.cvtusi2ss(<4 x float> [[A:%.*]], i32 [[B]], i32 4)5450; CHECK-NEXT: store <4 x i32> [[TMP8]], ptr @__msan_retval_tls, align 85451; CHECK-NEXT: ret <4 x float> [[RES]]5452;5453 %b = load i32, ptr %ptr5454 %res = call <4 x float> @llvm.x86.avx512.cvtusi2ss(<4 x float> %a, i32 %b, i32 4) ; <<<4 x float>> [#uses=1]5455 ret <4 x float> %res5456}5457declare <4 x float> @llvm.x86.avx512.cvtusi2ss(<4 x float>, i32, i32) nounwind readnone5458 5459declare <16 x i32> @llvm.x86.avx512.vpermi2var.d.512(<16 x i32>, <16 x i32>, <16 x i32>)5460 5461define <16 x i32>@test_int_x86_avx512_vpermi2var_d_512(<16 x i32> %x0, <16 x i32> %x1, ptr %x2p) #0 {5462; CHECK-LABEL: @test_int_x86_avx512_vpermi2var_d_512(5463; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 85464; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 85465; CHECK-NEXT: [[X1:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 85466; CHECK-NEXT: call void @llvm.donothing()5467; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05468; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF1]]5469; CHECK: 4:5470; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]5471; CHECK-NEXT: unreachable5472; CHECK: 5:5473; CHECK-NEXT: [[X2:%.*]] = load <16 x i32>, ptr [[X2P:%.*]], align 645474; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[X2P]] to i645475; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 879609302220805476; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr5477; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i32>, ptr [[TMP8]], align 645478; CHECK-NEXT: [[TMP13:%.*]] = trunc <16 x i32> [[X1]] to <16 x i4>5479; CHECK-NEXT: [[_MSPROP1:%.*]] = call <16 x i32> @llvm.x86.avx512.vpermi2var.d.512(<16 x i32> [[TMP2]], <16 x i32> [[X3:%.*]], <16 x i32> [[_MSLD]])5480; CHECK-NEXT: [[TMP10:%.*]] = bitcast <16 x i4> [[TMP13]] to i645481; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP10]], 05482; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP12:%.*]], label [[TMP14:%.*]], !prof [[PROF1]]5483; CHECK: 12:5484; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]5485; CHECK-NEXT: unreachable5486; CHECK: 13:5487; CHECK-NEXT: [[TMP9:%.*]] = call <16 x i32> @llvm.x86.avx512.vpermi2var.d.512(<16 x i32> [[X0:%.*]], <16 x i32> [[X3]], <16 x i32> [[X2]])5488; CHECK-NEXT: store <16 x i32> [[_MSPROP1]], ptr @__msan_retval_tls, align 85489; CHECK-NEXT: ret <16 x i32> [[TMP9]]5490;5491 %x2 = load <16 x i32>, ptr %x2p5492 %1 = call <16 x i32> @llvm.x86.avx512.vpermi2var.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2)5493 ret <16 x i32> %15494}5495 5496define <16 x i32>@test_int_x86_avx512_mask_vpermi2var_d_512(<16 x i32> %x0, <16 x i32> %x1, ptr %x2p, i16 %x3) #0 {5497; CHECK-LABEL: @test_int_x86_avx512_mask_vpermi2var_d_512(5498; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 85499; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 85500; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 85501; CHECK-NEXT: [[TMP4:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 136), align 85502; CHECK-NEXT: call void @llvm.donothing()5503; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05504; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]5505; CHECK: 5:5506; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]5507; CHECK-NEXT: unreachable5508; CHECK: 6:5509; CHECK-NEXT: [[X2:%.*]] = load <16 x i32>, ptr [[X2P:%.*]], align 645510; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[X2P]] to i645511; CHECK-NEXT: [[TMP8:%.*]] = xor i64 [[TMP7]], 879609302220805512; CHECK-NEXT: [[TMP9:%.*]] = inttoptr i64 [[TMP8]] to ptr5513; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i32>, ptr [[TMP9]], align 645514; CHECK-NEXT: [[TMP18:%.*]] = trunc <16 x i32> [[TMP3]] to <16 x i4>5515; CHECK-NEXT: [[_MSPROP1:%.*]] = call <16 x i32> @llvm.x86.avx512.vpermi2var.d.512(<16 x i32> [[TMP2]], <16 x i32> [[X1:%.*]], <16 x i32> [[_MSLD]])5516; CHECK-NEXT: [[TMP19:%.*]] = bitcast <16 x i4> [[TMP18]] to i645517; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP19]], 05518; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP20:%.*]], label [[TMP21:%.*]], !prof [[PROF1]]5519; CHECK: 13:5520; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]5521; CHECK-NEXT: unreachable5522; CHECK: 14:5523; CHECK-NEXT: [[TMP10:%.*]] = call <16 x i32> @llvm.x86.avx512.vpermi2var.d.512(<16 x i32> [[X0:%.*]], <16 x i32> [[X1]], <16 x i32> [[X2]])5524; CHECK-NEXT: [[TMP11:%.*]] = bitcast i16 [[TMP4]] to <16 x i1>5525; CHECK-NEXT: [[TMP12:%.*]] = bitcast i16 [[X3:%.*]] to <16 x i1>5526; CHECK-NEXT: [[TMP13:%.*]] = select <16 x i1> [[TMP12]], <16 x i32> [[_MSPROP1]], <16 x i32> [[TMP3]]5527; CHECK-NEXT: [[TMP14:%.*]] = xor <16 x i32> [[TMP10]], [[X1]]5528; CHECK-NEXT: [[TMP15:%.*]] = or <16 x i32> [[TMP14]], [[_MSPROP1]]5529; CHECK-NEXT: [[TMP16:%.*]] = or <16 x i32> [[TMP15]], [[TMP3]]5530; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP11]], <16 x i32> [[TMP16]], <16 x i32> [[TMP13]]5531; CHECK-NEXT: [[TMP17:%.*]] = select <16 x i1> [[TMP12]], <16 x i32> [[TMP10]], <16 x i32> [[X1]]5532; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 85533; CHECK-NEXT: ret <16 x i32> [[TMP17]]5534;5535 %x2 = load <16 x i32>, ptr %x2p5536 %1 = call <16 x i32> @llvm.x86.avx512.vpermi2var.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2)5537 %2 = bitcast i16 %x3 to <16 x i1>5538 %3 = select <16 x i1> %2, <16 x i32> %1, <16 x i32> %x15539 ret <16 x i32> %35540}5541 5542declare <8 x double> @llvm.x86.avx512.vpermi2var.pd.512(<8 x double>, <8 x i64>, <8 x double>)5543 5544define <8 x double>@test_int_x86_avx512_vpermi2var_pd_512(<8 x double> %x0, <8 x i64> %x1, <8 x double> %x2) #0 {5545; CHECK-LABEL: @test_int_x86_avx512_vpermi2var_pd_512(5546; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 85547; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 85548; CHECK-NEXT: [[X1:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 85549; CHECK-NEXT: call void @llvm.donothing()5550; CHECK-NEXT: [[TMP6:%.*]] = trunc <8 x i64> [[X1]] to <8 x i3>5551; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i64> [[TMP1]] to <8 x double>5552; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i64> [[TMP3]] to <8 x double>5553; CHECK-NEXT: [[TMP11:%.*]] = call <8 x double> @llvm.x86.avx512.vpermi2var.pd.512(<8 x double> [[TMP4]], <8 x i64> [[X3:%.*]], <8 x double> [[TMP5]])5554; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x double> [[TMP11]] to <8 x i64>5555; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i3> [[TMP6]] to i245556; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i24 [[TMP8]], 05557; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP10:%.*]], label [[TMP12:%.*]], !prof [[PROF1]]5558; CHECK: 10:5559; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]5560; CHECK-NEXT: unreachable5561; CHECK: 11:5562; CHECK-NEXT: [[TMP9:%.*]] = call <8 x double> @llvm.x86.avx512.vpermi2var.pd.512(<8 x double> [[X0:%.*]], <8 x i64> [[X3]], <8 x double> [[X2:%.*]])5563; CHECK-NEXT: store <8 x i64> [[TMP7]], ptr @__msan_retval_tls, align 85564; CHECK-NEXT: ret <8 x double> [[TMP9]]5565;5566 %1 = call <8 x double> @llvm.x86.avx512.vpermi2var.pd.512(<8 x double> %x0, <8 x i64> %x1, <8 x double> %x2)5567 ret <8 x double> %15568}5569 5570define <8 x double>@test_int_x86_avx512_mask_vpermi2var_pd_512(<8 x double> %x0, <8 x i64> %x1, <8 x double> %x2, i8 %x3) #0 {5571; CHECK-LABEL: @test_int_x86_avx512_mask_vpermi2var_pd_512(5572; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 85573; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 85574; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 85575; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 85576; CHECK-NEXT: call void @llvm.donothing()5577; CHECK-NEXT: [[TMP7:%.*]] = trunc <8 x i64> [[TMP2]] to <8 x i3>5578; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i64> [[TMP1]] to <8 x double>5579; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i64> [[TMP3]] to <8 x double>5580; CHECK-NEXT: [[TMP9:%.*]] = call <8 x double> @llvm.x86.avx512.vpermi2var.pd.512(<8 x double> [[TMP5]], <8 x i64> [[X1:%.*]], <8 x double> [[TMP6]])5581; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x double> [[TMP9]] to <8 x i64>5582; CHECK-NEXT: [[TMP21:%.*]] = bitcast <8 x i3> [[TMP7]] to i245583; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i24 [[TMP21]], 05584; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP22:%.*]], label [[TMP23:%.*]], !prof [[PROF1]]5585; CHECK: 11:5586; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]5587; CHECK-NEXT: unreachable5588; CHECK: 12:5589; CHECK-NEXT: [[TMP10:%.*]] = call <8 x double> @llvm.x86.avx512.vpermi2var.pd.512(<8 x double> [[X0:%.*]], <8 x i64> [[X1]], <8 x double> [[X2:%.*]])5590; CHECK-NEXT: [[TMP11:%.*]] = bitcast <8 x i64> [[X1]] to <8 x double>5591; CHECK-NEXT: [[TMP12:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>5592; CHECK-NEXT: [[TMP13:%.*]] = bitcast i8 [[X3:%.*]] to <8 x i1>5593; CHECK-NEXT: [[TMP14:%.*]] = select <8 x i1> [[TMP13]], <8 x i64> [[TMP8]], <8 x i64> [[TMP2]]5594; CHECK-NEXT: [[TMP15:%.*]] = bitcast <8 x double> [[TMP10]] to <8 x i64>5595; CHECK-NEXT: [[TMP16:%.*]] = bitcast <8 x double> [[TMP11]] to <8 x i64>5596; CHECK-NEXT: [[TMP17:%.*]] = xor <8 x i64> [[TMP15]], [[TMP16]]5597; CHECK-NEXT: [[TMP18:%.*]] = or <8 x i64> [[TMP17]], [[TMP8]]5598; CHECK-NEXT: [[TMP19:%.*]] = or <8 x i64> [[TMP18]], [[TMP2]]5599; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP12]], <8 x i64> [[TMP19]], <8 x i64> [[TMP14]]5600; CHECK-NEXT: [[TMP20:%.*]] = select <8 x i1> [[TMP13]], <8 x double> [[TMP10]], <8 x double> [[TMP11]]5601; CHECK-NEXT: store <8 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 85602; CHECK-NEXT: ret <8 x double> [[TMP20]]5603;5604 %1 = call <8 x double> @llvm.x86.avx512.vpermi2var.pd.512(<8 x double> %x0, <8 x i64> %x1, <8 x double> %x2)5605 %2 = bitcast <8 x i64> %x1 to <8 x double>5606 %3 = bitcast i8 %x3 to <8 x i1>5607 %4 = select <8 x i1> %3, <8 x double> %1, <8 x double> %25608 ret <8 x double> %45609}5610 5611declare <16 x float> @llvm.x86.avx512.vpermi2var.ps.512(<16 x float>, <16 x i32>, <16 x float>)5612 5613define <16 x float>@test_int_x86_avx512_vpermi2var_ps_512(<16 x float> %x0, <16 x i32> %x1, <16 x float> %x2) #0 {5614; CHECK-LABEL: @test_int_x86_avx512_vpermi2var_ps_512(5615; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 85616; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 85617; CHECK-NEXT: [[X1:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 85618; CHECK-NEXT: call void @llvm.donothing()5619; CHECK-NEXT: [[TMP6:%.*]] = trunc <16 x i32> [[X1]] to <16 x i4>5620; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP1]] to <16 x float>5621; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP3]] to <16 x float>5622; CHECK-NEXT: [[TMP11:%.*]] = call <16 x float> @llvm.x86.avx512.vpermi2var.ps.512(<16 x float> [[TMP4]], <16 x i32> [[X3:%.*]], <16 x float> [[TMP5]])5623; CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x float> [[TMP11]] to <16 x i32>5624; CHECK-NEXT: [[TMP8:%.*]] = bitcast <16 x i4> [[TMP6]] to i645625; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP8]], 05626; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP10:%.*]], label [[TMP12:%.*]], !prof [[PROF1]]5627; CHECK: 10:5628; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]5629; CHECK-NEXT: unreachable5630; CHECK: 11:5631; CHECK-NEXT: [[TMP9:%.*]] = call <16 x float> @llvm.x86.avx512.vpermi2var.ps.512(<16 x float> [[X0:%.*]], <16 x i32> [[X3]], <16 x float> [[X2:%.*]])5632; CHECK-NEXT: store <16 x i32> [[TMP7]], ptr @__msan_retval_tls, align 85633; CHECK-NEXT: ret <16 x float> [[TMP9]]5634;5635 %1 = call <16 x float> @llvm.x86.avx512.vpermi2var.ps.512(<16 x float> %x0, <16 x i32> %x1, <16 x float> %x2)5636 ret <16 x float> %15637}5638 5639define <16 x float>@test_int_x86_avx512_mask_vpermi2var_ps_512(<16 x float> %x0, <16 x i32> %x1, <16 x float> %x2, i16 %x3) #0 {5640; CHECK-LABEL: @test_int_x86_avx512_mask_vpermi2var_ps_512(5641; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 85642; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 85643; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 85644; CHECK-NEXT: [[TMP4:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 85645; CHECK-NEXT: call void @llvm.donothing()5646; CHECK-NEXT: [[TMP7:%.*]] = trunc <16 x i32> [[TMP2]] to <16 x i4>5647; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP1]] to <16 x float>5648; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i32> [[TMP3]] to <16 x float>5649; CHECK-NEXT: [[TMP9:%.*]] = call <16 x float> @llvm.x86.avx512.vpermi2var.ps.512(<16 x float> [[TMP5]], <16 x i32> [[X1:%.*]], <16 x float> [[TMP6]])5650; CHECK-NEXT: [[TMP8:%.*]] = bitcast <16 x float> [[TMP9]] to <16 x i32>5651; CHECK-NEXT: [[TMP21:%.*]] = bitcast <16 x i4> [[TMP7]] to i645652; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP21]], 05653; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP22:%.*]], label [[TMP23:%.*]], !prof [[PROF1]]5654; CHECK: 11:5655; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]5656; CHECK-NEXT: unreachable5657; CHECK: 12:5658; CHECK-NEXT: [[TMP10:%.*]] = call <16 x float> @llvm.x86.avx512.vpermi2var.ps.512(<16 x float> [[X0:%.*]], <16 x i32> [[X1]], <16 x float> [[X2:%.*]])5659; CHECK-NEXT: [[TMP11:%.*]] = bitcast <16 x i32> [[X1]] to <16 x float>5660; CHECK-NEXT: [[TMP12:%.*]] = bitcast i16 [[TMP4]] to <16 x i1>5661; CHECK-NEXT: [[TMP13:%.*]] = bitcast i16 [[X3:%.*]] to <16 x i1>5662; CHECK-NEXT: [[TMP14:%.*]] = select <16 x i1> [[TMP13]], <16 x i32> [[TMP8]], <16 x i32> [[TMP2]]5663; CHECK-NEXT: [[TMP15:%.*]] = bitcast <16 x float> [[TMP10]] to <16 x i32>5664; CHECK-NEXT: [[TMP16:%.*]] = bitcast <16 x float> [[TMP11]] to <16 x i32>5665; CHECK-NEXT: [[TMP17:%.*]] = xor <16 x i32> [[TMP15]], [[TMP16]]5666; CHECK-NEXT: [[TMP18:%.*]] = or <16 x i32> [[TMP17]], [[TMP8]]5667; CHECK-NEXT: [[TMP19:%.*]] = or <16 x i32> [[TMP18]], [[TMP2]]5668; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP12]], <16 x i32> [[TMP19]], <16 x i32> [[TMP14]]5669; CHECK-NEXT: [[TMP20:%.*]] = select <16 x i1> [[TMP13]], <16 x float> [[TMP10]], <16 x float> [[TMP11]]5670; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 85671; CHECK-NEXT: ret <16 x float> [[TMP20]]5672;5673 %1 = call <16 x float> @llvm.x86.avx512.vpermi2var.ps.512(<16 x float> %x0, <16 x i32> %x1, <16 x float> %x2)5674 %2 = bitcast <16 x i32> %x1 to <16 x float>5675 %3 = bitcast i16 %x3 to <16 x i1>5676 %4 = select <16 x i1> %3, <16 x float> %1, <16 x float> %25677 ret <16 x float> %45678}5679 5680declare <8 x i64> @llvm.x86.avx512.vpermi2var.q.512(<8 x i64>, <8 x i64>, <8 x i64>)5681 5682define <8 x i64>@test_int_x86_avx512_vpermi2var_q_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2) #0 {5683; CHECK-LABEL: @test_int_x86_avx512_vpermi2var_q_512(5684; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 85685; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 85686; CHECK-NEXT: [[X1:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 85687; CHECK-NEXT: call void @llvm.donothing()5688; CHECK-NEXT: [[TMP8:%.*]] = trunc <8 x i64> [[X1]] to <8 x i3>5689; CHECK-NEXT: [[_MSPROP1:%.*]] = call <8 x i64> @llvm.x86.avx512.vpermi2var.q.512(<8 x i64> [[TMP1]], <8 x i64> [[X3:%.*]], <8 x i64> [[TMP3]])5690; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i3> [[TMP8]] to i245691; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i24 [[TMP5]], 05692; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP7:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]5693; CHECK: 7:5694; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]5695; CHECK-NEXT: unreachable5696; CHECK: 8:5697; CHECK-NEXT: [[TMP4:%.*]] = call <8 x i64> @llvm.x86.avx512.vpermi2var.q.512(<8 x i64> [[X0:%.*]], <8 x i64> [[X3]], <8 x i64> [[X2:%.*]])5698; CHECK-NEXT: store <8 x i64> [[_MSPROP1]], ptr @__msan_retval_tls, align 85699; CHECK-NEXT: ret <8 x i64> [[TMP4]]5700;5701 %1 = call <8 x i64> @llvm.x86.avx512.vpermi2var.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2)5702 ret <8 x i64> %15703}5704 5705define <8 x i64>@test_int_x86_avx512_mask_vpermi2var_q_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) #0 {5706; CHECK-LABEL: @test_int_x86_avx512_mask_vpermi2var_q_512(5707; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 85708; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 85709; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 85710; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 85711; CHECK-NEXT: call void @llvm.donothing()5712; CHECK-NEXT: [[TMP13:%.*]] = trunc <8 x i64> [[TMP2]] to <8 x i3>5713; CHECK-NEXT: [[_MSPROP1:%.*]] = call <8 x i64> @llvm.x86.avx512.vpermi2var.q.512(<8 x i64> [[TMP1]], <8 x i64> [[X1:%.*]], <8 x i64> [[TMP3]])5714; CHECK-NEXT: [[TMP14:%.*]] = bitcast <8 x i3> [[TMP13]] to i245715; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i24 [[TMP14]], 05716; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP15:%.*]], label [[TMP16:%.*]], !prof [[PROF1]]5717; CHECK: 8:5718; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]5719; CHECK-NEXT: unreachable5720; CHECK: 9:5721; CHECK-NEXT: [[TMP5:%.*]] = call <8 x i64> @llvm.x86.avx512.vpermi2var.q.512(<8 x i64> [[X0:%.*]], <8 x i64> [[X1]], <8 x i64> [[X2:%.*]])5722; CHECK-NEXT: [[TMP6:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>5723; CHECK-NEXT: [[TMP7:%.*]] = bitcast i8 [[X3:%.*]] to <8 x i1>5724; CHECK-NEXT: [[TMP8:%.*]] = select <8 x i1> [[TMP7]], <8 x i64> [[_MSPROP1]], <8 x i64> [[TMP2]]5725; CHECK-NEXT: [[TMP9:%.*]] = xor <8 x i64> [[TMP5]], [[X1]]5726; CHECK-NEXT: [[TMP10:%.*]] = or <8 x i64> [[TMP9]], [[_MSPROP1]]5727; CHECK-NEXT: [[TMP11:%.*]] = or <8 x i64> [[TMP10]], [[TMP2]]5728; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP6]], <8 x i64> [[TMP11]], <8 x i64> [[TMP8]]5729; CHECK-NEXT: [[TMP12:%.*]] = select <8 x i1> [[TMP7]], <8 x i64> [[TMP5]], <8 x i64> [[X1]]5730; CHECK-NEXT: store <8 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 85731; CHECK-NEXT: ret <8 x i64> [[TMP12]]5732;5733 %1 = call <8 x i64> @llvm.x86.avx512.vpermi2var.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2)5734 %2 = bitcast i8 %x3 to <8 x i1>5735 %3 = select <8 x i1> %2, <8 x i64> %1, <8 x i64> %x15736 ret <8 x i64> %35737}5738 5739define <16 x i32>@test_int_x86_avx512_maskz_vpermt2var_d_512(<16 x i32> %x0, <16 x i32> %x1, ptr %x2p, i16 %x3) #0 {5740; CHECK-LABEL: @test_int_x86_avx512_maskz_vpermt2var_d_512(5741; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 85742; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 85743; CHECK-NEXT: [[X0:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 85744; CHECK-NEXT: [[TMP4:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 136), align 85745; CHECK-NEXT: call void @llvm.donothing()5746; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05747; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]5748; CHECK: 5:5749; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]5750; CHECK-NEXT: unreachable5751; CHECK: 6:5752; CHECK-NEXT: [[X2:%.*]] = load <16 x i32>, ptr [[X2P:%.*]], align 645753; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[X2P]] to i645754; CHECK-NEXT: [[TMP8:%.*]] = xor i64 [[TMP7]], 879609302220805755; CHECK-NEXT: [[TMP9:%.*]] = inttoptr i64 [[TMP8]] to ptr5756; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i32>, ptr [[TMP9]], align 645757; CHECK-NEXT: [[TMP18:%.*]] = trunc <16 x i32> [[X0]] to <16 x i4>5758; CHECK-NEXT: [[_MSPROP1:%.*]] = call <16 x i32> @llvm.x86.avx512.vpermi2var.d.512(<16 x i32> [[TMP2]], <16 x i32> [[X4:%.*]], <16 x i32> [[_MSLD]])5759; CHECK-NEXT: [[TMP19:%.*]] = bitcast <16 x i4> [[TMP18]] to i645760; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP19]], 05761; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP20:%.*]], label [[TMP21:%.*]], !prof [[PROF1]]5762; CHECK: 13:5763; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]5764; CHECK-NEXT: unreachable5765; CHECK: 14:5766; CHECK-NEXT: [[TMP10:%.*]] = call <16 x i32> @llvm.x86.avx512.vpermi2var.d.512(<16 x i32> [[X1:%.*]], <16 x i32> [[X4]], <16 x i32> [[X2]])5767; CHECK-NEXT: [[TMP11:%.*]] = bitcast i16 [[TMP4]] to <16 x i1>5768; CHECK-NEXT: [[TMP12:%.*]] = bitcast i16 [[X3:%.*]] to <16 x i1>5769; CHECK-NEXT: [[TMP13:%.*]] = select <16 x i1> [[TMP12]], <16 x i32> [[_MSPROP1]], <16 x i32> zeroinitializer5770; CHECK-NEXT: [[TMP14:%.*]] = xor <16 x i32> [[TMP10]], zeroinitializer5771; CHECK-NEXT: [[TMP15:%.*]] = or <16 x i32> [[TMP14]], [[_MSPROP1]]5772; CHECK-NEXT: [[TMP16:%.*]] = or <16 x i32> [[TMP15]], zeroinitializer5773; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP11]], <16 x i32> [[TMP16]], <16 x i32> [[TMP13]]5774; CHECK-NEXT: [[TMP17:%.*]] = select <16 x i1> [[TMP12]], <16 x i32> [[TMP10]], <16 x i32> zeroinitializer5775; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 85776; CHECK-NEXT: ret <16 x i32> [[TMP17]]5777;5778 %x2 = load <16 x i32>, ptr %x2p5779 %1 = call <16 x i32> @llvm.x86.avx512.vpermi2var.d.512(<16 x i32> %x1, <16 x i32> %x0, <16 x i32> %x2)5780 %2 = bitcast i16 %x3 to <16 x i1>5781 %3 = select <16 x i1> %2, <16 x i32> %1, <16 x i32> zeroinitializer5782 ret <16 x i32> %35783}5784 5785define <8 x double>@test_int_x86_avx512_maskz_vpermt2var_pd_512(<8 x i64> %x0, <8 x double> %x1, ptr %x2ptr, i8 %x3, <8 x double> %extra_param, <8 x double> %extra_param2) #0 {5786; CHECK-LABEL: @test_int_x86_avx512_maskz_vpermt2var_pd_512(5787; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 85788; CHECK-NEXT: [[TMP5:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 144), align 85789; CHECK-NEXT: [[TMP6:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 208), align 85790; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 85791; CHECK-NEXT: [[X0:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 85792; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 136), align 85793; CHECK-NEXT: call void @llvm.donothing()5794; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05795; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP10:%.*]], label [[TMP12:%.*]], !prof [[PROF1]]5796; CHECK: 7:5797; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]5798; CHECK-NEXT: unreachable5799; CHECK: 8:5800; CHECK-NEXT: [[X2S:%.*]] = load double, ptr [[X2PTR:%.*]], align 85801; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[X2PTR]] to i645802; CHECK-NEXT: [[TMP8:%.*]] = xor i64 [[TMP7]], 879609302220805803; CHECK-NEXT: [[TMP9:%.*]] = inttoptr i64 [[TMP8]] to ptr5804; CHECK-NEXT: [[_MSLD:%.*]] = load i64, ptr [[TMP9]], align 85805; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <8 x i64> [[TMP5]], i64 [[_MSLD]], i32 05806; CHECK-NEXT: [[X2INS:%.*]] = insertelement <8 x double> [[EXTRA_PARAM:%.*]], double [[X2S]], i32 05807; CHECK-NEXT: [[_MSPROP1:%.*]] = shufflevector <8 x i64> [[_MSPROP]], <8 x i64> [[TMP6]], <8 x i32> zeroinitializer5808; CHECK-NEXT: [[X2:%.*]] = shufflevector <8 x double> [[X2INS]], <8 x double> [[EXTRA_PARAM2:%.*]], <8 x i32> zeroinitializer5809; CHECK-NEXT: [[TMP11:%.*]] = trunc <8 x i64> [[X0]] to <8 x i3>5810; CHECK-NEXT: [[TMP24:%.*]] = bitcast <8 x i64> [[TMP2]] to <8 x double>5811; CHECK-NEXT: [[TMP13:%.*]] = bitcast <8 x i64> [[_MSPROP1]] to <8 x double>5812; CHECK-NEXT: [[TMP14:%.*]] = call <8 x double> @llvm.x86.avx512.vpermi2var.pd.512(<8 x double> [[TMP24]], <8 x i64> [[X4:%.*]], <8 x double> [[TMP13]])5813; CHECK-NEXT: [[TMP25:%.*]] = bitcast <8 x double> [[TMP14]] to <8 x i64>5814; CHECK-NEXT: [[TMP26:%.*]] = bitcast <8 x i3> [[TMP11]] to i245815; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i24 [[TMP26]], 05816; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP27:%.*]], label [[TMP28:%.*]], !prof [[PROF1]]5817; CHECK: 18:5818; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]5819; CHECK-NEXT: unreachable5820; CHECK: 19:5821; CHECK-NEXT: [[TMP15:%.*]] = call <8 x double> @llvm.x86.avx512.vpermi2var.pd.512(<8 x double> [[X1:%.*]], <8 x i64> [[X4]], <8 x double> [[X2]])5822; CHECK-NEXT: [[TMP16:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>5823; CHECK-NEXT: [[TMP17:%.*]] = bitcast i8 [[X3:%.*]] to <8 x i1>5824; CHECK-NEXT: [[TMP18:%.*]] = select <8 x i1> [[TMP17]], <8 x i64> [[TMP25]], <8 x i64> zeroinitializer5825; CHECK-NEXT: [[TMP19:%.*]] = bitcast <8 x double> [[TMP15]] to <8 x i64>5826; CHECK-NEXT: [[TMP20:%.*]] = xor <8 x i64> [[TMP19]], zeroinitializer5827; CHECK-NEXT: [[TMP21:%.*]] = or <8 x i64> [[TMP20]], [[TMP25]]5828; CHECK-NEXT: [[TMP22:%.*]] = or <8 x i64> [[TMP21]], zeroinitializer5829; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP16]], <8 x i64> [[TMP22]], <8 x i64> [[TMP18]]5830; CHECK-NEXT: [[TMP23:%.*]] = select <8 x i1> [[TMP17]], <8 x double> [[TMP15]], <8 x double> zeroinitializer5831; CHECK-NEXT: store <8 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 85832; CHECK-NEXT: ret <8 x double> [[TMP23]]5833;5834 %x2s = load double, ptr %x2ptr5835 %x2ins = insertelement <8 x double> %extra_param, double %x2s, i32 05836 %x2 = shufflevector <8 x double> %x2ins, <8 x double> %extra_param2, <8 x i32> zeroinitializer5837 %1 = call <8 x double> @llvm.x86.avx512.vpermi2var.pd.512(<8 x double> %x1, <8 x i64> %x0, <8 x double> %x2)5838 %2 = bitcast i8 %x3 to <8 x i1>5839 %3 = select <8 x i1> %2, <8 x double> %1, <8 x double> zeroinitializer5840 ret <8 x double> %35841}5842 5843define <16 x float>@test_int_x86_avx512_maskz_vpermt2var_ps_512(<16 x i32> %x0, <16 x float> %x1, <16 x float> %x2, i16 %x3) #0 {5844; CHECK-LABEL: @test_int_x86_avx512_maskz_vpermt2var_ps_512(5845; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 85846; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 85847; CHECK-NEXT: [[X0:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 85848; CHECK-NEXT: [[TMP4:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 85849; CHECK-NEXT: call void @llvm.donothing()5850; CHECK-NEXT: [[TMP7:%.*]] = trunc <16 x i32> [[X0]] to <16 x i4>5851; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP1]] to <16 x float>5852; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i32> [[TMP3]] to <16 x float>5853; CHECK-NEXT: [[TMP19:%.*]] = call <16 x float> @llvm.x86.avx512.vpermi2var.ps.512(<16 x float> [[TMP5]], <16 x i32> [[X4:%.*]], <16 x float> [[TMP6]])5854; CHECK-NEXT: [[TMP8:%.*]] = bitcast <16 x float> [[TMP19]] to <16 x i32>5855; CHECK-NEXT: [[TMP9:%.*]] = bitcast <16 x i4> [[TMP7]] to i645856; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP9]], 05857; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP20:%.*]], label [[TMP21:%.*]], !prof [[PROF1]]5858; CHECK: 11:5859; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]5860; CHECK-NEXT: unreachable5861; CHECK: 12:5862; CHECK-NEXT: [[TMP10:%.*]] = call <16 x float> @llvm.x86.avx512.vpermi2var.ps.512(<16 x float> [[X1:%.*]], <16 x i32> [[X4]], <16 x float> [[X2:%.*]])5863; CHECK-NEXT: [[TMP11:%.*]] = bitcast i16 [[TMP4]] to <16 x i1>5864; CHECK-NEXT: [[TMP12:%.*]] = bitcast i16 [[X3:%.*]] to <16 x i1>5865; CHECK-NEXT: [[TMP13:%.*]] = select <16 x i1> [[TMP12]], <16 x i32> [[TMP8]], <16 x i32> zeroinitializer5866; CHECK-NEXT: [[TMP14:%.*]] = bitcast <16 x float> [[TMP10]] to <16 x i32>5867; CHECK-NEXT: [[TMP15:%.*]] = xor <16 x i32> [[TMP14]], zeroinitializer5868; CHECK-NEXT: [[TMP16:%.*]] = or <16 x i32> [[TMP15]], [[TMP8]]5869; CHECK-NEXT: [[TMP17:%.*]] = or <16 x i32> [[TMP16]], zeroinitializer5870; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP11]], <16 x i32> [[TMP17]], <16 x i32> [[TMP13]]5871; CHECK-NEXT: [[TMP18:%.*]] = select <16 x i1> [[TMP12]], <16 x float> [[TMP10]], <16 x float> zeroinitializer5872; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 85873; CHECK-NEXT: ret <16 x float> [[TMP18]]5874;5875 %1 = call <16 x float> @llvm.x86.avx512.vpermi2var.ps.512(<16 x float> %x1, <16 x i32> %x0, <16 x float> %x2)5876 %2 = bitcast i16 %x3 to <16 x i1>5877 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> zeroinitializer5878 ret <16 x float> %35879}5880 5881define <8 x i64>@test_int_x86_avx512_maskz_vpermt2var_q_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) #0 {5882; CHECK-LABEL: @test_int_x86_avx512_maskz_vpermt2var_q_512(5883; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 85884; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 85885; CHECK-NEXT: [[X0:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 85886; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 85887; CHECK-NEXT: call void @llvm.donothing()5888; CHECK-NEXT: [[TMP13:%.*]] = trunc <8 x i64> [[X0]] to <8 x i3>5889; CHECK-NEXT: [[_MSPROP1:%.*]] = call <8 x i64> @llvm.x86.avx512.vpermi2var.q.512(<8 x i64> [[TMP1]], <8 x i64> [[X4:%.*]], <8 x i64> [[TMP3]])5890; CHECK-NEXT: [[TMP14:%.*]] = bitcast <8 x i3> [[TMP13]] to i245891; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i24 [[TMP14]], 05892; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP15:%.*]], label [[TMP16:%.*]], !prof [[PROF1]]5893; CHECK: 8:5894; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]5895; CHECK-NEXT: unreachable5896; CHECK: 9:5897; CHECK-NEXT: [[TMP5:%.*]] = call <8 x i64> @llvm.x86.avx512.vpermi2var.q.512(<8 x i64> [[X1:%.*]], <8 x i64> [[X4]], <8 x i64> [[X2:%.*]])5898; CHECK-NEXT: [[TMP6:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>5899; CHECK-NEXT: [[TMP7:%.*]] = bitcast i8 [[X3:%.*]] to <8 x i1>5900; CHECK-NEXT: [[TMP8:%.*]] = select <8 x i1> [[TMP7]], <8 x i64> [[_MSPROP1]], <8 x i64> zeroinitializer5901; CHECK-NEXT: [[TMP9:%.*]] = xor <8 x i64> [[TMP5]], zeroinitializer5902; CHECK-NEXT: [[TMP10:%.*]] = or <8 x i64> [[TMP9]], [[_MSPROP1]]5903; CHECK-NEXT: [[TMP11:%.*]] = or <8 x i64> [[TMP10]], zeroinitializer5904; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP6]], <8 x i64> [[TMP11]], <8 x i64> [[TMP8]]5905; CHECK-NEXT: [[TMP12:%.*]] = select <8 x i1> [[TMP7]], <8 x i64> [[TMP5]], <8 x i64> zeroinitializer5906; CHECK-NEXT: store <8 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 85907; CHECK-NEXT: ret <8 x i64> [[TMP12]]5908;5909 %1 = call <8 x i64> @llvm.x86.avx512.vpermi2var.q.512(<8 x i64> %x1, <8 x i64> %x0, <8 x i64> %x2)5910 %2 = bitcast i8 %x3 to <8 x i1>5911 %3 = select <8 x i1> %2, <8 x i64> %1, <8 x i64> zeroinitializer5912 ret <8 x i64> %35913}5914 5915define <16 x i32>@test_int_x86_avx512_vpermt2var_d_512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2) #0 {5916; CHECK-LABEL: @test_int_x86_avx512_vpermt2var_d_512(5917; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 85918; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 85919; CHECK-NEXT: [[X0:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 85920; CHECK-NEXT: call void @llvm.donothing()5921; CHECK-NEXT: [[TMP8:%.*]] = trunc <16 x i32> [[X0]] to <16 x i4>5922; CHECK-NEXT: [[_MSPROP1:%.*]] = call <16 x i32> @llvm.x86.avx512.vpermi2var.d.512(<16 x i32> [[TMP1]], <16 x i32> [[X3:%.*]], <16 x i32> [[TMP3]])5923; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i4> [[TMP8]] to i645924; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP5]], 05925; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP7:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]5926; CHECK: 7:5927; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]5928; CHECK-NEXT: unreachable5929; CHECK: 8:5930; CHECK-NEXT: [[TMP4:%.*]] = call <16 x i32> @llvm.x86.avx512.vpermi2var.d.512(<16 x i32> [[X1:%.*]], <16 x i32> [[X3]], <16 x i32> [[X2:%.*]])5931; CHECK-NEXT: store <16 x i32> [[_MSPROP1]], ptr @__msan_retval_tls, align 85932; CHECK-NEXT: ret <16 x i32> [[TMP4]]5933;5934 %1 = call <16 x i32> @llvm.x86.avx512.vpermi2var.d.512(<16 x i32> %x1, <16 x i32> %x0, <16 x i32> %x2)5935 ret <16 x i32> %15936}5937 5938define <16 x i32>@test_int_x86_avx512_mask_vpermt2var_d_512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3) #0 {5939; CHECK-LABEL: @test_int_x86_avx512_mask_vpermt2var_d_512(5940; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 85941; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 85942; CHECK-NEXT: [[X0:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 85943; CHECK-NEXT: [[TMP4:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 85944; CHECK-NEXT: call void @llvm.donothing()5945; CHECK-NEXT: [[TMP13:%.*]] = trunc <16 x i32> [[X0]] to <16 x i4>5946; CHECK-NEXT: [[_MSPROP1:%.*]] = call <16 x i32> @llvm.x86.avx512.vpermi2var.d.512(<16 x i32> [[TMP1]], <16 x i32> [[X4:%.*]], <16 x i32> [[TMP3]])5947; CHECK-NEXT: [[TMP14:%.*]] = bitcast <16 x i4> [[TMP13]] to i645948; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP14]], 05949; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP15:%.*]], label [[TMP16:%.*]], !prof [[PROF1]]5950; CHECK: 8:5951; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]5952; CHECK-NEXT: unreachable5953; CHECK: 9:5954; CHECK-NEXT: [[TMP5:%.*]] = call <16 x i32> @llvm.x86.avx512.vpermi2var.d.512(<16 x i32> [[X1:%.*]], <16 x i32> [[X4]], <16 x i32> [[X2:%.*]])5955; CHECK-NEXT: [[TMP6:%.*]] = bitcast i16 [[TMP4]] to <16 x i1>5956; CHECK-NEXT: [[TMP7:%.*]] = bitcast i16 [[X3:%.*]] to <16 x i1>5957; CHECK-NEXT: [[TMP8:%.*]] = select <16 x i1> [[TMP7]], <16 x i32> [[_MSPROP1]], <16 x i32> [[TMP1]]5958; CHECK-NEXT: [[TMP9:%.*]] = xor <16 x i32> [[TMP5]], [[X1]]5959; CHECK-NEXT: [[TMP10:%.*]] = or <16 x i32> [[TMP9]], [[_MSPROP1]]5960; CHECK-NEXT: [[TMP11:%.*]] = or <16 x i32> [[TMP10]], [[TMP1]]5961; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP6]], <16 x i32> [[TMP11]], <16 x i32> [[TMP8]]5962; CHECK-NEXT: [[TMP12:%.*]] = select <16 x i1> [[TMP7]], <16 x i32> [[TMP5]], <16 x i32> [[X1]]5963; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 85964; CHECK-NEXT: ret <16 x i32> [[TMP12]]5965;5966 %1 = call <16 x i32> @llvm.x86.avx512.vpermi2var.d.512(<16 x i32> %x1, <16 x i32> %x0, <16 x i32> %x2)5967 %2 = bitcast i16 %x3 to <16 x i1>5968 %3 = select <16 x i1> %2, <16 x i32> %1, <16 x i32> %x15969 ret <16 x i32> %35970}5971 5972declare <8 x double> @llvm.x86.avx512.mask.scalef.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32)5973define <8 x double>@test_int_x86_avx512_mask_scalef_pd_512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3) #0 {5974; CHECK-LABEL: @test_int_x86_avx512_mask_scalef_pd_512(5975; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 85976; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 85977; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 85978; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 85979; CHECK-NEXT: call void @llvm.donothing()5980; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i64> [[TMP1]] to i5125981; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP5]], 05982; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i64> [[TMP2]] to i5125983; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP6]], 05984; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]5985; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i64> [[TMP3]] to i5125986; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i512 [[TMP7]], 05987; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]5988; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 05989; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]5990; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]5991; CHECK: 8:5992; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]5993; CHECK-NEXT: unreachable5994; CHECK: 9:5995; CHECK-NEXT: [[RES:%.*]] = call <8 x double> @llvm.x86.avx512.mask.scalef.pd.512(<8 x double> [[X0:%.*]], <8 x double> [[X1:%.*]], <8 x double> [[X2:%.*]], i8 [[X3:%.*]], i32 11)5996; CHECK-NEXT: [[TMP10:%.*]] = bitcast <8 x i64> [[TMP1]] to i5125997; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i512 [[TMP10]], 05998; CHECK-NEXT: [[TMP11:%.*]] = bitcast <8 x i64> [[TMP2]] to i5125999; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i512 [[TMP11]], 06000; CHECK-NEXT: [[_MSOR8:%.*]] = or i1 [[_MSCMP6]], [[_MSCMP7]]6001; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x i64> [[TMP3]] to i5126002; CHECK-NEXT: [[_MSCMP9:%.*]] = icmp ne i512 [[TMP12]], 06003; CHECK-NEXT: [[_MSOR10:%.*]] = or i1 [[_MSOR8]], [[_MSCMP9]]6004; CHECK-NEXT: br i1 [[_MSOR10]], label [[TMP13:%.*]], label [[TMP14:%.*]], !prof [[PROF1]]6005; CHECK: 13:6006; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]6007; CHECK-NEXT: unreachable6008; CHECK: 14:6009; CHECK-NEXT: [[RES1:%.*]] = call <8 x double> @llvm.x86.avx512.mask.scalef.pd.512(<8 x double> [[X0]], <8 x double> [[X1]], <8 x double> [[X2]], i8 -1, i32 8)6010; CHECK-NEXT: [[RES2:%.*]] = fadd <8 x double> [[RES]], [[RES1]]6011; CHECK-NEXT: store <8 x i64> zeroinitializer, ptr @__msan_retval_tls, align 86012; CHECK-NEXT: ret <8 x double> [[RES2]]6013;6014 %res = call <8 x double> @llvm.x86.avx512.mask.scalef.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3, i32 11)6015 %res1 = call <8 x double> @llvm.x86.avx512.mask.scalef.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 -1, i32 8)6016 %res2 = fadd <8 x double> %res, %res16017 ret <8 x double> %res26018}6019 6020declare <16 x float> @llvm.x86.avx512.mask.scalef.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32)6021define <16 x float>@test_int_x86_avx512_mask_scalef_ps_512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 %x3) #0 {6022; CHECK-LABEL: @test_int_x86_avx512_mask_scalef_ps_512(6023; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 86024; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 86025; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 86026; CHECK-NEXT: [[TMP4:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 86027; CHECK-NEXT: call void @llvm.donothing()6028; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP1]] to i5126029; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP5]], 06030; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i32> [[TMP2]] to i5126031; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP6]], 06032; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6033; CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i32> [[TMP3]] to i5126034; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i512 [[TMP7]], 06035; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]6036; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i16 [[TMP4]], 06037; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]6038; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]6039; CHECK: 8:6040; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]6041; CHECK-NEXT: unreachable6042; CHECK: 9:6043; CHECK-NEXT: [[RES:%.*]] = call <16 x float> @llvm.x86.avx512.mask.scalef.ps.512(<16 x float> [[X0:%.*]], <16 x float> [[X1:%.*]], <16 x float> [[X2:%.*]], i16 [[X3:%.*]], i32 10)6044; CHECK-NEXT: [[TMP10:%.*]] = bitcast <16 x i32> [[TMP1]] to i5126045; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i512 [[TMP10]], 06046; CHECK-NEXT: [[TMP11:%.*]] = bitcast <16 x i32> [[TMP2]] to i5126047; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i512 [[TMP11]], 06048; CHECK-NEXT: [[_MSOR8:%.*]] = or i1 [[_MSCMP6]], [[_MSCMP7]]6049; CHECK-NEXT: [[TMP12:%.*]] = bitcast <16 x i32> [[TMP3]] to i5126050; CHECK-NEXT: [[_MSCMP9:%.*]] = icmp ne i512 [[TMP12]], 06051; CHECK-NEXT: [[_MSOR10:%.*]] = or i1 [[_MSOR8]], [[_MSCMP9]]6052; CHECK-NEXT: br i1 [[_MSOR10]], label [[TMP13:%.*]], label [[TMP14:%.*]], !prof [[PROF1]]6053; CHECK: 13:6054; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]6055; CHECK-NEXT: unreachable6056; CHECK: 14:6057; CHECK-NEXT: [[RES1:%.*]] = call <16 x float> @llvm.x86.avx512.mask.scalef.ps.512(<16 x float> [[X0]], <16 x float> [[X1]], <16 x float> [[X2]], i16 -1, i32 8)6058; CHECK-NEXT: [[RES2:%.*]] = fadd <16 x float> [[RES]], [[RES1]]6059; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 86060; CHECK-NEXT: ret <16 x float> [[RES2]]6061;6062 %res = call <16 x float> @llvm.x86.avx512.mask.scalef.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 %x3, i32 10)6063 %res1 = call <16 x float> @llvm.x86.avx512.mask.scalef.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 -1, i32 8)6064 %res2 = fadd <16 x float> %res, %res16065 ret <16 x float> %res26066}6067 6068declare <16 x i8> @llvm.x86.avx512.mask.pmov.qb.512(<8 x i64>, <16 x i8>, i8)6069 6070define <16 x i8>@test_int_x86_avx512_mask_pmov_qb_512(<8 x i64> %x0, <16 x i8> %x1, i8 %x2) #0 {6071; CHECK-LABEL: @test_int_x86_avx512_mask_pmov_qb_512(6072; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 86073; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 86074; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 80), align 86075; CHECK-NEXT: call void @llvm.donothing()6076; CHECK-NEXT: [[TMP4:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmov.qb.512(<8 x i64> [[TMP1]], <16 x i8> [[TMP2]], i8 -1)6077; CHECK-NEXT: [[_MSPROP2:%.*]] = or <16 x i8> zeroinitializer, [[TMP4]]6078; CHECK-NEXT: [[RES0:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmov.qb.512(<8 x i64> [[X0:%.*]], <16 x i8> [[X1:%.*]], i8 -1)6079; CHECK-NEXT: [[TMP8:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmov.qb.512(<8 x i64> [[TMP1]], <16 x i8> [[TMP2]], i8 [[X2:%.*]])6080; CHECK-NEXT: [[TMP6:%.*]] = zext i8 [[TMP3]] to i1286081; CHECK-NEXT: [[TMP7:%.*]] = bitcast i128 [[TMP6]] to <16 x i8>6082; CHECK-NEXT: [[_MSPROP4:%.*]] = or <16 x i8> [[TMP7]], [[TMP8]]6083; CHECK-NEXT: [[RES1:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmov.qb.512(<8 x i64> [[X0]], <16 x i8> [[X1]], i8 [[X2]])6084; CHECK-NEXT: [[TMP12:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmov.qb.512(<8 x i64> [[TMP1]], <16 x i8> zeroinitializer, i8 [[X2]])6085; CHECK-NEXT: [[TMP9:%.*]] = zext i8 [[TMP3]] to i1286086; CHECK-NEXT: [[TMP5:%.*]] = bitcast i128 [[TMP9]] to <16 x i8>6087; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i8> [[TMP5]], [[TMP12]]6088; CHECK-NEXT: [[RES2:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmov.qb.512(<8 x i64> [[X0]], <16 x i8> zeroinitializer, i8 [[X2]])6089; CHECK-NEXT: [[_MSPROP3:%.*]] = or <16 x i8> [[_MSPROP2]], [[_MSPROP4]]6090; CHECK-NEXT: [[RES3:%.*]] = add <16 x i8> [[RES0]], [[RES1]]6091; CHECK-NEXT: [[_MSPROP1:%.*]] = or <16 x i8> [[_MSPROP3]], [[_MSPROP]]6092; CHECK-NEXT: [[RES4:%.*]] = add <16 x i8> [[RES3]], [[RES2]]6093; CHECK-NEXT: store <16 x i8> [[_MSPROP1]], ptr @__msan_retval_tls, align 86094; CHECK-NEXT: ret <16 x i8> [[RES4]]6095;6096 %res0 = call <16 x i8> @llvm.x86.avx512.mask.pmov.qb.512(<8 x i64> %x0, <16 x i8> %x1, i8 -1)6097 %res1 = call <16 x i8> @llvm.x86.avx512.mask.pmov.qb.512(<8 x i64> %x0, <16 x i8> %x1, i8 %x2)6098 %res2 = call <16 x i8> @llvm.x86.avx512.mask.pmov.qb.512(<8 x i64> %x0, <16 x i8> zeroinitializer, i8 %x2)6099 %res3 = add <16 x i8> %res0, %res16100 %res4 = add <16 x i8> %res3, %res26101 ret <16 x i8> %res46102}6103 6104declare void @llvm.x86.avx512.mask.pmov.qb.mem.512(ptr %ptr, <8 x i64>, i8)6105 6106define void @test_int_x86_avx512_mask_pmov_qb_mem_512(ptr %ptr, <8 x i64> %x1, i8 %x2) #0 {6107; CHECK-LABEL: @test_int_x86_avx512_mask_pmov_qb_mem_512(6108; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 86109; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 86110; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 72), align 86111; CHECK-NEXT: call void @llvm.donothing()6112; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 06113; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i64> [[TMP2]] to i5126114; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 06115; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6116; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]6117; CHECK: 5:6118; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]6119; CHECK-NEXT: unreachable6120; CHECK: 6:6121; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmov.qb.mem.512(ptr [[PTR:%.*]], <8 x i64> [[X1:%.*]], i8 -1)6122; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 06123; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i64> [[TMP2]] to i5126124; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i512 [[TMP7]], 06125; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]6126; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 06127; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]6128; CHECK-NEXT: br i1 [[_MSOR6]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]6129; CHECK: 8:6130; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]6131; CHECK-NEXT: unreachable6132; CHECK: 9:6133; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmov.qb.mem.512(ptr [[PTR]], <8 x i64> [[X1]], i8 [[X2:%.*]])6134; CHECK-NEXT: ret void6135;6136 call void @llvm.x86.avx512.mask.pmov.qb.mem.512(ptr %ptr, <8 x i64> %x1, i8 -1)6137 call void @llvm.x86.avx512.mask.pmov.qb.mem.512(ptr %ptr, <8 x i64> %x1, i8 %x2)6138 ret void6139}6140 6141declare <16 x i8> @llvm.x86.avx512.mask.pmovs.qb.512(<8 x i64>, <16 x i8>, i8)6142 6143define <16 x i8>@test_int_x86_avx512_mask_pmovs_qb_512(<8 x i64> %x0, <16 x i8> %x1, i8 %x2) #0 {6144; CHECK-LABEL: @test_int_x86_avx512_mask_pmovs_qb_512(6145; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 86146; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 86147; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 80), align 86148; CHECK-NEXT: call void @llvm.donothing()6149; CHECK-NEXT: [[TMP4:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmov.qb.512(<8 x i64> [[TMP1]], <16 x i8> [[TMP2]], i8 -1)6150; CHECK-NEXT: [[TMP5:%.*]] = or <16 x i8> zeroinitializer, [[TMP4]]6151; CHECK-NEXT: [[RES0:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmovs.qb.512(<8 x i64> [[X0:%.*]], <16 x i8> [[X1:%.*]], i8 -1)6152; CHECK-NEXT: [[TMP11:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmov.qb.512(<8 x i64> [[TMP1]], <16 x i8> [[TMP2]], i8 [[X2:%.*]])6153; CHECK-NEXT: [[TMP6:%.*]] = zext i8 [[TMP3]] to i1286154; CHECK-NEXT: [[TMP7:%.*]] = bitcast i128 [[TMP6]] to <16 x i8>6155; CHECK-NEXT: [[TMP12:%.*]] = or <16 x i8> [[TMP7]], [[TMP11]]6156; CHECK-NEXT: [[RES1:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmovs.qb.512(<8 x i64> [[X0]], <16 x i8> [[X1]], i8 [[X2]])6157; CHECK-NEXT: [[TMP8:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmov.qb.512(<8 x i64> [[TMP1]], <16 x i8> zeroinitializer, i8 [[X2]])6158; CHECK-NEXT: [[TMP9:%.*]] = zext i8 [[TMP3]] to i1286159; CHECK-NEXT: [[TMP10:%.*]] = bitcast i128 [[TMP9]] to <16 x i8>6160; CHECK-NEXT: [[TMP19:%.*]] = or <16 x i8> [[TMP10]], [[TMP8]]6161; CHECK-NEXT: [[RES2:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmovs.qb.512(<8 x i64> [[X0]], <16 x i8> zeroinitializer, i8 [[X2]])6162; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i8> [[TMP5]], [[TMP12]]6163; CHECK-NEXT: [[RES3:%.*]] = add <16 x i8> [[RES0]], [[RES1]]6164; CHECK-NEXT: [[_MSPROP1:%.*]] = or <16 x i8> [[_MSPROP]], [[TMP19]]6165; CHECK-NEXT: [[RES4:%.*]] = add <16 x i8> [[RES3]], [[RES2]]6166; CHECK-NEXT: store <16 x i8> [[_MSPROP1]], ptr @__msan_retval_tls, align 86167; CHECK-NEXT: ret <16 x i8> [[RES4]]6168;6169 %res0 = call <16 x i8> @llvm.x86.avx512.mask.pmovs.qb.512(<8 x i64> %x0, <16 x i8> %x1, i8 -1)6170 %res1 = call <16 x i8> @llvm.x86.avx512.mask.pmovs.qb.512(<8 x i64> %x0, <16 x i8> %x1, i8 %x2)6171 %res2 = call <16 x i8> @llvm.x86.avx512.mask.pmovs.qb.512(<8 x i64> %x0, <16 x i8> zeroinitializer, i8 %x2)6172 %res3 = add <16 x i8> %res0, %res16173 %res4 = add <16 x i8> %res3, %res26174 ret <16 x i8> %res46175}6176 6177declare void @llvm.x86.avx512.mask.pmovs.qb.mem.512(ptr %ptr, <8 x i64>, i8)6178 6179define void @test_int_x86_avx512_mask_pmovs_qb_mem_512(ptr %ptr, <8 x i64> %x1, i8 %x2) #0 {6180; CHECK-LABEL: @test_int_x86_avx512_mask_pmovs_qb_mem_512(6181; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 86182; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 86183; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 72), align 86184; CHECK-NEXT: call void @llvm.donothing()6185; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 06186; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i64> [[TMP2]] to i5126187; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 06188; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6189; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]6190; CHECK: 5:6191; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]6192; CHECK-NEXT: unreachable6193; CHECK: 6:6194; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovs.qb.mem.512(ptr [[PTR:%.*]], <8 x i64> [[X1:%.*]], i8 -1)6195; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 06196; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i64> [[TMP2]] to i5126197; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i512 [[TMP7]], 06198; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]6199; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 06200; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]6201; CHECK-NEXT: br i1 [[_MSOR6]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]6202; CHECK: 8:6203; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]6204; CHECK-NEXT: unreachable6205; CHECK: 9:6206; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovs.qb.mem.512(ptr [[PTR]], <8 x i64> [[X1]], i8 [[X2:%.*]])6207; CHECK-NEXT: ret void6208;6209 call void @llvm.x86.avx512.mask.pmovs.qb.mem.512(ptr %ptr, <8 x i64> %x1, i8 -1)6210 call void @llvm.x86.avx512.mask.pmovs.qb.mem.512(ptr %ptr, <8 x i64> %x1, i8 %x2)6211 ret void6212}6213 6214declare <16 x i8> @llvm.x86.avx512.mask.pmovus.qb.512(<8 x i64>, <16 x i8>, i8)6215 6216define <16 x i8>@test_int_x86_avx512_mask_pmovus_qb_512(<8 x i64> %x0, <16 x i8> %x1, i8 %x2) #0 {6217; CHECK-LABEL: @test_int_x86_avx512_mask_pmovus_qb_512(6218; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 86219; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 86220; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 80), align 86221; CHECK-NEXT: call void @llvm.donothing()6222; CHECK-NEXT: [[TMP4:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmov.qb.512(<8 x i64> [[TMP1]], <16 x i8> [[TMP2]], i8 -1)6223; CHECK-NEXT: [[TMP5:%.*]] = or <16 x i8> zeroinitializer, [[TMP4]]6224; CHECK-NEXT: [[RES0:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmovus.qb.512(<8 x i64> [[X0:%.*]], <16 x i8> [[X1:%.*]], i8 -1)6225; CHECK-NEXT: [[TMP11:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmov.qb.512(<8 x i64> [[TMP1]], <16 x i8> [[TMP2]], i8 [[X2:%.*]])6226; CHECK-NEXT: [[TMP6:%.*]] = zext i8 [[TMP3]] to i1286227; CHECK-NEXT: [[TMP7:%.*]] = bitcast i128 [[TMP6]] to <16 x i8>6228; CHECK-NEXT: [[TMP12:%.*]] = or <16 x i8> [[TMP7]], [[TMP11]]6229; CHECK-NEXT: [[RES1:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmovus.qb.512(<8 x i64> [[X0]], <16 x i8> [[X1]], i8 [[X2]])6230; CHECK-NEXT: [[TMP8:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmov.qb.512(<8 x i64> [[TMP1]], <16 x i8> zeroinitializer, i8 [[X2]])6231; CHECK-NEXT: [[TMP9:%.*]] = zext i8 [[TMP3]] to i1286232; CHECK-NEXT: [[TMP10:%.*]] = bitcast i128 [[TMP9]] to <16 x i8>6233; CHECK-NEXT: [[TMP19:%.*]] = or <16 x i8> [[TMP10]], [[TMP8]]6234; CHECK-NEXT: [[RES2:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmovus.qb.512(<8 x i64> [[X0]], <16 x i8> zeroinitializer, i8 [[X2]])6235; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i8> [[TMP5]], [[TMP12]]6236; CHECK-NEXT: [[RES3:%.*]] = add <16 x i8> [[RES0]], [[RES1]]6237; CHECK-NEXT: [[_MSPROP1:%.*]] = or <16 x i8> [[_MSPROP]], [[TMP19]]6238; CHECK-NEXT: [[RES4:%.*]] = add <16 x i8> [[RES3]], [[RES2]]6239; CHECK-NEXT: store <16 x i8> [[_MSPROP1]], ptr @__msan_retval_tls, align 86240; CHECK-NEXT: ret <16 x i8> [[RES4]]6241;6242 %res0 = call <16 x i8> @llvm.x86.avx512.mask.pmovus.qb.512(<8 x i64> %x0, <16 x i8> %x1, i8 -1)6243 %res1 = call <16 x i8> @llvm.x86.avx512.mask.pmovus.qb.512(<8 x i64> %x0, <16 x i8> %x1, i8 %x2)6244 %res2 = call <16 x i8> @llvm.x86.avx512.mask.pmovus.qb.512(<8 x i64> %x0, <16 x i8> zeroinitializer, i8 %x2)6245 %res3 = add <16 x i8> %res0, %res16246 %res4 = add <16 x i8> %res3, %res26247 ret <16 x i8> %res46248}6249 6250declare void @llvm.x86.avx512.mask.pmovus.qb.mem.512(ptr %ptr, <8 x i64>, i8)6251 6252define void @test_int_x86_avx512_mask_pmovus_qb_mem_512(ptr %ptr, <8 x i64> %x1, i8 %x2) #0 {6253; CHECK-LABEL: @test_int_x86_avx512_mask_pmovus_qb_mem_512(6254; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 86255; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 86256; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 72), align 86257; CHECK-NEXT: call void @llvm.donothing()6258; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 06259; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i64> [[TMP2]] to i5126260; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 06261; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6262; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]6263; CHECK: 5:6264; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]6265; CHECK-NEXT: unreachable6266; CHECK: 6:6267; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovus.qb.mem.512(ptr [[PTR:%.*]], <8 x i64> [[X1:%.*]], i8 -1)6268; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 06269; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i64> [[TMP2]] to i5126270; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i512 [[TMP7]], 06271; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]6272; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 06273; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]6274; CHECK-NEXT: br i1 [[_MSOR6]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]6275; CHECK: 8:6276; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]6277; CHECK-NEXT: unreachable6278; CHECK: 9:6279; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovus.qb.mem.512(ptr [[PTR]], <8 x i64> [[X1]], i8 [[X2:%.*]])6280; CHECK-NEXT: ret void6281;6282 call void @llvm.x86.avx512.mask.pmovus.qb.mem.512(ptr %ptr, <8 x i64> %x1, i8 -1)6283 call void @llvm.x86.avx512.mask.pmovus.qb.mem.512(ptr %ptr, <8 x i64> %x1, i8 %x2)6284 ret void6285}6286 6287declare <8 x i16> @llvm.x86.avx512.mask.pmov.qw.512(<8 x i64>, <8 x i16>, i8)6288 6289define <8 x i16>@test_int_x86_avx512_mask_pmov_qw_512(<8 x i64> %x0, <8 x i16> %x1, i8 %x2) #0 {6290; CHECK-LABEL: @test_int_x86_avx512_mask_pmov_qw_512(6291; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 86292; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 86293; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 80), align 86294; CHECK-NEXT: call void @llvm.donothing()6295; CHECK-NEXT: [[TMP8:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmov.qw.512(<8 x i64> [[TMP1]], <8 x i16> [[TMP2]], i8 -1)6296; CHECK-NEXT: [[_MSPROP2:%.*]] = or <8 x i16> zeroinitializer, [[TMP8]]6297; CHECK-NEXT: [[RES0:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmov.qw.512(<8 x i64> [[X0:%.*]], <8 x i16> [[X1:%.*]], i8 -1)6298; CHECK-NEXT: [[TMP5:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmov.qw.512(<8 x i64> [[TMP1]], <8 x i16> [[TMP2]], i8 [[TMP6:%.*]])6299; CHECK-NEXT: [[TMP10:%.*]] = zext i8 [[TMP3]] to i1286300; CHECK-NEXT: [[TMP7:%.*]] = bitcast i128 [[TMP10]] to <8 x i16>6301; CHECK-NEXT: [[_MSPROP4:%.*]] = or <8 x i16> [[TMP7]], [[TMP5]]6302; CHECK-NEXT: [[RES1:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmov.qw.512(<8 x i64> [[X0]], <8 x i16> [[X1]], i8 [[TMP6]])6303; CHECK-NEXT: [[TMP9:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmov.qw.512(<8 x i64> [[TMP1]], <8 x i16> zeroinitializer, i8 [[TMP6]])6304; CHECK-NEXT: [[TMP11:%.*]] = zext i8 [[TMP3]] to i1286305; CHECK-NEXT: [[TMP4:%.*]] = bitcast i128 [[TMP11]] to <8 x i16>6306; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP4]], [[TMP9]]6307; CHECK-NEXT: [[RES2:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmov.qw.512(<8 x i64> [[X0]], <8 x i16> zeroinitializer, i8 [[TMP6]])6308; CHECK-NEXT: [[_MSPROP3:%.*]] = or <8 x i16> [[_MSPROP2]], [[_MSPROP4]]6309; CHECK-NEXT: [[RES3:%.*]] = add <8 x i16> [[RES0]], [[RES1]]6310; CHECK-NEXT: [[_MSPROP1:%.*]] = or <8 x i16> [[_MSPROP3]], [[_MSPROP]]6311; CHECK-NEXT: [[RES4:%.*]] = add <8 x i16> [[RES3]], [[RES2]]6312; CHECK-NEXT: store <8 x i16> [[_MSPROP1]], ptr @__msan_retval_tls, align 86313; CHECK-NEXT: ret <8 x i16> [[RES4]]6314;6315 %res0 = call <8 x i16> @llvm.x86.avx512.mask.pmov.qw.512(<8 x i64> %x0, <8 x i16> %x1, i8 -1)6316 %res1 = call <8 x i16> @llvm.x86.avx512.mask.pmov.qw.512(<8 x i64> %x0, <8 x i16> %x1, i8 %x2)6317 %res2 = call <8 x i16> @llvm.x86.avx512.mask.pmov.qw.512(<8 x i64> %x0, <8 x i16> zeroinitializer, i8 %x2)6318 %res3 = add <8 x i16> %res0, %res16319 %res4 = add <8 x i16> %res3, %res26320 ret <8 x i16> %res46321}6322 6323declare void @llvm.x86.avx512.mask.pmov.qw.mem.512(ptr %ptr, <8 x i64>, i8)6324 6325define void @test_int_x86_avx512_mask_pmov_qw_mem_512(ptr %ptr, <8 x i64> %x1, i8 %x2) #0 {6326; CHECK-LABEL: @test_int_x86_avx512_mask_pmov_qw_mem_512(6327; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 86328; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 86329; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 72), align 86330; CHECK-NEXT: call void @llvm.donothing()6331; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 06332; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i64> [[TMP2]] to i5126333; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 06334; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6335; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]6336; CHECK: 5:6337; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]6338; CHECK-NEXT: unreachable6339; CHECK: 6:6340; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmov.qw.mem.512(ptr [[PTR:%.*]], <8 x i64> [[X1:%.*]], i8 -1)6341; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 06342; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i64> [[TMP2]] to i5126343; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i512 [[TMP7]], 06344; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]6345; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 06346; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]6347; CHECK-NEXT: br i1 [[_MSOR6]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]6348; CHECK: 8:6349; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]6350; CHECK-NEXT: unreachable6351; CHECK: 9:6352; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmov.qw.mem.512(ptr [[PTR]], <8 x i64> [[X1]], i8 [[X2:%.*]])6353; CHECK-NEXT: ret void6354;6355 call void @llvm.x86.avx512.mask.pmov.qw.mem.512(ptr %ptr, <8 x i64> %x1, i8 -1)6356 call void @llvm.x86.avx512.mask.pmov.qw.mem.512(ptr %ptr, <8 x i64> %x1, i8 %x2)6357 ret void6358}6359 6360declare <8 x i16> @llvm.x86.avx512.mask.pmovs.qw.512(<8 x i64>, <8 x i16>, i8)6361 6362define <8 x i16>@test_int_x86_avx512_mask_pmovs_qw_512(<8 x i64> %x0, <8 x i16> %x1, i8 %x2) #0 {6363; CHECK-LABEL: @test_int_x86_avx512_mask_pmovs_qw_512(6364; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 86365; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 86366; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 80), align 86367; CHECK-NEXT: call void @llvm.donothing()6368; CHECK-NEXT: [[TMP11:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmov.qw.512(<8 x i64> [[TMP1]], <8 x i16> [[TMP2]], i8 -1)6369; CHECK-NEXT: [[TMP4:%.*]] = or <8 x i16> zeroinitializer, [[TMP11]]6370; CHECK-NEXT: [[RES0:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmovs.qw.512(<8 x i64> [[X0:%.*]], <8 x i16> [[X1:%.*]], i8 -1)6371; CHECK-NEXT: [[TMP5:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmov.qw.512(<8 x i64> [[TMP1]], <8 x i16> [[TMP2]], i8 [[TMP6:%.*]])6372; CHECK-NEXT: [[TMP12:%.*]] = zext i8 [[TMP3]] to i1286373; CHECK-NEXT: [[TMP7:%.*]] = bitcast i128 [[TMP12]] to <8 x i16>6374; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i16> [[TMP7]], [[TMP5]]6375; CHECK-NEXT: [[RES1:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmovs.qw.512(<8 x i64> [[X0]], <8 x i16> [[X1]], i8 [[TMP6]])6376; CHECK-NEXT: [[TMP8:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmov.qw.512(<8 x i64> [[TMP1]], <8 x i16> zeroinitializer, i8 [[TMP6]])6377; CHECK-NEXT: [[TMP13:%.*]] = zext i8 [[TMP3]] to i1286378; CHECK-NEXT: [[TMP10:%.*]] = bitcast i128 [[TMP13]] to <8 x i16>6379; CHECK-NEXT: [[TMP14:%.*]] = or <8 x i16> [[TMP10]], [[TMP8]]6380; CHECK-NEXT: [[RES2:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmovs.qw.512(<8 x i64> [[X0]], <8 x i16> zeroinitializer, i8 [[TMP6]])6381; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP4]], [[TMP9]]6382; CHECK-NEXT: [[RES3:%.*]] = add <8 x i16> [[RES0]], [[RES1]]6383; CHECK-NEXT: [[_MSPROP1:%.*]] = or <8 x i16> [[_MSPROP]], [[TMP14]]6384; CHECK-NEXT: [[RES4:%.*]] = add <8 x i16> [[RES3]], [[RES2]]6385; CHECK-NEXT: store <8 x i16> [[_MSPROP1]], ptr @__msan_retval_tls, align 86386; CHECK-NEXT: ret <8 x i16> [[RES4]]6387;6388 %res0 = call <8 x i16> @llvm.x86.avx512.mask.pmovs.qw.512(<8 x i64> %x0, <8 x i16> %x1, i8 -1)6389 %res1 = call <8 x i16> @llvm.x86.avx512.mask.pmovs.qw.512(<8 x i64> %x0, <8 x i16> %x1, i8 %x2)6390 %res2 = call <8 x i16> @llvm.x86.avx512.mask.pmovs.qw.512(<8 x i64> %x0, <8 x i16> zeroinitializer, i8 %x2)6391 %res3 = add <8 x i16> %res0, %res16392 %res4 = add <8 x i16> %res3, %res26393 ret <8 x i16> %res46394}6395 6396declare void @llvm.x86.avx512.mask.pmovs.qw.mem.512(ptr %ptr, <8 x i64>, i8)6397 6398define void @test_int_x86_avx512_mask_pmovs_qw_mem_512(ptr %ptr, <8 x i64> %x1, i8 %x2) #0 {6399; CHECK-LABEL: @test_int_x86_avx512_mask_pmovs_qw_mem_512(6400; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 86401; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 86402; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 72), align 86403; CHECK-NEXT: call void @llvm.donothing()6404; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 06405; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i64> [[TMP2]] to i5126406; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 06407; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6408; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]6409; CHECK: 5:6410; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]6411; CHECK-NEXT: unreachable6412; CHECK: 6:6413; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovs.qw.mem.512(ptr [[PTR:%.*]], <8 x i64> [[X1:%.*]], i8 -1)6414; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 06415; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i64> [[TMP2]] to i5126416; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i512 [[TMP7]], 06417; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]6418; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 06419; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]6420; CHECK-NEXT: br i1 [[_MSOR6]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]6421; CHECK: 8:6422; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]6423; CHECK-NEXT: unreachable6424; CHECK: 9:6425; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovs.qw.mem.512(ptr [[PTR]], <8 x i64> [[X1]], i8 [[X2:%.*]])6426; CHECK-NEXT: ret void6427;6428 call void @llvm.x86.avx512.mask.pmovs.qw.mem.512(ptr %ptr, <8 x i64> %x1, i8 -1)6429 call void @llvm.x86.avx512.mask.pmovs.qw.mem.512(ptr %ptr, <8 x i64> %x1, i8 %x2)6430 ret void6431}6432 6433declare <8 x i16> @llvm.x86.avx512.mask.pmovus.qw.512(<8 x i64>, <8 x i16>, i8)6434 6435define <8 x i16>@test_int_x86_avx512_mask_pmovus_qw_512(<8 x i64> %x0, <8 x i16> %x1, i8 %x2) #0 {6436; CHECK-LABEL: @test_int_x86_avx512_mask_pmovus_qw_512(6437; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 86438; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 86439; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 80), align 86440; CHECK-NEXT: call void @llvm.donothing()6441; CHECK-NEXT: [[TMP11:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmov.qw.512(<8 x i64> [[TMP1]], <8 x i16> [[TMP2]], i8 -1)6442; CHECK-NEXT: [[TMP4:%.*]] = or <8 x i16> zeroinitializer, [[TMP11]]6443; CHECK-NEXT: [[RES0:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmovus.qw.512(<8 x i64> [[X0:%.*]], <8 x i16> [[X1:%.*]], i8 -1)6444; CHECK-NEXT: [[TMP5:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmov.qw.512(<8 x i64> [[TMP1]], <8 x i16> [[TMP2]], i8 [[TMP6:%.*]])6445; CHECK-NEXT: [[TMP12:%.*]] = zext i8 [[TMP3]] to i1286446; CHECK-NEXT: [[TMP7:%.*]] = bitcast i128 [[TMP12]] to <8 x i16>6447; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i16> [[TMP7]], [[TMP5]]6448; CHECK-NEXT: [[RES1:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmovus.qw.512(<8 x i64> [[X0]], <8 x i16> [[X1]], i8 [[TMP6]])6449; CHECK-NEXT: [[TMP8:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmov.qw.512(<8 x i64> [[TMP1]], <8 x i16> zeroinitializer, i8 [[TMP6]])6450; CHECK-NEXT: [[TMP13:%.*]] = zext i8 [[TMP3]] to i1286451; CHECK-NEXT: [[TMP10:%.*]] = bitcast i128 [[TMP13]] to <8 x i16>6452; CHECK-NEXT: [[TMP14:%.*]] = or <8 x i16> [[TMP10]], [[TMP8]]6453; CHECK-NEXT: [[RES2:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmovus.qw.512(<8 x i64> [[X0]], <8 x i16> zeroinitializer, i8 [[TMP6]])6454; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP4]], [[TMP9]]6455; CHECK-NEXT: [[RES3:%.*]] = add <8 x i16> [[RES0]], [[RES1]]6456; CHECK-NEXT: [[_MSPROP1:%.*]] = or <8 x i16> [[_MSPROP]], [[TMP14]]6457; CHECK-NEXT: [[RES4:%.*]] = add <8 x i16> [[RES3]], [[RES2]]6458; CHECK-NEXT: store <8 x i16> [[_MSPROP1]], ptr @__msan_retval_tls, align 86459; CHECK-NEXT: ret <8 x i16> [[RES4]]6460;6461 %res0 = call <8 x i16> @llvm.x86.avx512.mask.pmovus.qw.512(<8 x i64> %x0, <8 x i16> %x1, i8 -1)6462 %res1 = call <8 x i16> @llvm.x86.avx512.mask.pmovus.qw.512(<8 x i64> %x0, <8 x i16> %x1, i8 %x2)6463 %res2 = call <8 x i16> @llvm.x86.avx512.mask.pmovus.qw.512(<8 x i64> %x0, <8 x i16> zeroinitializer, i8 %x2)6464 %res3 = add <8 x i16> %res0, %res16465 %res4 = add <8 x i16> %res3, %res26466 ret <8 x i16> %res46467}6468 6469declare void @llvm.x86.avx512.mask.pmovus.qw.mem.512(ptr %ptr, <8 x i64>, i8)6470 6471define void @test_int_x86_avx512_mask_pmovus_qw_mem_512(ptr %ptr, <8 x i64> %x1, i8 %x2) #0 {6472; CHECK-LABEL: @test_int_x86_avx512_mask_pmovus_qw_mem_512(6473; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 86474; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 86475; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 72), align 86476; CHECK-NEXT: call void @llvm.donothing()6477; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 06478; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i64> [[TMP2]] to i5126479; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 06480; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6481; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]6482; CHECK: 5:6483; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]6484; CHECK-NEXT: unreachable6485; CHECK: 6:6486; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovus.qw.mem.512(ptr [[PTR:%.*]], <8 x i64> [[X1:%.*]], i8 -1)6487; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 06488; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i64> [[TMP2]] to i5126489; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i512 [[TMP7]], 06490; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]6491; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 06492; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]6493; CHECK-NEXT: br i1 [[_MSOR6]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]6494; CHECK: 8:6495; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]6496; CHECK-NEXT: unreachable6497; CHECK: 9:6498; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovus.qw.mem.512(ptr [[PTR]], <8 x i64> [[X1]], i8 [[X2:%.*]])6499; CHECK-NEXT: ret void6500;6501 call void @llvm.x86.avx512.mask.pmovus.qw.mem.512(ptr %ptr, <8 x i64> %x1, i8 -1)6502 call void @llvm.x86.avx512.mask.pmovus.qw.mem.512(ptr %ptr, <8 x i64> %x1, i8 %x2)6503 ret void6504}6505 6506define <8 x i32>@test_int_x86_avx512_pmov_qd_512(<8 x i64> %x0, <8 x i32> %x1) #0 {6507; CHECK-LABEL: @test_int_x86_avx512_pmov_qd_512(6508; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 86509; CHECK-NEXT: call void @llvm.donothing()6510; CHECK-NEXT: [[_MSPROP:%.*]] = trunc <8 x i64> [[TMP1]] to <8 x i32>6511; CHECK-NEXT: [[TMP2:%.*]] = trunc <8 x i64> [[X0:%.*]] to <8 x i32>6512; CHECK-NEXT: store <8 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 86513; CHECK-NEXT: ret <8 x i32> [[TMP2]]6514;6515 %1 = trunc <8 x i64> %x0 to <8 x i32>6516 ret <8 x i32> %16517}6518 6519define <8 x i32>@test_int_x86_avx512_mask_pmov_qd_512(<8 x i64> %x0, <8 x i32> %x1, i8 %x2) #0 {6520; CHECK-LABEL: @test_int_x86_avx512_mask_pmov_qd_512(6521; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 86522; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 86523; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 86524; CHECK-NEXT: call void @llvm.donothing()6525; CHECK-NEXT: [[_MSPROP:%.*]] = trunc <8 x i64> [[TMP1]] to <8 x i32>6526; CHECK-NEXT: [[TMP4:%.*]] = trunc <8 x i64> [[X0:%.*]] to <8 x i32>6527; CHECK-NEXT: [[TMP5:%.*]] = bitcast i8 [[TMP2]] to <8 x i1>6528; CHECK-NEXT: [[TMP6:%.*]] = bitcast i8 [[X2:%.*]] to <8 x i1>6529; CHECK-NEXT: [[TMP7:%.*]] = select <8 x i1> [[TMP6]], <8 x i32> [[_MSPROP]], <8 x i32> [[TMP3]]6530; CHECK-NEXT: [[TMP8:%.*]] = xor <8 x i32> [[TMP4]], [[X1:%.*]]6531; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i32> [[TMP8]], [[_MSPROP]]6532; CHECK-NEXT: [[TMP10:%.*]] = or <8 x i32> [[TMP9]], [[TMP3]]6533; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP5]], <8 x i32> [[TMP10]], <8 x i32> [[TMP7]]6534; CHECK-NEXT: [[TMP11:%.*]] = select <8 x i1> [[TMP6]], <8 x i32> [[TMP4]], <8 x i32> [[X1]]6535; CHECK-NEXT: store <8 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 86536; CHECK-NEXT: ret <8 x i32> [[TMP11]]6537;6538 %1 = trunc <8 x i64> %x0 to <8 x i32>6539 %2 = bitcast i8 %x2 to <8 x i1>6540 %3 = select <8 x i1> %2, <8 x i32> %1, <8 x i32> %x16541 ret <8 x i32> %36542}6543 6544define <8 x i32>@test_int_x86_avx512_maskz_pmov_qd_512(<8 x i64> %x0, i8 %x2) #0 {6545; CHECK-LABEL: @test_int_x86_avx512_maskz_pmov_qd_512(6546; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 86547; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 86548; CHECK-NEXT: call void @llvm.donothing()6549; CHECK-NEXT: [[_MSPROP:%.*]] = trunc <8 x i64> [[TMP1]] to <8 x i32>6550; CHECK-NEXT: [[TMP3:%.*]] = trunc <8 x i64> [[X0:%.*]] to <8 x i32>6551; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8 [[TMP2]] to <8 x i1>6552; CHECK-NEXT: [[TMP5:%.*]] = bitcast i8 [[X2:%.*]] to <8 x i1>6553; CHECK-NEXT: [[TMP6:%.*]] = select <8 x i1> [[TMP5]], <8 x i32> [[_MSPROP]], <8 x i32> zeroinitializer6554; CHECK-NEXT: [[TMP7:%.*]] = xor <8 x i32> [[TMP3]], zeroinitializer6555; CHECK-NEXT: [[TMP8:%.*]] = or <8 x i32> [[TMP7]], [[_MSPROP]]6556; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i32> [[TMP8]], zeroinitializer6557; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP4]], <8 x i32> [[TMP9]], <8 x i32> [[TMP6]]6558; CHECK-NEXT: [[TMP10:%.*]] = select <8 x i1> [[TMP5]], <8 x i32> [[TMP3]], <8 x i32> zeroinitializer6559; CHECK-NEXT: store <8 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 86560; CHECK-NEXT: ret <8 x i32> [[TMP10]]6561;6562 %1 = trunc <8 x i64> %x0 to <8 x i32>6563 %2 = bitcast i8 %x2 to <8 x i1>6564 %3 = select <8 x i1> %2, <8 x i32> %1, <8 x i32> zeroinitializer6565 ret <8 x i32> %36566}6567 6568declare void @llvm.x86.avx512.mask.pmov.qd.mem.512(ptr %ptr, <8 x i64>, i8)6569 6570define void @test_int_x86_avx512_mask_pmov_qd_mem_512(ptr %ptr, <8 x i64> %x1, i8 %x2) #0 {6571; CHECK-LABEL: @test_int_x86_avx512_mask_pmov_qd_mem_512(6572; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 86573; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 86574; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 72), align 86575; CHECK-NEXT: call void @llvm.donothing()6576; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 06577; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i64> [[TMP2]] to i5126578; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 06579; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6580; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]6581; CHECK: 5:6582; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]6583; CHECK-NEXT: unreachable6584; CHECK: 6:6585; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmov.qd.mem.512(ptr [[PTR:%.*]], <8 x i64> [[X1:%.*]], i8 -1)6586; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 06587; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i64> [[TMP2]] to i5126588; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i512 [[TMP7]], 06589; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]6590; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 06591; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]6592; CHECK-NEXT: br i1 [[_MSOR6]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]6593; CHECK: 8:6594; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]6595; CHECK-NEXT: unreachable6596; CHECK: 9:6597; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmov.qd.mem.512(ptr [[PTR]], <8 x i64> [[X1]], i8 [[X2:%.*]])6598; CHECK-NEXT: ret void6599;6600 call void @llvm.x86.avx512.mask.pmov.qd.mem.512(ptr %ptr, <8 x i64> %x1, i8 -1)6601 call void @llvm.x86.avx512.mask.pmov.qd.mem.512(ptr %ptr, <8 x i64> %x1, i8 %x2)6602 ret void6603}6604 6605declare <8 x i32> @llvm.x86.avx512.mask.pmovs.qd.512(<8 x i64>, <8 x i32>, i8)6606 6607define <8 x i32>@test_int_x86_avx512_pmovs_qd_512(<8 x i64> %x0, <8 x i32> %x1) #0 {6608; CHECK-LABEL: @test_int_x86_avx512_pmovs_qd_512(6609; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 86610; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 86611; CHECK-NEXT: call void @llvm.donothing()6612; CHECK-NEXT: [[TMP3:%.*]] = trunc <8 x i64> [[TMP1]] to <8 x i32>6613; CHECK-NEXT: [[TMP4:%.*]] = select <8 x i1> splat (i1 true), <8 x i32> [[TMP3]], <8 x i32> [[TMP2]]6614; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx512.mask.pmovs.qd.512(<8 x i64> [[X0:%.*]], <8 x i32> [[X1:%.*]], i8 -1)6615; CHECK-NEXT: store <8 x i32> [[TMP4]], ptr @__msan_retval_tls, align 86616; CHECK-NEXT: ret <8 x i32> [[RES]]6617;6618 %res = call <8 x i32> @llvm.x86.avx512.mask.pmovs.qd.512(<8 x i64> %x0, <8 x i32> %x1, i8 -1)6619 ret <8 x i32> %res6620}6621 6622define <8 x i32>@test_int_x86_avx512_mask_pmovs_qd_512(<8 x i64> %x0, <8 x i32> %x1, i8 %x2) #0 {6623; CHECK-LABEL: @test_int_x86_avx512_mask_pmovs_qd_512(6624; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 86625; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 86626; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 86627; CHECK-NEXT: call void @llvm.donothing()6628; CHECK-NEXT: [[TMP5:%.*]] = bitcast i8 [[TMP4:%.*]] to <8 x i1>6629; CHECK-NEXT: [[TMP6:%.*]] = trunc <8 x i64> [[TMP1]] to <8 x i32>6630; CHECK-NEXT: [[TMP7:%.*]] = select <8 x i1> [[TMP5]], <8 x i32> [[TMP6]], <8 x i32> [[TMP2]]6631; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i8 [[TMP3]], 06632; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]6633; CHECK: 6:6634; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]6635; CHECK-NEXT: unreachable6636; CHECK: 7:6637; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx512.mask.pmovs.qd.512(<8 x i64> [[X0:%.*]], <8 x i32> [[X1:%.*]], i8 [[TMP4]])6638; CHECK-NEXT: store <8 x i32> [[TMP7]], ptr @__msan_retval_tls, align 86639; CHECK-NEXT: ret <8 x i32> [[RES]]6640;6641 %res = call <8 x i32> @llvm.x86.avx512.mask.pmovs.qd.512(<8 x i64> %x0, <8 x i32> %x1, i8 %x2)6642 ret <8 x i32> %res6643}6644 6645define <8 x i32>@test_int_x86_avx512_maskz_pmovs_qd_512(<8 x i64> %x0, i8 %x2) #0 {6646; CHECK-LABEL: @test_int_x86_avx512_maskz_pmovs_qd_512(6647; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 86648; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 86649; CHECK-NEXT: call void @llvm.donothing()6650; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8 [[TMP3:%.*]] to <8 x i1>6651; CHECK-NEXT: [[TMP5:%.*]] = trunc <8 x i64> [[TMP1]] to <8 x i32>6652; CHECK-NEXT: [[TMP6:%.*]] = select <8 x i1> [[TMP4]], <8 x i32> [[TMP5]], <8 x i32> zeroinitializer6653; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i8 [[TMP2]], 06654; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]6655; CHECK: 5:6656; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]6657; CHECK-NEXT: unreachable6658; CHECK: 6:6659; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx512.mask.pmovs.qd.512(<8 x i64> [[X0:%.*]], <8 x i32> zeroinitializer, i8 [[TMP3]])6660; CHECK-NEXT: store <8 x i32> [[TMP6]], ptr @__msan_retval_tls, align 86661; CHECK-NEXT: ret <8 x i32> [[RES]]6662;6663 %res = call <8 x i32> @llvm.x86.avx512.mask.pmovs.qd.512(<8 x i64> %x0, <8 x i32> zeroinitializer, i8 %x2)6664 ret <8 x i32> %res6665}6666 6667declare void @llvm.x86.avx512.mask.pmovs.qd.mem.512(ptr %ptr, <8 x i64>, i8)6668 6669define void @test_int_x86_avx512_mask_pmovs_qd_mem_512(ptr %ptr, <8 x i64> %x1, i8 %x2) #0 {6670; CHECK-LABEL: @test_int_x86_avx512_mask_pmovs_qd_mem_512(6671; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 86672; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 86673; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 72), align 86674; CHECK-NEXT: call void @llvm.donothing()6675; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 06676; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i64> [[TMP2]] to i5126677; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 06678; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6679; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]6680; CHECK: 5:6681; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]6682; CHECK-NEXT: unreachable6683; CHECK: 6:6684; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovs.qd.mem.512(ptr [[PTR:%.*]], <8 x i64> [[X1:%.*]], i8 -1)6685; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 06686; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i64> [[TMP2]] to i5126687; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i512 [[TMP7]], 06688; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]6689; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 06690; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]6691; CHECK-NEXT: br i1 [[_MSOR6]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]6692; CHECK: 8:6693; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]6694; CHECK-NEXT: unreachable6695; CHECK: 9:6696; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovs.qd.mem.512(ptr [[PTR]], <8 x i64> [[X1]], i8 [[X2:%.*]])6697; CHECK-NEXT: ret void6698;6699 call void @llvm.x86.avx512.mask.pmovs.qd.mem.512(ptr %ptr, <8 x i64> %x1, i8 -1)6700 call void @llvm.x86.avx512.mask.pmovs.qd.mem.512(ptr %ptr, <8 x i64> %x1, i8 %x2)6701 ret void6702}6703 6704declare <8 x i32> @llvm.x86.avx512.mask.pmovus.qd.512(<8 x i64>, <8 x i32>, i8)6705 6706define <8 x i32>@test_int_x86_avx512_pmovus_qd_512(<8 x i64> %x0, <8 x i32> %x1) #0 {6707; CHECK-LABEL: @test_int_x86_avx512_pmovus_qd_512(6708; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 86709; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 86710; CHECK-NEXT: call void @llvm.donothing()6711; CHECK-NEXT: [[TMP3:%.*]] = trunc <8 x i64> [[TMP1]] to <8 x i32>6712; CHECK-NEXT: [[TMP4:%.*]] = select <8 x i1> splat (i1 true), <8 x i32> [[TMP3]], <8 x i32> [[TMP2]]6713; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx512.mask.pmovus.qd.512(<8 x i64> [[X0:%.*]], <8 x i32> [[X1:%.*]], i8 -1)6714; CHECK-NEXT: store <8 x i32> [[TMP4]], ptr @__msan_retval_tls, align 86715; CHECK-NEXT: ret <8 x i32> [[RES]]6716;6717 %res = call <8 x i32> @llvm.x86.avx512.mask.pmovus.qd.512(<8 x i64> %x0, <8 x i32> %x1, i8 -1)6718 ret <8 x i32> %res6719}6720 6721define <8 x i32>@test_int_x86_avx512_mask_pmovus_qd_512(<8 x i64> %x0, <8 x i32> %x1, i8 %x2) #0 {6722; CHECK-LABEL: @test_int_x86_avx512_mask_pmovus_qd_512(6723; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 86724; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 86725; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 86726; CHECK-NEXT: call void @llvm.donothing()6727; CHECK-NEXT: [[TMP5:%.*]] = bitcast i8 [[TMP4:%.*]] to <8 x i1>6728; CHECK-NEXT: [[TMP6:%.*]] = trunc <8 x i64> [[TMP1]] to <8 x i32>6729; CHECK-NEXT: [[TMP7:%.*]] = select <8 x i1> [[TMP5]], <8 x i32> [[TMP6]], <8 x i32> [[TMP2]]6730; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i8 [[TMP3]], 06731; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]6732; CHECK: 6:6733; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]6734; CHECK-NEXT: unreachable6735; CHECK: 7:6736; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx512.mask.pmovus.qd.512(<8 x i64> [[X0:%.*]], <8 x i32> [[X1:%.*]], i8 [[TMP4]])6737; CHECK-NEXT: store <8 x i32> [[TMP7]], ptr @__msan_retval_tls, align 86738; CHECK-NEXT: ret <8 x i32> [[RES]]6739;6740 %res = call <8 x i32> @llvm.x86.avx512.mask.pmovus.qd.512(<8 x i64> %x0, <8 x i32> %x1, i8 %x2)6741 ret <8 x i32> %res6742}6743 6744define <8 x i32>@test_int_x86_avx512_maskz_pmovus_qd_512(<8 x i64> %x0, i8 %x2) #0 {6745; CHECK-LABEL: @test_int_x86_avx512_maskz_pmovus_qd_512(6746; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 86747; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 86748; CHECK-NEXT: call void @llvm.donothing()6749; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8 [[TMP3:%.*]] to <8 x i1>6750; CHECK-NEXT: [[TMP5:%.*]] = trunc <8 x i64> [[TMP1]] to <8 x i32>6751; CHECK-NEXT: [[TMP6:%.*]] = select <8 x i1> [[TMP4]], <8 x i32> [[TMP5]], <8 x i32> zeroinitializer6752; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i8 [[TMP2]], 06753; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]6754; CHECK: 5:6755; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]6756; CHECK-NEXT: unreachable6757; CHECK: 6:6758; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx512.mask.pmovus.qd.512(<8 x i64> [[X0:%.*]], <8 x i32> zeroinitializer, i8 [[TMP3]])6759; CHECK-NEXT: store <8 x i32> [[TMP6]], ptr @__msan_retval_tls, align 86760; CHECK-NEXT: ret <8 x i32> [[RES]]6761;6762 %res = call <8 x i32> @llvm.x86.avx512.mask.pmovus.qd.512(<8 x i64> %x0, <8 x i32> zeroinitializer, i8 %x2)6763 ret <8 x i32> %res6764}6765 6766declare void @llvm.x86.avx512.mask.pmovus.qd.mem.512(ptr %ptr, <8 x i64>, i8)6767 6768define void @test_int_x86_avx512_mask_pmovus_qd_mem_512(ptr %ptr, <8 x i64> %x1, i8 %x2) #0 {6769; CHECK-LABEL: @test_int_x86_avx512_mask_pmovus_qd_mem_512(6770; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 86771; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 86772; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 72), align 86773; CHECK-NEXT: call void @llvm.donothing()6774; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 06775; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i64> [[TMP2]] to i5126776; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 06777; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6778; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]6779; CHECK: 5:6780; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]6781; CHECK-NEXT: unreachable6782; CHECK: 6:6783; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovus.qd.mem.512(ptr [[PTR:%.*]], <8 x i64> [[X1:%.*]], i8 -1)6784; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 06785; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i64> [[TMP2]] to i5126786; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i512 [[TMP7]], 06787; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]6788; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 06789; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]6790; CHECK-NEXT: br i1 [[_MSOR6]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]6791; CHECK: 8:6792; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]6793; CHECK-NEXT: unreachable6794; CHECK: 9:6795; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovus.qd.mem.512(ptr [[PTR]], <8 x i64> [[X1]], i8 [[X2:%.*]])6796; CHECK-NEXT: ret void6797;6798 call void @llvm.x86.avx512.mask.pmovus.qd.mem.512(ptr %ptr, <8 x i64> %x1, i8 -1)6799 call void @llvm.x86.avx512.mask.pmovus.qd.mem.512(ptr %ptr, <8 x i64> %x1, i8 %x2)6800 ret void6801}6802 6803declare <16 x i8> @llvm.x86.avx512.mask.pmov.db.512(<16 x i32>, <16 x i8>, i16)6804 6805define <16 x i8>@test_int_x86_avx512_mask_pmov_db_512(<16 x i32> %x0, <16 x i8> %x1, i16 %x2) #0 {6806; CHECK-LABEL: @test_int_x86_avx512_mask_pmov_db_512(6807; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 86808; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 86809; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 80), align 86810; CHECK-NEXT: call void @llvm.donothing()6811; CHECK-NEXT: [[TMP8:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmov.db.512(<16 x i32> [[TMP1]], <16 x i8> [[TMP2]], i16 -1)6812; CHECK-NEXT: [[_MSPROP2:%.*]] = or <16 x i8> zeroinitializer, [[TMP8]]6813; CHECK-NEXT: [[RES0:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmov.db.512(<16 x i32> [[X0:%.*]], <16 x i8> [[X1:%.*]], i16 -1)6814; CHECK-NEXT: [[TMP5:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmov.db.512(<16 x i32> [[TMP1]], <16 x i8> [[TMP2]], i16 [[TMP6:%.*]])6815; CHECK-NEXT: [[TMP10:%.*]] = zext i16 [[TMP3]] to i1286816; CHECK-NEXT: [[TMP7:%.*]] = bitcast i128 [[TMP10]] to <16 x i8>6817; CHECK-NEXT: [[_MSPROP4:%.*]] = or <16 x i8> [[TMP7]], [[TMP5]]6818; CHECK-NEXT: [[RES1:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmov.db.512(<16 x i32> [[X0]], <16 x i8> [[X1]], i16 [[TMP6]])6819; CHECK-NEXT: [[TMP9:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmov.db.512(<16 x i32> [[TMP1]], <16 x i8> zeroinitializer, i16 [[TMP6]])6820; CHECK-NEXT: [[TMP11:%.*]] = zext i16 [[TMP3]] to i1286821; CHECK-NEXT: [[TMP4:%.*]] = bitcast i128 [[TMP11]] to <16 x i8>6822; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i8> [[TMP4]], [[TMP9]]6823; CHECK-NEXT: [[RES2:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmov.db.512(<16 x i32> [[X0]], <16 x i8> zeroinitializer, i16 [[TMP6]])6824; CHECK-NEXT: [[_MSPROP3:%.*]] = or <16 x i8> [[_MSPROP2]], [[_MSPROP4]]6825; CHECK-NEXT: [[RES3:%.*]] = add <16 x i8> [[RES0]], [[RES1]]6826; CHECK-NEXT: [[_MSPROP1:%.*]] = or <16 x i8> [[_MSPROP3]], [[_MSPROP]]6827; CHECK-NEXT: [[RES4:%.*]] = add <16 x i8> [[RES3]], [[RES2]]6828; CHECK-NEXT: store <16 x i8> [[_MSPROP1]], ptr @__msan_retval_tls, align 86829; CHECK-NEXT: ret <16 x i8> [[RES4]]6830;6831 %res0 = call <16 x i8> @llvm.x86.avx512.mask.pmov.db.512(<16 x i32> %x0, <16 x i8> %x1, i16 -1)6832 %res1 = call <16 x i8> @llvm.x86.avx512.mask.pmov.db.512(<16 x i32> %x0, <16 x i8> %x1, i16 %x2)6833 %res2 = call <16 x i8> @llvm.x86.avx512.mask.pmov.db.512(<16 x i32> %x0, <16 x i8> zeroinitializer, i16 %x2)6834 %res3 = add <16 x i8> %res0, %res16835 %res4 = add <16 x i8> %res3, %res26836 ret <16 x i8> %res46837}6838 6839declare void @llvm.x86.avx512.mask.pmov.db.mem.512(ptr %ptr, <16 x i32>, i16)6840 6841define void @test_int_x86_avx512_mask_pmov_db_mem_512(ptr %ptr, <16 x i32> %x1, i16 %x2) #0 {6842; CHECK-LABEL: @test_int_x86_avx512_mask_pmov_db_mem_512(6843; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 86844; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 86845; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 72), align 86846; CHECK-NEXT: call void @llvm.donothing()6847; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 06848; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP2]] to i5126849; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 06850; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6851; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]6852; CHECK: 5:6853; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]6854; CHECK-NEXT: unreachable6855; CHECK: 6:6856; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmov.db.mem.512(ptr [[PTR:%.*]], <16 x i32> [[X1:%.*]], i16 -1)6857; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 06858; CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i32> [[TMP2]] to i5126859; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i512 [[TMP7]], 06860; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]6861; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i16 [[TMP3]], 06862; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]6863; CHECK-NEXT: br i1 [[_MSOR6]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]6864; CHECK: 8:6865; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]6866; CHECK-NEXT: unreachable6867; CHECK: 9:6868; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmov.db.mem.512(ptr [[PTR]], <16 x i32> [[X1]], i16 [[X2:%.*]])6869; CHECK-NEXT: ret void6870;6871 call void @llvm.x86.avx512.mask.pmov.db.mem.512(ptr %ptr, <16 x i32> %x1, i16 -1)6872 call void @llvm.x86.avx512.mask.pmov.db.mem.512(ptr %ptr, <16 x i32> %x1, i16 %x2)6873 ret void6874}6875 6876declare <16 x i8> @llvm.x86.avx512.mask.pmovs.db.512(<16 x i32>, <16 x i8>, i16)6877 6878define <16 x i8>@test_int_x86_avx512_mask_pmovs_db_512(<16 x i32> %x0, <16 x i8> %x1, i16 %x2) #0 {6879; CHECK-LABEL: @test_int_x86_avx512_mask_pmovs_db_512(6880; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 86881; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 86882; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 80), align 86883; CHECK-NEXT: call void @llvm.donothing()6884; CHECK-NEXT: [[TMP11:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmov.db.512(<16 x i32> [[TMP1]], <16 x i8> [[TMP2]], i16 -1)6885; CHECK-NEXT: [[TMP4:%.*]] = or <16 x i8> zeroinitializer, [[TMP11]]6886; CHECK-NEXT: [[RES0:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmovs.db.512(<16 x i32> [[X0:%.*]], <16 x i8> [[X1:%.*]], i16 -1)6887; CHECK-NEXT: [[TMP5:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmov.db.512(<16 x i32> [[TMP1]], <16 x i8> [[TMP2]], i16 [[TMP6:%.*]])6888; CHECK-NEXT: [[TMP12:%.*]] = zext i16 [[TMP3]] to i1286889; CHECK-NEXT: [[TMP7:%.*]] = bitcast i128 [[TMP12]] to <16 x i8>6890; CHECK-NEXT: [[TMP9:%.*]] = or <16 x i8> [[TMP7]], [[TMP5]]6891; CHECK-NEXT: [[RES1:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmovs.db.512(<16 x i32> [[X0]], <16 x i8> [[X1]], i16 [[TMP6]])6892; CHECK-NEXT: [[TMP8:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmov.db.512(<16 x i32> [[TMP1]], <16 x i8> zeroinitializer, i16 [[TMP6]])6893; CHECK-NEXT: [[TMP13:%.*]] = zext i16 [[TMP3]] to i1286894; CHECK-NEXT: [[TMP10:%.*]] = bitcast i128 [[TMP13]] to <16 x i8>6895; CHECK-NEXT: [[TMP14:%.*]] = or <16 x i8> [[TMP10]], [[TMP8]]6896; CHECK-NEXT: [[RES2:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmovs.db.512(<16 x i32> [[X0]], <16 x i8> zeroinitializer, i16 [[TMP6]])6897; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i8> [[TMP4]], [[TMP9]]6898; CHECK-NEXT: [[RES3:%.*]] = add <16 x i8> [[RES0]], [[RES1]]6899; CHECK-NEXT: [[_MSPROP1:%.*]] = or <16 x i8> [[_MSPROP]], [[TMP14]]6900; CHECK-NEXT: [[RES4:%.*]] = add <16 x i8> [[RES3]], [[RES2]]6901; CHECK-NEXT: store <16 x i8> [[_MSPROP1]], ptr @__msan_retval_tls, align 86902; CHECK-NEXT: ret <16 x i8> [[RES4]]6903;6904 %res0 = call <16 x i8> @llvm.x86.avx512.mask.pmovs.db.512(<16 x i32> %x0, <16 x i8> %x1, i16 -1)6905 %res1 = call <16 x i8> @llvm.x86.avx512.mask.pmovs.db.512(<16 x i32> %x0, <16 x i8> %x1, i16 %x2)6906 %res2 = call <16 x i8> @llvm.x86.avx512.mask.pmovs.db.512(<16 x i32> %x0, <16 x i8> zeroinitializer, i16 %x2)6907 %res3 = add <16 x i8> %res0, %res16908 %res4 = add <16 x i8> %res3, %res26909 ret <16 x i8> %res46910}6911 6912declare void @llvm.x86.avx512.mask.pmovs.db.mem.512(ptr %ptr, <16 x i32>, i16)6913 6914define void @test_int_x86_avx512_mask_pmovs_db_mem_512(ptr %ptr, <16 x i32> %x1, i16 %x2) #0 {6915; CHECK-LABEL: @test_int_x86_avx512_mask_pmovs_db_mem_512(6916; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 86917; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 86918; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 72), align 86919; CHECK-NEXT: call void @llvm.donothing()6920; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 06921; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP2]] to i5126922; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 06923; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6924; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]6925; CHECK: 5:6926; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]6927; CHECK-NEXT: unreachable6928; CHECK: 6:6929; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovs.db.mem.512(ptr [[PTR:%.*]], <16 x i32> [[X1:%.*]], i16 -1)6930; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 06931; CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i32> [[TMP2]] to i5126932; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i512 [[TMP7]], 06933; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]6934; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i16 [[TMP3]], 06935; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]6936; CHECK-NEXT: br i1 [[_MSOR6]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]6937; CHECK: 8:6938; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]6939; CHECK-NEXT: unreachable6940; CHECK: 9:6941; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovs.db.mem.512(ptr [[PTR]], <16 x i32> [[X1]], i16 [[X2:%.*]])6942; CHECK-NEXT: ret void6943;6944 call void @llvm.x86.avx512.mask.pmovs.db.mem.512(ptr %ptr, <16 x i32> %x1, i16 -1)6945 call void @llvm.x86.avx512.mask.pmovs.db.mem.512(ptr %ptr, <16 x i32> %x1, i16 %x2)6946 ret void6947}6948 6949declare <16 x i8> @llvm.x86.avx512.mask.pmovus.db.512(<16 x i32>, <16 x i8>, i16)6950 6951define <16 x i8>@test_int_x86_avx512_mask_pmovus_db_512(<16 x i32> %x0, <16 x i8> %x1, i16 %x2) #0 {6952; CHECK-LABEL: @test_int_x86_avx512_mask_pmovus_db_512(6953; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 86954; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 86955; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 80), align 86956; CHECK-NEXT: call void @llvm.donothing()6957; CHECK-NEXT: [[TMP11:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmov.db.512(<16 x i32> [[TMP1]], <16 x i8> [[TMP2]], i16 -1)6958; CHECK-NEXT: [[TMP4:%.*]] = or <16 x i8> zeroinitializer, [[TMP11]]6959; CHECK-NEXT: [[RES0:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmovus.db.512(<16 x i32> [[X0:%.*]], <16 x i8> [[X1:%.*]], i16 -1)6960; CHECK-NEXT: [[TMP5:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmov.db.512(<16 x i32> [[TMP1]], <16 x i8> [[TMP2]], i16 [[TMP6:%.*]])6961; CHECK-NEXT: [[TMP12:%.*]] = zext i16 [[TMP3]] to i1286962; CHECK-NEXT: [[TMP7:%.*]] = bitcast i128 [[TMP12]] to <16 x i8>6963; CHECK-NEXT: [[TMP9:%.*]] = or <16 x i8> [[TMP7]], [[TMP5]]6964; CHECK-NEXT: [[RES1:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmovus.db.512(<16 x i32> [[X0]], <16 x i8> [[X1]], i16 [[TMP6]])6965; CHECK-NEXT: [[TMP8:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmov.db.512(<16 x i32> [[TMP1]], <16 x i8> zeroinitializer, i16 [[TMP6]])6966; CHECK-NEXT: [[TMP13:%.*]] = zext i16 [[TMP3]] to i1286967; CHECK-NEXT: [[TMP10:%.*]] = bitcast i128 [[TMP13]] to <16 x i8>6968; CHECK-NEXT: [[TMP14:%.*]] = or <16 x i8> [[TMP10]], [[TMP8]]6969; CHECK-NEXT: [[RES2:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmovus.db.512(<16 x i32> [[X0]], <16 x i8> zeroinitializer, i16 [[TMP6]])6970; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i8> [[TMP4]], [[TMP9]]6971; CHECK-NEXT: [[RES3:%.*]] = add <16 x i8> [[RES0]], [[RES1]]6972; CHECK-NEXT: [[_MSPROP1:%.*]] = or <16 x i8> [[_MSPROP]], [[TMP14]]6973; CHECK-NEXT: [[RES4:%.*]] = add <16 x i8> [[RES3]], [[RES2]]6974; CHECK-NEXT: store <16 x i8> [[_MSPROP1]], ptr @__msan_retval_tls, align 86975; CHECK-NEXT: ret <16 x i8> [[RES4]]6976;6977 %res0 = call <16 x i8> @llvm.x86.avx512.mask.pmovus.db.512(<16 x i32> %x0, <16 x i8> %x1, i16 -1)6978 %res1 = call <16 x i8> @llvm.x86.avx512.mask.pmovus.db.512(<16 x i32> %x0, <16 x i8> %x1, i16 %x2)6979 %res2 = call <16 x i8> @llvm.x86.avx512.mask.pmovus.db.512(<16 x i32> %x0, <16 x i8> zeroinitializer, i16 %x2)6980 %res3 = add <16 x i8> %res0, %res16981 %res4 = add <16 x i8> %res3, %res26982 ret <16 x i8> %res46983}6984 6985declare void @llvm.x86.avx512.mask.pmovus.db.mem.512(ptr %ptr, <16 x i32>, i16)6986 6987define void @test_int_x86_avx512_mask_pmovus_db_mem_512(ptr %ptr, <16 x i32> %x1, i16 %x2) #0 {6988; CHECK-LABEL: @test_int_x86_avx512_mask_pmovus_db_mem_512(6989; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 86990; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 86991; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 72), align 86992; CHECK-NEXT: call void @llvm.donothing()6993; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 06994; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP2]] to i5126995; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 06996; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6997; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]6998; CHECK: 5:6999; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]7000; CHECK-NEXT: unreachable7001; CHECK: 6:7002; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovus.db.mem.512(ptr [[PTR:%.*]], <16 x i32> [[X1:%.*]], i16 -1)7003; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 07004; CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i32> [[TMP2]] to i5127005; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i512 [[TMP7]], 07006; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]7007; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i16 [[TMP3]], 07008; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]7009; CHECK-NEXT: br i1 [[_MSOR6]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]7010; CHECK: 8:7011; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]7012; CHECK-NEXT: unreachable7013; CHECK: 9:7014; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovus.db.mem.512(ptr [[PTR]], <16 x i32> [[X1]], i16 [[X2:%.*]])7015; CHECK-NEXT: ret void7016;7017 call void @llvm.x86.avx512.mask.pmovus.db.mem.512(ptr %ptr, <16 x i32> %x1, i16 -1)7018 call void @llvm.x86.avx512.mask.pmovus.db.mem.512(ptr %ptr, <16 x i32> %x1, i16 %x2)7019 ret void7020}7021 7022declare <16 x i16> @llvm.x86.avx512.mask.pmov.dw.512(<16 x i32>, <16 x i16>, i16)7023 7024define <16 x i16>@test_int_x86_avx512_mask_pmov_dw_512(<16 x i32> %x0, <16 x i16> %x1, i16 %x2) #0 {7025; CHECK-LABEL: @test_int_x86_avx512_mask_pmov_dw_512(7026; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 87027; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 87028; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 87029; CHECK-NEXT: call void @llvm.donothing()7030; CHECK-NEXT: [[TMP8:%.*]] = call <16 x i16> @llvm.x86.avx512.mask.pmov.dw.512(<16 x i32> [[TMP1]], <16 x i16> [[TMP2]], i16 -1)7031; CHECK-NEXT: [[_MSPROP2:%.*]] = or <16 x i16> zeroinitializer, [[TMP8]]7032; CHECK-NEXT: [[RES0:%.*]] = call <16 x i16> @llvm.x86.avx512.mask.pmov.dw.512(<16 x i32> [[X0:%.*]], <16 x i16> [[X1:%.*]], i16 -1)7033; CHECK-NEXT: [[TMP5:%.*]] = call <16 x i16> @llvm.x86.avx512.mask.pmov.dw.512(<16 x i32> [[TMP1]], <16 x i16> [[TMP2]], i16 [[TMP6:%.*]])7034; CHECK-NEXT: [[TMP10:%.*]] = zext i16 [[TMP3]] to i2567035; CHECK-NEXT: [[TMP7:%.*]] = bitcast i256 [[TMP10]] to <16 x i16>7036; CHECK-NEXT: [[_MSPROP4:%.*]] = or <16 x i16> [[TMP7]], [[TMP5]]7037; CHECK-NEXT: [[RES1:%.*]] = call <16 x i16> @llvm.x86.avx512.mask.pmov.dw.512(<16 x i32> [[X0]], <16 x i16> [[X1]], i16 [[TMP6]])7038; CHECK-NEXT: [[TMP9:%.*]] = call <16 x i16> @llvm.x86.avx512.mask.pmov.dw.512(<16 x i32> [[TMP1]], <16 x i16> zeroinitializer, i16 [[TMP6]])7039; CHECK-NEXT: [[TMP11:%.*]] = zext i16 [[TMP3]] to i2567040; CHECK-NEXT: [[TMP4:%.*]] = bitcast i256 [[TMP11]] to <16 x i16>7041; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i16> [[TMP4]], [[TMP9]]7042; CHECK-NEXT: [[RES2:%.*]] = call <16 x i16> @llvm.x86.avx512.mask.pmov.dw.512(<16 x i32> [[X0]], <16 x i16> zeroinitializer, i16 [[TMP6]])7043; CHECK-NEXT: [[_MSPROP3:%.*]] = or <16 x i16> [[_MSPROP2]], [[_MSPROP4]]7044; CHECK-NEXT: [[RES3:%.*]] = add <16 x i16> [[RES0]], [[RES1]]7045; CHECK-NEXT: [[_MSPROP1:%.*]] = or <16 x i16> [[_MSPROP3]], [[_MSPROP]]7046; CHECK-NEXT: [[RES4:%.*]] = add <16 x i16> [[RES3]], [[RES2]]7047; CHECK-NEXT: store <16 x i16> [[_MSPROP1]], ptr @__msan_retval_tls, align 87048; CHECK-NEXT: ret <16 x i16> [[RES4]]7049;7050 %res0 = call <16 x i16> @llvm.x86.avx512.mask.pmov.dw.512(<16 x i32> %x0, <16 x i16> %x1, i16 -1)7051 %res1 = call <16 x i16> @llvm.x86.avx512.mask.pmov.dw.512(<16 x i32> %x0, <16 x i16> %x1, i16 %x2)7052 %res2 = call <16 x i16> @llvm.x86.avx512.mask.pmov.dw.512(<16 x i32> %x0, <16 x i16> zeroinitializer, i16 %x2)7053 %res3 = add <16 x i16> %res0, %res17054 %res4 = add <16 x i16> %res3, %res27055 ret <16 x i16> %res47056}7057 7058declare void @llvm.x86.avx512.mask.pmov.dw.mem.512(ptr %ptr, <16 x i32>, i16)7059 7060define void @test_int_x86_avx512_mask_pmov_dw_mem_512(ptr %ptr, <16 x i32> %x1, i16 %x2) #0 {7061; CHECK-LABEL: @test_int_x86_avx512_mask_pmov_dw_mem_512(7062; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 87063; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 87064; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 72), align 87065; CHECK-NEXT: call void @llvm.donothing()7066; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 07067; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP2]] to i5127068; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 07069; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]7070; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]7071; CHECK: 5:7072; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]7073; CHECK-NEXT: unreachable7074; CHECK: 6:7075; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmov.dw.mem.512(ptr [[PTR:%.*]], <16 x i32> [[X1:%.*]], i16 -1)7076; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 07077; CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i32> [[TMP2]] to i5127078; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i512 [[TMP7]], 07079; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]7080; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i16 [[TMP3]], 07081; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]7082; CHECK-NEXT: br i1 [[_MSOR6]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]7083; CHECK: 8:7084; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]7085; CHECK-NEXT: unreachable7086; CHECK: 9:7087; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmov.dw.mem.512(ptr [[PTR]], <16 x i32> [[X1]], i16 [[X2:%.*]])7088; CHECK-NEXT: ret void7089;7090 call void @llvm.x86.avx512.mask.pmov.dw.mem.512(ptr %ptr, <16 x i32> %x1, i16 -1)7091 call void @llvm.x86.avx512.mask.pmov.dw.mem.512(ptr %ptr, <16 x i32> %x1, i16 %x2)7092 ret void7093}7094 7095declare <16 x i16> @llvm.x86.avx512.mask.pmovs.dw.512(<16 x i32>, <16 x i16>, i16)7096 7097define <16 x i16>@test_int_x86_avx512_mask_pmovs_dw_512(<16 x i32> %x0, <16 x i16> %x1, i16 %x2) #0 {7098; CHECK-LABEL: @test_int_x86_avx512_mask_pmovs_dw_512(7099; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 87100; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 87101; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 87102; CHECK-NEXT: call void @llvm.donothing()7103; CHECK-NEXT: [[TMP11:%.*]] = call <16 x i16> @llvm.x86.avx512.mask.pmov.dw.512(<16 x i32> [[TMP1]], <16 x i16> [[TMP2]], i16 -1)7104; CHECK-NEXT: [[TMP4:%.*]] = or <16 x i16> zeroinitializer, [[TMP11]]7105; CHECK-NEXT: [[RES0:%.*]] = call <16 x i16> @llvm.x86.avx512.mask.pmovs.dw.512(<16 x i32> [[X0:%.*]], <16 x i16> [[X1:%.*]], i16 -1)7106; CHECK-NEXT: [[TMP5:%.*]] = call <16 x i16> @llvm.x86.avx512.mask.pmov.dw.512(<16 x i32> [[TMP1]], <16 x i16> [[TMP2]], i16 [[TMP6:%.*]])7107; CHECK-NEXT: [[TMP12:%.*]] = zext i16 [[TMP3]] to i2567108; CHECK-NEXT: [[TMP7:%.*]] = bitcast i256 [[TMP12]] to <16 x i16>7109; CHECK-NEXT: [[TMP9:%.*]] = or <16 x i16> [[TMP7]], [[TMP5]]7110; CHECK-NEXT: [[RES1:%.*]] = call <16 x i16> @llvm.x86.avx512.mask.pmovs.dw.512(<16 x i32> [[X0]], <16 x i16> [[X1]], i16 [[TMP6]])7111; CHECK-NEXT: [[TMP8:%.*]] = call <16 x i16> @llvm.x86.avx512.mask.pmov.dw.512(<16 x i32> [[TMP1]], <16 x i16> zeroinitializer, i16 [[TMP6]])7112; CHECK-NEXT: [[TMP13:%.*]] = zext i16 [[TMP3]] to i2567113; CHECK-NEXT: [[TMP10:%.*]] = bitcast i256 [[TMP13]] to <16 x i16>7114; CHECK-NEXT: [[TMP14:%.*]] = or <16 x i16> [[TMP10]], [[TMP8]]7115; CHECK-NEXT: [[RES2:%.*]] = call <16 x i16> @llvm.x86.avx512.mask.pmovs.dw.512(<16 x i32> [[X0]], <16 x i16> zeroinitializer, i16 [[TMP6]])7116; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i16> [[TMP4]], [[TMP9]]7117; CHECK-NEXT: [[RES3:%.*]] = add <16 x i16> [[RES0]], [[RES1]]7118; CHECK-NEXT: [[_MSPROP1:%.*]] = or <16 x i16> [[_MSPROP]], [[TMP14]]7119; CHECK-NEXT: [[RES4:%.*]] = add <16 x i16> [[RES3]], [[RES2]]7120; CHECK-NEXT: store <16 x i16> [[_MSPROP1]], ptr @__msan_retval_tls, align 87121; CHECK-NEXT: ret <16 x i16> [[RES4]]7122;7123 %res0 = call <16 x i16> @llvm.x86.avx512.mask.pmovs.dw.512(<16 x i32> %x0, <16 x i16> %x1, i16 -1)7124 %res1 = call <16 x i16> @llvm.x86.avx512.mask.pmovs.dw.512(<16 x i32> %x0, <16 x i16> %x1, i16 %x2)7125 %res2 = call <16 x i16> @llvm.x86.avx512.mask.pmovs.dw.512(<16 x i32> %x0, <16 x i16> zeroinitializer, i16 %x2)7126 %res3 = add <16 x i16> %res0, %res17127 %res4 = add <16 x i16> %res3, %res27128 ret <16 x i16> %res47129}7130 7131declare void @llvm.x86.avx512.mask.pmovs.dw.mem.512(ptr %ptr, <16 x i32>, i16)7132 7133define void @test_int_x86_avx512_mask_pmovs_dw_mem_512(ptr %ptr, <16 x i32> %x1, i16 %x2) #0 {7134; CHECK-LABEL: @test_int_x86_avx512_mask_pmovs_dw_mem_512(7135; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 87136; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 87137; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 72), align 87138; CHECK-NEXT: call void @llvm.donothing()7139; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 07140; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP2]] to i5127141; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 07142; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]7143; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]7144; CHECK: 5:7145; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]7146; CHECK-NEXT: unreachable7147; CHECK: 6:7148; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovs.dw.mem.512(ptr [[PTR:%.*]], <16 x i32> [[X1:%.*]], i16 -1)7149; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 07150; CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i32> [[TMP2]] to i5127151; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i512 [[TMP7]], 07152; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]7153; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i16 [[TMP3]], 07154; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]7155; CHECK-NEXT: br i1 [[_MSOR6]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]7156; CHECK: 8:7157; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]7158; CHECK-NEXT: unreachable7159; CHECK: 9:7160; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovs.dw.mem.512(ptr [[PTR]], <16 x i32> [[X1]], i16 [[X2:%.*]])7161; CHECK-NEXT: ret void7162;7163 call void @llvm.x86.avx512.mask.pmovs.dw.mem.512(ptr %ptr, <16 x i32> %x1, i16 -1)7164 call void @llvm.x86.avx512.mask.pmovs.dw.mem.512(ptr %ptr, <16 x i32> %x1, i16 %x2)7165 ret void7166}7167 7168declare <16 x i16> @llvm.x86.avx512.mask.pmovus.dw.512(<16 x i32>, <16 x i16>, i16)7169 7170define <16 x i16>@test_int_x86_avx512_mask_pmovus_dw_512(<16 x i32> %x0, <16 x i16> %x1, i16 %x2) #0 {7171; CHECK-LABEL: @test_int_x86_avx512_mask_pmovus_dw_512(7172; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 87173; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 87174; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 87175; CHECK-NEXT: call void @llvm.donothing()7176; CHECK-NEXT: [[TMP11:%.*]] = call <16 x i16> @llvm.x86.avx512.mask.pmov.dw.512(<16 x i32> [[TMP1]], <16 x i16> [[TMP2]], i16 -1)7177; CHECK-NEXT: [[TMP4:%.*]] = or <16 x i16> zeroinitializer, [[TMP11]]7178; CHECK-NEXT: [[RES0:%.*]] = call <16 x i16> @llvm.x86.avx512.mask.pmovus.dw.512(<16 x i32> [[X0:%.*]], <16 x i16> [[X1:%.*]], i16 -1)7179; CHECK-NEXT: [[TMP5:%.*]] = call <16 x i16> @llvm.x86.avx512.mask.pmov.dw.512(<16 x i32> [[TMP1]], <16 x i16> [[TMP2]], i16 [[TMP6:%.*]])7180; CHECK-NEXT: [[TMP12:%.*]] = zext i16 [[TMP3]] to i2567181; CHECK-NEXT: [[TMP7:%.*]] = bitcast i256 [[TMP12]] to <16 x i16>7182; CHECK-NEXT: [[TMP9:%.*]] = or <16 x i16> [[TMP7]], [[TMP5]]7183; CHECK-NEXT: [[RES1:%.*]] = call <16 x i16> @llvm.x86.avx512.mask.pmovus.dw.512(<16 x i32> [[X0]], <16 x i16> [[X1]], i16 [[TMP6]])7184; CHECK-NEXT: [[TMP8:%.*]] = call <16 x i16> @llvm.x86.avx512.mask.pmov.dw.512(<16 x i32> [[TMP1]], <16 x i16> zeroinitializer, i16 [[TMP6]])7185; CHECK-NEXT: [[TMP13:%.*]] = zext i16 [[TMP3]] to i2567186; CHECK-NEXT: [[TMP10:%.*]] = bitcast i256 [[TMP13]] to <16 x i16>7187; CHECK-NEXT: [[TMP14:%.*]] = or <16 x i16> [[TMP10]], [[TMP8]]7188; CHECK-NEXT: [[RES2:%.*]] = call <16 x i16> @llvm.x86.avx512.mask.pmovus.dw.512(<16 x i32> [[X0]], <16 x i16> zeroinitializer, i16 [[TMP6]])7189; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i16> [[TMP4]], [[TMP9]]7190; CHECK-NEXT: [[RES3:%.*]] = add <16 x i16> [[RES0]], [[RES1]]7191; CHECK-NEXT: [[_MSPROP1:%.*]] = or <16 x i16> [[_MSPROP]], [[TMP14]]7192; CHECK-NEXT: [[RES4:%.*]] = add <16 x i16> [[RES3]], [[RES2]]7193; CHECK-NEXT: store <16 x i16> [[_MSPROP1]], ptr @__msan_retval_tls, align 87194; CHECK-NEXT: ret <16 x i16> [[RES4]]7195;7196 %res0 = call <16 x i16> @llvm.x86.avx512.mask.pmovus.dw.512(<16 x i32> %x0, <16 x i16> %x1, i16 -1)7197 %res1 = call <16 x i16> @llvm.x86.avx512.mask.pmovus.dw.512(<16 x i32> %x0, <16 x i16> %x1, i16 %x2)7198 %res2 = call <16 x i16> @llvm.x86.avx512.mask.pmovus.dw.512(<16 x i32> %x0, <16 x i16> zeroinitializer, i16 %x2)7199 %res3 = add <16 x i16> %res0, %res17200 %res4 = add <16 x i16> %res3, %res27201 ret <16 x i16> %res47202}7203 7204declare void @llvm.x86.avx512.mask.pmovus.dw.mem.512(ptr %ptr, <16 x i32>, i16)7205 7206define void @test_int_x86_avx512_mask_pmovus_dw_mem_512(ptr %ptr, <16 x i32> %x1, i16 %x2) #0 {7207; CHECK-LABEL: @test_int_x86_avx512_mask_pmovus_dw_mem_512(7208; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 87209; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 87210; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 72), align 87211; CHECK-NEXT: call void @llvm.donothing()7212; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 07213; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP2]] to i5127214; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 07215; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]7216; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]7217; CHECK: 5:7218; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]7219; CHECK-NEXT: unreachable7220; CHECK: 6:7221; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovus.dw.mem.512(ptr [[PTR:%.*]], <16 x i32> [[X1:%.*]], i16 -1)7222; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 07223; CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i32> [[TMP2]] to i5127224; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i512 [[TMP7]], 07225; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]7226; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i16 [[TMP3]], 07227; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]7228; CHECK-NEXT: br i1 [[_MSOR6]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]7229; CHECK: 8:7230; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]7231; CHECK-NEXT: unreachable7232; CHECK: 9:7233; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovus.dw.mem.512(ptr [[PTR]], <16 x i32> [[X1]], i16 [[X2:%.*]])7234; CHECK-NEXT: ret void7235;7236 call void @llvm.x86.avx512.mask.pmovus.dw.mem.512(ptr %ptr, <16 x i32> %x1, i16 -1)7237 call void @llvm.x86.avx512.mask.pmovus.dw.mem.512(ptr %ptr, <16 x i32> %x1, i16 %x2)7238 ret void7239}7240 7241declare <16 x float> @llvm.x86.avx512.sitofp.round.v16f32.v16i32(<16 x i32>, i32)7242 7243define <16 x float>@test_int_x86_avx512_mask_cvt_dq2ps_512(<16 x i32> %x0, <16 x float> %x1, i16 %x2) #0 {7244; CHECK-LABEL: @test_int_x86_avx512_mask_cvt_dq2ps_512(7245; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 87246; CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 87247; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 87248; CHECK-NEXT: call void @llvm.donothing()7249; CHECK-NEXT: [[CVT:%.*]] = sitofp <16 x i32> [[X0:%.*]] to <16 x float>7250; CHECK-NEXT: [[TMP4:%.*]] = bitcast i16 [[TMP2]] to <16 x i1>7251; CHECK-NEXT: [[TMP5:%.*]] = bitcast i16 [[X2:%.*]] to <16 x i1>7252; CHECK-NEXT: [[TMP6:%.*]] = select <16 x i1> [[TMP5]], <16 x i32> [[TMP1]], <16 x i32> [[TMP3]]7253; CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x float> [[CVT]] to <16 x i32>7254; CHECK-NEXT: [[TMP8:%.*]] = bitcast <16 x float> [[X1:%.*]] to <16 x i32>7255; CHECK-NEXT: [[TMP9:%.*]] = xor <16 x i32> [[TMP7]], [[TMP8]]7256; CHECK-NEXT: [[TMP10:%.*]] = or <16 x i32> [[TMP9]], [[TMP1]]7257; CHECK-NEXT: [[TMP11:%.*]] = or <16 x i32> [[TMP10]], [[TMP3]]7258; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP4]], <16 x i32> [[TMP11]], <16 x i32> [[TMP6]]7259; CHECK-NEXT: [[TMP12:%.*]] = select <16 x i1> [[TMP5]], <16 x float> [[CVT]], <16 x float> [[X1]]7260; CHECK-NEXT: [[TMP13:%.*]] = bitcast <16 x i32> [[TMP1]] to i5127261; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP13]], 07262; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP14:%.*]], label [[TMP15:%.*]], !prof [[PROF1]]7263; CHECK: 14:7264; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]7265; CHECK-NEXT: unreachable7266; CHECK: 15:7267; CHECK-NEXT: [[TMP16:%.*]] = call <16 x float> @llvm.x86.avx512.sitofp.round.v16f32.v16i32(<16 x i32> [[X0]], i32 8)7268; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i32> [[_MSPROP_SELECT]], zeroinitializer7269; CHECK-NEXT: [[RES2:%.*]] = fadd <16 x float> [[TMP12]], [[TMP16]]7270; CHECK-NEXT: store <16 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 87271; CHECK-NEXT: ret <16 x float> [[RES2]]7272;7273 %cvt = sitofp <16 x i32> %x0 to <16 x float>7274 %1 = bitcast i16 %x2 to <16 x i1>7275 %2 = select <16 x i1> %1, <16 x float> %cvt, <16 x float> %x17276 %3 = call <16 x float> @llvm.x86.avx512.sitofp.round.v16f32.v16i32(<16 x i32> %x0, i32 8)7277 %res2 = fadd <16 x float> %2, %37278 ret <16 x float> %res27279}7280 7281declare <8 x i32> @llvm.x86.avx512.mask.cvtpd2dq.512(<8 x double>, <8 x i32>, i8, i32)7282 7283define <8 x i32>@test_int_x86_avx512_mask_cvt_pd2dq_512(<8 x double> %x0, <8 x i32> %x1, i8 %x2) #0 {7284; CHECK-LABEL: @test_int_x86_avx512_mask_cvt_pd2dq_512(7285; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 87286; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 87287; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 87288; CHECK-NEXT: call void @llvm.donothing()7289; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i64> [[TMP1]] to i5127290; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP4]], 07291; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i32> [[TMP2]] to i2567292; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP5]], 07293; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]7294; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 07295; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]7296; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]7297; CHECK: 6:7298; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]7299; CHECK-NEXT: unreachable7300; CHECK: 7:7301; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx512.mask.cvtpd2dq.512(<8 x double> [[X0:%.*]], <8 x i32> [[X1:%.*]], i8 [[X2:%.*]], i32 4)7302; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i64> [[TMP1]] to i5127303; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i512 [[TMP8]], 07304; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i32> [[TMP2]] to i2567305; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i256 [[TMP9]], 07306; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSCMP4]], [[_MSCMP5]]7307; CHECK-NEXT: br i1 [[_MSOR6]], label [[TMP10:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]7308; CHECK: 10:7309; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]7310; CHECK-NEXT: unreachable7311; CHECK: 11:7312; CHECK-NEXT: [[RES1:%.*]] = call <8 x i32> @llvm.x86.avx512.mask.cvtpd2dq.512(<8 x double> [[X0]], <8 x i32> [[X1]], i8 -1, i32 8)7313; CHECK-NEXT: [[RES2:%.*]] = add <8 x i32> [[RES]], [[RES1]]7314; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 87315; CHECK-NEXT: ret <8 x i32> [[RES2]]7316;7317 %res = call <8 x i32> @llvm.x86.avx512.mask.cvtpd2dq.512(<8 x double> %x0, <8 x i32> %x1, i8 %x2, i32 4)7318 %res1 = call <8 x i32> @llvm.x86.avx512.mask.cvtpd2dq.512(<8 x double> %x0, <8 x i32> %x1, i8 -1, i32 8)7319 %res2 = add <8 x i32> %res, %res17320 ret <8 x i32> %res27321}7322 7323declare <8 x float> @llvm.x86.avx512.mask.cvtpd2ps.512(<8 x double>, <8 x float>, i8, i32)7324 7325define <8 x float>@test_int_x86_avx512_mask_cvt_pd2ps_512(<8 x double> %x0, <8 x float> %x1, i8 %x2) #0 {7326; CHECK-LABEL: @test_int_x86_avx512_mask_cvt_pd2ps_512(7327; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 87328; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 87329; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 87330; CHECK-NEXT: call void @llvm.donothing()7331; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i64> [[TMP1]] to i5127332; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP4]], 07333; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i32> [[TMP2]] to i2567334; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP5]], 07335; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]7336; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 07337; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]7338; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]7339; CHECK: 6:7340; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]7341; CHECK-NEXT: unreachable7342; CHECK: 7:7343; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx512.mask.cvtpd2ps.512(<8 x double> [[X0:%.*]], <8 x float> [[X1:%.*]], i8 [[X2:%.*]], i32 4)7344; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i64> [[TMP1]] to i5127345; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i512 [[TMP8]], 07346; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i32> [[TMP2]] to i2567347; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i256 [[TMP9]], 07348; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSCMP4]], [[_MSCMP5]]7349; CHECK-NEXT: br i1 [[_MSOR6]], label [[TMP10:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]7350; CHECK: 10:7351; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]7352; CHECK-NEXT: unreachable7353; CHECK: 11:7354; CHECK-NEXT: [[RES1:%.*]] = call <8 x float> @llvm.x86.avx512.mask.cvtpd2ps.512(<8 x double> [[X0]], <8 x float> [[X1]], i8 -1, i32 10)7355; CHECK-NEXT: [[RES2:%.*]] = fadd <8 x float> [[RES]], [[RES1]]7356; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 87357; CHECK-NEXT: ret <8 x float> [[RES2]]7358;7359 %res = call <8 x float> @llvm.x86.avx512.mask.cvtpd2ps.512(<8 x double> %x0, <8 x float> %x1, i8 %x2, i32 4)7360 %res1 = call <8 x float> @llvm.x86.avx512.mask.cvtpd2ps.512(<8 x double> %x0, <8 x float> %x1, i8 -1, i32 10)7361 %res2 = fadd <8 x float> %res, %res17362 ret <8 x float> %res27363}7364 7365declare <8 x i32> @llvm.x86.avx512.mask.cvtpd2udq.512(<8 x double>, <8 x i32>, i8, i32)7366 7367define <8 x i32>@test_int_x86_avx512_mask_cvt_pd2udq_512(<8 x double> %x0, <8 x i32> %x1, i8 %x2) #0 {7368; CHECK-LABEL: @test_int_x86_avx512_mask_cvt_pd2udq_512(7369; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 87370; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 87371; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 87372; CHECK-NEXT: call void @llvm.donothing()7373; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i64> [[TMP1]] to i5127374; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP4]], 07375; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i32> [[TMP2]] to i2567376; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP5]], 07377; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]7378; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 07379; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]7380; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]7381; CHECK: 6:7382; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]7383; CHECK-NEXT: unreachable7384; CHECK: 7:7385; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx512.mask.cvtpd2udq.512(<8 x double> [[X0:%.*]], <8 x i32> [[X1:%.*]], i8 [[X2:%.*]], i32 10)7386; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i64> [[TMP1]] to i5127387; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i512 [[TMP8]], 07388; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i32> [[TMP2]] to i2567389; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i256 [[TMP9]], 07390; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSCMP4]], [[_MSCMP5]]7391; CHECK-NEXT: br i1 [[_MSOR6]], label [[TMP10:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]7392; CHECK: 10:7393; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]7394; CHECK-NEXT: unreachable7395; CHECK: 11:7396; CHECK-NEXT: [[RES1:%.*]] = call <8 x i32> @llvm.x86.avx512.mask.cvtpd2udq.512(<8 x double> [[X0]], <8 x i32> [[X1]], i8 -1, i32 8)7397; CHECK-NEXT: [[RES2:%.*]] = add <8 x i32> [[RES]], [[RES1]]7398; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 87399; CHECK-NEXT: ret <8 x i32> [[RES2]]7400;7401 %res = call <8 x i32> @llvm.x86.avx512.mask.cvtpd2udq.512(<8 x double> %x0, <8 x i32> %x1, i8 %x2, i32 10)7402 %res1 = call <8 x i32> @llvm.x86.avx512.mask.cvtpd2udq.512(<8 x double> %x0, <8 x i32> %x1, i8 -1, i32 8)7403 %res2 = add <8 x i32> %res, %res17404 ret <8 x i32> %res27405}7406 7407declare <16 x i32> @llvm.x86.avx512.mask.cvtps2dq.512(<16 x float>, <16 x i32>, i16, i32)7408 7409define <16 x i32>@test_int_x86_avx512_mask_cvt_ps2dq_512(<16 x float> %x0, <16 x i32> %x1, i16 %x2) #0 {7410; CHECK-LABEL: @test_int_x86_avx512_mask_cvt_ps2dq_512(7411; CHECK-NEXT: [[TMP10:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 87412; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 87413; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 87414; CHECK-NEXT: call void @llvm.donothing()7415; CHECK-NEXT: [[TMP3:%.*]] = bitcast i16 [[X2:%.*]] to <16 x i1>7416; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <16 x i32> [[TMP1]], zeroinitializer7417; CHECK-NEXT: [[TMP5:%.*]] = sext <16 x i1> [[TMP4]] to <16 x i32>7418; CHECK-NEXT: [[TMP6:%.*]] = select <16 x i1> [[TMP3]], <16 x i32> [[TMP5]], <16 x i32> [[TMP2]]7419; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i16 [[TMP10]], 07420; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP11:%.*]], label [[TMP12:%.*]], !prof [[PROF1]]7421; CHECK: 5:7422; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]7423; CHECK-NEXT: unreachable7424; CHECK: 6:7425; CHECK-NEXT: [[RES:%.*]] = call <16 x i32> @llvm.x86.avx512.mask.cvtps2dq.512(<16 x float> [[X0:%.*]], <16 x i32> [[X1:%.*]], i16 [[X2]], i32 10)7426; CHECK-NEXT: [[TMP7:%.*]] = icmp ne <16 x i32> [[TMP1]], zeroinitializer7427; CHECK-NEXT: [[TMP8:%.*]] = sext <16 x i1> [[TMP7]] to <16 x i32>7428; CHECK-NEXT: [[TMP9:%.*]] = select <16 x i1> splat (i1 true), <16 x i32> [[TMP8]], <16 x i32> [[TMP2]]7429; CHECK-NEXT: [[RES1:%.*]] = call <16 x i32> @llvm.x86.avx512.mask.cvtps2dq.512(<16 x float> [[X0]], <16 x i32> [[X1]], i16 -1, i32 8)7430; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i32> [[TMP6]], [[TMP9]]7431; CHECK-NEXT: [[RES2:%.*]] = add <16 x i32> [[RES]], [[RES1]]7432; CHECK-NEXT: store <16 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 87433; CHECK-NEXT: ret <16 x i32> [[RES2]]7434;7435 %res = call <16 x i32> @llvm.x86.avx512.mask.cvtps2dq.512(<16 x float> %x0, <16 x i32> %x1, i16 %x2, i32 10)7436 %res1 = call <16 x i32> @llvm.x86.avx512.mask.cvtps2dq.512(<16 x float> %x0, <16 x i32> %x1, i16 -1, i32 8)7437 %res2 = add <16 x i32> %res, %res17438 ret <16 x i32> %res27439}7440 7441declare <8 x double> @llvm.x86.avx512.mask.cvtps2pd.512(<8 x float>, <8 x double>, i8, i32)7442 7443define <8 x double>@test_int_x86_avx512_mask_cvt_ps2pd_512(<8 x float> %x0, <8 x double> %x1, i8 %x2) #0 {7444; CHECK-LABEL: @test_int_x86_avx512_mask_cvt_ps2pd_512(7445; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 87446; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 87447; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 87448; CHECK-NEXT: call void @llvm.donothing()7449; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i32> [[TMP1]] to i2567450; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP4]], 07451; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i64> [[TMP2]] to i5127452; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP5]], 07453; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]7454; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 07455; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]7456; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]7457; CHECK: 6:7458; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]7459; CHECK-NEXT: unreachable7460; CHECK: 7:7461; CHECK-NEXT: [[RES:%.*]] = call <8 x double> @llvm.x86.avx512.mask.cvtps2pd.512(<8 x float> [[X0:%.*]], <8 x double> [[X1:%.*]], i8 [[X2:%.*]], i32 4)7462; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i32> [[TMP1]] to i2567463; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i256 [[TMP8]], 07464; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i64> [[TMP2]] to i5127465; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i512 [[TMP9]], 07466; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSCMP4]], [[_MSCMP5]]7467; CHECK-NEXT: br i1 [[_MSOR6]], label [[TMP10:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]7468; CHECK: 10:7469; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]7470; CHECK-NEXT: unreachable7471; CHECK: 11:7472; CHECK-NEXT: [[RES1:%.*]] = call <8 x double> @llvm.x86.avx512.mask.cvtps2pd.512(<8 x float> [[X0]], <8 x double> [[X1]], i8 -1, i32 8)7473; CHECK-NEXT: [[RES2:%.*]] = fadd <8 x double> [[RES]], [[RES1]]7474; CHECK-NEXT: store <8 x i64> zeroinitializer, ptr @__msan_retval_tls, align 87475; CHECK-NEXT: ret <8 x double> [[RES2]]7476;7477 %res = call <8 x double> @llvm.x86.avx512.mask.cvtps2pd.512(<8 x float> %x0, <8 x double> %x1, i8 %x2, i32 4)7478 %res1 = call <8 x double> @llvm.x86.avx512.mask.cvtps2pd.512(<8 x float> %x0, <8 x double> %x1, i8 -1, i32 8)7479 %res2 = fadd <8 x double> %res, %res17480 ret <8 x double> %res27481}7482 7483declare <16 x i32> @llvm.x86.avx512.mask.cvtps2udq.512(<16 x float>, <16 x i32>, i16, i32)7484 7485define <16 x i32>@test_int_x86_avx512_mask_cvt_ps2udq_512(<16 x float> %x0, <16 x i32> %x1, i16 %x2) #0 {7486; CHECK-LABEL: @test_int_x86_avx512_mask_cvt_ps2udq_512(7487; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 87488; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 87489; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 87490; CHECK-NEXT: call void @llvm.donothing()7491; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP1]] to i5127492; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP4]], 07493; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP2]] to i5127494; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP5]], 07495; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]7496; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i16 [[TMP3]], 07497; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]7498; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]7499; CHECK: 6:7500; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]7501; CHECK-NEXT: unreachable7502; CHECK: 7:7503; CHECK-NEXT: [[RES:%.*]] = call <16 x i32> @llvm.x86.avx512.mask.cvtps2udq.512(<16 x float> [[X0:%.*]], <16 x i32> [[X1:%.*]], i16 [[X2:%.*]], i32 10)7504; CHECK-NEXT: [[TMP8:%.*]] = bitcast <16 x i32> [[TMP1]] to i5127505; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i512 [[TMP8]], 07506; CHECK-NEXT: [[TMP9:%.*]] = bitcast <16 x i32> [[TMP2]] to i5127507; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i512 [[TMP9]], 07508; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSCMP4]], [[_MSCMP5]]7509; CHECK-NEXT: br i1 [[_MSOR6]], label [[TMP10:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]7510; CHECK: 10:7511; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]7512; CHECK-NEXT: unreachable7513; CHECK: 11:7514; CHECK-NEXT: [[RES1:%.*]] = call <16 x i32> @llvm.x86.avx512.mask.cvtps2udq.512(<16 x float> [[X0]], <16 x i32> [[X1]], i16 -1, i32 8)7515; CHECK-NEXT: [[RES2:%.*]] = add <16 x i32> [[RES]], [[RES1]]7516; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 87517; CHECK-NEXT: ret <16 x i32> [[RES2]]7518;7519 %res = call <16 x i32> @llvm.x86.avx512.mask.cvtps2udq.512(<16 x float> %x0, <16 x i32> %x1, i16 %x2, i32 10)7520 %res1 = call <16 x i32> @llvm.x86.avx512.mask.cvtps2udq.512(<16 x float> %x0, <16 x i32> %x1, i16 -1, i32 8)7521 %res2 = add <16 x i32> %res, %res17522 ret <16 x i32> %res27523}7524 7525declare <8 x i32> @llvm.x86.avx512.mask.cvttpd2dq.512(<8 x double>, <8 x i32>, i8, i32)7526 7527define <8 x i32>@test_int_x86_avx512_mask_cvtt_pd2dq_512(<8 x double> %x0, <8 x i32> %x1, i8 %x2) #0 {7528; CHECK-LABEL: @test_int_x86_avx512_mask_cvtt_pd2dq_512(7529; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 87530; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 87531; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 87532; CHECK-NEXT: call void @llvm.donothing()7533; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i64> [[TMP1]] to i5127534; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP4]], 07535; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i32> [[TMP2]] to i2567536; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP5]], 07537; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]7538; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 07539; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]7540; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]7541; CHECK: 6:7542; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]7543; CHECK-NEXT: unreachable7544; CHECK: 7:7545; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx512.mask.cvttpd2dq.512(<8 x double> [[X0:%.*]], <8 x i32> [[X1:%.*]], i8 [[X2:%.*]], i32 4)7546; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i64> [[TMP1]] to i5127547; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i512 [[TMP8]], 07548; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i32> [[TMP2]] to i2567549; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i256 [[TMP9]], 07550; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSCMP4]], [[_MSCMP5]]7551; CHECK-NEXT: br i1 [[_MSOR6]], label [[TMP10:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]7552; CHECK: 10:7553; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]7554; CHECK-NEXT: unreachable7555; CHECK: 11:7556; CHECK-NEXT: [[RES1:%.*]] = call <8 x i32> @llvm.x86.avx512.mask.cvttpd2dq.512(<8 x double> [[X0]], <8 x i32> [[X1]], i8 -1, i32 8)7557; CHECK-NEXT: [[RES2:%.*]] = add <8 x i32> [[RES]], [[RES1]]7558; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 87559; CHECK-NEXT: ret <8 x i32> [[RES2]]7560;7561 %res = call <8 x i32> @llvm.x86.avx512.mask.cvttpd2dq.512(<8 x double> %x0, <8 x i32> %x1, i8 %x2, i32 4)7562 %res1 = call <8 x i32> @llvm.x86.avx512.mask.cvttpd2dq.512(<8 x double> %x0, <8 x i32> %x1, i8 -1, i32 8)7563 %res2 = add <8 x i32> %res, %res17564 ret <8 x i32> %res27565}7566 7567declare <16 x float> @llvm.x86.avx512.uitofp.round.v16f32.v16i32(<16 x i32>, i32)7568 7569define <16 x float>@test_int_x86_avx512_mask_cvt_udq2ps_512(<16 x i32> %x0, <16 x float> %x1, i16 %x2) #0 {7570; CHECK-LABEL: @test_int_x86_avx512_mask_cvt_udq2ps_512(7571; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 87572; CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 87573; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 87574; CHECK-NEXT: call void @llvm.donothing()7575; CHECK-NEXT: [[CVT:%.*]] = uitofp <16 x i32> [[X0:%.*]] to <16 x float>7576; CHECK-NEXT: [[TMP4:%.*]] = bitcast i16 [[TMP2]] to <16 x i1>7577; CHECK-NEXT: [[TMP5:%.*]] = bitcast i16 [[X2:%.*]] to <16 x i1>7578; CHECK-NEXT: [[TMP6:%.*]] = select <16 x i1> [[TMP5]], <16 x i32> [[TMP1]], <16 x i32> [[TMP3]]7579; CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x float> [[CVT]] to <16 x i32>7580; CHECK-NEXT: [[TMP8:%.*]] = bitcast <16 x float> [[X1:%.*]] to <16 x i32>7581; CHECK-NEXT: [[TMP9:%.*]] = xor <16 x i32> [[TMP7]], [[TMP8]]7582; CHECK-NEXT: [[TMP10:%.*]] = or <16 x i32> [[TMP9]], [[TMP1]]7583; CHECK-NEXT: [[TMP11:%.*]] = or <16 x i32> [[TMP10]], [[TMP3]]7584; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP4]], <16 x i32> [[TMP11]], <16 x i32> [[TMP6]]7585; CHECK-NEXT: [[TMP12:%.*]] = select <16 x i1> [[TMP5]], <16 x float> [[CVT]], <16 x float> [[X1]]7586; CHECK-NEXT: [[TMP13:%.*]] = bitcast <16 x i32> [[TMP1]] to i5127587; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP13]], 07588; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP14:%.*]], label [[TMP15:%.*]], !prof [[PROF1]]7589; CHECK: 14:7590; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]7591; CHECK-NEXT: unreachable7592; CHECK: 15:7593; CHECK-NEXT: [[TMP16:%.*]] = call <16 x float> @llvm.x86.avx512.uitofp.round.v16f32.v16i32(<16 x i32> [[X0]], i32 8)7594; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i32> [[_MSPROP_SELECT]], zeroinitializer7595; CHECK-NEXT: [[RES2:%.*]] = fadd <16 x float> [[TMP12]], [[TMP16]]7596; CHECK-NEXT: store <16 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 87597; CHECK-NEXT: ret <16 x float> [[RES2]]7598;7599 %cvt = uitofp <16 x i32> %x0 to <16 x float>7600 %1 = bitcast i16 %x2 to <16 x i1>7601 %2 = select <16 x i1> %1, <16 x float> %cvt, <16 x float> %x17602 %3 = call <16 x float> @llvm.x86.avx512.uitofp.round.v16f32.v16i32(<16 x i32> %x0, i32 8)7603 %res2 = fadd <16 x float> %2, %37604 ret <16 x float> %res27605}7606 7607declare <8 x i32> @llvm.x86.avx512.mask.cvttpd2udq.512(<8 x double>, <8 x i32>, i8, i32)7608 7609define <8 x i32>@test_int_x86_avx512_mask_cvtt_pd2udq_512(<8 x double> %x0, <8 x i32> %x1, i8 %x2) #0 {7610; CHECK-LABEL: @test_int_x86_avx512_mask_cvtt_pd2udq_512(7611; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 87612; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 87613; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 87614; CHECK-NEXT: call void @llvm.donothing()7615; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i64> [[TMP1]] to i5127616; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP4]], 07617; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i32> [[TMP2]] to i2567618; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP5]], 07619; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]7620; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 07621; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]7622; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]7623; CHECK: 6:7624; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]7625; CHECK-NEXT: unreachable7626; CHECK: 7:7627; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx512.mask.cvttpd2udq.512(<8 x double> [[X0:%.*]], <8 x i32> [[X1:%.*]], i8 [[X2:%.*]], i32 4)7628; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i64> [[TMP1]] to i5127629; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i512 [[TMP8]], 07630; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i32> [[TMP2]] to i2567631; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i256 [[TMP9]], 07632; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSCMP4]], [[_MSCMP5]]7633; CHECK-NEXT: br i1 [[_MSOR6]], label [[TMP10:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]7634; CHECK: 10:7635; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]7636; CHECK-NEXT: unreachable7637; CHECK: 11:7638; CHECK-NEXT: [[RES1:%.*]] = call <8 x i32> @llvm.x86.avx512.mask.cvttpd2udq.512(<8 x double> [[X0]], <8 x i32> [[X1]], i8 -1, i32 8)7639; CHECK-NEXT: [[RES2:%.*]] = add <8 x i32> [[RES]], [[RES1]]7640; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 87641; CHECK-NEXT: ret <8 x i32> [[RES2]]7642;7643 %res = call <8 x i32> @llvm.x86.avx512.mask.cvttpd2udq.512(<8 x double> %x0, <8 x i32> %x1, i8 %x2, i32 4)7644 %res1 = call <8 x i32> @llvm.x86.avx512.mask.cvttpd2udq.512(<8 x double> %x0, <8 x i32> %x1, i8 -1, i32 8)7645 %res2 = add <8 x i32> %res, %res17646 ret <8 x i32> %res27647}7648 7649declare <16 x i32> @llvm.x86.avx512.mask.cvttps2dq.512(<16 x float>, <16 x i32>, i16, i32)7650 7651define <16 x i32>@test_int_x86_avx512_mask_cvtt_ps2dq_512(<16 x float> %x0, <16 x i32> %x1, i16 %x2) #0 {7652; CHECK-LABEL: @test_int_x86_avx512_mask_cvtt_ps2dq_512(7653; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 87654; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 87655; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 87656; CHECK-NEXT: call void @llvm.donothing()7657; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP1]] to i5127658; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP4]], 07659; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP2]] to i5127660; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP5]], 07661; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]7662; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i16 [[TMP3]], 07663; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]7664; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]7665; CHECK: 6:7666; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]7667; CHECK-NEXT: unreachable7668; CHECK: 7:7669; CHECK-NEXT: [[RES:%.*]] = call <16 x i32> @llvm.x86.avx512.mask.cvttps2dq.512(<16 x float> [[X0:%.*]], <16 x i32> [[X1:%.*]], i16 [[X2:%.*]], i32 4)7670; CHECK-NEXT: [[TMP8:%.*]] = bitcast <16 x i32> [[TMP1]] to i5127671; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i512 [[TMP8]], 07672; CHECK-NEXT: [[TMP9:%.*]] = bitcast <16 x i32> [[TMP2]] to i5127673; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i512 [[TMP9]], 07674; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSCMP4]], [[_MSCMP5]]7675; CHECK-NEXT: br i1 [[_MSOR6]], label [[TMP10:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]7676; CHECK: 10:7677; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]7678; CHECK-NEXT: unreachable7679; CHECK: 11:7680; CHECK-NEXT: [[RES1:%.*]] = call <16 x i32> @llvm.x86.avx512.mask.cvttps2dq.512(<16 x float> [[X0]], <16 x i32> [[X1]], i16 -1, i32 8)7681; CHECK-NEXT: [[RES2:%.*]] = add <16 x i32> [[RES]], [[RES1]]7682; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 87683; CHECK-NEXT: ret <16 x i32> [[RES2]]7684;7685 %res = call <16 x i32> @llvm.x86.avx512.mask.cvttps2dq.512(<16 x float> %x0, <16 x i32> %x1, i16 %x2, i32 4)7686 %res1 = call <16 x i32> @llvm.x86.avx512.mask.cvttps2dq.512(<16 x float> %x0, <16 x i32> %x1, i16 -1, i32 8)7687 %res2 = add <16 x i32> %res, %res17688 ret <16 x i32> %res27689}7690 7691declare <16 x i32> @llvm.x86.avx512.mask.cvttps2udq.512(<16 x float>, <16 x i32>, i16, i32)7692 7693define <16 x i32>@test_int_x86_avx512_mask_cvtt_ps2udq_512(<16 x float> %x0, <16 x i32> %x1, i16 %x2) #0 {7694; CHECK-LABEL: @test_int_x86_avx512_mask_cvtt_ps2udq_512(7695; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 87696; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 87697; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 87698; CHECK-NEXT: call void @llvm.donothing()7699; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP1]] to i5127700; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP4]], 07701; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP2]] to i5127702; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP5]], 07703; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]7704; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i16 [[TMP3]], 07705; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]7706; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]7707; CHECK: 6:7708; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]7709; CHECK-NEXT: unreachable7710; CHECK: 7:7711; CHECK-NEXT: [[RES:%.*]] = call <16 x i32> @llvm.x86.avx512.mask.cvttps2udq.512(<16 x float> [[X0:%.*]], <16 x i32> [[X1:%.*]], i16 [[X2:%.*]], i32 4)7712; CHECK-NEXT: [[TMP8:%.*]] = bitcast <16 x i32> [[TMP1]] to i5127713; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i512 [[TMP8]], 07714; CHECK-NEXT: [[TMP9:%.*]] = bitcast <16 x i32> [[TMP2]] to i5127715; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i512 [[TMP9]], 07716; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSCMP4]], [[_MSCMP5]]7717; CHECK-NEXT: br i1 [[_MSOR6]], label [[TMP10:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]7718; CHECK: 10:7719; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]7720; CHECK-NEXT: unreachable7721; CHECK: 11:7722; CHECK-NEXT: [[RES1:%.*]] = call <16 x i32> @llvm.x86.avx512.mask.cvttps2udq.512(<16 x float> [[X0]], <16 x i32> [[X1]], i16 -1, i32 8)7723; CHECK-NEXT: [[RES2:%.*]] = add <16 x i32> [[RES]], [[RES1]]7724; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 87725; CHECK-NEXT: ret <16 x i32> [[RES2]]7726;7727 %res = call <16 x i32> @llvm.x86.avx512.mask.cvttps2udq.512(<16 x float> %x0, <16 x i32> %x1, i16 %x2, i32 4)7728 %res1 = call <16 x i32> @llvm.x86.avx512.mask.cvttps2udq.512(<16 x float> %x0, <16 x i32> %x1, i16 -1, i32 8)7729 %res2 = add <16 x i32> %res, %res17730 ret <16 x i32> %res27731}7732 7733declare <4 x float> @llvm.x86.avx512.mask.getexp.ss(<4 x float>, <4 x float>, <4 x float>, i8, i32) nounwind readnone7734 7735define <4 x float> @test_getexp_ss(<4 x float> %a0, <4 x float> %a1) #0 {7736; CHECK-LABEL: @test_getexp_ss(7737; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 87738; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 87739; CHECK-NEXT: call void @llvm.donothing()7740; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP1]] to i1287741; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 07742; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i1287743; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 07744; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]7745; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]7746; CHECK: 5:7747; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]7748; CHECK-NEXT: unreachable7749; CHECK: 6:7750; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.mask.getexp.ss(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], <4 x float> zeroinitializer, i8 -1, i32 8)7751; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 87752; CHECK-NEXT: ret <4 x float> [[RES]]7753;7754 %res = call <4 x float> @llvm.x86.avx512.mask.getexp.ss(<4 x float>%a0, <4 x float> %a1, <4 x float> zeroinitializer, i8 -1, i32 8)7755 ret <4 x float> %res7756}7757 7758define <4 x float> @test_mask_getexp_ss(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) #0 {7759; CHECK-LABEL: @test_mask_getexp_ss(7760; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 87761; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 87762; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 87763; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 87764; CHECK-NEXT: call void @llvm.donothing()7765; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP1]] to i1287766; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 07767; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i32> [[TMP2]] to i1287768; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP6]], 07769; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]7770; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i32> [[TMP3]] to i1287771; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 07772; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]7773; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 07774; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]7775; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]7776; CHECK: 8:7777; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]7778; CHECK-NEXT: unreachable7779; CHECK: 9:7780; CHECK-NEXT: [[RES0:%.*]] = call <4 x float> @llvm.x86.avx512.mask.getexp.ss(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], <4 x float> [[A2:%.*]], i8 [[MASK:%.*]], i32 4)7781; CHECK-NEXT: [[TMP10:%.*]] = bitcast <4 x i32> [[TMP1]] to i1287782; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i128 [[TMP10]], 07783; CHECK-NEXT: [[TMP11:%.*]] = bitcast <4 x i32> [[TMP2]] to i1287784; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i128 [[TMP11]], 07785; CHECK-NEXT: [[_MSOR8:%.*]] = or i1 [[_MSCMP6]], [[_MSCMP7]]7786; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i32> [[TMP3]] to i1287787; CHECK-NEXT: [[_MSCMP9:%.*]] = icmp ne i128 [[TMP12]], 07788; CHECK-NEXT: [[_MSOR10:%.*]] = or i1 [[_MSOR8]], [[_MSCMP9]]7789; CHECK-NEXT: [[_MSCMP11:%.*]] = icmp ne i8 [[TMP4]], 07790; CHECK-NEXT: [[_MSOR12:%.*]] = or i1 [[_MSOR10]], [[_MSCMP11]]7791; CHECK-NEXT: br i1 [[_MSOR12]], label [[TMP13:%.*]], label [[TMP14:%.*]], !prof [[PROF1]]7792; CHECK: 13:7793; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]7794; CHECK-NEXT: unreachable7795; CHECK: 14:7796; CHECK-NEXT: [[RES1:%.*]] = call <4 x float> @llvm.x86.avx512.mask.getexp.ss(<4 x float> [[A0]], <4 x float> [[A1]], <4 x float> [[A2]], i8 [[MASK]], i32 8)7797; CHECK-NEXT: [[RES_1:%.*]] = fadd <4 x float> [[RES0]], [[RES1]]7798; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 87799; CHECK-NEXT: ret <4 x float> [[RES_1]]7800;7801 %res0 = call <4 x float> @llvm.x86.avx512.mask.getexp.ss(<4 x float>%a0, <4 x float> %a1, <4 x float> %a2, i8 %mask, i32 4)7802 %res1 = call <4 x float> @llvm.x86.avx512.mask.getexp.ss(<4 x float>%a0, <4 x float> %a1, <4 x float> %a2, i8 %mask, i32 8)7803 %res.1 = fadd <4 x float> %res0, %res17804 ret <4 x float> %res.17805}7806 7807define <4 x float> @test_maskz_getexp_ss(<4 x float> %a0, <4 x float> %a1, i8 %mask) #0 {7808; CHECK-LABEL: @test_maskz_getexp_ss(7809; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 87810; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 87811; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 87812; CHECK-NEXT: call void @llvm.donothing()7813; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP1]] to i1287814; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 07815; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP2]] to i1287816; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 07817; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]7818; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 07819; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]7820; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]7821; CHECK: 6:7822; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]7823; CHECK-NEXT: unreachable7824; CHECK: 7:7825; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.mask.getexp.ss(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], <4 x float> zeroinitializer, i8 [[MASK:%.*]], i32 8)7826; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 87827; CHECK-NEXT: ret <4 x float> [[RES]]7828;7829 %res = call <4 x float> @llvm.x86.avx512.mask.getexp.ss(<4 x float>%a0, <4 x float> %a1, <4 x float> zeroinitializer, i8 %mask, i32 8)7830 ret <4 x float> %res7831}7832 7833declare <2 x double> @llvm.x86.avx512.mask.getexp.sd(<2 x double>, <2 x double>, <2 x double>, i8, i32) nounwind readnone7834 7835define <2 x double> @test_getexp_sd(<2 x double> %a0, <2 x double> %a1) #0 {7836; CHECK-LABEL: @test_getexp_sd(7837; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 87838; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 87839; CHECK-NEXT: call void @llvm.donothing()7840; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP1]] to i1287841; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 07842; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP2]] to i1287843; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 07844; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]7845; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]7846; CHECK: 5:7847; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]7848; CHECK-NEXT: unreachable7849; CHECK: 6:7850; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx512.mask.getexp.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]], <2 x double> zeroinitializer, i8 -1, i32 4)7851; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 87852; CHECK-NEXT: ret <2 x double> [[RES]]7853;7854 %res = call <2 x double> @llvm.x86.avx512.mask.getexp.sd(<2 x double>%a0, <2 x double> %a1, <2 x double> zeroinitializer, i8 -1, i32 4)7855 ret <2 x double> %res7856}7857 7858define <2 x double> @test_mask_getexp_sd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) #0 {7859; CHECK-LABEL: @test_mask_getexp_sd(7860; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 87861; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 87862; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 87863; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 87864; CHECK-NEXT: call void @llvm.donothing()7865; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP1]] to i1287866; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 07867; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i64> [[TMP2]] to i1287868; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP6]], 07869; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]7870; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i64> [[TMP3]] to i1287871; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 07872; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]7873; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 07874; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]7875; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]7876; CHECK: 8:7877; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]7878; CHECK-NEXT: unreachable7879; CHECK: 9:7880; CHECK-NEXT: [[RES0:%.*]] = call <2 x double> @llvm.x86.avx512.mask.getexp.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]], <2 x double> [[A2:%.*]], i8 [[MASK:%.*]], i32 4)7881; CHECK-NEXT: [[TMP10:%.*]] = bitcast <2 x i64> [[TMP1]] to i1287882; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i128 [[TMP10]], 07883; CHECK-NEXT: [[TMP11:%.*]] = bitcast <2 x i64> [[TMP2]] to i1287884; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i128 [[TMP11]], 07885; CHECK-NEXT: [[_MSOR8:%.*]] = or i1 [[_MSCMP6]], [[_MSCMP7]]7886; CHECK-NEXT: [[TMP12:%.*]] = bitcast <2 x i64> [[TMP3]] to i1287887; CHECK-NEXT: [[_MSCMP9:%.*]] = icmp ne i128 [[TMP12]], 07888; CHECK-NEXT: [[_MSOR10:%.*]] = or i1 [[_MSOR8]], [[_MSCMP9]]7889; CHECK-NEXT: [[_MSCMP11:%.*]] = icmp ne i8 [[TMP4]], 07890; CHECK-NEXT: [[_MSOR12:%.*]] = or i1 [[_MSOR10]], [[_MSCMP11]]7891; CHECK-NEXT: br i1 [[_MSOR12]], label [[TMP13:%.*]], label [[TMP14:%.*]], !prof [[PROF1]]7892; CHECK: 13:7893; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]7894; CHECK-NEXT: unreachable7895; CHECK: 14:7896; CHECK-NEXT: [[RES1:%.*]] = call <2 x double> @llvm.x86.avx512.mask.getexp.sd(<2 x double> [[A0]], <2 x double> [[A1]], <2 x double> [[A2]], i8 [[MASK]], i32 8)7897; CHECK-NEXT: [[RES_1:%.*]] = fadd <2 x double> [[RES0]], [[RES1]]7898; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 87899; CHECK-NEXT: ret <2 x double> [[RES_1]]7900;7901 %res0 = call <2 x double> @llvm.x86.avx512.mask.getexp.sd(<2 x double>%a0, <2 x double> %a1, <2 x double> %a2, i8 %mask, i32 4)7902 %res1 = call <2 x double> @llvm.x86.avx512.mask.getexp.sd(<2 x double>%a0, <2 x double> %a1, <2 x double> %a2, i8 %mask, i32 8)7903 %res.1 = fadd <2 x double> %res0, %res17904 ret <2 x double> %res.17905}7906 7907define <2 x double> @test_maskz_getexp_sd(<2 x double> %a0, <2 x double> %a1, i8 %mask) #0 {7908; CHECK-LABEL: @test_maskz_getexp_sd(7909; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 87910; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 87911; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 87912; CHECK-NEXT: call void @llvm.donothing()7913; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP1]] to i1287914; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 07915; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP2]] to i1287916; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 07917; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]7918; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 07919; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]7920; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]7921; CHECK: 6:7922; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]7923; CHECK-NEXT: unreachable7924; CHECK: 7:7925; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx512.mask.getexp.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]], <2 x double> zeroinitializer, i8 [[MASK:%.*]], i32 8)7926; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 87927; CHECK-NEXT: ret <2 x double> [[RES]]7928;7929 %res = call <2 x double> @llvm.x86.avx512.mask.getexp.sd(<2 x double>%a0, <2 x double> %a1, <2 x double> zeroinitializer, i8 %mask, i32 8)7930 ret <2 x double> %res7931}7932 7933declare i8 @llvm.x86.avx512.mask.cmp.sd(<2 x double>, <2 x double>, i32, i8, i32)7934 7935define i8@test_int_x86_avx512_mask_cmp_sd(<2 x double> %x0, <2 x double> %x1, i8 %x3, i32 %x4) #0 {7936; CHECK-LABEL: @test_int_x86_avx512_mask_cmp_sd(7937; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 87938; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 87939; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 87940; CHECK-NEXT: call void @llvm.donothing()7941; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP1]] to i1287942; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 07943; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP2]] to i1287944; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 07945; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]7946; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 07947; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]7948; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]7949; CHECK: 6:7950; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]7951; CHECK-NEXT: unreachable7952; CHECK: 7:7953; CHECK-NEXT: [[RES4:%.*]] = call i8 @llvm.x86.avx512.mask.cmp.sd(<2 x double> [[X0:%.*]], <2 x double> [[X1:%.*]], i32 5, i8 [[X3:%.*]], i32 8)7954; CHECK-NEXT: store i8 0, ptr @__msan_retval_tls, align 87955; CHECK-NEXT: ret i8 [[RES4]]7956;7957 %res4 = call i8 @llvm.x86.avx512.mask.cmp.sd(<2 x double> %x0, <2 x double> %x1, i32 5, i8 %x3, i32 8)7958 ret i8 %res47959}7960 7961define i8@test_int_x86_avx512_mask_cmp_sd_all(<2 x double> %x0, <2 x double> %x1, i8 %x3, i32 %x4) #0 {7962; CHECK-LABEL: @test_int_x86_avx512_mask_cmp_sd_all(7963; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 87964; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 87965; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 87966; CHECK-NEXT: call void @llvm.donothing()7967; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP1]] to i1287968; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 07969; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP2]] to i1287970; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 07971; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]7972; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]7973; CHECK: 6:7974; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]7975; CHECK-NEXT: unreachable7976; CHECK: 7:7977; CHECK-NEXT: [[RES1:%.*]] = call i8 @llvm.x86.avx512.mask.cmp.sd(<2 x double> [[X0:%.*]], <2 x double> [[X1:%.*]], i32 2, i8 -1, i32 4)7978; CHECK-NEXT: [[TMP8:%.*]] = bitcast <2 x i64> [[TMP1]] to i1287979; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP8]], 07980; CHECK-NEXT: [[TMP9:%.*]] = bitcast <2 x i64> [[TMP2]] to i1287981; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP9]], 07982; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]7983; CHECK-NEXT: br i1 [[_MSOR4]], label [[TMP10:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]7984; CHECK: 10:7985; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]7986; CHECK-NEXT: unreachable7987; CHECK: 11:7988; CHECK-NEXT: [[RES2:%.*]] = call i8 @llvm.x86.avx512.mask.cmp.sd(<2 x double> [[X0]], <2 x double> [[X1]], i32 3, i8 -1, i32 8)7989; CHECK-NEXT: [[TMP12:%.*]] = bitcast <2 x i64> [[TMP1]] to i1287990; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i128 [[TMP12]], 07991; CHECK-NEXT: [[TMP13:%.*]] = bitcast <2 x i64> [[TMP2]] to i1287992; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i128 [[TMP13]], 07993; CHECK-NEXT: [[_MSOR7:%.*]] = or i1 [[_MSCMP5]], [[_MSCMP6]]7994; CHECK-NEXT: [[_MSCMP8:%.*]] = icmp ne i8 [[TMP3]], 07995; CHECK-NEXT: [[_MSOR9:%.*]] = or i1 [[_MSOR7]], [[_MSCMP8]]7996; CHECK-NEXT: br i1 [[_MSOR9]], label [[TMP14:%.*]], label [[TMP15:%.*]], !prof [[PROF1]]7997; CHECK: 14:7998; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]7999; CHECK-NEXT: unreachable8000; CHECK: 15:8001; CHECK-NEXT: [[RES3:%.*]] = call i8 @llvm.x86.avx512.mask.cmp.sd(<2 x double> [[X0]], <2 x double> [[X1]], i32 4, i8 [[X3:%.*]], i32 4)8002; CHECK-NEXT: [[TMP16:%.*]] = bitcast <2 x i64> [[TMP1]] to i1288003; CHECK-NEXT: [[_MSCMP10:%.*]] = icmp ne i128 [[TMP16]], 08004; CHECK-NEXT: [[TMP17:%.*]] = bitcast <2 x i64> [[TMP2]] to i1288005; CHECK-NEXT: [[_MSCMP11:%.*]] = icmp ne i128 [[TMP17]], 08006; CHECK-NEXT: [[_MSOR12:%.*]] = or i1 [[_MSCMP10]], [[_MSCMP11]]8007; CHECK-NEXT: [[_MSCMP13:%.*]] = icmp ne i8 [[TMP3]], 08008; CHECK-NEXT: [[_MSOR14:%.*]] = or i1 [[_MSOR12]], [[_MSCMP13]]8009; CHECK-NEXT: br i1 [[_MSOR14]], label [[TMP18:%.*]], label [[TMP19:%.*]], !prof [[PROF1]]8010; CHECK: 18:8011; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]8012; CHECK-NEXT: unreachable8013; CHECK: 19:8014; CHECK-NEXT: [[RES4:%.*]] = call i8 @llvm.x86.avx512.mask.cmp.sd(<2 x double> [[X0]], <2 x double> [[X1]], i32 5, i8 [[X3]], i32 8)8015; CHECK-NEXT: [[TMP20:%.*]] = xor i8 [[RES1]], -18016; CHECK-NEXT: [[TMP21:%.*]] = xor i8 [[RES2]], -18017; CHECK-NEXT: [[TMP22:%.*]] = and i8 [[TMP20]], 08018; CHECK-NEXT: [[TMP23:%.*]] = and i8 0, [[TMP21]]8019; CHECK-NEXT: [[TMP24:%.*]] = or i8 0, [[TMP22]]8020; CHECK-NEXT: [[TMP25:%.*]] = or i8 [[TMP24]], [[TMP23]]8021; CHECK-NEXT: [[RES11:%.*]] = or i8 [[RES1]], [[RES2]]8022; CHECK-NEXT: [[TMP26:%.*]] = xor i8 [[RES3]], -18023; CHECK-NEXT: [[TMP27:%.*]] = xor i8 [[RES4]], -18024; CHECK-NEXT: [[TMP28:%.*]] = and i8 [[TMP26]], 08025; CHECK-NEXT: [[TMP29:%.*]] = and i8 0, [[TMP27]]8026; CHECK-NEXT: [[TMP30:%.*]] = or i8 0, [[TMP28]]8027; CHECK-NEXT: [[TMP31:%.*]] = or i8 [[TMP30]], [[TMP29]]8028; CHECK-NEXT: [[RES12:%.*]] = or i8 [[RES3]], [[RES4]]8029; CHECK-NEXT: [[TMP32:%.*]] = xor i8 [[RES11]], -18030; CHECK-NEXT: [[TMP33:%.*]] = xor i8 [[RES12]], -18031; CHECK-NEXT: [[TMP34:%.*]] = and i8 [[TMP25]], [[TMP31]]8032; CHECK-NEXT: [[TMP35:%.*]] = and i8 [[TMP32]], [[TMP31]]8033; CHECK-NEXT: [[TMP36:%.*]] = and i8 [[TMP25]], [[TMP33]]8034; CHECK-NEXT: [[TMP37:%.*]] = or i8 [[TMP34]], [[TMP35]]8035; CHECK-NEXT: [[TMP38:%.*]] = or i8 [[TMP37]], [[TMP36]]8036; CHECK-NEXT: [[RES13:%.*]] = or i8 [[RES11]], [[RES12]]8037; CHECK-NEXT: store i8 [[TMP38]], ptr @__msan_retval_tls, align 88038; CHECK-NEXT: ret i8 [[RES13]]8039;8040 %res1 = call i8 @llvm.x86.avx512.mask.cmp.sd(<2 x double> %x0, <2 x double> %x1, i32 2, i8 -1, i32 4)8041 %res2 = call i8 @llvm.x86.avx512.mask.cmp.sd(<2 x double> %x0, <2 x double> %x1, i32 3, i8 -1, i32 8)8042 %res3 = call i8 @llvm.x86.avx512.mask.cmp.sd(<2 x double> %x0, <2 x double> %x1, i32 4, i8 %x3, i32 4)8043 %res4 = call i8 @llvm.x86.avx512.mask.cmp.sd(<2 x double> %x0, <2 x double> %x1, i32 5, i8 %x3, i32 8)8044 8045 %res11 = or i8 %res1, %res28046 %res12 = or i8 %res3, %res48047 %res13 = or i8 %res11, %res128048 ret i8 %res138049}8050 8051declare i8 @llvm.x86.avx512.mask.cmp.ss(<4 x float>, <4 x float>, i32, i8, i32)8052 8053define i8@test_int_x86_avx512_mask_cmp_ss(<4 x float> %x0, <4 x float> %x1, i8 %x3, i32 %x4) #0 {8054; CHECK-LABEL: @test_int_x86_avx512_mask_cmp_ss(8055; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 88056; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 88057; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 88058; CHECK-NEXT: call void @llvm.donothing()8059; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP1]] to i1288060; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 08061; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP2]] to i1288062; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 08063; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]8064; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 08065; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]8066; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]8067; CHECK: 6:8068; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]8069; CHECK-NEXT: unreachable8070; CHECK: 7:8071; CHECK-NEXT: [[RES2:%.*]] = call i8 @llvm.x86.avx512.mask.cmp.ss(<4 x float> [[X0:%.*]], <4 x float> [[X1:%.*]], i32 3, i8 [[X3:%.*]], i32 4)8072; CHECK-NEXT: store i8 0, ptr @__msan_retval_tls, align 88073; CHECK-NEXT: ret i8 [[RES2]]8074;8075 %res2 = call i8 @llvm.x86.avx512.mask.cmp.ss(<4 x float> %x0, <4 x float> %x1, i32 3, i8 %x3, i32 4)8076 ret i8 %res28077}8078 8079 8080define i8@test_int_x86_avx512_mask_cmp_ss_all(<4 x float> %x0, <4 x float> %x1, i8 %x3, i32 %x4) #0 {8081; CHECK-LABEL: @test_int_x86_avx512_mask_cmp_ss_all(8082; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 88083; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 88084; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 88085; CHECK-NEXT: call void @llvm.donothing()8086; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP1]] to i1288087; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 08088; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP2]] to i1288089; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 08090; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]8091; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]8092; CHECK: 6:8093; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]8094; CHECK-NEXT: unreachable8095; CHECK: 7:8096; CHECK-NEXT: [[RES1:%.*]] = call i8 @llvm.x86.avx512.mask.cmp.ss(<4 x float> [[X0:%.*]], <4 x float> [[X1:%.*]], i32 2, i8 -1, i32 4)8097; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x i32> [[TMP1]] to i1288098; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP8]], 08099; CHECK-NEXT: [[TMP9:%.*]] = bitcast <4 x i32> [[TMP2]] to i1288100; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP9]], 08101; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]8102; CHECK-NEXT: br i1 [[_MSOR4]], label [[TMP10:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]8103; CHECK: 10:8104; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]8105; CHECK-NEXT: unreachable8106; CHECK: 11:8107; CHECK-NEXT: [[RES2:%.*]] = call i8 @llvm.x86.avx512.mask.cmp.ss(<4 x float> [[X0]], <4 x float> [[X1]], i32 3, i8 -1, i32 8)8108; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i32> [[TMP1]] to i1288109; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i128 [[TMP12]], 08110; CHECK-NEXT: [[TMP13:%.*]] = bitcast <4 x i32> [[TMP2]] to i1288111; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i128 [[TMP13]], 08112; CHECK-NEXT: [[_MSOR7:%.*]] = or i1 [[_MSCMP5]], [[_MSCMP6]]8113; CHECK-NEXT: [[_MSCMP8:%.*]] = icmp ne i8 [[TMP3]], 08114; CHECK-NEXT: [[_MSOR9:%.*]] = or i1 [[_MSOR7]], [[_MSCMP8]]8115; CHECK-NEXT: br i1 [[_MSOR9]], label [[TMP14:%.*]], label [[TMP15:%.*]], !prof [[PROF1]]8116; CHECK: 14:8117; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]8118; CHECK-NEXT: unreachable8119; CHECK: 15:8120; CHECK-NEXT: [[RES3:%.*]] = call i8 @llvm.x86.avx512.mask.cmp.ss(<4 x float> [[X0]], <4 x float> [[X1]], i32 4, i8 [[X3:%.*]], i32 4)8121; CHECK-NEXT: [[TMP16:%.*]] = bitcast <4 x i32> [[TMP1]] to i1288122; CHECK-NEXT: [[_MSCMP10:%.*]] = icmp ne i128 [[TMP16]], 08123; CHECK-NEXT: [[TMP17:%.*]] = bitcast <4 x i32> [[TMP2]] to i1288124; CHECK-NEXT: [[_MSCMP11:%.*]] = icmp ne i128 [[TMP17]], 08125; CHECK-NEXT: [[_MSOR12:%.*]] = or i1 [[_MSCMP10]], [[_MSCMP11]]8126; CHECK-NEXT: [[_MSCMP13:%.*]] = icmp ne i8 [[TMP3]], 08127; CHECK-NEXT: [[_MSOR14:%.*]] = or i1 [[_MSOR12]], [[_MSCMP13]]8128; CHECK-NEXT: br i1 [[_MSOR14]], label [[TMP18:%.*]], label [[TMP19:%.*]], !prof [[PROF1]]8129; CHECK: 18:8130; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]8131; CHECK-NEXT: unreachable8132; CHECK: 19:8133; CHECK-NEXT: [[RES4:%.*]] = call i8 @llvm.x86.avx512.mask.cmp.ss(<4 x float> [[X0]], <4 x float> [[X1]], i32 5, i8 [[X3]], i32 8)8134; CHECK-NEXT: [[TMP20:%.*]] = and i8 [[RES1]], 08135; CHECK-NEXT: [[TMP21:%.*]] = and i8 0, [[RES2]]8136; CHECK-NEXT: [[TMP22:%.*]] = or i8 0, [[TMP20]]8137; CHECK-NEXT: [[TMP23:%.*]] = or i8 [[TMP22]], [[TMP21]]8138; CHECK-NEXT: [[RES11:%.*]] = and i8 [[RES1]], [[RES2]]8139; CHECK-NEXT: [[TMP24:%.*]] = and i8 [[RES3]], 08140; CHECK-NEXT: [[TMP25:%.*]] = and i8 0, [[RES4]]8141; CHECK-NEXT: [[TMP26:%.*]] = or i8 0, [[TMP24]]8142; CHECK-NEXT: [[TMP27:%.*]] = or i8 [[TMP26]], [[TMP25]]8143; CHECK-NEXT: [[RES12:%.*]] = and i8 [[RES3]], [[RES4]]8144; CHECK-NEXT: [[TMP28:%.*]] = and i8 [[TMP23]], [[TMP27]]8145; CHECK-NEXT: [[TMP29:%.*]] = and i8 [[RES11]], [[TMP27]]8146; CHECK-NEXT: [[TMP30:%.*]] = and i8 [[TMP23]], [[RES12]]8147; CHECK-NEXT: [[TMP31:%.*]] = or i8 [[TMP28]], [[TMP29]]8148; CHECK-NEXT: [[TMP32:%.*]] = or i8 [[TMP31]], [[TMP30]]8149; CHECK-NEXT: [[RES13:%.*]] = and i8 [[RES11]], [[RES12]]8150; CHECK-NEXT: store i8 [[TMP32]], ptr @__msan_retval_tls, align 88151; CHECK-NEXT: ret i8 [[RES13]]8152;8153 %res1 = call i8 @llvm.x86.avx512.mask.cmp.ss(<4 x float> %x0, <4 x float> %x1, i32 2, i8 -1, i32 4)8154 %res2 = call i8 @llvm.x86.avx512.mask.cmp.ss(<4 x float> %x0, <4 x float> %x1, i32 3, i8 -1, i32 8)8155 %res3 = call i8 @llvm.x86.avx512.mask.cmp.ss(<4 x float> %x0, <4 x float> %x1, i32 4, i8 %x3, i32 4)8156 %res4 = call i8 @llvm.x86.avx512.mask.cmp.ss(<4 x float> %x0, <4 x float> %x1, i32 5, i8 %x3, i32 8)8157 8158 %res11 = and i8 %res1, %res28159 %res12 = and i8 %res3, %res48160 %res13 = and i8 %res11, %res128161 ret i8 %res138162}8163 8164declare <8 x double> @llvm.x86.avx512.mask.getmant.pd.512(<8 x double>, i32, <8 x double>, i8, i32)8165 8166define <8 x double>@test_int_x86_avx512_mask_getmant_pd_512(<8 x double> %x0, <8 x double> %x2, i8 %x3) #0 {8167; CHECK-LABEL: @test_int_x86_avx512_mask_getmant_pd_512(8168; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 88169; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 88170; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 88171; CHECK-NEXT: call void @llvm.donothing()8172; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i64> [[TMP1]] to i5128173; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP4]], 08174; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i64> [[TMP2]] to i5128175; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP5]], 08176; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]8177; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 08178; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]8179; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]8180; CHECK: 6:8181; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]8182; CHECK-NEXT: unreachable8183; CHECK: 7:8184; CHECK-NEXT: [[RES:%.*]] = call <8 x double> @llvm.x86.avx512.mask.getmant.pd.512(<8 x double> [[X0:%.*]], i32 11, <8 x double> [[X2:%.*]], i8 [[X3:%.*]], i32 4)8185; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i64> [[TMP1]] to i5128186; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i512 [[TMP8]], 08187; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i64> [[TMP2]] to i5128188; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i512 [[TMP9]], 08189; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSCMP4]], [[_MSCMP5]]8190; CHECK-NEXT: br i1 [[_MSOR6]], label [[TMP10:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]8191; CHECK: 10:8192; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]8193; CHECK-NEXT: unreachable8194; CHECK: 11:8195; CHECK-NEXT: [[RES1:%.*]] = call <8 x double> @llvm.x86.avx512.mask.getmant.pd.512(<8 x double> [[X0]], i32 11, <8 x double> [[X2]], i8 -1, i32 8)8196; CHECK-NEXT: [[RES2:%.*]] = fadd <8 x double> [[RES]], [[RES1]]8197; CHECK-NEXT: store <8 x i64> zeroinitializer, ptr @__msan_retval_tls, align 88198; CHECK-NEXT: ret <8 x double> [[RES2]]8199;8200 %res = call <8 x double> @llvm.x86.avx512.mask.getmant.pd.512(<8 x double> %x0, i32 11, <8 x double> %x2, i8 %x3, i32 4)8201 %res1 = call <8 x double> @llvm.x86.avx512.mask.getmant.pd.512(<8 x double> %x0, i32 11, <8 x double> %x2, i8 -1, i32 8)8202 %res2 = fadd <8 x double> %res, %res18203 ret <8 x double> %res28204}8205 8206declare <16 x float> @llvm.x86.avx512.mask.getmant.ps.512(<16 x float>, i32, <16 x float>, i16, i32)8207 8208define <16 x float>@test_int_x86_avx512_mask_getmant_ps_512(<16 x float> %x0, <16 x float> %x2, i16 %x3) #0 {8209; CHECK-LABEL: @test_int_x86_avx512_mask_getmant_ps_512(8210; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 88211; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 88212; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 88213; CHECK-NEXT: call void @llvm.donothing()8214; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP1]] to i5128215; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP4]], 08216; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP2]] to i5128217; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP5]], 08218; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]8219; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i16 [[TMP3]], 08220; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]8221; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]8222; CHECK: 6:8223; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]8224; CHECK-NEXT: unreachable8225; CHECK: 7:8226; CHECK-NEXT: [[RES:%.*]] = call <16 x float> @llvm.x86.avx512.mask.getmant.ps.512(<16 x float> [[X0:%.*]], i32 11, <16 x float> [[X2:%.*]], i16 [[X3:%.*]], i32 4)8227; CHECK-NEXT: [[TMP8:%.*]] = bitcast <16 x i32> [[TMP1]] to i5128228; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i512 [[TMP8]], 08229; CHECK-NEXT: [[TMP9:%.*]] = bitcast <16 x i32> [[TMP2]] to i5128230; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i512 [[TMP9]], 08231; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSCMP4]], [[_MSCMP5]]8232; CHECK-NEXT: br i1 [[_MSOR6]], label [[TMP10:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]8233; CHECK: 10:8234; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]8235; CHECK-NEXT: unreachable8236; CHECK: 11:8237; CHECK-NEXT: [[RES1:%.*]] = call <16 x float> @llvm.x86.avx512.mask.getmant.ps.512(<16 x float> [[X0]], i32 11, <16 x float> [[X2]], i16 -1, i32 8)8238; CHECK-NEXT: [[RES2:%.*]] = fadd <16 x float> [[RES]], [[RES1]]8239; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 88240; CHECK-NEXT: ret <16 x float> [[RES2]]8241;8242 %res = call <16 x float> @llvm.x86.avx512.mask.getmant.ps.512(<16 x float> %x0, i32 11, <16 x float> %x2, i16 %x3, i32 4)8243 %res1 = call <16 x float> @llvm.x86.avx512.mask.getmant.ps.512(<16 x float> %x0, i32 11, <16 x float> %x2, i16 -1, i32 8)8244 %res2 = fadd <16 x float> %res, %res18245 ret <16 x float> %res28246}8247 8248declare <2 x double> @llvm.x86.avx512.mask.getmant.sd(<2 x double>, <2 x double>, i32, <2 x double>, i8, i32)8249 8250define <2 x double>@test_int_x86_avx512_mask_getmant_sd(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) #0 {8251; CHECK-LABEL: @test_int_x86_avx512_mask_getmant_sd(8252; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 88253; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 88254; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 88255; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 88256; CHECK-NEXT: call void @llvm.donothing()8257; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP1]] to i1288258; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 08259; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i64> [[TMP2]] to i1288260; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP6]], 08261; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]8262; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i64> [[TMP3]] to i1288263; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 08264; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]8265; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 08266; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]8267; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]8268; CHECK: 8:8269; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]8270; CHECK-NEXT: unreachable8271; CHECK: 9:8272; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx512.mask.getmant.sd(<2 x double> [[X0:%.*]], <2 x double> [[X1:%.*]], i32 11, <2 x double> [[X2:%.*]], i8 [[X3:%.*]], i32 4)8273; CHECK-NEXT: [[TMP10:%.*]] = bitcast <2 x i64> [[TMP1]] to i1288274; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i128 [[TMP10]], 08275; CHECK-NEXT: [[TMP11:%.*]] = bitcast <2 x i64> [[TMP2]] to i1288276; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i128 [[TMP11]], 08277; CHECK-NEXT: [[_MSOR8:%.*]] = or i1 [[_MSCMP6]], [[_MSCMP7]]8278; CHECK-NEXT: [[_MSCMP9:%.*]] = icmp ne i8 [[TMP4]], 08279; CHECK-NEXT: [[_MSOR10:%.*]] = or i1 [[_MSOR8]], [[_MSCMP9]]8280; CHECK-NEXT: br i1 [[_MSOR10]], label [[TMP12:%.*]], label [[TMP13:%.*]], !prof [[PROF1]]8281; CHECK: 12:8282; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]8283; CHECK-NEXT: unreachable8284; CHECK: 13:8285; CHECK-NEXT: [[RES1:%.*]] = call <2 x double> @llvm.x86.avx512.mask.getmant.sd(<2 x double> [[X0]], <2 x double> [[X1]], i32 12, <2 x double> zeroinitializer, i8 [[X3]], i32 4)8286; CHECK-NEXT: [[TMP14:%.*]] = bitcast <2 x i64> [[TMP1]] to i1288287; CHECK-NEXT: [[_MSCMP11:%.*]] = icmp ne i128 [[TMP14]], 08288; CHECK-NEXT: [[TMP15:%.*]] = bitcast <2 x i64> [[TMP2]] to i1288289; CHECK-NEXT: [[_MSCMP12:%.*]] = icmp ne i128 [[TMP15]], 08290; CHECK-NEXT: [[_MSOR13:%.*]] = or i1 [[_MSCMP11]], [[_MSCMP12]]8291; CHECK-NEXT: [[TMP16:%.*]] = bitcast <2 x i64> [[TMP3]] to i1288292; CHECK-NEXT: [[_MSCMP14:%.*]] = icmp ne i128 [[TMP16]], 08293; CHECK-NEXT: [[_MSOR15:%.*]] = or i1 [[_MSOR13]], [[_MSCMP14]]8294; CHECK-NEXT: [[_MSCMP16:%.*]] = icmp ne i8 [[TMP4]], 08295; CHECK-NEXT: [[_MSOR17:%.*]] = or i1 [[_MSOR15]], [[_MSCMP16]]8296; CHECK-NEXT: br i1 [[_MSOR17]], label [[TMP17:%.*]], label [[TMP18:%.*]], !prof [[PROF1]]8297; CHECK: 17:8298; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]8299; CHECK-NEXT: unreachable8300; CHECK: 18:8301; CHECK-NEXT: [[RES2:%.*]] = call <2 x double> @llvm.x86.avx512.mask.getmant.sd(<2 x double> [[X0]], <2 x double> [[X1]], i32 13, <2 x double> [[X2]], i8 [[X3]], i32 8)8302; CHECK-NEXT: [[TMP19:%.*]] = bitcast <2 x i64> [[TMP1]] to i1288303; CHECK-NEXT: [[_MSCMP18:%.*]] = icmp ne i128 [[TMP19]], 08304; CHECK-NEXT: [[TMP20:%.*]] = bitcast <2 x i64> [[TMP2]] to i1288305; CHECK-NEXT: [[_MSCMP19:%.*]] = icmp ne i128 [[TMP20]], 08306; CHECK-NEXT: [[_MSOR20:%.*]] = or i1 [[_MSCMP18]], [[_MSCMP19]]8307; CHECK-NEXT: [[TMP21:%.*]] = bitcast <2 x i64> [[TMP3]] to i1288308; CHECK-NEXT: [[_MSCMP21:%.*]] = icmp ne i128 [[TMP21]], 08309; CHECK-NEXT: [[_MSOR22:%.*]] = or i1 [[_MSOR20]], [[_MSCMP21]]8310; CHECK-NEXT: br i1 [[_MSOR22]], label [[TMP22:%.*]], label [[TMP23:%.*]], !prof [[PROF1]]8311; CHECK: 22:8312; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]8313; CHECK-NEXT: unreachable8314; CHECK: 23:8315; CHECK-NEXT: [[RES3:%.*]] = call <2 x double> @llvm.x86.avx512.mask.getmant.sd(<2 x double> [[X0]], <2 x double> [[X1]], i32 14, <2 x double> [[X2]], i8 -1, i32 4)8316; CHECK-NEXT: [[RES11:%.*]] = fadd <2 x double> [[RES]], [[RES1]]8317; CHECK-NEXT: [[RES12:%.*]] = fadd <2 x double> [[RES2]], [[RES3]]8318; CHECK-NEXT: [[RES13:%.*]] = fadd <2 x double> [[RES11]], [[RES12]]8319; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 88320; CHECK-NEXT: ret <2 x double> [[RES13]]8321;8322 %res = call <2 x double> @llvm.x86.avx512.mask.getmant.sd(<2 x double> %x0, <2 x double> %x1, i32 11, <2 x double> %x2, i8 %x3, i32 4)8323 %res1 = call <2 x double> @llvm.x86.avx512.mask.getmant.sd(<2 x double> %x0, <2 x double> %x1, i32 12, <2 x double> zeroinitializer, i8 %x3, i32 4)8324 %res2 = call <2 x double> @llvm.x86.avx512.mask.getmant.sd(<2 x double> %x0, <2 x double> %x1, i32 13, <2 x double> %x2, i8 %x3, i32 8)8325 %res3 = call <2 x double> @llvm.x86.avx512.mask.getmant.sd(<2 x double> %x0, <2 x double> %x1, i32 14, <2 x double> %x2, i8 -1, i32 4)8326 %res11 = fadd <2 x double> %res, %res18327 %res12 = fadd <2 x double> %res2, %res38328 %res13 = fadd <2 x double> %res11, %res128329 ret <2 x double> %res138330}8331 8332declare <4 x float> @llvm.x86.avx512.mask.getmant.ss(<4 x float>, <4 x float>, i32, <4 x float>, i8, i32)8333 8334define <4 x float>@test_int_x86_avx512_mask_getmant_ss(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) #0 {8335; CHECK-LABEL: @test_int_x86_avx512_mask_getmant_ss(8336; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 88337; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 88338; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 88339; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 88340; CHECK-NEXT: call void @llvm.donothing()8341; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP1]] to i1288342; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 08343; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i32> [[TMP2]] to i1288344; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP6]], 08345; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]8346; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i32> [[TMP3]] to i1288347; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 08348; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]8349; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 08350; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]8351; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]8352; CHECK: 8:8353; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]8354; CHECK-NEXT: unreachable8355; CHECK: 9:8356; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.mask.getmant.ss(<4 x float> [[X0:%.*]], <4 x float> [[X1:%.*]], i32 11, <4 x float> [[X2:%.*]], i8 [[X3:%.*]], i32 4)8357; CHECK-NEXT: [[TMP10:%.*]] = bitcast <4 x i32> [[TMP1]] to i1288358; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i128 [[TMP10]], 08359; CHECK-NEXT: [[TMP11:%.*]] = bitcast <4 x i32> [[TMP2]] to i1288360; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i128 [[TMP11]], 08361; CHECK-NEXT: [[_MSOR8:%.*]] = or i1 [[_MSCMP6]], [[_MSCMP7]]8362; CHECK-NEXT: [[_MSCMP9:%.*]] = icmp ne i8 [[TMP4]], 08363; CHECK-NEXT: [[_MSOR10:%.*]] = or i1 [[_MSOR8]], [[_MSCMP9]]8364; CHECK-NEXT: br i1 [[_MSOR10]], label [[TMP12:%.*]], label [[TMP13:%.*]], !prof [[PROF1]]8365; CHECK: 12:8366; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]8367; CHECK-NEXT: unreachable8368; CHECK: 13:8369; CHECK-NEXT: [[RES1:%.*]] = call <4 x float> @llvm.x86.avx512.mask.getmant.ss(<4 x float> [[X0]], <4 x float> [[X1]], i32 12, <4 x float> zeroinitializer, i8 [[X3]], i32 4)8370; CHECK-NEXT: [[TMP14:%.*]] = bitcast <4 x i32> [[TMP1]] to i1288371; CHECK-NEXT: [[_MSCMP11:%.*]] = icmp ne i128 [[TMP14]], 08372; CHECK-NEXT: [[TMP15:%.*]] = bitcast <4 x i32> [[TMP2]] to i1288373; CHECK-NEXT: [[_MSCMP12:%.*]] = icmp ne i128 [[TMP15]], 08374; CHECK-NEXT: [[_MSOR13:%.*]] = or i1 [[_MSCMP11]], [[_MSCMP12]]8375; CHECK-NEXT: [[TMP16:%.*]] = bitcast <4 x i32> [[TMP3]] to i1288376; CHECK-NEXT: [[_MSCMP14:%.*]] = icmp ne i128 [[TMP16]], 08377; CHECK-NEXT: [[_MSOR15:%.*]] = or i1 [[_MSOR13]], [[_MSCMP14]]8378; CHECK-NEXT: br i1 [[_MSOR15]], label [[TMP17:%.*]], label [[TMP18:%.*]], !prof [[PROF1]]8379; CHECK: 17:8380; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]8381; CHECK-NEXT: unreachable8382; CHECK: 18:8383; CHECK-NEXT: [[RES2:%.*]] = call <4 x float> @llvm.x86.avx512.mask.getmant.ss(<4 x float> [[X0]], <4 x float> [[X1]], i32 13, <4 x float> [[X2]], i8 -1, i32 8)8384; CHECK-NEXT: [[TMP19:%.*]] = bitcast <4 x i32> [[TMP1]] to i1288385; CHECK-NEXT: [[_MSCMP16:%.*]] = icmp ne i128 [[TMP19]], 08386; CHECK-NEXT: [[TMP20:%.*]] = bitcast <4 x i32> [[TMP2]] to i1288387; CHECK-NEXT: [[_MSCMP17:%.*]] = icmp ne i128 [[TMP20]], 08388; CHECK-NEXT: [[_MSOR18:%.*]] = or i1 [[_MSCMP16]], [[_MSCMP17]]8389; CHECK-NEXT: [[TMP21:%.*]] = bitcast <4 x i32> [[TMP3]] to i1288390; CHECK-NEXT: [[_MSCMP19:%.*]] = icmp ne i128 [[TMP21]], 08391; CHECK-NEXT: [[_MSOR20:%.*]] = or i1 [[_MSOR18]], [[_MSCMP19]]8392; CHECK-NEXT: br i1 [[_MSOR20]], label [[TMP22:%.*]], label [[TMP23:%.*]], !prof [[PROF1]]8393; CHECK: 22:8394; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]8395; CHECK-NEXT: unreachable8396; CHECK: 23:8397; CHECK-NEXT: [[RES3:%.*]] = call <4 x float> @llvm.x86.avx512.mask.getmant.ss(<4 x float> [[X0]], <4 x float> [[X1]], i32 14, <4 x float> [[X2]], i8 -1, i32 4)8398; CHECK-NEXT: [[RES11:%.*]] = fadd <4 x float> [[RES]], [[RES1]]8399; CHECK-NEXT: [[RES12:%.*]] = fadd <4 x float> [[RES2]], [[RES3]]8400; CHECK-NEXT: [[RES13:%.*]] = fadd <4 x float> [[RES11]], [[RES12]]8401; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 88402; CHECK-NEXT: ret <4 x float> [[RES13]]8403;8404 %res = call <4 x float> @llvm.x86.avx512.mask.getmant.ss(<4 x float> %x0, <4 x float> %x1, i32 11, <4 x float> %x2, i8 %x3, i32 4)8405 %res1 = call <4 x float> @llvm.x86.avx512.mask.getmant.ss(<4 x float> %x0, <4 x float> %x1, i32 12, <4 x float> zeroinitializer, i8 %x3, i32 4)8406 %res2 = call <4 x float> @llvm.x86.avx512.mask.getmant.ss(<4 x float> %x0, <4 x float> %x1, i32 13, <4 x float> %x2, i8 -1, i32 8)8407 %res3 = call <4 x float> @llvm.x86.avx512.mask.getmant.ss(<4 x float> %x0, <4 x float> %x1, i32 14, <4 x float> %x2, i8 -1, i32 4)8408 %res11 = fadd <4 x float> %res, %res18409 %res12 = fadd <4 x float> %res2, %res38410 %res13 = fadd <4 x float> %res11, %res128411 ret <4 x float> %res138412}8413 8414define <4 x float> @test_int_x86_avx512_mask_getmant_ss_load(<4 x float> %x0, ptr %x1p, <4 x float> %extra_param) #0 {8415; CHECK-LABEL: @test_int_x86_avx512_mask_getmant_ss_load(8416; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 88417; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 88418; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 88419; CHECK-NEXT: call void @llvm.donothing()8420; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 08421; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP4:%.*]], label [[TMP10:%.*]], !prof [[PROF1]]8422; CHECK: 4:8423; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]8424; CHECK-NEXT: unreachable8425; CHECK: 5:8426; CHECK-NEXT: [[X1:%.*]] = load <4 x float>, ptr [[X1P:%.*]], align 168427; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[X1P]] to i648428; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 879609302220808429; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr8430; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 168431; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x i32> [[TMP2]] to i1288432; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP8]], 08433; CHECK-NEXT: [[TMP9:%.*]] = bitcast <4 x i32> [[_MSLD]] to i1288434; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP9]], 08435; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP1]], [[_MSCMP2]]8436; CHECK-NEXT: [[TMP11:%.*]] = bitcast <4 x i32> [[TMP3]] to i1288437; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP11]], 08438; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSOR]], [[_MSCMP3]]8439; CHECK-NEXT: br i1 [[_MSOR4]], label [[TMP12:%.*]], label [[TMP13:%.*]], !prof [[PROF1]]8440; CHECK: 12:8441; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]8442; CHECK-NEXT: unreachable8443; CHECK: 13:8444; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.mask.getmant.ss(<4 x float> [[X0:%.*]], <4 x float> [[X1]], i32 11, <4 x float> [[EXTRA_PARAM:%.*]], i8 -1, i32 4)8445; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 88446; CHECK-NEXT: ret <4 x float> [[RES]]8447;8448 %x1 = load <4 x float>, ptr %x1p8449 %res = call <4 x float> @llvm.x86.avx512.mask.getmant.ss(<4 x float> %x0, <4 x float> %x1, i32 11, <4 x float> %extra_param, i8 -1, i32 4)8450 ret <4 x float> %res8451}8452 8453declare <8 x double> @llvm.x86.avx512.vpermilvar.pd.512(<8 x double>, <8 x i64>)8454 8455define <8 x double>@test_int_x86_avx512_vpermilvar_pd_512(<8 x double> %x0, <8 x i64> %x1) #0 {8456; CHECK-LABEL: @test_int_x86_avx512_vpermilvar_pd_512(8457; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 88458; CHECK-NEXT: [[X1:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 88459; CHECK-NEXT: call void @llvm.donothing()8460; CHECK-NEXT: [[TMP2:%.*]] = trunc <8 x i64> [[X1]] to <8 x i3>8461; CHECK-NEXT: [[X0:%.*]] = bitcast <8 x i64> [[TMP1]] to <8 x double>8462; CHECK-NEXT: [[RES:%.*]] = call <8 x double> @llvm.x86.avx512.vpermilvar.pd.512(<8 x double> [[X0]], <8 x i64> [[X2:%.*]])8463; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x double> [[RES]] to <8 x i64>8464; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i3> [[TMP2]] to i248465; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i24 [[TMP6]], 08466; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]8467; CHECK: 8:8468; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]8469; CHECK-NEXT: unreachable8470; CHECK: 9:8471; CHECK-NEXT: [[RES1:%.*]] = call <8 x double> @llvm.x86.avx512.vpermilvar.pd.512(<8 x double> [[X3:%.*]], <8 x i64> [[X2]])8472; CHECK-NEXT: store <8 x i64> [[TMP4]], ptr @__msan_retval_tls, align 88473; CHECK-NEXT: ret <8 x double> [[RES1]]8474;8475 %res = call <8 x double> @llvm.x86.avx512.vpermilvar.pd.512(<8 x double> %x0, <8 x i64> %x1)8476 ret <8 x double> %res8477}8478 8479define <8 x double>@test_int_x86_avx512_vpermilvar_pd_512_mask(<8 x double> %x0, <8 x i64> %x1, <8 x double> %x2, i8 %mask) #0 {8480; CHECK-LABEL: @test_int_x86_avx512_vpermilvar_pd_512_mask(8481; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 88482; CHECK-NEXT: [[X1:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 88483; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 88484; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 88485; CHECK-NEXT: call void @llvm.donothing()8486; CHECK-NEXT: [[TMP5:%.*]] = trunc <8 x i64> [[X1]] to <8 x i3>8487; CHECK-NEXT: [[X0:%.*]] = bitcast <8 x i64> [[TMP1]] to <8 x double>8488; CHECK-NEXT: [[RES:%.*]] = call <8 x double> @llvm.x86.avx512.vpermilvar.pd.512(<8 x double> [[X0]], <8 x i64> [[X3:%.*]])8489; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x double> [[RES]] to <8 x i64>8490; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i3> [[TMP5]] to i248491; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i24 [[TMP8]], 08492; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP16:%.*]], label [[TMP17:%.*]], !prof [[PROF1]]8493; CHECK: 10:8494; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]8495; CHECK-NEXT: unreachable8496; CHECK: 11:8497; CHECK-NEXT: [[RES1:%.*]] = call <8 x double> @llvm.x86.avx512.vpermilvar.pd.512(<8 x double> [[X4:%.*]], <8 x i64> [[X3]])8498; CHECK-NEXT: [[TMP9:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>8499; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>8500; CHECK-NEXT: [[TMP10:%.*]] = select <8 x i1> [[MASK_CAST]], <8 x i64> [[TMP6]], <8 x i64> [[TMP4]]8501; CHECK-NEXT: [[TMP11:%.*]] = bitcast <8 x double> [[RES1]] to <8 x i64>8502; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x double> [[X2:%.*]] to <8 x i64>8503; CHECK-NEXT: [[TMP13:%.*]] = xor <8 x i64> [[TMP11]], [[TMP12]]8504; CHECK-NEXT: [[TMP14:%.*]] = or <8 x i64> [[TMP13]], [[TMP6]]8505; CHECK-NEXT: [[TMP15:%.*]] = or <8 x i64> [[TMP14]], [[TMP4]]8506; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP9]], <8 x i64> [[TMP15]], <8 x i64> [[TMP10]]8507; CHECK-NEXT: [[RES2:%.*]] = select <8 x i1> [[MASK_CAST]], <8 x double> [[RES1]], <8 x double> [[X2]]8508; CHECK-NEXT: store <8 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 88509; CHECK-NEXT: ret <8 x double> [[RES2]]8510;8511 %res = call <8 x double> @llvm.x86.avx512.vpermilvar.pd.512(<8 x double> %x0, <8 x i64> %x1)8512 %mask.cast = bitcast i8 %mask to <8 x i1>8513 %res2 = select <8 x i1> %mask.cast, <8 x double> %res, <8 x double> %x28514 ret <8 x double> %res28515}8516 8517define <8 x double>@test_int_x86_avx512_vpermilvar_pd_512_maskz(<8 x double> %x0, <8 x i64> %x1, i8 %mask) #0 {8518; CHECK-LABEL: @test_int_x86_avx512_vpermilvar_pd_512_maskz(8519; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 88520; CHECK-NEXT: [[X1:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 88521; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 88522; CHECK-NEXT: call void @llvm.donothing()8523; CHECK-NEXT: [[TMP4:%.*]] = trunc <8 x i64> [[X1]] to <8 x i3>8524; CHECK-NEXT: [[X0:%.*]] = bitcast <8 x i64> [[TMP1]] to <8 x double>8525; CHECK-NEXT: [[RES:%.*]] = call <8 x double> @llvm.x86.avx512.vpermilvar.pd.512(<8 x double> [[X0]], <8 x i64> [[X2:%.*]])8526; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x double> [[RES]] to <8 x i64>8527; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i3> [[TMP4]] to i248528; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i24 [[TMP7]], 08529; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP14:%.*]], label [[TMP15:%.*]], !prof [[PROF1]]8530; CHECK: 9:8531; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]8532; CHECK-NEXT: unreachable8533; CHECK: 10:8534; CHECK-NEXT: [[RES1:%.*]] = call <8 x double> @llvm.x86.avx512.vpermilvar.pd.512(<8 x double> [[X3:%.*]], <8 x i64> [[X2]])8535; CHECK-NEXT: [[TMP8:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>8536; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>8537; CHECK-NEXT: [[TMP9:%.*]] = select <8 x i1> [[MASK_CAST]], <8 x i64> [[TMP5]], <8 x i64> zeroinitializer8538; CHECK-NEXT: [[TMP10:%.*]] = bitcast <8 x double> [[RES1]] to <8 x i64>8539; CHECK-NEXT: [[TMP11:%.*]] = xor <8 x i64> [[TMP10]], zeroinitializer8540; CHECK-NEXT: [[TMP12:%.*]] = or <8 x i64> [[TMP11]], [[TMP5]]8541; CHECK-NEXT: [[TMP13:%.*]] = or <8 x i64> [[TMP12]], zeroinitializer8542; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP8]], <8 x i64> [[TMP13]], <8 x i64> [[TMP9]]8543; CHECK-NEXT: [[RES2:%.*]] = select <8 x i1> [[MASK_CAST]], <8 x double> [[RES1]], <8 x double> zeroinitializer8544; CHECK-NEXT: store <8 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 88545; CHECK-NEXT: ret <8 x double> [[RES2]]8546;8547 %res = call <8 x double> @llvm.x86.avx512.vpermilvar.pd.512(<8 x double> %x0, <8 x i64> %x1)8548 %mask.cast = bitcast i8 %mask to <8 x i1>8549 %res2 = select <8 x i1> %mask.cast, <8 x double> %res, <8 x double> zeroinitializer8550 ret <8 x double> %res28551}8552 8553declare <16 x float> @llvm.x86.avx512.vpermilvar.ps.512(<16 x float>, <16 x i32>)8554 8555define <16 x float>@test_int_x86_avx512_vpermilvar_ps_512(<16 x float> %x0, <16 x i32> %x1) #0 {8556; CHECK-LABEL: @test_int_x86_avx512_vpermilvar_ps_512(8557; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 88558; CHECK-NEXT: [[X1:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 88559; CHECK-NEXT: call void @llvm.donothing()8560; CHECK-NEXT: [[TMP2:%.*]] = trunc <16 x i32> [[X1]] to <16 x i4>8561; CHECK-NEXT: [[X0:%.*]] = bitcast <16 x i32> [[TMP1]] to <16 x float>8562; CHECK-NEXT: [[RES:%.*]] = call <16 x float> @llvm.x86.avx512.vpermilvar.ps.512(<16 x float> [[X0]], <16 x i32> [[X2:%.*]])8563; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x float> [[RES]] to <16 x i32>8564; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i4> [[TMP2]] to i648565; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP6]], 08566; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]8567; CHECK: 8:8568; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]8569; CHECK-NEXT: unreachable8570; CHECK: 9:8571; CHECK-NEXT: [[RES1:%.*]] = call <16 x float> @llvm.x86.avx512.vpermilvar.ps.512(<16 x float> [[X3:%.*]], <16 x i32> [[X2]])8572; CHECK-NEXT: store <16 x i32> [[TMP4]], ptr @__msan_retval_tls, align 88573; CHECK-NEXT: ret <16 x float> [[RES1]]8574;8575 %res = call <16 x float> @llvm.x86.avx512.vpermilvar.ps.512(<16 x float> %x0, <16 x i32> %x1)8576 ret <16 x float> %res8577}8578 8579define <16 x float>@test_int_x86_avx512_vpermilvar_ps_512_mask(<16 x float> %x0, <16 x i32> %x1, <16 x float> %x2, i16 %mask) #0 {8580; CHECK-LABEL: @test_int_x86_avx512_vpermilvar_ps_512_mask(8581; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 88582; CHECK-NEXT: [[X1:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 88583; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 88584; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 88585; CHECK-NEXT: call void @llvm.donothing()8586; CHECK-NEXT: [[TMP5:%.*]] = trunc <16 x i32> [[X1]] to <16 x i4>8587; CHECK-NEXT: [[X0:%.*]] = bitcast <16 x i32> [[TMP1]] to <16 x float>8588; CHECK-NEXT: [[RES:%.*]] = call <16 x float> @llvm.x86.avx512.vpermilvar.ps.512(<16 x float> [[X0]], <16 x i32> [[X3:%.*]])8589; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x float> [[RES]] to <16 x i32>8590; CHECK-NEXT: [[TMP8:%.*]] = bitcast <16 x i4> [[TMP5]] to i648591; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP8]], 08592; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP16:%.*]], label [[TMP17:%.*]], !prof [[PROF1]]8593; CHECK: 10:8594; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]8595; CHECK-NEXT: unreachable8596; CHECK: 11:8597; CHECK-NEXT: [[RES1:%.*]] = call <16 x float> @llvm.x86.avx512.vpermilvar.ps.512(<16 x float> [[X4:%.*]], <16 x i32> [[X3]])8598; CHECK-NEXT: [[TMP9:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>8599; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>8600; CHECK-NEXT: [[TMP10:%.*]] = select <16 x i1> [[MASK_CAST]], <16 x i32> [[TMP6]], <16 x i32> [[TMP4]]8601; CHECK-NEXT: [[TMP11:%.*]] = bitcast <16 x float> [[RES1]] to <16 x i32>8602; CHECK-NEXT: [[TMP12:%.*]] = bitcast <16 x float> [[X2:%.*]] to <16 x i32>8603; CHECK-NEXT: [[TMP13:%.*]] = xor <16 x i32> [[TMP11]], [[TMP12]]8604; CHECK-NEXT: [[TMP14:%.*]] = or <16 x i32> [[TMP13]], [[TMP6]]8605; CHECK-NEXT: [[TMP15:%.*]] = or <16 x i32> [[TMP14]], [[TMP4]]8606; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP9]], <16 x i32> [[TMP15]], <16 x i32> [[TMP10]]8607; CHECK-NEXT: [[RES2:%.*]] = select <16 x i1> [[MASK_CAST]], <16 x float> [[RES1]], <16 x float> [[X2]]8608; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 88609; CHECK-NEXT: ret <16 x float> [[RES2]]8610;8611 %res = call <16 x float> @llvm.x86.avx512.vpermilvar.ps.512(<16 x float> %x0, <16 x i32> %x1)8612 %mask.cast = bitcast i16 %mask to <16 x i1>8613 %res2 = select <16 x i1> %mask.cast, <16 x float> %res, <16 x float> %x28614 ret <16 x float> %res28615}8616 8617define <16 x float>@test_int_x86_avx512_vpermilvar_ps_512_maskz(<16 x float> %x0, <16 x i32> %x1, i16 %mask) #0 {8618; CHECK-LABEL: @test_int_x86_avx512_vpermilvar_ps_512_maskz(8619; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 88620; CHECK-NEXT: [[X1:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 88621; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 88622; CHECK-NEXT: call void @llvm.donothing()8623; CHECK-NEXT: [[TMP4:%.*]] = trunc <16 x i32> [[X1]] to <16 x i4>8624; CHECK-NEXT: [[X0:%.*]] = bitcast <16 x i32> [[TMP1]] to <16 x float>8625; CHECK-NEXT: [[RES:%.*]] = call <16 x float> @llvm.x86.avx512.vpermilvar.ps.512(<16 x float> [[X0]], <16 x i32> [[X2:%.*]])8626; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x float> [[RES]] to <16 x i32>8627; CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i4> [[TMP4]] to i648628; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP7]], 08629; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP14:%.*]], label [[TMP15:%.*]], !prof [[PROF1]]8630; CHECK: 9:8631; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]8632; CHECK-NEXT: unreachable8633; CHECK: 10:8634; CHECK-NEXT: [[RES1:%.*]] = call <16 x float> @llvm.x86.avx512.vpermilvar.ps.512(<16 x float> [[X3:%.*]], <16 x i32> [[X2]])8635; CHECK-NEXT: [[TMP8:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>8636; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>8637; CHECK-NEXT: [[TMP9:%.*]] = select <16 x i1> [[MASK_CAST]], <16 x i32> [[TMP5]], <16 x i32> zeroinitializer8638; CHECK-NEXT: [[TMP10:%.*]] = bitcast <16 x float> [[RES1]] to <16 x i32>8639; CHECK-NEXT: [[TMP11:%.*]] = xor <16 x i32> [[TMP10]], zeroinitializer8640; CHECK-NEXT: [[TMP12:%.*]] = or <16 x i32> [[TMP11]], [[TMP5]]8641; CHECK-NEXT: [[TMP13:%.*]] = or <16 x i32> [[TMP12]], zeroinitializer8642; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP8]], <16 x i32> [[TMP13]], <16 x i32> [[TMP9]]8643; CHECK-NEXT: [[RES2:%.*]] = select <16 x i1> [[MASK_CAST]], <16 x float> [[RES1]], <16 x float> zeroinitializer8644; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 88645; CHECK-NEXT: ret <16 x float> [[RES2]]8646;8647 %res = call <16 x float> @llvm.x86.avx512.vpermilvar.ps.512(<16 x float> %x0, <16 x i32> %x1)8648 %mask.cast = bitcast i16 %mask to <16 x i1>8649 %res2 = select <16 x i1> %mask.cast, <16 x float> %res, <16 x float> zeroinitializer8650 ret <16 x float> %res28651}8652 8653define <16 x float>@test_int_x86_avx512_vpermilvar_ps_512_constant_pool(<16 x float> %x0, <16 x i32> %x1) #0 {8654; CHECK-LABEL: @test_int_x86_avx512_vpermilvar_ps_512_constant_pool(8655; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 88656; CHECK-NEXT: call void @llvm.donothing()8657; CHECK-NEXT: [[X0:%.*]] = bitcast <16 x i32> [[TMP1]] to <16 x float>8658; CHECK-NEXT: [[RES:%.*]] = call <16 x float> @llvm.x86.avx512.vpermilvar.ps.512(<16 x float> [[X0]], <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 1, i32 0>)8659; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x float> [[RES]] to <16 x i32>8660; CHECK-NEXT: [[RES1:%.*]] = call <16 x float> @llvm.x86.avx512.vpermilvar.ps.512(<16 x float> [[X1:%.*]], <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 1, i32 0>)8661; CHECK-NEXT: store <16 x i32> [[TMP4]], ptr @__msan_retval_tls, align 88662; CHECK-NEXT: ret <16 x float> [[RES1]]8663;8664 %res = call <16 x float> @llvm.x86.avx512.vpermilvar.ps.512(<16 x float> %x0, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 1, i32 0>)8665 ret <16 x float> %res8666}8667 8668define <16 x float>@test_int_x86_avx512_vpermilvar_ps_512_constant_pool_mask(<16 x float> %x0, <16 x i32> %x1, <16 x float> %x2, i16 %mask) #0 {8669; CHECK-LABEL: @test_int_x86_avx512_vpermilvar_ps_512_constant_pool_mask(8670; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 88671; CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 88672; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 88673; CHECK-NEXT: call void @llvm.donothing()8674; CHECK-NEXT: [[X0:%.*]] = bitcast <16 x i32> [[TMP1]] to <16 x float>8675; CHECK-NEXT: [[RES:%.*]] = call <16 x float> @llvm.x86.avx512.vpermilvar.ps.512(<16 x float> [[X0]], <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 1, i32 0>)8676; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x float> [[RES]] to <16 x i32>8677; CHECK-NEXT: [[RES1:%.*]] = call <16 x float> @llvm.x86.avx512.vpermilvar.ps.512(<16 x float> [[X1:%.*]], <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 1, i32 0>)8678; CHECK-NEXT: [[TMP7:%.*]] = bitcast i16 [[TMP2]] to <16 x i1>8679; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>8680; CHECK-NEXT: [[TMP8:%.*]] = select <16 x i1> [[MASK_CAST]], <16 x i32> [[TMP6]], <16 x i32> [[TMP3]]8681; CHECK-NEXT: [[TMP9:%.*]] = bitcast <16 x float> [[RES1]] to <16 x i32>8682; CHECK-NEXT: [[TMP10:%.*]] = bitcast <16 x float> [[X2:%.*]] to <16 x i32>8683; CHECK-NEXT: [[TMP11:%.*]] = xor <16 x i32> [[TMP9]], [[TMP10]]8684; CHECK-NEXT: [[TMP12:%.*]] = or <16 x i32> [[TMP11]], [[TMP6]]8685; CHECK-NEXT: [[TMP13:%.*]] = or <16 x i32> [[TMP12]], [[TMP3]]8686; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP7]], <16 x i32> [[TMP13]], <16 x i32> [[TMP8]]8687; CHECK-NEXT: [[RES2:%.*]] = select <16 x i1> [[MASK_CAST]], <16 x float> [[RES1]], <16 x float> [[X2]]8688; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 88689; CHECK-NEXT: ret <16 x float> [[RES2]]8690;8691 %res = call <16 x float> @llvm.x86.avx512.vpermilvar.ps.512(<16 x float> %x0, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 1, i32 0>)8692 %mask.cast = bitcast i16 %mask to <16 x i1>8693 %res2 = select <16 x i1> %mask.cast, <16 x float> %res, <16 x float> %x28694 ret <16 x float> %res28695}8696 8697define <16 x float>@test_int_x86_avx512_vpermilvar_ps_512_constant_pool_maskz(<16 x float> %x0, <16 x i32> %x1, i16 %mask) #0 {8698; CHECK-LABEL: @test_int_x86_avx512_vpermilvar_ps_512_constant_pool_maskz(8699; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 88700; CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 88701; CHECK-NEXT: call void @llvm.donothing()8702; CHECK-NEXT: [[X0:%.*]] = bitcast <16 x i32> [[TMP1]] to <16 x float>8703; CHECK-NEXT: [[RES:%.*]] = call <16 x float> @llvm.x86.avx512.vpermilvar.ps.512(<16 x float> [[X0]], <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 1, i32 0>)8704; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x float> [[RES]] to <16 x i32>8705; CHECK-NEXT: [[RES1:%.*]] = call <16 x float> @llvm.x86.avx512.vpermilvar.ps.512(<16 x float> [[X1:%.*]], <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 1, i32 0>)8706; CHECK-NEXT: [[TMP6:%.*]] = bitcast i16 [[TMP2]] to <16 x i1>8707; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>8708; CHECK-NEXT: [[TMP7:%.*]] = select <16 x i1> [[MASK_CAST]], <16 x i32> [[TMP5]], <16 x i32> zeroinitializer8709; CHECK-NEXT: [[TMP8:%.*]] = bitcast <16 x float> [[RES1]] to <16 x i32>8710; CHECK-NEXT: [[TMP9:%.*]] = xor <16 x i32> [[TMP8]], zeroinitializer8711; CHECK-NEXT: [[TMP10:%.*]] = or <16 x i32> [[TMP9]], [[TMP5]]8712; CHECK-NEXT: [[TMP11:%.*]] = or <16 x i32> [[TMP10]], zeroinitializer8713; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP6]], <16 x i32> [[TMP11]], <16 x i32> [[TMP7]]8714; CHECK-NEXT: [[RES2:%.*]] = select <16 x i1> [[MASK_CAST]], <16 x float> [[RES1]], <16 x float> zeroinitializer8715; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 88716; CHECK-NEXT: ret <16 x float> [[RES2]]8717;8718 %res = call <16 x float> @llvm.x86.avx512.vpermilvar.ps.512(<16 x float> %x0, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 1, i32 0>)8719 %mask.cast = bitcast i16 %mask to <16 x i1>8720 %res2 = select <16 x i1> %mask.cast, <16 x float> %res, <16 x float> zeroinitializer8721 ret <16 x float> %res28722}8723 8724declare <2 x double> @llvm.x86.avx512.mask.cvtss2sd.round(<2 x double>, <4 x float>, <2 x double>, i8, i32)8725 8726define <2 x double>@test_int_x86_avx512_mask_cvt_ss2sd_round(<2 x double> %x0,<4 x float> %x1, <2 x double> %x2, i8 %x3) #0 {8727; CHECK-LABEL: @test_int_x86_avx512_mask_cvt_ss2sd_round(8728; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 88729; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 88730; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 88731; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 88732; CHECK-NEXT: call void @llvm.donothing()8733; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP1]] to i1288734; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 08735; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i32> [[TMP2]] to i1288736; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP6]], 08737; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]8738; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i64> [[TMP3]] to i1288739; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 08740; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]8741; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 08742; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]8743; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]8744; CHECK: 8:8745; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]8746; CHECK-NEXT: unreachable8747; CHECK: 9:8748; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx512.mask.cvtss2sd.round(<2 x double> [[X0:%.*]], <4 x float> [[X1:%.*]], <2 x double> [[X2:%.*]], i8 [[X3:%.*]], i32 4)8749; CHECK-NEXT: [[TMP10:%.*]] = bitcast <2 x i64> [[TMP1]] to i1288750; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i128 [[TMP10]], 08751; CHECK-NEXT: [[TMP11:%.*]] = bitcast <4 x i32> [[TMP2]] to i1288752; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i128 [[TMP11]], 08753; CHECK-NEXT: [[_MSOR8:%.*]] = or i1 [[_MSCMP6]], [[_MSCMP7]]8754; CHECK-NEXT: [[TMP12:%.*]] = bitcast <2 x i64> [[TMP3]] to i1288755; CHECK-NEXT: [[_MSCMP9:%.*]] = icmp ne i128 [[TMP12]], 08756; CHECK-NEXT: [[_MSOR10:%.*]] = or i1 [[_MSOR8]], [[_MSCMP9]]8757; CHECK-NEXT: br i1 [[_MSOR10]], label [[TMP13:%.*]], label [[TMP14:%.*]], !prof [[PROF1]]8758; CHECK: 13:8759; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]8760; CHECK-NEXT: unreachable8761; CHECK: 14:8762; CHECK-NEXT: [[RES1:%.*]] = call <2 x double> @llvm.x86.avx512.mask.cvtss2sd.round(<2 x double> [[X0]], <4 x float> [[X1]], <2 x double> [[X2]], i8 -1, i32 8)8763; CHECK-NEXT: [[RES2:%.*]] = fadd <2 x double> [[RES]], [[RES1]]8764; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 88765; CHECK-NEXT: ret <2 x double> [[RES2]]8766;8767 %res = call <2 x double> @llvm.x86.avx512.mask.cvtss2sd.round(<2 x double> %x0, <4 x float> %x1, <2 x double> %x2, i8 %x3, i32 4)8768 %res1 = call <2 x double> @llvm.x86.avx512.mask.cvtss2sd.round(<2 x double> %x0, <4 x float> %x1, <2 x double> %x2, i8 -1, i32 8)8769 %res2 = fadd <2 x double> %res, %res18770 ret <2 x double> %res28771}8772 8773declare <4 x float> @llvm.x86.avx512.mask.cvtsd2ss.round(<4 x float>, <2 x double>, <4 x float>, i8, i32)8774 8775define <4 x float>@test_int_x86_avx512_mask_cvt_sd2ss_round(<4 x float> %x0,<2 x double> %x1, <4 x float> %x2, i8 %x3) #0 {8776; CHECK-LABEL: @test_int_x86_avx512_mask_cvt_sd2ss_round(8777; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 88778; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 88779; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 88780; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 88781; CHECK-NEXT: call void @llvm.donothing()8782; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP1]] to i1288783; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 08784; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i64> [[TMP2]] to i1288785; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP6]], 08786; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]8787; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i32> [[TMP3]] to i1288788; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 08789; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]8790; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 08791; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]8792; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]8793; CHECK: 8:8794; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]8795; CHECK-NEXT: unreachable8796; CHECK: 9:8797; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.mask.cvtsd2ss.round(<4 x float> [[X0:%.*]], <2 x double> [[X1:%.*]], <4 x float> [[X2:%.*]], i8 [[X3:%.*]], i32 11)8798; CHECK-NEXT: [[TMP10:%.*]] = bitcast <4 x i32> [[TMP1]] to i1288799; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i128 [[TMP10]], 08800; CHECK-NEXT: [[TMP11:%.*]] = bitcast <2 x i64> [[TMP2]] to i1288801; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i128 [[TMP11]], 08802; CHECK-NEXT: [[_MSOR8:%.*]] = or i1 [[_MSCMP6]], [[_MSCMP7]]8803; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i32> [[TMP3]] to i1288804; CHECK-NEXT: [[_MSCMP9:%.*]] = icmp ne i128 [[TMP12]], 08805; CHECK-NEXT: [[_MSOR10:%.*]] = or i1 [[_MSOR8]], [[_MSCMP9]]8806; CHECK-NEXT: br i1 [[_MSOR10]], label [[TMP13:%.*]], label [[TMP14:%.*]], !prof [[PROF1]]8807; CHECK: 13:8808; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]8809; CHECK-NEXT: unreachable8810; CHECK: 14:8811; CHECK-NEXT: [[RES1:%.*]] = call <4 x float> @llvm.x86.avx512.mask.cvtsd2ss.round(<4 x float> [[X0]], <2 x double> [[X1]], <4 x float> [[X2]], i8 -1, i32 8)8812; CHECK-NEXT: [[RES2:%.*]] = fadd <4 x float> [[RES]], [[RES1]]8813; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 88814; CHECK-NEXT: ret <4 x float> [[RES2]]8815;8816 %res = call <4 x float> @llvm.x86.avx512.mask.cvtsd2ss.round(<4 x float> %x0, <2 x double> %x1, <4 x float> %x2, i8 %x3, i32 11)8817 %res1 = call <4 x float> @llvm.x86.avx512.mask.cvtsd2ss.round(<4 x float> %x0, <2 x double> %x1, <4 x float> %x2, i8 -1, i32 8)8818 %res2 = fadd <4 x float> %res, %res18819 ret <4 x float> %res28820}8821 8822declare <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i32)8823 8824define <16 x i32>@test_int_x86_avx512_pternlog_d_512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2) #0 {8825; CHECK-LABEL: @test_int_x86_avx512_pternlog_d_512(8826; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 88827; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 88828; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 88829; CHECK-NEXT: call void @llvm.donothing()8830; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP1]] to i5128831; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP4]], 08832; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP2]] to i5128833; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP5]], 08834; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]8835; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i32> [[TMP3]] to i5128836; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i512 [[TMP6]], 08837; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]8838; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]8839; CHECK: 7:8840; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]8841; CHECK-NEXT: unreachable8842; CHECK: 8:8843; CHECK-NEXT: [[TMP9:%.*]] = call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> [[X0:%.*]], <16 x i32> [[X1:%.*]], <16 x i32> [[X2:%.*]], i32 33)8844; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 88845; CHECK-NEXT: ret <16 x i32> [[TMP9]]8846;8847 %1 = call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i32 33)8848 ret <16 x i32> %18849}8850 8851define <16 x i32>@test_int_x86_avx512_mask_pternlog_d_512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x4) #0 {8852; CHECK-LABEL: @test_int_x86_avx512_mask_pternlog_d_512(8853; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 88854; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 88855; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 88856; CHECK-NEXT: [[TMP4:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 88857; CHECK-NEXT: call void @llvm.donothing()8858; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP1]] to i5128859; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP5]], 08860; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i32> [[TMP2]] to i5128861; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP6]], 08862; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]8863; CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i32> [[TMP3]] to i5128864; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i512 [[TMP7]], 08865; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]8866; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]8867; CHECK: 8:8868; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]8869; CHECK-NEXT: unreachable8870; CHECK: 9:8871; CHECK-NEXT: [[TMP10:%.*]] = call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> [[X0:%.*]], <16 x i32> [[X1:%.*]], <16 x i32> [[X2:%.*]], i32 33)8872; CHECK-NEXT: [[TMP11:%.*]] = bitcast i16 [[TMP4]] to <16 x i1>8873; CHECK-NEXT: [[TMP12:%.*]] = bitcast i16 [[X4:%.*]] to <16 x i1>8874; CHECK-NEXT: [[TMP13:%.*]] = select <16 x i1> [[TMP12]], <16 x i32> zeroinitializer, <16 x i32> [[TMP1]]8875; CHECK-NEXT: [[TMP14:%.*]] = xor <16 x i32> [[TMP10]], [[X0]]8876; CHECK-NEXT: [[TMP15:%.*]] = or <16 x i32> [[TMP14]], zeroinitializer8877; CHECK-NEXT: [[TMP16:%.*]] = or <16 x i32> [[TMP15]], [[TMP1]]8878; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP11]], <16 x i32> [[TMP16]], <16 x i32> [[TMP13]]8879; CHECK-NEXT: [[TMP17:%.*]] = select <16 x i1> [[TMP12]], <16 x i32> [[TMP10]], <16 x i32> [[X0]]8880; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 88881; CHECK-NEXT: ret <16 x i32> [[TMP17]]8882;8883 %1 = call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i32 33)8884 %2 = bitcast i16 %x4 to <16 x i1>8885 %3 = select <16 x i1> %2, <16 x i32> %1, <16 x i32> %x08886 ret <16 x i32> %38887}8888 8889define <16 x i32>@test_int_x86_avx512_maskz_pternlog_d_512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x4) #0 {8890; CHECK-LABEL: @test_int_x86_avx512_maskz_pternlog_d_512(8891; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 88892; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 88893; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 88894; CHECK-NEXT: [[TMP4:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 88895; CHECK-NEXT: call void @llvm.donothing()8896; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP1]] to i5128897; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP5]], 08898; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i32> [[TMP2]] to i5128899; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP6]], 08900; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]8901; CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i32> [[TMP3]] to i5128902; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i512 [[TMP7]], 08903; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]8904; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]8905; CHECK: 8:8906; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]8907; CHECK-NEXT: unreachable8908; CHECK: 9:8909; CHECK-NEXT: [[TMP10:%.*]] = call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> [[X0:%.*]], <16 x i32> [[X1:%.*]], <16 x i32> [[X2:%.*]], i32 33)8910; CHECK-NEXT: [[TMP11:%.*]] = bitcast i16 [[TMP4]] to <16 x i1>8911; CHECK-NEXT: [[TMP12:%.*]] = bitcast i16 [[X4:%.*]] to <16 x i1>8912; CHECK-NEXT: [[TMP13:%.*]] = select <16 x i1> [[TMP12]], <16 x i32> zeroinitializer, <16 x i32> zeroinitializer8913; CHECK-NEXT: [[TMP14:%.*]] = xor <16 x i32> [[TMP10]], zeroinitializer8914; CHECK-NEXT: [[TMP15:%.*]] = or <16 x i32> [[TMP14]], zeroinitializer8915; CHECK-NEXT: [[TMP16:%.*]] = or <16 x i32> [[TMP15]], zeroinitializer8916; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP11]], <16 x i32> [[TMP16]], <16 x i32> [[TMP13]]8917; CHECK-NEXT: [[TMP17:%.*]] = select <16 x i1> [[TMP12]], <16 x i32> [[TMP10]], <16 x i32> zeroinitializer8918; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 88919; CHECK-NEXT: ret <16 x i32> [[TMP17]]8920;8921 %1 = call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i32 33)8922 %2 = bitcast i16 %x4 to <16 x i1>8923 %3 = select <16 x i1> %2, <16 x i32> %1, <16 x i32> zeroinitializer8924 ret <16 x i32> %38925}8926 8927declare <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i32)8928 8929define <8 x i64>@test_int_x86_avx512_pternlog_q_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2) #0 {8930; CHECK-LABEL: @test_int_x86_avx512_pternlog_q_512(8931; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 88932; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 88933; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 88934; CHECK-NEXT: call void @llvm.donothing()8935; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i64> [[TMP1]] to i5128936; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP4]], 08937; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i64> [[TMP2]] to i5128938; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP5]], 08939; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]8940; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i64> [[TMP3]] to i5128941; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i512 [[TMP6]], 08942; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]8943; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]8944; CHECK: 7:8945; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]8946; CHECK-NEXT: unreachable8947; CHECK: 8:8948; CHECK-NEXT: [[TMP9:%.*]] = call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> [[X0:%.*]], <8 x i64> [[X1:%.*]], <8 x i64> [[X2:%.*]], i32 33)8949; CHECK-NEXT: store <8 x i64> zeroinitializer, ptr @__msan_retval_tls, align 88950; CHECK-NEXT: ret <8 x i64> [[TMP9]]8951;8952 %1 = call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i32 33)8953 ret <8 x i64> %18954}8955 8956define <8 x i64>@test_int_x86_avx512_mask_pternlog_q_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x4) #0 {8957; CHECK-LABEL: @test_int_x86_avx512_mask_pternlog_q_512(8958; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 88959; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 88960; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 88961; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 88962; CHECK-NEXT: call void @llvm.donothing()8963; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i64> [[TMP1]] to i5128964; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP5]], 08965; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i64> [[TMP2]] to i5128966; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP6]], 08967; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]8968; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i64> [[TMP3]] to i5128969; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i512 [[TMP7]], 08970; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]8971; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]8972; CHECK: 8:8973; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]8974; CHECK-NEXT: unreachable8975; CHECK: 9:8976; CHECK-NEXT: [[TMP10:%.*]] = call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> [[X0:%.*]], <8 x i64> [[X1:%.*]], <8 x i64> [[X2:%.*]], i32 33)8977; CHECK-NEXT: [[TMP11:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>8978; CHECK-NEXT: [[TMP12:%.*]] = bitcast i8 [[X4:%.*]] to <8 x i1>8979; CHECK-NEXT: [[TMP13:%.*]] = select <8 x i1> [[TMP12]], <8 x i64> zeroinitializer, <8 x i64> [[TMP1]]8980; CHECK-NEXT: [[TMP14:%.*]] = xor <8 x i64> [[TMP10]], [[X0]]8981; CHECK-NEXT: [[TMP15:%.*]] = or <8 x i64> [[TMP14]], zeroinitializer8982; CHECK-NEXT: [[TMP16:%.*]] = or <8 x i64> [[TMP15]], [[TMP1]]8983; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP11]], <8 x i64> [[TMP16]], <8 x i64> [[TMP13]]8984; CHECK-NEXT: [[TMP17:%.*]] = select <8 x i1> [[TMP12]], <8 x i64> [[TMP10]], <8 x i64> [[X0]]8985; CHECK-NEXT: store <8 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 88986; CHECK-NEXT: ret <8 x i64> [[TMP17]]8987;8988 %1 = call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i32 33)8989 %2 = bitcast i8 %x4 to <8 x i1>8990 %3 = select <8 x i1> %2, <8 x i64> %1, <8 x i64> %x08991 ret <8 x i64> %38992}8993 8994define <8 x i64>@test_int_x86_avx512_maskz_pternlog_q_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x4) #0 {8995; CHECK-LABEL: @test_int_x86_avx512_maskz_pternlog_q_512(8996; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 88997; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 88998; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 88999; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 89000; CHECK-NEXT: call void @llvm.donothing()9001; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i64> [[TMP1]] to i5129002; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP5]], 09003; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i64> [[TMP2]] to i5129004; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP6]], 09005; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]9006; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i64> [[TMP3]] to i5129007; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i512 [[TMP7]], 09008; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]9009; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]9010; CHECK: 8:9011; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]9012; CHECK-NEXT: unreachable9013; CHECK: 9:9014; CHECK-NEXT: [[TMP10:%.*]] = call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> [[X0:%.*]], <8 x i64> [[X1:%.*]], <8 x i64> [[X2:%.*]], i32 33)9015; CHECK-NEXT: [[TMP11:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>9016; CHECK-NEXT: [[TMP12:%.*]] = bitcast i8 [[X4:%.*]] to <8 x i1>9017; CHECK-NEXT: [[TMP13:%.*]] = select <8 x i1> [[TMP12]], <8 x i64> zeroinitializer, <8 x i64> zeroinitializer9018; CHECK-NEXT: [[TMP14:%.*]] = xor <8 x i64> [[TMP10]], zeroinitializer9019; CHECK-NEXT: [[TMP15:%.*]] = or <8 x i64> [[TMP14]], zeroinitializer9020; CHECK-NEXT: [[TMP16:%.*]] = or <8 x i64> [[TMP15]], zeroinitializer9021; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP11]], <8 x i64> [[TMP16]], <8 x i64> [[TMP13]]9022; CHECK-NEXT: [[TMP17:%.*]] = select <8 x i1> [[TMP12]], <8 x i64> [[TMP10]], <8 x i64> zeroinitializer9023; CHECK-NEXT: store <8 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 89024; CHECK-NEXT: ret <8 x i64> [[TMP17]]9025;9026 %1 = call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i32 33)9027 %2 = bitcast i8 %x4 to <8 x i1>9028 %3 = select <8 x i1> %2, <8 x i64> %1, <8 x i64> zeroinitializer9029 ret <8 x i64> %39030}9031 9032define i32 @test_x86_avx512_comi_sd_eq_sae(<2 x double> %a0, <2 x double> %a1) #0 {9033; CHECK-LABEL: @test_x86_avx512_comi_sd_eq_sae(9034; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 89035; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 89036; CHECK-NEXT: call void @llvm.donothing()9037; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP1]] to i1289038; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 09039; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP2]] to i1289040; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 09041; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]9042; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]9043; CHECK: 5:9044; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]9045; CHECK-NEXT: unreachable9046; CHECK: 6:9047; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx512.vcomi.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]], i32 0, i32 8)9048; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 89049; CHECK-NEXT: ret i32 [[RES]]9050;9051 %res = call i32 @llvm.x86.avx512.vcomi.sd(<2 x double> %a0, <2 x double> %a1, i32 0, i32 8)9052 ret i32 %res9053}9054 9055define i32 @test_x86_avx512_ucomi_sd_eq_sae(<2 x double> %a0, <2 x double> %a1) #0 {9056; CHECK-LABEL: @test_x86_avx512_ucomi_sd_eq_sae(9057; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 89058; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 89059; CHECK-NEXT: call void @llvm.donothing()9060; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP1]] to i1289061; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 09062; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP2]] to i1289063; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 09064; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]9065; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]9066; CHECK: 5:9067; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]9068; CHECK-NEXT: unreachable9069; CHECK: 6:9070; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx512.vcomi.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]], i32 8, i32 8)9071; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 89072; CHECK-NEXT: ret i32 [[RES]]9073;9074 %res = call i32 @llvm.x86.avx512.vcomi.sd(<2 x double> %a0, <2 x double> %a1, i32 8, i32 8)9075 ret i32 %res9076}9077 9078define i32 @test_x86_avx512_comi_sd_eq(<2 x double> %a0, <2 x double> %a1) #0 {9079; CHECK-LABEL: @test_x86_avx512_comi_sd_eq(9080; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 89081; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 89082; CHECK-NEXT: call void @llvm.donothing()9083; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP1]] to i1289084; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 09085; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP2]] to i1289086; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 09087; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]9088; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]9089; CHECK: 5:9090; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]9091; CHECK-NEXT: unreachable9092; CHECK: 6:9093; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx512.vcomi.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]], i32 0, i32 4)9094; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 89095; CHECK-NEXT: ret i32 [[RES]]9096;9097 %res = call i32 @llvm.x86.avx512.vcomi.sd(<2 x double> %a0, <2 x double> %a1, i32 0, i32 4)9098 ret i32 %res9099}9100 9101define i32 @test_x86_avx512_ucomi_sd_eq(<2 x double> %a0, <2 x double> %a1) #0 {9102; CHECK-LABEL: @test_x86_avx512_ucomi_sd_eq(9103; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 89104; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 89105; CHECK-NEXT: call void @llvm.donothing()9106; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP1]] to i1289107; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 09108; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP2]] to i1289109; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 09110; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]9111; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]9112; CHECK: 5:9113; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]9114; CHECK-NEXT: unreachable9115; CHECK: 6:9116; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx512.vcomi.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]], i32 8, i32 4)9117; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 89118; CHECK-NEXT: ret i32 [[RES]]9119;9120 %res = call i32 @llvm.x86.avx512.vcomi.sd(<2 x double> %a0, <2 x double> %a1, i32 8, i32 4)9121 ret i32 %res9122}9123 9124define i32 @test_x86_avx512_comi_sd_lt_sae(<2 x double> %a0, <2 x double> %a1) #0 {9125; CHECK-LABEL: @test_x86_avx512_comi_sd_lt_sae(9126; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 89127; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 89128; CHECK-NEXT: call void @llvm.donothing()9129; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP1]] to i1289130; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 09131; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP2]] to i1289132; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 09133; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]9134; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]9135; CHECK: 5:9136; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]9137; CHECK-NEXT: unreachable9138; CHECK: 6:9139; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx512.vcomi.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]], i32 1, i32 8)9140; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 89141; CHECK-NEXT: ret i32 [[RES]]9142;9143 %res = call i32 @llvm.x86.avx512.vcomi.sd(<2 x double> %a0, <2 x double> %a1, i32 1, i32 8)9144 ret i32 %res9145}9146 9147define i32 @test_x86_avx512_ucomi_sd_lt_sae(<2 x double> %a0, <2 x double> %a1) #0 {9148; CHECK-LABEL: @test_x86_avx512_ucomi_sd_lt_sae(9149; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 89150; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 89151; CHECK-NEXT: call void @llvm.donothing()9152; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP1]] to i1289153; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 09154; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP2]] to i1289155; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 09156; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]9157; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]9158; CHECK: 5:9159; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]9160; CHECK-NEXT: unreachable9161; CHECK: 6:9162; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx512.vcomi.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]], i32 9, i32 8)9163; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 89164; CHECK-NEXT: ret i32 [[RES]]9165;9166 %res = call i32 @llvm.x86.avx512.vcomi.sd(<2 x double> %a0, <2 x double> %a1, i32 9, i32 8)9167 ret i32 %res9168}9169 9170define i32 @test_x86_avx512_comi_sd_lt(<2 x double> %a0, <2 x double> %a1) #0 {9171; CHECK-LABEL: @test_x86_avx512_comi_sd_lt(9172; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 89173; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 89174; CHECK-NEXT: call void @llvm.donothing()9175; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP1]] to i1289176; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 09177; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP2]] to i1289178; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 09179; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]9180; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]9181; CHECK: 5:9182; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]9183; CHECK-NEXT: unreachable9184; CHECK: 6:9185; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx512.vcomi.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]], i32 1, i32 4)9186; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 89187; CHECK-NEXT: ret i32 [[RES]]9188;9189 %res = call i32 @llvm.x86.avx512.vcomi.sd(<2 x double> %a0, <2 x double> %a1, i32 1, i32 4)9190 ret i32 %res9191}9192 9193define i32 @test_x86_avx512_ucomi_sd_lt(<2 x double> %a0, <2 x double> %a1) #0 {9194; CHECK-LABEL: @test_x86_avx512_ucomi_sd_lt(9195; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 89196; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 89197; CHECK-NEXT: call void @llvm.donothing()9198; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP1]] to i1289199; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 09200; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP2]] to i1289201; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 09202; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]9203; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]9204; CHECK: 5:9205; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]9206; CHECK-NEXT: unreachable9207; CHECK: 6:9208; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx512.vcomi.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]], i32 9, i32 4)9209; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 89210; CHECK-NEXT: ret i32 [[RES]]9211;9212 %res = call i32 @llvm.x86.avx512.vcomi.sd(<2 x double> %a0, <2 x double> %a1, i32 9, i32 4)9213 ret i32 %res9214}9215 9216declare i32 @llvm.x86.avx512.vcomi.sd(<2 x double>, <2 x double>, i32, i32)9217 9218define i32 @test_x86_avx512_ucomi_ss_lt(<4 x float> %a0, <4 x float> %a1) #0 {9219; CHECK-LABEL: @test_x86_avx512_ucomi_ss_lt(9220; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 89221; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 89222; CHECK-NEXT: call void @llvm.donothing()9223; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP1]] to i1289224; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 09225; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i1289226; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 09227; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]9228; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]9229; CHECK: 5:9230; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]9231; CHECK-NEXT: unreachable9232; CHECK: 6:9233; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx512.vcomi.ss(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], i32 9, i32 4)9234; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 89235; CHECK-NEXT: ret i32 [[RES]]9236;9237 %res = call i32 @llvm.x86.avx512.vcomi.ss(<4 x float> %a0, <4 x float> %a1, i32 9, i32 4)9238 ret i32 %res9239}9240 9241declare i32 @llvm.x86.avx512.vcomi.ss(<4 x float>, <4 x float>, i32, i32)9242 9243declare <8 x double> @llvm.x86.avx512.permvar.df.512(<8 x double>, <8 x i64>)9244 9245define <8 x double>@test_int_x86_avx512_permvar_df_512(<8 x double> %x0, <8 x i64> %x1) #0 {9246; CHECK-LABEL: @test_int_x86_avx512_permvar_df_512(9247; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 89248; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 89249; CHECK-NEXT: call void @llvm.donothing()9250; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i64> [[TMP1]] to i5129251; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP3]], 09252; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i64> [[TMP2]] to i5129253; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 09254; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]9255; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]9256; CHECK: 5:9257; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]9258; CHECK-NEXT: unreachable9259; CHECK: 6:9260; CHECK-NEXT: [[TMP7:%.*]] = call <8 x double> @llvm.x86.avx512.permvar.df.512(<8 x double> [[X0:%.*]], <8 x i64> [[X1:%.*]])9261; CHECK-NEXT: store <8 x i64> zeroinitializer, ptr @__msan_retval_tls, align 89262; CHECK-NEXT: ret <8 x double> [[TMP7]]9263;9264 %1 = call <8 x double> @llvm.x86.avx512.permvar.df.512(<8 x double> %x0, <8 x i64> %x1)9265 ret <8 x double> %19266}9267 9268define <8 x double>@test_int_x86_avx512_mask_permvar_df_512(<8 x double> %x0, <8 x i64> %x1, <8 x double> %x2, i8 %x3) #0 {9269; CHECK-LABEL: @test_int_x86_avx512_mask_permvar_df_512(9270; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 89271; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 89272; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 89273; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 89274; CHECK-NEXT: call void @llvm.donothing()9275; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i64> [[TMP1]] to i5129276; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP5]], 09277; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i64> [[TMP2]] to i5129278; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP6]], 09279; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]9280; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]9281; CHECK: 7:9282; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]9283; CHECK-NEXT: unreachable9284; CHECK: 8:9285; CHECK-NEXT: [[TMP9:%.*]] = call <8 x double> @llvm.x86.avx512.permvar.df.512(<8 x double> [[X0:%.*]], <8 x i64> [[X1:%.*]])9286; CHECK-NEXT: [[TMP10:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>9287; CHECK-NEXT: [[TMP11:%.*]] = bitcast i8 [[X3:%.*]] to <8 x i1>9288; CHECK-NEXT: [[TMP12:%.*]] = select <8 x i1> [[TMP11]], <8 x i64> zeroinitializer, <8 x i64> [[TMP4]]9289; CHECK-NEXT: [[TMP13:%.*]] = bitcast <8 x double> [[TMP9]] to <8 x i64>9290; CHECK-NEXT: [[TMP14:%.*]] = bitcast <8 x double> [[X2:%.*]] to <8 x i64>9291; CHECK-NEXT: [[TMP15:%.*]] = xor <8 x i64> [[TMP13]], [[TMP14]]9292; CHECK-NEXT: [[TMP16:%.*]] = or <8 x i64> [[TMP15]], zeroinitializer9293; CHECK-NEXT: [[TMP17:%.*]] = or <8 x i64> [[TMP16]], [[TMP4]]9294; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP10]], <8 x i64> [[TMP17]], <8 x i64> [[TMP12]]9295; CHECK-NEXT: [[TMP18:%.*]] = select <8 x i1> [[TMP11]], <8 x double> [[TMP9]], <8 x double> [[X2]]9296; CHECK-NEXT: store <8 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 89297; CHECK-NEXT: ret <8 x double> [[TMP18]]9298;9299 %1 = call <8 x double> @llvm.x86.avx512.permvar.df.512(<8 x double> %x0, <8 x i64> %x1)9300 %2 = bitcast i8 %x3 to <8 x i1>9301 %3 = select <8 x i1> %2, <8 x double> %1, <8 x double> %x29302 ret <8 x double> %39303}9304 9305define <8 x double>@test_int_x86_avx512_maskz_permvar_df_512(<8 x double> %x0, <8 x i64> %x1, i8 %x3) #0 {9306; CHECK-LABEL: @test_int_x86_avx512_maskz_permvar_df_512(9307; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 89308; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 89309; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 89310; CHECK-NEXT: call void @llvm.donothing()9311; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i64> [[TMP1]] to i5129312; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP4]], 09313; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i64> [[TMP2]] to i5129314; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP5]], 09315; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]9316; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]9317; CHECK: 6:9318; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]9319; CHECK-NEXT: unreachable9320; CHECK: 7:9321; CHECK-NEXT: [[TMP8:%.*]] = call <8 x double> @llvm.x86.avx512.permvar.df.512(<8 x double> [[X0:%.*]], <8 x i64> [[X1:%.*]])9322; CHECK-NEXT: [[TMP9:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>9323; CHECK-NEXT: [[TMP10:%.*]] = bitcast i8 [[X3:%.*]] to <8 x i1>9324; CHECK-NEXT: [[TMP11:%.*]] = select <8 x i1> [[TMP10]], <8 x i64> zeroinitializer, <8 x i64> zeroinitializer9325; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x double> [[TMP8]] to <8 x i64>9326; CHECK-NEXT: [[TMP13:%.*]] = xor <8 x i64> [[TMP12]], zeroinitializer9327; CHECK-NEXT: [[TMP14:%.*]] = or <8 x i64> [[TMP13]], zeroinitializer9328; CHECK-NEXT: [[TMP15:%.*]] = or <8 x i64> [[TMP14]], zeroinitializer9329; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP9]], <8 x i64> [[TMP15]], <8 x i64> [[TMP11]]9330; CHECK-NEXT: [[TMP16:%.*]] = select <8 x i1> [[TMP10]], <8 x double> [[TMP8]], <8 x double> zeroinitializer9331; CHECK-NEXT: store <8 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 89332; CHECK-NEXT: ret <8 x double> [[TMP16]]9333;9334 %1 = call <8 x double> @llvm.x86.avx512.permvar.df.512(<8 x double> %x0, <8 x i64> %x1)9335 %2 = bitcast i8 %x3 to <8 x i1>9336 %3 = select <8 x i1> %2, <8 x double> %1, <8 x double> zeroinitializer9337 ret <8 x double> %39338}9339 9340declare <8 x i64> @llvm.x86.avx512.permvar.di.512(<8 x i64>, <8 x i64>)9341 9342define <8 x i64>@test_int_x86_avx512_permvar_di_512(<8 x i64> %x0, <8 x i64> %x1) #0 {9343; CHECK-LABEL: @test_int_x86_avx512_permvar_di_512(9344; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 89345; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 89346; CHECK-NEXT: call void @llvm.donothing()9347; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i64> [[TMP1]], [[TMP2]]9348; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i64> @llvm.x86.avx512.permvar.di.512(<8 x i64> [[X0:%.*]], <8 x i64> [[X1:%.*]])9349; CHECK-NEXT: store <8 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 89350; CHECK-NEXT: ret <8 x i64> [[TMP3]]9351;9352 %1 = call <8 x i64> @llvm.x86.avx512.permvar.di.512(<8 x i64> %x0, <8 x i64> %x1)9353 ret <8 x i64> %19354}9355 9356define <8 x i64>@test_int_x86_avx512_mask_permvar_di_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) #0 {9357; CHECK-LABEL: @test_int_x86_avx512_mask_permvar_di_512(9358; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 89359; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 89360; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 89361; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 89362; CHECK-NEXT: call void @llvm.donothing()9363; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i64> [[TMP1]], [[TMP2]]9364; CHECK-NEXT: [[TMP5:%.*]] = call <8 x i64> @llvm.x86.avx512.permvar.di.512(<8 x i64> [[X0:%.*]], <8 x i64> [[X1:%.*]])9365; CHECK-NEXT: [[TMP6:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>9366; CHECK-NEXT: [[TMP7:%.*]] = bitcast i8 [[X3:%.*]] to <8 x i1>9367; CHECK-NEXT: [[TMP8:%.*]] = select <8 x i1> [[TMP7]], <8 x i64> [[_MSPROP]], <8 x i64> [[TMP4]]9368; CHECK-NEXT: [[TMP9:%.*]] = xor <8 x i64> [[TMP5]], [[X2:%.*]]9369; CHECK-NEXT: [[TMP10:%.*]] = or <8 x i64> [[TMP9]], [[_MSPROP]]9370; CHECK-NEXT: [[TMP11:%.*]] = or <8 x i64> [[TMP10]], [[TMP4]]9371; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP6]], <8 x i64> [[TMP11]], <8 x i64> [[TMP8]]9372; CHECK-NEXT: [[TMP12:%.*]] = select <8 x i1> [[TMP7]], <8 x i64> [[TMP5]], <8 x i64> [[X2]]9373; CHECK-NEXT: store <8 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 89374; CHECK-NEXT: ret <8 x i64> [[TMP12]]9375;9376 %1 = call <8 x i64> @llvm.x86.avx512.permvar.di.512(<8 x i64> %x0, <8 x i64> %x1)9377 %2 = bitcast i8 %x3 to <8 x i1>9378 %3 = select <8 x i1> %2, <8 x i64> %1, <8 x i64> %x29379 ret <8 x i64> %39380}9381 9382define <8 x i64>@test_int_x86_avx512_maskz_permvar_di_512(<8 x i64> %x0, <8 x i64> %x1, i8 %x3) #0 {9383; CHECK-LABEL: @test_int_x86_avx512_maskz_permvar_di_512(9384; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 89385; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 89386; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 89387; CHECK-NEXT: call void @llvm.donothing()9388; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i64> [[TMP1]], [[TMP2]]9389; CHECK-NEXT: [[TMP4:%.*]] = call <8 x i64> @llvm.x86.avx512.permvar.di.512(<8 x i64> [[X0:%.*]], <8 x i64> [[X1:%.*]])9390; CHECK-NEXT: [[TMP5:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>9391; CHECK-NEXT: [[TMP6:%.*]] = bitcast i8 [[X3:%.*]] to <8 x i1>9392; CHECK-NEXT: [[TMP7:%.*]] = select <8 x i1> [[TMP6]], <8 x i64> [[_MSPROP]], <8 x i64> zeroinitializer9393; CHECK-NEXT: [[TMP8:%.*]] = xor <8 x i64> [[TMP4]], zeroinitializer9394; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i64> [[TMP8]], [[_MSPROP]]9395; CHECK-NEXT: [[TMP10:%.*]] = or <8 x i64> [[TMP9]], zeroinitializer9396; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP5]], <8 x i64> [[TMP10]], <8 x i64> [[TMP7]]9397; CHECK-NEXT: [[TMP11:%.*]] = select <8 x i1> [[TMP6]], <8 x i64> [[TMP4]], <8 x i64> zeroinitializer9398; CHECK-NEXT: store <8 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 89399; CHECK-NEXT: ret <8 x i64> [[TMP11]]9400;9401 %1 = call <8 x i64> @llvm.x86.avx512.permvar.di.512(<8 x i64> %x0, <8 x i64> %x1)9402 %2 = bitcast i8 %x3 to <8 x i1>9403 %3 = select <8 x i1> %2, <8 x i64> %1, <8 x i64> zeroinitializer9404 ret <8 x i64> %39405}9406 9407declare <16 x float> @llvm.x86.avx512.permvar.sf.512(<16 x float>, <16 x i32>)9408 9409define <16 x float>@test_int_x86_avx512_permvar_sf_512(<16 x float> %x0, <16 x i32> %x1) #0 {9410; CHECK-LABEL: @test_int_x86_avx512_permvar_sf_512(9411; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 89412; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 89413; CHECK-NEXT: call void @llvm.donothing()9414; CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i32> [[TMP1]] to i5129415; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP3]], 09416; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP2]] to i5129417; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP4]], 09418; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]9419; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]9420; CHECK: 5:9421; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]9422; CHECK-NEXT: unreachable9423; CHECK: 6:9424; CHECK-NEXT: [[TMP7:%.*]] = call <16 x float> @llvm.x86.avx512.permvar.sf.512(<16 x float> [[X0:%.*]], <16 x i32> [[X1:%.*]])9425; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 89426; CHECK-NEXT: ret <16 x float> [[TMP7]]9427;9428 %1 = call <16 x float> @llvm.x86.avx512.permvar.sf.512(<16 x float> %x0, <16 x i32> %x1)9429 ret <16 x float> %19430}9431 9432define <16 x float>@test_int_x86_avx512_mask_permvar_sf_512(<16 x float> %x0, <16 x i32> %x1, <16 x float> %x2, i16 %x3) #0 {9433; CHECK-LABEL: @test_int_x86_avx512_mask_permvar_sf_512(9434; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 89435; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 89436; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 89437; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 89438; CHECK-NEXT: call void @llvm.donothing()9439; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP1]] to i5129440; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP5]], 09441; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i32> [[TMP2]] to i5129442; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP6]], 09443; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]9444; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]9445; CHECK: 7:9446; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]9447; CHECK-NEXT: unreachable9448; CHECK: 8:9449; CHECK-NEXT: [[TMP9:%.*]] = call <16 x float> @llvm.x86.avx512.permvar.sf.512(<16 x float> [[X0:%.*]], <16 x i32> [[X1:%.*]])9450; CHECK-NEXT: [[TMP10:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>9451; CHECK-NEXT: [[TMP11:%.*]] = bitcast i16 [[X3:%.*]] to <16 x i1>9452; CHECK-NEXT: [[TMP12:%.*]] = select <16 x i1> [[TMP11]], <16 x i32> zeroinitializer, <16 x i32> [[TMP4]]9453; CHECK-NEXT: [[TMP13:%.*]] = bitcast <16 x float> [[TMP9]] to <16 x i32>9454; CHECK-NEXT: [[TMP14:%.*]] = bitcast <16 x float> [[X2:%.*]] to <16 x i32>9455; CHECK-NEXT: [[TMP15:%.*]] = xor <16 x i32> [[TMP13]], [[TMP14]]9456; CHECK-NEXT: [[TMP16:%.*]] = or <16 x i32> [[TMP15]], zeroinitializer9457; CHECK-NEXT: [[TMP17:%.*]] = or <16 x i32> [[TMP16]], [[TMP4]]9458; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP10]], <16 x i32> [[TMP17]], <16 x i32> [[TMP12]]9459; CHECK-NEXT: [[TMP18:%.*]] = select <16 x i1> [[TMP11]], <16 x float> [[TMP9]], <16 x float> [[X2]]9460; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 89461; CHECK-NEXT: ret <16 x float> [[TMP18]]9462;9463 %1 = call <16 x float> @llvm.x86.avx512.permvar.sf.512(<16 x float> %x0, <16 x i32> %x1)9464 %2 = bitcast i16 %x3 to <16 x i1>9465 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> %x29466 ret <16 x float> %39467}9468 9469define <16 x float>@test_int_x86_avx512_maskz_permvar_sf_512(<16 x float> %x0, <16 x i32> %x1, i16 %x3) #0 {9470; CHECK-LABEL: @test_int_x86_avx512_maskz_permvar_sf_512(9471; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 89472; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 89473; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 89474; CHECK-NEXT: call void @llvm.donothing()9475; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP1]] to i5129476; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP4]], 09477; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP2]] to i5129478; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP5]], 09479; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]9480; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]9481; CHECK: 6:9482; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]9483; CHECK-NEXT: unreachable9484; CHECK: 7:9485; CHECK-NEXT: [[TMP8:%.*]] = call <16 x float> @llvm.x86.avx512.permvar.sf.512(<16 x float> [[X0:%.*]], <16 x i32> [[X1:%.*]])9486; CHECK-NEXT: [[TMP9:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>9487; CHECK-NEXT: [[TMP10:%.*]] = bitcast i16 [[X3:%.*]] to <16 x i1>9488; CHECK-NEXT: [[TMP11:%.*]] = select <16 x i1> [[TMP10]], <16 x i32> zeroinitializer, <16 x i32> zeroinitializer9489; CHECK-NEXT: [[TMP12:%.*]] = bitcast <16 x float> [[TMP8]] to <16 x i32>9490; CHECK-NEXT: [[TMP13:%.*]] = xor <16 x i32> [[TMP12]], zeroinitializer9491; CHECK-NEXT: [[TMP14:%.*]] = or <16 x i32> [[TMP13]], zeroinitializer9492; CHECK-NEXT: [[TMP15:%.*]] = or <16 x i32> [[TMP14]], zeroinitializer9493; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP9]], <16 x i32> [[TMP15]], <16 x i32> [[TMP11]]9494; CHECK-NEXT: [[TMP16:%.*]] = select <16 x i1> [[TMP10]], <16 x float> [[TMP8]], <16 x float> zeroinitializer9495; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 89496; CHECK-NEXT: ret <16 x float> [[TMP16]]9497;9498 %1 = call <16 x float> @llvm.x86.avx512.permvar.sf.512(<16 x float> %x0, <16 x i32> %x1)9499 %2 = bitcast i16 %x3 to <16 x i1>9500 %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> zeroinitializer9501 ret <16 x float> %39502}9503 9504declare <16 x i32> @llvm.x86.avx512.permvar.si.512(<16 x i32>, <16 x i32>)9505 9506define <16 x i32>@test_int_x86_avx512_permvar_si_512(<16 x i32> %x0, <16 x i32> %x1) #0 {9507; CHECK-LABEL: @test_int_x86_avx512_permvar_si_512(9508; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 89509; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 89510; CHECK-NEXT: call void @llvm.donothing()9511; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i32> [[TMP1]], [[TMP2]]9512; CHECK-NEXT: [[TMP3:%.*]] = call <16 x i32> @llvm.x86.avx512.permvar.si.512(<16 x i32> [[X0:%.*]], <16 x i32> [[X1:%.*]])9513; CHECK-NEXT: store <16 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 89514; CHECK-NEXT: ret <16 x i32> [[TMP3]]9515;9516 %1 = call <16 x i32> @llvm.x86.avx512.permvar.si.512(<16 x i32> %x0, <16 x i32> %x1)9517 ret <16 x i32> %19518}9519 9520define <16 x i32>@test_int_x86_avx512_mask_permvar_si_512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3) #0 {9521; CHECK-LABEL: @test_int_x86_avx512_mask_permvar_si_512(9522; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 89523; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 89524; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 89525; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 89526; CHECK-NEXT: call void @llvm.donothing()9527; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i32> [[TMP1]], [[TMP2]]9528; CHECK-NEXT: [[TMP5:%.*]] = call <16 x i32> @llvm.x86.avx512.permvar.si.512(<16 x i32> [[X0:%.*]], <16 x i32> [[X1:%.*]])9529; CHECK-NEXT: [[TMP6:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>9530; CHECK-NEXT: [[TMP7:%.*]] = bitcast i16 [[X3:%.*]] to <16 x i1>9531; CHECK-NEXT: [[TMP8:%.*]] = select <16 x i1> [[TMP7]], <16 x i32> [[_MSPROP]], <16 x i32> [[TMP4]]9532; CHECK-NEXT: [[TMP9:%.*]] = xor <16 x i32> [[TMP5]], [[X2:%.*]]9533; CHECK-NEXT: [[TMP10:%.*]] = or <16 x i32> [[TMP9]], [[_MSPROP]]9534; CHECK-NEXT: [[TMP11:%.*]] = or <16 x i32> [[TMP10]], [[TMP4]]9535; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP6]], <16 x i32> [[TMP11]], <16 x i32> [[TMP8]]9536; CHECK-NEXT: [[TMP12:%.*]] = select <16 x i1> [[TMP7]], <16 x i32> [[TMP5]], <16 x i32> [[X2]]9537; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 89538; CHECK-NEXT: ret <16 x i32> [[TMP12]]9539;9540 %1 = call <16 x i32> @llvm.x86.avx512.permvar.si.512(<16 x i32> %x0, <16 x i32> %x1)9541 %2 = bitcast i16 %x3 to <16 x i1>9542 %3 = select <16 x i1> %2, <16 x i32> %1, <16 x i32> %x29543 ret <16 x i32> %39544}9545 9546define <16 x i32>@test_int_x86_avx512_maskz_permvar_si_512(<16 x i32> %x0, <16 x i32> %x1, i16 %x3) #0 {9547; CHECK-LABEL: @test_int_x86_avx512_maskz_permvar_si_512(9548; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 89549; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 89550; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 89551; CHECK-NEXT: call void @llvm.donothing()9552; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i32> [[TMP1]], [[TMP2]]9553; CHECK-NEXT: [[TMP4:%.*]] = call <16 x i32> @llvm.x86.avx512.permvar.si.512(<16 x i32> [[X0:%.*]], <16 x i32> [[X1:%.*]])9554; CHECK-NEXT: [[TMP5:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>9555; CHECK-NEXT: [[TMP6:%.*]] = bitcast i16 [[X3:%.*]] to <16 x i1>9556; CHECK-NEXT: [[TMP7:%.*]] = select <16 x i1> [[TMP6]], <16 x i32> [[_MSPROP]], <16 x i32> zeroinitializer9557; CHECK-NEXT: [[TMP8:%.*]] = xor <16 x i32> [[TMP4]], zeroinitializer9558; CHECK-NEXT: [[TMP9:%.*]] = or <16 x i32> [[TMP8]], [[_MSPROP]]9559; CHECK-NEXT: [[TMP10:%.*]] = or <16 x i32> [[TMP9]], zeroinitializer9560; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP5]], <16 x i32> [[TMP10]], <16 x i32> [[TMP7]]9561; CHECK-NEXT: [[TMP11:%.*]] = select <16 x i1> [[TMP6]], <16 x i32> [[TMP4]], <16 x i32> zeroinitializer9562; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 89563; CHECK-NEXT: ret <16 x i32> [[TMP11]]9564;9565 %1 = call <16 x i32> @llvm.x86.avx512.permvar.si.512(<16 x i32> %x0, <16 x i32> %x1)9566 %2 = bitcast i16 %x3 to <16 x i1>9567 %3 = select <16 x i1> %2, <16 x i32> %1, <16 x i32> zeroinitializer9568 ret <16 x i32> %39569}9570 9571declare <8 x double> @llvm.x86.avx512.mask.fixupimm.pd.512(<8 x double>, <8 x double>, <8 x i64>, i32, i8, i32)9572 9573define <8 x double>@test_int_x86_avx512_mask_fixupimm_pd_512(<8 x double> %x0, <8 x double> %x1, <8 x i64> %x2, i8 %x4) #0 {9574; CHECK-LABEL: @test_int_x86_avx512_mask_fixupimm_pd_512(9575; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 89576; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 89577; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 89578; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 89579; CHECK-NEXT: call void @llvm.donothing()9580; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i64> [[TMP1]] to i5129581; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP5]], 09582; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i64> [[TMP2]] to i5129583; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP6]], 09584; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]9585; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i64> [[TMP3]] to i5129586; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i512 [[TMP7]], 09587; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]9588; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 09589; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]9590; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]9591; CHECK: 8:9592; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]9593; CHECK-NEXT: unreachable9594; CHECK: 9:9595; CHECK-NEXT: [[RES:%.*]] = call <8 x double> @llvm.x86.avx512.mask.fixupimm.pd.512(<8 x double> [[X0:%.*]], <8 x double> [[X1:%.*]], <8 x i64> [[X2:%.*]], i32 4, i8 [[X4:%.*]], i32 4)9596; CHECK-NEXT: [[TMP10:%.*]] = bitcast <8 x i64> [[TMP2]] to i5129597; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i512 [[TMP10]], 09598; CHECK-NEXT: [[TMP11:%.*]] = bitcast <8 x i64> [[TMP3]] to i5129599; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i512 [[TMP11]], 09600; CHECK-NEXT: [[_MSOR8:%.*]] = or i1 [[_MSCMP6]], [[_MSCMP7]]9601; CHECK-NEXT: [[_MSCMP9:%.*]] = icmp ne i8 [[TMP4]], 09602; CHECK-NEXT: [[_MSOR10:%.*]] = or i1 [[_MSOR8]], [[_MSCMP9]]9603; CHECK-NEXT: br i1 [[_MSOR10]], label [[TMP12:%.*]], label [[TMP13:%.*]], !prof [[PROF1]]9604; CHECK: 12:9605; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]9606; CHECK-NEXT: unreachable9607; CHECK: 13:9608; CHECK-NEXT: [[RES1:%.*]] = call <8 x double> @llvm.x86.avx512.mask.fixupimm.pd.512(<8 x double> zeroinitializer, <8 x double> [[X1]], <8 x i64> [[X2]], i32 5, i8 [[X4]], i32 4)9609; CHECK-NEXT: [[TMP14:%.*]] = bitcast <8 x i64> [[TMP1]] to i5129610; CHECK-NEXT: [[_MSCMP11:%.*]] = icmp ne i512 [[TMP14]], 09611; CHECK-NEXT: [[TMP15:%.*]] = bitcast <8 x i64> [[TMP2]] to i5129612; CHECK-NEXT: [[_MSCMP12:%.*]] = icmp ne i512 [[TMP15]], 09613; CHECK-NEXT: [[_MSOR13:%.*]] = or i1 [[_MSCMP11]], [[_MSCMP12]]9614; CHECK-NEXT: [[TMP16:%.*]] = bitcast <8 x i64> [[TMP3]] to i5129615; CHECK-NEXT: [[_MSCMP14:%.*]] = icmp ne i512 [[TMP16]], 09616; CHECK-NEXT: [[_MSOR15:%.*]] = or i1 [[_MSOR13]], [[_MSCMP14]]9617; CHECK-NEXT: br i1 [[_MSOR15]], label [[TMP17:%.*]], label [[TMP18:%.*]], !prof [[PROF1]]9618; CHECK: 17:9619; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]9620; CHECK-NEXT: unreachable9621; CHECK: 18:9622; CHECK-NEXT: [[RES2:%.*]] = call <8 x double> @llvm.x86.avx512.mask.fixupimm.pd.512(<8 x double> [[X0]], <8 x double> [[X1]], <8 x i64> [[X2]], i32 3, i8 -1, i32 8)9623; CHECK-NEXT: [[RES3:%.*]] = fadd <8 x double> [[RES]], [[RES1]]9624; CHECK-NEXT: [[RES4:%.*]] = fadd <8 x double> [[RES3]], [[RES2]]9625; CHECK-NEXT: store <8 x i64> zeroinitializer, ptr @__msan_retval_tls, align 89626; CHECK-NEXT: ret <8 x double> [[RES4]]9627;9628 %res = call <8 x double> @llvm.x86.avx512.mask.fixupimm.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x i64> %x2, i32 4, i8 %x4, i32 4)9629 %res1 = call <8 x double> @llvm.x86.avx512.mask.fixupimm.pd.512(<8 x double> zeroinitializer, <8 x double> %x1, <8 x i64> %x2, i32 5, i8 %x4, i32 4)9630 %res2 = call <8 x double> @llvm.x86.avx512.mask.fixupimm.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x i64> %x2, i32 3, i8 -1, i32 8)9631 %res3 = fadd <8 x double> %res, %res19632 %res4 = fadd <8 x double> %res3, %res29633 ret <8 x double> %res49634}9635 9636define <8 x double>@test_int_x86_avx512_mask_fixupimm_pd_512_load(<8 x double> %x0, <8 x double> %x1, ptr %x2ptr) #0 {9637; CHECK-LABEL: @test_int_x86_avx512_mask_fixupimm_pd_512_load(9638; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 89639; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 89640; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 89641; CHECK-NEXT: call void @llvm.donothing()9642; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 09643; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF1]]9644; CHECK: 4:9645; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]9646; CHECK-NEXT: unreachable9647; CHECK: 5:9648; CHECK-NEXT: [[X2:%.*]] = load <8 x i64>, ptr [[X2PTR:%.*]], align 649649; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[X2PTR]] to i649650; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 879609302220809651; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr9652; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i64>, ptr [[TMP8]], align 649653; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i64> [[TMP2]] to i5129654; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP9]], 09655; CHECK-NEXT: [[TMP10:%.*]] = bitcast <8 x i64> [[TMP3]] to i5129656; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i512 [[TMP10]], 09657; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP1]], [[_MSCMP2]]9658; CHECK-NEXT: [[TMP11:%.*]] = bitcast <8 x i64> [[_MSLD]] to i5129659; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i512 [[TMP11]], 09660; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSOR]], [[_MSCMP3]]9661; CHECK-NEXT: br i1 [[_MSOR4]], label [[TMP12:%.*]], label [[TMP13:%.*]], !prof [[PROF1]]9662; CHECK: 12:9663; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]9664; CHECK-NEXT: unreachable9665; CHECK: 13:9666; CHECK-NEXT: [[RES:%.*]] = call <8 x double> @llvm.x86.avx512.mask.fixupimm.pd.512(<8 x double> [[X0:%.*]], <8 x double> [[X1:%.*]], <8 x i64> [[X2]], i32 3, i8 -1, i32 4)9667; CHECK-NEXT: store <8 x i64> zeroinitializer, ptr @__msan_retval_tls, align 89668; CHECK-NEXT: ret <8 x double> [[RES]]9669;9670 %x2 = load <8 x i64>, ptr %x2ptr9671 %res = call <8 x double> @llvm.x86.avx512.mask.fixupimm.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x i64> %x2, i32 3, i8 -1, i32 4)9672 ret <8 x double> %res9673}9674 9675declare <8 x double> @llvm.x86.avx512.maskz.fixupimm.pd.512(<8 x double>, <8 x double>, <8 x i64>, i32, i8, i32)9676 9677define <8 x double>@test_int_x86_avx512_maskz_fixupimm_pd_512(<8 x double> %x0, <8 x double> %x1, <8 x i64> %x2, i8 %x4) #0 {9678; CHECK-LABEL: @test_int_x86_avx512_maskz_fixupimm_pd_512(9679; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 89680; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 89681; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 89682; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 89683; CHECK-NEXT: call void @llvm.donothing()9684; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i64> [[TMP1]] to i5129685; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP5]], 09686; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i64> [[TMP2]] to i5129687; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP6]], 09688; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]9689; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i64> [[TMP3]] to i5129690; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i512 [[TMP7]], 09691; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]9692; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 09693; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]9694; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]9695; CHECK: 8:9696; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]9697; CHECK-NEXT: unreachable9698; CHECK: 9:9699; CHECK-NEXT: [[RES:%.*]] = call <8 x double> @llvm.x86.avx512.maskz.fixupimm.pd.512(<8 x double> [[X0:%.*]], <8 x double> [[X1:%.*]], <8 x i64> [[X2:%.*]], i32 3, i8 [[X4:%.*]], i32 4)9700; CHECK-NEXT: [[TMP10:%.*]] = bitcast <8 x i64> [[TMP1]] to i5129701; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i512 [[TMP10]], 09702; CHECK-NEXT: [[TMP11:%.*]] = bitcast <8 x i64> [[TMP2]] to i5129703; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i512 [[TMP11]], 09704; CHECK-NEXT: [[_MSOR8:%.*]] = or i1 [[_MSCMP6]], [[_MSCMP7]]9705; CHECK-NEXT: [[_MSCMP9:%.*]] = icmp ne i8 [[TMP4]], 09706; CHECK-NEXT: [[_MSOR10:%.*]] = or i1 [[_MSOR8]], [[_MSCMP9]]9707; CHECK-NEXT: br i1 [[_MSOR10]], label [[TMP12:%.*]], label [[TMP13:%.*]], !prof [[PROF1]]9708; CHECK: 12:9709; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]9710; CHECK-NEXT: unreachable9711; CHECK: 13:9712; CHECK-NEXT: [[RES1:%.*]] = call <8 x double> @llvm.x86.avx512.maskz.fixupimm.pd.512(<8 x double> [[X0]], <8 x double> [[X1]], <8 x i64> zeroinitializer, i32 5, i8 [[X4]], i32 4)9713; CHECK-NEXT: [[TMP14:%.*]] = bitcast <8 x i64> [[TMP1]] to i5129714; CHECK-NEXT: [[_MSCMP11:%.*]] = icmp ne i512 [[TMP14]], 09715; CHECK-NEXT: [[TMP15:%.*]] = bitcast <8 x i64> [[TMP2]] to i5129716; CHECK-NEXT: [[_MSCMP12:%.*]] = icmp ne i512 [[TMP15]], 09717; CHECK-NEXT: [[_MSOR13:%.*]] = or i1 [[_MSCMP11]], [[_MSCMP12]]9718; CHECK-NEXT: [[TMP16:%.*]] = bitcast <8 x i64> [[TMP3]] to i5129719; CHECK-NEXT: [[_MSCMP14:%.*]] = icmp ne i512 [[TMP16]], 09720; CHECK-NEXT: [[_MSOR15:%.*]] = or i1 [[_MSOR13]], [[_MSCMP14]]9721; CHECK-NEXT: br i1 [[_MSOR15]], label [[TMP17:%.*]], label [[TMP18:%.*]], !prof [[PROF1]]9722; CHECK: 17:9723; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]9724; CHECK-NEXT: unreachable9725; CHECK: 18:9726; CHECK-NEXT: [[RES2:%.*]] = call <8 x double> @llvm.x86.avx512.maskz.fixupimm.pd.512(<8 x double> [[X0]], <8 x double> [[X1]], <8 x i64> [[X2]], i32 2, i8 -1, i32 8)9727; CHECK-NEXT: [[RES3:%.*]] = fadd <8 x double> [[RES]], [[RES1]]9728; CHECK-NEXT: [[RES4:%.*]] = fadd <8 x double> [[RES3]], [[RES2]]9729; CHECK-NEXT: store <8 x i64> zeroinitializer, ptr @__msan_retval_tls, align 89730; CHECK-NEXT: ret <8 x double> [[RES4]]9731;9732 %res = call <8 x double> @llvm.x86.avx512.maskz.fixupimm.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x i64> %x2, i32 3, i8 %x4, i32 4)9733 %res1 = call <8 x double> @llvm.x86.avx512.maskz.fixupimm.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x i64> zeroinitializer, i32 5, i8 %x4, i32 4)9734 %res2 = call <8 x double> @llvm.x86.avx512.maskz.fixupimm.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x i64> %x2, i32 2, i8 -1, i32 8)9735 %res3 = fadd <8 x double> %res, %res19736 %res4 = fadd <8 x double> %res3, %res29737 ret <8 x double> %res49738}9739 9740declare <4 x float> @llvm.x86.avx512.mask.fixupimm.ss(<4 x float>, <4 x float>, <4 x i32>, i32, i8, i32)9741 9742define <4 x float>@test_int_x86_avx512_mask_fixupimm_ss(<4 x float> %x0, <4 x float> %x1, <4 x i32> %x2, i8 %x4) #0 {9743; CHECK-LABEL: @test_int_x86_avx512_mask_fixupimm_ss(9744; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 89745; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 89746; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 89747; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 89748; CHECK-NEXT: call void @llvm.donothing()9749; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP1]] to i1289750; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 09751; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i32> [[TMP2]] to i1289752; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP6]], 09753; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]9754; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i32> [[TMP3]] to i1289755; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 09756; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]9757; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 09758; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]9759; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]9760; CHECK: 8:9761; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]9762; CHECK-NEXT: unreachable9763; CHECK: 9:9764; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.mask.fixupimm.ss(<4 x float> [[X0:%.*]], <4 x float> [[X1:%.*]], <4 x i32> [[X2:%.*]], i32 5, i8 [[X4:%.*]], i32 4)9765; CHECK-NEXT: [[TMP10:%.*]] = bitcast <4 x i32> [[TMP1]] to i1289766; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i128 [[TMP10]], 09767; CHECK-NEXT: [[TMP11:%.*]] = bitcast <4 x i32> [[TMP2]] to i1289768; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i128 [[TMP11]], 09769; CHECK-NEXT: [[_MSOR8:%.*]] = or i1 [[_MSCMP6]], [[_MSCMP7]]9770; CHECK-NEXT: [[_MSCMP9:%.*]] = icmp ne i8 [[TMP4]], 09771; CHECK-NEXT: [[_MSOR10:%.*]] = or i1 [[_MSOR8]], [[_MSCMP9]]9772; CHECK-NEXT: br i1 [[_MSOR10]], label [[TMP12:%.*]], label [[TMP13:%.*]], !prof [[PROF1]]9773; CHECK: 12:9774; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]9775; CHECK-NEXT: unreachable9776; CHECK: 13:9777; CHECK-NEXT: [[RES1:%.*]] = call <4 x float> @llvm.x86.avx512.mask.fixupimm.ss(<4 x float> [[X0]], <4 x float> [[X1]], <4 x i32> zeroinitializer, i32 5, i8 [[X4]], i32 4)9778; CHECK-NEXT: [[TMP14:%.*]] = bitcast <4 x i32> [[TMP1]] to i1289779; CHECK-NEXT: [[_MSCMP11:%.*]] = icmp ne i128 [[TMP14]], 09780; CHECK-NEXT: [[TMP15:%.*]] = bitcast <4 x i32> [[TMP2]] to i1289781; CHECK-NEXT: [[_MSCMP12:%.*]] = icmp ne i128 [[TMP15]], 09782; CHECK-NEXT: [[_MSOR13:%.*]] = or i1 [[_MSCMP11]], [[_MSCMP12]]9783; CHECK-NEXT: [[TMP16:%.*]] = bitcast <4 x i32> [[TMP3]] to i1289784; CHECK-NEXT: [[_MSCMP14:%.*]] = icmp ne i128 [[TMP16]], 09785; CHECK-NEXT: [[_MSOR15:%.*]] = or i1 [[_MSOR13]], [[_MSCMP14]]9786; CHECK-NEXT: br i1 [[_MSOR15]], label [[TMP17:%.*]], label [[TMP18:%.*]], !prof [[PROF1]]9787; CHECK: 17:9788; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]9789; CHECK-NEXT: unreachable9790; CHECK: 18:9791; CHECK-NEXT: [[RES2:%.*]] = call <4 x float> @llvm.x86.avx512.mask.fixupimm.ss(<4 x float> [[X0]], <4 x float> [[X1]], <4 x i32> [[X2]], i32 5, i8 -1, i32 8)9792; CHECK-NEXT: [[RES3:%.*]] = fadd <4 x float> [[RES]], [[RES1]]9793; CHECK-NEXT: [[RES4:%.*]] = fadd <4 x float> [[RES3]], [[RES2]]9794; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 89795; CHECK-NEXT: ret <4 x float> [[RES4]]9796;9797 %res = call <4 x float> @llvm.x86.avx512.mask.fixupimm.ss(<4 x float> %x0, <4 x float> %x1, <4 x i32> %x2, i32 5, i8 %x4, i32 4)9798 %res1 = call <4 x float> @llvm.x86.avx512.mask.fixupimm.ss(<4 x float> %x0, <4 x float> %x1, <4 x i32> zeroinitializer, i32 5, i8 %x4, i32 4)9799 %res2 = call <4 x float> @llvm.x86.avx512.mask.fixupimm.ss(<4 x float> %x0, <4 x float> %x1, <4 x i32> %x2, i32 5, i8 -1, i32 8)9800 %res3 = fadd <4 x float> %res, %res19801 %res4 = fadd <4 x float> %res3, %res29802 ret <4 x float> %res49803}9804 9805declare <4 x float> @llvm.x86.avx512.maskz.fixupimm.ss(<4 x float>, <4 x float>, <4 x i32>, i32, i8, i32)9806 9807define <4 x float>@test_int_x86_avx512_maskz_fixupimm_ss(<4 x float> %x0, <4 x float> %x1, <4 x i32> %x2, i8 %x4) #0 {9808; CHECK-LABEL: @test_int_x86_avx512_maskz_fixupimm_ss(9809; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 89810; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 89811; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 89812; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 89813; CHECK-NEXT: call void @llvm.donothing()9814; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP1]] to i1289815; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 09816; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i32> [[TMP2]] to i1289817; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP6]], 09818; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]9819; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i32> [[TMP3]] to i1289820; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 09821; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]9822; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 09823; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]9824; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]9825; CHECK: 8:9826; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]9827; CHECK-NEXT: unreachable9828; CHECK: 9:9829; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.maskz.fixupimm.ss(<4 x float> [[X0:%.*]], <4 x float> [[X1:%.*]], <4 x i32> [[X2:%.*]], i32 5, i8 [[X4:%.*]], i32 4)9830; CHECK-NEXT: [[TMP10:%.*]] = bitcast <4 x i32> [[TMP1]] to i1289831; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i128 [[TMP10]], 09832; CHECK-NEXT: [[TMP11:%.*]] = bitcast <4 x i32> [[TMP2]] to i1289833; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i128 [[TMP11]], 09834; CHECK-NEXT: [[_MSOR8:%.*]] = or i1 [[_MSCMP6]], [[_MSCMP7]]9835; CHECK-NEXT: [[_MSCMP9:%.*]] = icmp ne i8 [[TMP4]], 09836; CHECK-NEXT: [[_MSOR10:%.*]] = or i1 [[_MSOR8]], [[_MSCMP9]]9837; CHECK-NEXT: br i1 [[_MSOR10]], label [[TMP12:%.*]], label [[TMP13:%.*]], !prof [[PROF1]]9838; CHECK: 12:9839; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]9840; CHECK-NEXT: unreachable9841; CHECK: 13:9842; CHECK-NEXT: [[RES1:%.*]] = call <4 x float> @llvm.x86.avx512.maskz.fixupimm.ss(<4 x float> [[X0]], <4 x float> [[X1]], <4 x i32> zeroinitializer, i32 5, i8 [[X4]], i32 8)9843; CHECK-NEXT: [[TMP14:%.*]] = bitcast <4 x i32> [[TMP1]] to i1289844; CHECK-NEXT: [[_MSCMP11:%.*]] = icmp ne i128 [[TMP14]], 09845; CHECK-NEXT: [[TMP15:%.*]] = bitcast <4 x i32> [[TMP2]] to i1289846; CHECK-NEXT: [[_MSCMP12:%.*]] = icmp ne i128 [[TMP15]], 09847; CHECK-NEXT: [[_MSOR13:%.*]] = or i1 [[_MSCMP11]], [[_MSCMP12]]9848; CHECK-NEXT: [[TMP16:%.*]] = bitcast <4 x i32> [[TMP3]] to i1289849; CHECK-NEXT: [[_MSCMP14:%.*]] = icmp ne i128 [[TMP16]], 09850; CHECK-NEXT: [[_MSOR15:%.*]] = or i1 [[_MSOR13]], [[_MSCMP14]]9851; CHECK-NEXT: br i1 [[_MSOR15]], label [[TMP17:%.*]], label [[TMP18:%.*]], !prof [[PROF1]]9852; CHECK: 17:9853; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]9854; CHECK-NEXT: unreachable9855; CHECK: 18:9856; CHECK-NEXT: [[RES2:%.*]] = call <4 x float> @llvm.x86.avx512.maskz.fixupimm.ss(<4 x float> [[X0]], <4 x float> [[X1]], <4 x i32> [[X2]], i32 6, i8 -1, i32 4)9857; CHECK-NEXT: [[RES3:%.*]] = fadd <4 x float> [[RES]], [[RES1]]9858; CHECK-NEXT: [[RES4:%.*]] = fadd <4 x float> [[RES3]], [[RES2]]9859; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 89860; CHECK-NEXT: ret <4 x float> [[RES4]]9861;9862 %res = call <4 x float> @llvm.x86.avx512.maskz.fixupimm.ss(<4 x float> %x0, <4 x float> %x1, <4 x i32> %x2, i32 5, i8 %x4, i32 4)9863 %res1 = call <4 x float> @llvm.x86.avx512.maskz.fixupimm.ss(<4 x float> %x0, <4 x float> %x1, <4 x i32> zeroinitializer, i32 5, i8 %x4, i32 8)9864 %res2 = call <4 x float> @llvm.x86.avx512.maskz.fixupimm.ss(<4 x float> %x0, <4 x float> %x1, <4 x i32> %x2, i32 6, i8 -1, i32 4)9865 %res3 = fadd <4 x float> %res, %res19866 %res4 = fadd <4 x float> %res3, %res29867 ret <4 x float> %res49868}9869 9870declare <16 x float> @llvm.x86.avx512.mask.fixupimm.ps.512(<16 x float>, <16 x float>, <16 x i32>, i32, i16, i32)9871 9872define <16 x float>@test_int_x86_avx512_mask_fixupimm_ps_512(<16 x float> %x0, <16 x float> %x1, <16 x i32> %x2, i16 %x4) #0 {9873; CHECK-LABEL: @test_int_x86_avx512_mask_fixupimm_ps_512(9874; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 89875; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 89876; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 89877; CHECK-NEXT: [[TMP4:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 89878; CHECK-NEXT: call void @llvm.donothing()9879; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP1]] to i5129880; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP5]], 09881; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i32> [[TMP2]] to i5129882; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP6]], 09883; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]9884; CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i32> [[TMP3]] to i5129885; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i512 [[TMP7]], 09886; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]9887; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i16 [[TMP4]], 09888; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]9889; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]9890; CHECK: 8:9891; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]9892; CHECK-NEXT: unreachable9893; CHECK: 9:9894; CHECK-NEXT: [[RES:%.*]] = call <16 x float> @llvm.x86.avx512.mask.fixupimm.ps.512(<16 x float> [[X0:%.*]], <16 x float> [[X1:%.*]], <16 x i32> [[X2:%.*]], i32 5, i16 [[X4:%.*]], i32 4)9895; CHECK-NEXT: [[TMP10:%.*]] = bitcast <16 x i32> [[TMP1]] to i5129896; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i512 [[TMP10]], 09897; CHECK-NEXT: [[TMP11:%.*]] = bitcast <16 x i32> [[TMP2]] to i5129898; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i512 [[TMP11]], 09899; CHECK-NEXT: [[_MSOR8:%.*]] = or i1 [[_MSCMP6]], [[_MSCMP7]]9900; CHECK-NEXT: [[_MSCMP9:%.*]] = icmp ne i16 [[TMP4]], 09901; CHECK-NEXT: [[_MSOR10:%.*]] = or i1 [[_MSOR8]], [[_MSCMP9]]9902; CHECK-NEXT: br i1 [[_MSOR10]], label [[TMP12:%.*]], label [[TMP13:%.*]], !prof [[PROF1]]9903; CHECK: 12:9904; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]9905; CHECK-NEXT: unreachable9906; CHECK: 13:9907; CHECK-NEXT: [[RES1:%.*]] = call <16 x float> @llvm.x86.avx512.mask.fixupimm.ps.512(<16 x float> [[X0]], <16 x float> [[X1]], <16 x i32> zeroinitializer, i32 5, i16 [[X4]], i32 4)9908; CHECK-NEXT: [[TMP14:%.*]] = bitcast <16 x i32> [[TMP1]] to i5129909; CHECK-NEXT: [[_MSCMP11:%.*]] = icmp ne i512 [[TMP14]], 09910; CHECK-NEXT: [[TMP15:%.*]] = bitcast <16 x i32> [[TMP2]] to i5129911; CHECK-NEXT: [[_MSCMP12:%.*]] = icmp ne i512 [[TMP15]], 09912; CHECK-NEXT: [[_MSOR13:%.*]] = or i1 [[_MSCMP11]], [[_MSCMP12]]9913; CHECK-NEXT: [[TMP16:%.*]] = bitcast <16 x i32> [[TMP3]] to i5129914; CHECK-NEXT: [[_MSCMP14:%.*]] = icmp ne i512 [[TMP16]], 09915; CHECK-NEXT: [[_MSOR15:%.*]] = or i1 [[_MSOR13]], [[_MSCMP14]]9916; CHECK-NEXT: br i1 [[_MSOR15]], label [[TMP17:%.*]], label [[TMP18:%.*]], !prof [[PROF1]]9917; CHECK: 17:9918; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]9919; CHECK-NEXT: unreachable9920; CHECK: 18:9921; CHECK-NEXT: [[RES2:%.*]] = call <16 x float> @llvm.x86.avx512.mask.fixupimm.ps.512(<16 x float> [[X0]], <16 x float> [[X1]], <16 x i32> [[X2]], i32 5, i16 -1, i32 8)9922; CHECK-NEXT: [[RES3:%.*]] = fadd <16 x float> [[RES]], [[RES1]]9923; CHECK-NEXT: [[RES4:%.*]] = fadd <16 x float> [[RES3]], [[RES2]]9924; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 89925; CHECK-NEXT: ret <16 x float> [[RES4]]9926;9927 %res = call <16 x float> @llvm.x86.avx512.mask.fixupimm.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x i32> %x2, i32 5, i16 %x4, i32 4)9928 %res1 = call <16 x float> @llvm.x86.avx512.mask.fixupimm.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x i32> zeroinitializer, i32 5, i16 %x4, i32 4)9929 %res2 = call <16 x float> @llvm.x86.avx512.mask.fixupimm.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x i32> %x2, i32 5, i16 -1, i32 8)9930 %res3 = fadd <16 x float> %res, %res19931 %res4 = fadd <16 x float> %res3, %res29932 ret <16 x float> %res49933}9934 9935define <16 x float>@test_int_x86_avx512_mask_fixupimm_ps_512_load(<16 x float> %x0, <16 x float> %x1, ptr %x2ptr) #0 {9936; CHECK-LABEL: @test_int_x86_avx512_mask_fixupimm_ps_512_load(9937; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 89938; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 89939; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 89940; CHECK-NEXT: call void @llvm.donothing()9941; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 09942; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF1]]9943; CHECK: 4:9944; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]9945; CHECK-NEXT: unreachable9946; CHECK: 5:9947; CHECK-NEXT: [[X2:%.*]] = load <16 x i32>, ptr [[X2PTR:%.*]], align 649948; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[X2PTR]] to i649949; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 879609302220809950; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr9951; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i32>, ptr [[TMP8]], align 649952; CHECK-NEXT: [[TMP9:%.*]] = bitcast <16 x i32> [[TMP2]] to i5129953; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP9]], 09954; CHECK-NEXT: [[TMP10:%.*]] = bitcast <16 x i32> [[TMP3]] to i5129955; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i512 [[TMP10]], 09956; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP1]], [[_MSCMP2]]9957; CHECK-NEXT: [[TMP11:%.*]] = bitcast <16 x i32> [[_MSLD]] to i5129958; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i512 [[TMP11]], 09959; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSOR]], [[_MSCMP3]]9960; CHECK-NEXT: br i1 [[_MSOR4]], label [[TMP12:%.*]], label [[TMP13:%.*]], !prof [[PROF1]]9961; CHECK: 12:9962; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]9963; CHECK-NEXT: unreachable9964; CHECK: 13:9965; CHECK-NEXT: [[RES:%.*]] = call <16 x float> @llvm.x86.avx512.mask.fixupimm.ps.512(<16 x float> [[X0:%.*]], <16 x float> [[X1:%.*]], <16 x i32> [[X2]], i32 5, i16 -1, i32 4)9966; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 89967; CHECK-NEXT: ret <16 x float> [[RES]]9968;9969 %x2 = load <16 x i32>, ptr %x2ptr9970 %res = call <16 x float> @llvm.x86.avx512.mask.fixupimm.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x i32> %x2, i32 5, i16 -1, i32 4)9971 ret <16 x float> %res9972}9973 9974declare <16 x float> @llvm.x86.avx512.maskz.fixupimm.ps.512(<16 x float>, <16 x float>, <16 x i32>, i32, i16, i32)9975 9976define <16 x float>@test_int_x86_avx512_maskz_fixupimm_ps_512(<16 x float> %x0, <16 x float> %x1, <16 x i32> %x2, i16 %x4) #0 {9977; CHECK-LABEL: @test_int_x86_avx512_maskz_fixupimm_ps_512(9978; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 89979; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 89980; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 89981; CHECK-NEXT: [[TMP4:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 89982; CHECK-NEXT: call void @llvm.donothing()9983; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP1]] to i5129984; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP5]], 09985; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i32> [[TMP2]] to i5129986; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP6]], 09987; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]9988; CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i32> [[TMP3]] to i5129989; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i512 [[TMP7]], 09990; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]9991; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i16 [[TMP4]], 09992; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]9993; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]9994; CHECK: 8:9995; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]9996; CHECK-NEXT: unreachable9997; CHECK: 9:9998; CHECK-NEXT: [[RES:%.*]] = call <16 x float> @llvm.x86.avx512.maskz.fixupimm.ps.512(<16 x float> [[X0:%.*]], <16 x float> [[X1:%.*]], <16 x i32> [[X2:%.*]], i32 5, i16 [[X4:%.*]], i32 4)9999; CHECK-NEXT: [[TMP10:%.*]] = bitcast <16 x i32> [[TMP1]] to i51210000; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i512 [[TMP10]], 010001; CHECK-NEXT: [[TMP11:%.*]] = bitcast <16 x i32> [[TMP2]] to i51210002; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i512 [[TMP11]], 010003; CHECK-NEXT: [[_MSOR8:%.*]] = or i1 [[_MSCMP6]], [[_MSCMP7]]10004; CHECK-NEXT: [[_MSCMP9:%.*]] = icmp ne i16 [[TMP4]], 010005; CHECK-NEXT: [[_MSOR10:%.*]] = or i1 [[_MSOR8]], [[_MSCMP9]]10006; CHECK-NEXT: br i1 [[_MSOR10]], label [[TMP12:%.*]], label [[TMP13:%.*]], !prof [[PROF1]]10007; CHECK: 12:10008; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]10009; CHECK-NEXT: unreachable10010; CHECK: 13:10011; CHECK-NEXT: [[RES1:%.*]] = call <16 x float> @llvm.x86.avx512.maskz.fixupimm.ps.512(<16 x float> [[X0]], <16 x float> [[X1]], <16 x i32> zeroinitializer, i32 6, i16 [[X4]], i32 8)10012; CHECK-NEXT: [[TMP14:%.*]] = bitcast <16 x i32> [[TMP1]] to i51210013; CHECK-NEXT: [[_MSCMP11:%.*]] = icmp ne i512 [[TMP14]], 010014; CHECK-NEXT: [[TMP15:%.*]] = bitcast <16 x i32> [[TMP2]] to i51210015; CHECK-NEXT: [[_MSCMP12:%.*]] = icmp ne i512 [[TMP15]], 010016; CHECK-NEXT: [[_MSOR13:%.*]] = or i1 [[_MSCMP11]], [[_MSCMP12]]10017; CHECK-NEXT: [[TMP16:%.*]] = bitcast <16 x i32> [[TMP3]] to i51210018; CHECK-NEXT: [[_MSCMP14:%.*]] = icmp ne i512 [[TMP16]], 010019; CHECK-NEXT: [[_MSOR15:%.*]] = or i1 [[_MSOR13]], [[_MSCMP14]]10020; CHECK-NEXT: br i1 [[_MSOR15]], label [[TMP17:%.*]], label [[TMP18:%.*]], !prof [[PROF1]]10021; CHECK: 17:10022; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]10023; CHECK-NEXT: unreachable10024; CHECK: 18:10025; CHECK-NEXT: [[RES2:%.*]] = call <16 x float> @llvm.x86.avx512.maskz.fixupimm.ps.512(<16 x float> [[X0]], <16 x float> [[X1]], <16 x i32> [[X2]], i32 7, i16 -1, i32 4)10026; CHECK-NEXT: [[RES3:%.*]] = fadd <16 x float> [[RES]], [[RES1]]10027; CHECK-NEXT: [[RES4:%.*]] = fadd <16 x float> [[RES3]], [[RES2]]10028; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 810029; CHECK-NEXT: ret <16 x float> [[RES4]]10030;10031 %res = call <16 x float> @llvm.x86.avx512.maskz.fixupimm.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x i32> %x2, i32 5, i16 %x4, i32 4)10032 %res1 = call <16 x float> @llvm.x86.avx512.maskz.fixupimm.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x i32> zeroinitializer, i32 6, i16 %x4, i32 8)10033 %res2 = call <16 x float> @llvm.x86.avx512.maskz.fixupimm.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x i32> %x2, i32 7, i16 -1, i32 4)10034 %res3 = fadd <16 x float> %res, %res110035 %res4 = fadd <16 x float> %res3, %res210036 ret <16 x float> %res410037}10038 10039declare <2 x double> @llvm.x86.avx512.mask.fixupimm.sd(<2 x double>, <2 x double>, <2 x i64>, i32, i8, i32)10040 10041define <2 x double>@test_int_x86_avx512_mask_fixupimm_sd(<2 x double> %x0, <2 x double> %x1, <2 x i64> %x2, i8 %x4) #0 {10042; CHECK-LABEL: @test_int_x86_avx512_mask_fixupimm_sd(10043; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 810044; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 810045; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 810046; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 810047; CHECK-NEXT: call void @llvm.donothing()10048; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP1]] to i12810049; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 010050; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i64> [[TMP2]] to i12810051; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP6]], 010052; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]10053; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i64> [[TMP3]] to i12810054; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 010055; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]10056; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 010057; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]10058; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]10059; CHECK: 8:10060; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]10061; CHECK-NEXT: unreachable10062; CHECK: 9:10063; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx512.mask.fixupimm.sd(<2 x double> [[X0:%.*]], <2 x double> [[X1:%.*]], <2 x i64> [[X2:%.*]], i32 5, i8 [[X4:%.*]], i32 4)10064; CHECK-NEXT: [[TMP10:%.*]] = bitcast <2 x i64> [[TMP1]] to i12810065; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i128 [[TMP10]], 010066; CHECK-NEXT: [[TMP11:%.*]] = bitcast <2 x i64> [[TMP2]] to i12810067; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i128 [[TMP11]], 010068; CHECK-NEXT: [[_MSOR8:%.*]] = or i1 [[_MSCMP6]], [[_MSCMP7]]10069; CHECK-NEXT: [[_MSCMP9:%.*]] = icmp ne i8 [[TMP4]], 010070; CHECK-NEXT: [[_MSOR10:%.*]] = or i1 [[_MSOR8]], [[_MSCMP9]]10071; CHECK-NEXT: br i1 [[_MSOR10]], label [[TMP12:%.*]], label [[TMP13:%.*]], !prof [[PROF1]]10072; CHECK: 12:10073; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]10074; CHECK-NEXT: unreachable10075; CHECK: 13:10076; CHECK-NEXT: [[RES1:%.*]] = call <2 x double> @llvm.x86.avx512.mask.fixupimm.sd(<2 x double> [[X0]], <2 x double> [[X1]], <2 x i64> zeroinitializer, i32 5, i8 [[X4]], i32 8)10077; CHECK-NEXT: [[TMP14:%.*]] = bitcast <2 x i64> [[TMP1]] to i12810078; CHECK-NEXT: [[_MSCMP11:%.*]] = icmp ne i128 [[TMP14]], 010079; CHECK-NEXT: [[TMP15:%.*]] = bitcast <2 x i64> [[TMP2]] to i12810080; CHECK-NEXT: [[_MSCMP12:%.*]] = icmp ne i128 [[TMP15]], 010081; CHECK-NEXT: [[_MSOR13:%.*]] = or i1 [[_MSCMP11]], [[_MSCMP12]]10082; CHECK-NEXT: [[TMP16:%.*]] = bitcast <2 x i64> [[TMP3]] to i12810083; CHECK-NEXT: [[_MSCMP14:%.*]] = icmp ne i128 [[TMP16]], 010084; CHECK-NEXT: [[_MSOR15:%.*]] = or i1 [[_MSOR13]], [[_MSCMP14]]10085; CHECK-NEXT: br i1 [[_MSOR15]], label [[TMP17:%.*]], label [[TMP18:%.*]], !prof [[PROF1]]10086; CHECK: 17:10087; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]10088; CHECK-NEXT: unreachable10089; CHECK: 18:10090; CHECK-NEXT: [[RES2:%.*]] = call <2 x double> @llvm.x86.avx512.mask.fixupimm.sd(<2 x double> [[X0]], <2 x double> [[X1]], <2 x i64> [[X2]], i32 6, i8 -1, i32 4)10091; CHECK-NEXT: [[RES3:%.*]] = fadd <2 x double> [[RES]], [[RES1]]10092; CHECK-NEXT: [[RES4:%.*]] = fadd <2 x double> [[RES3]], [[RES2]]10093; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 810094; CHECK-NEXT: ret <2 x double> [[RES4]]10095;10096 %res = call <2 x double> @llvm.x86.avx512.mask.fixupimm.sd(<2 x double> %x0, <2 x double> %x1, <2 x i64> %x2, i32 5, i8 %x4, i32 4)10097 %res1 = call <2 x double> @llvm.x86.avx512.mask.fixupimm.sd(<2 x double> %x0, <2 x double> %x1, <2 x i64> zeroinitializer, i32 5, i8 %x4, i32 8)10098 %res2 = call <2 x double> @llvm.x86.avx512.mask.fixupimm.sd(<2 x double> %x0, <2 x double> %x1, <2 x i64> %x2, i32 6, i8 -1, i32 4)10099 %res3 = fadd <2 x double> %res, %res110100 %res4 = fadd <2 x double> %res3, %res210101 ret <2 x double> %res410102}10103 10104declare <2 x double> @llvm.x86.avx512.maskz.fixupimm.sd(<2 x double>, <2 x double>, <2 x i64>, i32, i8, i32)10105 10106define <2 x double>@test_int_x86_avx512_maskz_fixupimm_sd(<2 x double> %x0, <2 x double> %x1, <2 x i64> %x2, i8 %x4) #0 {10107; CHECK-LABEL: @test_int_x86_avx512_maskz_fixupimm_sd(10108; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 810109; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 810110; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 810111; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 810112; CHECK-NEXT: call void @llvm.donothing()10113; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP1]] to i12810114; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 010115; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i64> [[TMP2]] to i12810116; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP6]], 010117; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]10118; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i64> [[TMP3]] to i12810119; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 010120; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]10121; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 010122; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]10123; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]10124; CHECK: 8:10125; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]10126; CHECK-NEXT: unreachable10127; CHECK: 9:10128; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx512.maskz.fixupimm.sd(<2 x double> [[X0:%.*]], <2 x double> [[X1:%.*]], <2 x i64> [[X2:%.*]], i32 5, i8 [[X4:%.*]], i32 4)10129; CHECK-NEXT: [[TMP10:%.*]] = bitcast <2 x i64> [[TMP1]] to i12810130; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i128 [[TMP10]], 010131; CHECK-NEXT: [[TMP11:%.*]] = bitcast <2 x i64> [[TMP2]] to i12810132; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i128 [[TMP11]], 010133; CHECK-NEXT: [[_MSOR8:%.*]] = or i1 [[_MSCMP6]], [[_MSCMP7]]10134; CHECK-NEXT: [[_MSCMP9:%.*]] = icmp ne i8 [[TMP4]], 010135; CHECK-NEXT: [[_MSOR10:%.*]] = or i1 [[_MSOR8]], [[_MSCMP9]]10136; CHECK-NEXT: br i1 [[_MSOR10]], label [[TMP12:%.*]], label [[TMP13:%.*]], !prof [[PROF1]]10137; CHECK: 12:10138; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]10139; CHECK-NEXT: unreachable10140; CHECK: 13:10141; CHECK-NEXT: [[RES1:%.*]] = call <2 x double> @llvm.x86.avx512.maskz.fixupimm.sd(<2 x double> [[X0]], <2 x double> [[X1]], <2 x i64> zeroinitializer, i32 5, i8 [[X4]], i32 8)10142; CHECK-NEXT: [[TMP14:%.*]] = bitcast <2 x i64> [[TMP1]] to i12810143; CHECK-NEXT: [[_MSCMP11:%.*]] = icmp ne i128 [[TMP14]], 010144; CHECK-NEXT: [[TMP15:%.*]] = bitcast <2 x i64> [[TMP2]] to i12810145; CHECK-NEXT: [[_MSCMP12:%.*]] = icmp ne i128 [[TMP15]], 010146; CHECK-NEXT: [[_MSOR13:%.*]] = or i1 [[_MSCMP11]], [[_MSCMP12]]10147; CHECK-NEXT: [[TMP16:%.*]] = bitcast <2 x i64> [[TMP3]] to i12810148; CHECK-NEXT: [[_MSCMP14:%.*]] = icmp ne i128 [[TMP16]], 010149; CHECK-NEXT: [[_MSOR15:%.*]] = or i1 [[_MSOR13]], [[_MSCMP14]]10150; CHECK-NEXT: [[_MSCMP16:%.*]] = icmp ne i8 [[TMP4]], 010151; CHECK-NEXT: [[_MSOR17:%.*]] = or i1 [[_MSOR15]], [[_MSCMP16]]10152; CHECK-NEXT: br i1 [[_MSOR17]], label [[TMP17:%.*]], label [[TMP18:%.*]], !prof [[PROF1]]10153; CHECK: 17:10154; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]10155; CHECK-NEXT: unreachable10156; CHECK: 18:10157; CHECK-NEXT: [[RES2:%.*]] = call <2 x double> @llvm.x86.avx512.maskz.fixupimm.sd(<2 x double> [[X0]], <2 x double> [[X1]], <2 x i64> [[X2]], i32 5, i8 [[X4]], i32 8)10158; CHECK-NEXT: [[RES3:%.*]] = fadd <2 x double> [[RES]], [[RES1]]10159; CHECK-NEXT: [[RES4:%.*]] = fadd <2 x double> [[RES3]], [[RES2]]10160; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 810161; CHECK-NEXT: ret <2 x double> [[RES4]]10162;10163 %res = call <2 x double> @llvm.x86.avx512.maskz.fixupimm.sd(<2 x double> %x0, <2 x double> %x1, <2 x i64> %x2, i32 5, i8 %x4, i32 4)10164 %res1 = call <2 x double> @llvm.x86.avx512.maskz.fixupimm.sd(<2 x double> %x0, <2 x double> %x1, <2 x i64> zeroinitializer, i32 5, i8 %x4, i32 8)10165 %res2 = call <2 x double> @llvm.x86.avx512.maskz.fixupimm.sd(<2 x double> %x0, <2 x double> %x1, <2 x i64> %x2, i32 5, i8 %x4, i32 8)10166 %res3 = fadd <2 x double> %res, %res110167 %res4 = fadd <2 x double> %res3, %res210168 ret <2 x double> %res410169}10170 10171declare double @llvm.fma.f64(double, double, double) #110172declare double @llvm.x86.avx512.vfmadd.f64(double, double, double, i32) #010173 10174define <2 x double> @test_int_x86_avx512_mask_vfmadd_sd(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3, i32 %x4) #0 {10175; CHECK-LABEL: @test_int_x86_avx512_mask_vfmadd_sd(10176; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 810177; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 810178; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 810179; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 810180; CHECK-NEXT: call void @llvm.donothing()10181; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <2 x i64> [[TMP1]], i64 010182; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[X0:%.*]], i64 010183; CHECK-NEXT: [[_MSPROP1:%.*]] = extractelement <2 x i64> [[TMP2]], i64 010184; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x double> [[X1:%.*]], i64 010185; CHECK-NEXT: [[_MSPROP2:%.*]] = extractelement <2 x i64> [[TMP3]], i64 010186; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x double> [[X2:%.*]], i64 010187; CHECK-NEXT: [[_MSPROP3:%.*]] = or i64 [[_MSPROP]], [[_MSPROP1]]10188; CHECK-NEXT: [[_MSPROP4:%.*]] = or i64 [[_MSPROP3]], [[_MSPROP2]]10189; CHECK-NEXT: [[TMP8:%.*]] = call double @llvm.fma.f64(double [[TMP5]], double [[TMP6]], double [[TMP7]])10190; CHECK-NEXT: [[TMP9:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>10191; CHECK-NEXT: [[TMP10:%.*]] = bitcast i8 [[X3:%.*]] to <8 x i1>10192; CHECK-NEXT: [[_MSPROP5:%.*]] = extractelement <8 x i1> [[TMP9]], i64 010193; CHECK-NEXT: [[TMP11:%.*]] = extractelement <8 x i1> [[TMP10]], i64 010194; CHECK-NEXT: [[TMP12:%.*]] = select i1 [[TMP11]], i64 [[_MSPROP4]], i64 [[_MSPROP]]10195; CHECK-NEXT: [[TMP13:%.*]] = bitcast double [[TMP8]] to i6410196; CHECK-NEXT: [[TMP14:%.*]] = bitcast double [[TMP5]] to i6410197; CHECK-NEXT: [[TMP15:%.*]] = xor i64 [[TMP13]], [[TMP14]]10198; CHECK-NEXT: [[TMP16:%.*]] = or i64 [[TMP15]], [[_MSPROP4]]10199; CHECK-NEXT: [[TMP17:%.*]] = or i64 [[TMP16]], [[_MSPROP]]10200; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select i1 [[_MSPROP5]], i64 [[TMP17]], i64 [[TMP12]]10201; CHECK-NEXT: [[TMP18:%.*]] = select i1 [[TMP11]], double [[TMP8]], double [[TMP5]]10202; CHECK-NEXT: [[_MSPROP6:%.*]] = insertelement <2 x i64> [[TMP1]], i64 [[_MSPROP_SELECT]], i64 010203; CHECK-NEXT: [[TMP19:%.*]] = insertelement <2 x double> [[X0]], double [[TMP18]], i64 010204; CHECK-NEXT: [[_MSPROP7:%.*]] = extractelement <2 x i64> [[TMP1]], i64 010205; CHECK-NEXT: [[TMP20:%.*]] = extractelement <2 x double> [[X0]], i64 010206; CHECK-NEXT: [[_MSPROP8:%.*]] = extractelement <2 x i64> [[TMP2]], i64 010207; CHECK-NEXT: [[TMP21:%.*]] = extractelement <2 x double> [[X1]], i64 010208; CHECK-NEXT: [[_MSPROP9:%.*]] = extractelement <2 x i64> [[TMP3]], i64 010209; CHECK-NEXT: [[TMP22:%.*]] = extractelement <2 x double> [[X2]], i64 010210; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[_MSPROP7]], 010211; CHECK-NEXT: [[_MSCMP19:%.*]] = icmp ne i64 [[_MSPROP8]], 010212; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP19]]10213; CHECK-NEXT: [[_MSCMP20:%.*]] = icmp ne i64 [[_MSPROP9]], 010214; CHECK-NEXT: [[_MSOR21:%.*]] = or i1 [[_MSOR]], [[_MSCMP20]]10215; CHECK-NEXT: br i1 [[_MSOR21]], label [[TMP23:%.*]], label [[TMP24:%.*]], !prof [[PROF1]]10216; CHECK: 23:10217; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]10218; CHECK-NEXT: unreachable10219; CHECK: 24:10220; CHECK-NEXT: [[TMP25:%.*]] = call double @llvm.x86.avx512.vfmadd.f64(double [[TMP20]], double [[TMP21]], double [[TMP22]], i32 11)10221; CHECK-NEXT: [[_MSPROP10:%.*]] = insertelement <2 x i64> [[TMP1]], i64 0, i64 010222; CHECK-NEXT: [[TMP26:%.*]] = insertelement <2 x double> [[X0]], double [[TMP25]], i64 010223; CHECK-NEXT: [[_MSPROP11:%.*]] = extractelement <2 x i64> [[TMP1]], i64 010224; CHECK-NEXT: [[TMP27:%.*]] = extractelement <2 x double> [[X0]], i64 010225; CHECK-NEXT: [[_MSPROP12:%.*]] = extractelement <2 x i64> [[TMP2]], i64 010226; CHECK-NEXT: [[TMP28:%.*]] = extractelement <2 x double> [[X1]], i64 010227; CHECK-NEXT: [[_MSPROP13:%.*]] = extractelement <2 x i64> [[TMP3]], i64 010228; CHECK-NEXT: [[TMP29:%.*]] = extractelement <2 x double> [[X2]], i64 010229; CHECK-NEXT: [[_MSCMP22:%.*]] = icmp ne i64 [[_MSPROP11]], 010230; CHECK-NEXT: [[_MSCMP23:%.*]] = icmp ne i64 [[_MSPROP12]], 010231; CHECK-NEXT: [[_MSOR24:%.*]] = or i1 [[_MSCMP22]], [[_MSCMP23]]10232; CHECK-NEXT: [[_MSCMP25:%.*]] = icmp ne i64 [[_MSPROP13]], 010233; CHECK-NEXT: [[_MSOR26:%.*]] = or i1 [[_MSOR24]], [[_MSCMP25]]10234; CHECK-NEXT: br i1 [[_MSOR26]], label [[TMP30:%.*]], label [[TMP31:%.*]], !prof [[PROF1]]10235; CHECK: 30:10236; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]10237; CHECK-NEXT: unreachable10238; CHECK: 31:10239; CHECK-NEXT: [[TMP32:%.*]] = call double @llvm.x86.avx512.vfmadd.f64(double [[TMP27]], double [[TMP28]], double [[TMP29]], i32 10)10240; CHECK-NEXT: [[TMP33:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>10241; CHECK-NEXT: [[TMP34:%.*]] = bitcast i8 [[X3]] to <8 x i1>10242; CHECK-NEXT: [[_MSPROP14:%.*]] = extractelement <8 x i1> [[TMP33]], i64 010243; CHECK-NEXT: [[TMP35:%.*]] = extractelement <8 x i1> [[TMP34]], i64 010244; CHECK-NEXT: [[TMP36:%.*]] = select i1 [[TMP35]], i64 0, i64 [[_MSPROP11]]10245; CHECK-NEXT: [[TMP37:%.*]] = bitcast double [[TMP32]] to i6410246; CHECK-NEXT: [[TMP38:%.*]] = bitcast double [[TMP27]] to i6410247; CHECK-NEXT: [[TMP39:%.*]] = xor i64 [[TMP37]], [[TMP38]]10248; CHECK-NEXT: [[TMP40:%.*]] = or i64 [[TMP39]], 010249; CHECK-NEXT: [[TMP41:%.*]] = or i64 [[TMP40]], [[_MSPROP11]]10250; CHECK-NEXT: [[_MSPROP_SELECT15:%.*]] = select i1 [[_MSPROP14]], i64 [[TMP41]], i64 [[TMP36]]10251; CHECK-NEXT: [[TMP42:%.*]] = select i1 [[TMP35]], double [[TMP32]], double [[TMP27]]10252; CHECK-NEXT: [[_MSPROP16:%.*]] = insertelement <2 x i64> [[TMP1]], i64 [[_MSPROP_SELECT15]], i64 010253; CHECK-NEXT: [[TMP43:%.*]] = insertelement <2 x double> [[X0]], double [[TMP42]], i64 010254; CHECK-NEXT: [[_MSPROP17:%.*]] = or <2 x i64> [[_MSPROP6]], [[_MSPROP10]]10255; CHECK-NEXT: [[RES3:%.*]] = fadd <2 x double> [[TMP19]], [[TMP26]]10256; CHECK-NEXT: [[_MSPROP18:%.*]] = or <2 x i64> [[_MSPROP16]], [[_MSPROP17]]10257; CHECK-NEXT: [[RES4:%.*]] = fadd <2 x double> [[TMP43]], [[RES3]]10258; CHECK-NEXT: store <2 x i64> [[_MSPROP18]], ptr @__msan_retval_tls, align 810259; CHECK-NEXT: ret <2 x double> [[RES4]]10260;10261 %1 = extractelement <2 x double> %x0, i64 010262 %2 = extractelement <2 x double> %x1, i64 010263 %3 = extractelement <2 x double> %x2, i64 010264 %4 = call double @llvm.fma.f64(double %1, double %2, double %3)10265 %5 = bitcast i8 %x3 to <8 x i1>10266 %6 = extractelement <8 x i1> %5, i64 010267 %7 = select i1 %6, double %4, double %110268 %8 = insertelement <2 x double> %x0, double %7, i64 010269 %9 = extractelement <2 x double> %x0, i64 010270 %10 = extractelement <2 x double> %x1, i64 010271 %11 = extractelement <2 x double> %x2, i64 010272 %12 = call double @llvm.x86.avx512.vfmadd.f64(double %9, double %10, double %11, i32 11)10273 %13 = insertelement <2 x double> %x0, double %12, i64 010274 %14 = extractelement <2 x double> %x0, i64 010275 %15 = extractelement <2 x double> %x1, i64 010276 %16 = extractelement <2 x double> %x2, i64 010277 %17 = call double @llvm.x86.avx512.vfmadd.f64(double %14, double %15, double %16, i32 10)10278 %18 = bitcast i8 %x3 to <8 x i1>10279 %19 = extractelement <8 x i1> %18, i64 010280 %20 = select i1 %19, double %17, double %1410281 %21 = insertelement <2 x double> %x0, double %20, i64 010282 %res3 = fadd <2 x double> %8, %1310283 %res4 = fadd <2 x double> %21, %res310284 ret <2 x double> %res410285}10286 10287define <4 x float> @test_int_x86_avx512_mask_vfmadd_ss(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3, i32 %x4) #0 {10288; CHECK-LABEL: @test_int_x86_avx512_mask_vfmadd_ss(10289; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 810290; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 810291; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 810292; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 810293; CHECK-NEXT: call void @llvm.donothing()10294; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <4 x i32> [[TMP1]], i64 010295; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x float> [[X0:%.*]], i64 010296; CHECK-NEXT: [[_MSPROP1:%.*]] = extractelement <4 x i32> [[TMP2]], i64 010297; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x float> [[X1:%.*]], i64 010298; CHECK-NEXT: [[_MSPROP2:%.*]] = extractelement <4 x i32> [[TMP3]], i64 010299; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x float> [[X2:%.*]], i64 010300; CHECK-NEXT: [[_MSPROP3:%.*]] = or i32 [[_MSPROP]], [[_MSPROP1]]10301; CHECK-NEXT: [[_MSPROP4:%.*]] = or i32 [[_MSPROP3]], [[_MSPROP2]]10302; CHECK-NEXT: [[TMP8:%.*]] = call float @llvm.fma.f32(float [[TMP5]], float [[TMP6]], float [[TMP7]])10303; CHECK-NEXT: [[TMP9:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>10304; CHECK-NEXT: [[TMP10:%.*]] = bitcast i8 [[X3:%.*]] to <8 x i1>10305; CHECK-NEXT: [[_MSPROP5:%.*]] = extractelement <8 x i1> [[TMP9]], i64 010306; CHECK-NEXT: [[TMP11:%.*]] = extractelement <8 x i1> [[TMP10]], i64 010307; CHECK-NEXT: [[TMP12:%.*]] = select i1 [[TMP11]], i32 [[_MSPROP4]], i32 [[_MSPROP]]10308; CHECK-NEXT: [[TMP13:%.*]] = bitcast float [[TMP8]] to i3210309; CHECK-NEXT: [[TMP14:%.*]] = bitcast float [[TMP5]] to i3210310; CHECK-NEXT: [[TMP15:%.*]] = xor i32 [[TMP13]], [[TMP14]]10311; CHECK-NEXT: [[TMP16:%.*]] = or i32 [[TMP15]], [[_MSPROP4]]10312; CHECK-NEXT: [[TMP17:%.*]] = or i32 [[TMP16]], [[_MSPROP]]10313; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select i1 [[_MSPROP5]], i32 [[TMP17]], i32 [[TMP12]]10314; CHECK-NEXT: [[TMP18:%.*]] = select i1 [[TMP11]], float [[TMP8]], float [[TMP5]]10315; CHECK-NEXT: [[_MSPROP6:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[_MSPROP_SELECT]], i64 010316; CHECK-NEXT: [[TMP19:%.*]] = insertelement <4 x float> [[X0]], float [[TMP18]], i64 010317; CHECK-NEXT: [[_MSPROP7:%.*]] = extractelement <4 x i32> [[TMP1]], i64 010318; CHECK-NEXT: [[TMP20:%.*]] = extractelement <4 x float> [[X0]], i64 010319; CHECK-NEXT: [[_MSPROP8:%.*]] = extractelement <4 x i32> [[TMP2]], i64 010320; CHECK-NEXT: [[TMP21:%.*]] = extractelement <4 x float> [[X1]], i64 010321; CHECK-NEXT: [[_MSPROP9:%.*]] = extractelement <4 x i32> [[TMP3]], i64 010322; CHECK-NEXT: [[TMP22:%.*]] = extractelement <4 x float> [[X2]], i64 010323; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[_MSPROP7]], 010324; CHECK-NEXT: [[_MSCMP19:%.*]] = icmp ne i32 [[_MSPROP8]], 010325; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP19]]10326; CHECK-NEXT: [[_MSCMP20:%.*]] = icmp ne i32 [[_MSPROP9]], 010327; CHECK-NEXT: [[_MSOR21:%.*]] = or i1 [[_MSOR]], [[_MSCMP20]]10328; CHECK-NEXT: br i1 [[_MSOR21]], label [[TMP23:%.*]], label [[TMP24:%.*]], !prof [[PROF1]]10329; CHECK: 23:10330; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]10331; CHECK-NEXT: unreachable10332; CHECK: 24:10333; CHECK-NEXT: [[TMP25:%.*]] = call float @llvm.x86.avx512.vfmadd.f32(float [[TMP20]], float [[TMP21]], float [[TMP22]], i32 11)10334; CHECK-NEXT: [[_MSPROP10:%.*]] = insertelement <4 x i32> [[TMP1]], i32 0, i64 010335; CHECK-NEXT: [[TMP26:%.*]] = insertelement <4 x float> [[X0]], float [[TMP25]], i64 010336; CHECK-NEXT: [[_MSPROP11:%.*]] = extractelement <4 x i32> [[TMP1]], i64 010337; CHECK-NEXT: [[TMP27:%.*]] = extractelement <4 x float> [[X0]], i64 010338; CHECK-NEXT: [[_MSPROP12:%.*]] = extractelement <4 x i32> [[TMP2]], i64 010339; CHECK-NEXT: [[TMP28:%.*]] = extractelement <4 x float> [[X1]], i64 010340; CHECK-NEXT: [[_MSPROP13:%.*]] = extractelement <4 x i32> [[TMP3]], i64 010341; CHECK-NEXT: [[TMP29:%.*]] = extractelement <4 x float> [[X2]], i64 010342; CHECK-NEXT: [[_MSCMP22:%.*]] = icmp ne i32 [[_MSPROP11]], 010343; CHECK-NEXT: [[_MSCMP23:%.*]] = icmp ne i32 [[_MSPROP12]], 010344; CHECK-NEXT: [[_MSOR24:%.*]] = or i1 [[_MSCMP22]], [[_MSCMP23]]10345; CHECK-NEXT: [[_MSCMP25:%.*]] = icmp ne i32 [[_MSPROP13]], 010346; CHECK-NEXT: [[_MSOR26:%.*]] = or i1 [[_MSOR24]], [[_MSCMP25]]10347; CHECK-NEXT: br i1 [[_MSOR26]], label [[TMP30:%.*]], label [[TMP31:%.*]], !prof [[PROF1]]10348; CHECK: 30:10349; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]10350; CHECK-NEXT: unreachable10351; CHECK: 31:10352; CHECK-NEXT: [[TMP32:%.*]] = call float @llvm.x86.avx512.vfmadd.f32(float [[TMP27]], float [[TMP28]], float [[TMP29]], i32 10)10353; CHECK-NEXT: [[TMP33:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>10354; CHECK-NEXT: [[TMP34:%.*]] = bitcast i8 [[X3]] to <8 x i1>10355; CHECK-NEXT: [[_MSPROP14:%.*]] = extractelement <8 x i1> [[TMP33]], i64 010356; CHECK-NEXT: [[TMP35:%.*]] = extractelement <8 x i1> [[TMP34]], i64 010357; CHECK-NEXT: [[TMP36:%.*]] = select i1 [[TMP35]], i32 0, i32 [[_MSPROP11]]10358; CHECK-NEXT: [[TMP37:%.*]] = bitcast float [[TMP32]] to i3210359; CHECK-NEXT: [[TMP38:%.*]] = bitcast float [[TMP27]] to i3210360; CHECK-NEXT: [[TMP39:%.*]] = xor i32 [[TMP37]], [[TMP38]]10361; CHECK-NEXT: [[TMP40:%.*]] = or i32 [[TMP39]], 010362; CHECK-NEXT: [[TMP41:%.*]] = or i32 [[TMP40]], [[_MSPROP11]]10363; CHECK-NEXT: [[_MSPROP_SELECT15:%.*]] = select i1 [[_MSPROP14]], i32 [[TMP41]], i32 [[TMP36]]10364; CHECK-NEXT: [[TMP42:%.*]] = select i1 [[TMP35]], float [[TMP32]], float [[TMP27]]10365; CHECK-NEXT: [[_MSPROP16:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[_MSPROP_SELECT15]], i64 010366; CHECK-NEXT: [[TMP43:%.*]] = insertelement <4 x float> [[X0]], float [[TMP42]], i64 010367; CHECK-NEXT: [[_MSPROP17:%.*]] = or <4 x i32> [[_MSPROP6]], [[_MSPROP10]]10368; CHECK-NEXT: [[RES3:%.*]] = fadd <4 x float> [[TMP19]], [[TMP26]]10369; CHECK-NEXT: [[_MSPROP18:%.*]] = or <4 x i32> [[_MSPROP16]], [[_MSPROP17]]10370; CHECK-NEXT: [[RES4:%.*]] = fadd <4 x float> [[TMP43]], [[RES3]]10371; CHECK-NEXT: store <4 x i32> [[_MSPROP18]], ptr @__msan_retval_tls, align 810372; CHECK-NEXT: ret <4 x float> [[RES4]]10373;10374 %1 = extractelement <4 x float> %x0, i64 010375 %2 = extractelement <4 x float> %x1, i64 010376 %3 = extractelement <4 x float> %x2, i64 010377 %4 = call float @llvm.fma.f32(float %1, float %2, float %3)10378 %5 = bitcast i8 %x3 to <8 x i1>10379 %6 = extractelement <8 x i1> %5, i64 010380 %7 = select i1 %6, float %4, float %110381 %8 = insertelement <4 x float> %x0, float %7, i64 010382 %9 = extractelement <4 x float> %x0, i64 010383 %10 = extractelement <4 x float> %x1, i64 010384 %11 = extractelement <4 x float> %x2, i64 010385 %12 = call float @llvm.x86.avx512.vfmadd.f32(float %9, float %10, float %11, i32 11)10386 %13 = insertelement <4 x float> %x0, float %12, i64 010387 %14 = extractelement <4 x float> %x0, i64 010388 %15 = extractelement <4 x float> %x1, i64 010389 %16 = extractelement <4 x float> %x2, i64 010390 %17 = call float @llvm.x86.avx512.vfmadd.f32(float %14, float %15, float %16, i32 10)10391 %18 = bitcast i8 %x3 to <8 x i1>10392 %19 = extractelement <8 x i1> %18, i64 010393 %20 = select i1 %19, float %17, float %1410394 %21 = insertelement <4 x float> %x0, float %20, i64 010395 %res3 = fadd <4 x float> %8, %1310396 %res4 = fadd <4 x float> %21, %res310397 ret <4 x float> %res410398}10399 10400define <2 x double>@test_int_x86_avx512_maskz_vfmadd_sd(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3,i32 %x4 ){10401; CHECK-LABEL: @test_int_x86_avx512_maskz_vfmadd_sd(10402; CHECK-NEXT: call void @llvm.donothing()10403; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x double> [[X0:%.*]], i64 010404; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x double> [[X1:%.*]], i64 010405; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x double> [[X2:%.*]], i64 010406; CHECK-NEXT: [[TMP4:%.*]] = call double @llvm.fma.f64(double [[TMP1]], double [[TMP2]], double [[TMP3]])10407; CHECK-NEXT: [[TMP5:%.*]] = bitcast i8 [[X3:%.*]] to <8 x i1>10408; CHECK-NEXT: [[TMP6:%.*]] = extractelement <8 x i1> [[TMP5]], i64 010409; CHECK-NEXT: [[TMP7:%.*]] = select i1 [[TMP6]], i64 0, i64 010410; CHECK-NEXT: [[TMP8:%.*]] = bitcast double [[TMP4]] to i6410411; CHECK-NEXT: [[TMP9:%.*]] = xor i64 [[TMP8]], 010412; CHECK-NEXT: [[TMP10:%.*]] = or i64 [[TMP9]], 010413; CHECK-NEXT: [[TMP11:%.*]] = or i64 [[TMP10]], 010414; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select i1 false, i64 [[TMP11]], i64 [[TMP7]]10415; CHECK-NEXT: [[TMP12:%.*]] = select i1 [[TMP6]], double [[TMP4]], double 0.000000e+0010416; CHECK-NEXT: [[TMP13:%.*]] = insertelement <2 x double> [[X0]], double [[TMP12]], i64 010417; CHECK-NEXT: [[TMP14:%.*]] = extractelement <2 x double> [[X0]], i64 010418; CHECK-NEXT: [[TMP15:%.*]] = extractelement <2 x double> [[X1]], i64 010419; CHECK-NEXT: [[TMP16:%.*]] = extractelement <2 x double> [[X2]], i64 010420; CHECK-NEXT: [[TMP17:%.*]] = call double @llvm.x86.avx512.vfmadd.f64(double [[TMP14]], double [[TMP15]], double [[TMP16]], i32 11)10421; CHECK-NEXT: [[TMP18:%.*]] = bitcast i8 [[X3]] to <8 x i1>10422; CHECK-NEXT: [[TMP19:%.*]] = extractelement <8 x i1> [[TMP18]], i64 010423; CHECK-NEXT: [[TMP20:%.*]] = select i1 [[TMP19]], i64 0, i64 010424; CHECK-NEXT: [[TMP21:%.*]] = bitcast double [[TMP17]] to i6410425; CHECK-NEXT: [[TMP22:%.*]] = xor i64 [[TMP21]], 010426; CHECK-NEXT: [[TMP23:%.*]] = or i64 [[TMP22]], 010427; CHECK-NEXT: [[TMP24:%.*]] = or i64 [[TMP23]], 010428; CHECK-NEXT: [[_MSPROP_SELECT1:%.*]] = select i1 false, i64 [[TMP24]], i64 [[TMP20]]10429; CHECK-NEXT: [[TMP25:%.*]] = select i1 [[TMP19]], double [[TMP17]], double 0.000000e+0010430; CHECK-NEXT: [[TMP26:%.*]] = insertelement <2 x double> [[X0]], double [[TMP25]], i64 010431; CHECK-NEXT: [[RES2:%.*]] = fadd <2 x double> [[TMP13]], [[TMP26]]10432; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 810433; CHECK-NEXT: ret <2 x double> [[RES2]]10434;10435 %1 = extractelement <2 x double> %x0, i64 010436 %2 = extractelement <2 x double> %x1, i64 010437 %3 = extractelement <2 x double> %x2, i64 010438 %4 = call double @llvm.fma.f64(double %1, double %2, double %3)10439 %5 = bitcast i8 %x3 to <8 x i1>10440 %6 = extractelement <8 x i1> %5, i64 010441 %7 = select i1 %6, double %4, double 0.000000e+0010442 %8 = insertelement <2 x double> %x0, double %7, i64 010443 %9 = extractelement <2 x double> %x0, i64 010444 %10 = extractelement <2 x double> %x1, i64 010445 %11 = extractelement <2 x double> %x2, i64 010446 %12 = call double @llvm.x86.avx512.vfmadd.f64(double %9, double %10, double %11, i32 11)10447 %13 = bitcast i8 %x3 to <8 x i1>10448 %14 = extractelement <8 x i1> %13, i64 010449 %15 = select i1 %14, double %12, double 0.000000e+0010450 %16 = insertelement <2 x double> %x0, double %15, i64 010451 %res2 = fadd <2 x double> %8, %1610452 ret <2 x double> %res210453}10454 10455declare float @llvm.fma.f32(float, float, float) #110456declare float @llvm.x86.avx512.vfmadd.f32(float, float, float, i32) #010457 10458define <4 x float>@test_int_x86_avx512_maskz_vfmadd_ss(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3,i32 %x4 ){10459; CHECK-LABEL: @test_int_x86_avx512_maskz_vfmadd_ss(10460; CHECK-NEXT: call void @llvm.donothing()10461; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x float> [[X0:%.*]], i64 010462; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x float> [[X1:%.*]], i64 010463; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x float> [[X2:%.*]], i64 010464; CHECK-NEXT: [[TMP4:%.*]] = call float @llvm.fma.f32(float [[TMP1]], float [[TMP2]], float [[TMP3]])10465; CHECK-NEXT: [[TMP5:%.*]] = bitcast i8 [[X3:%.*]] to <8 x i1>10466; CHECK-NEXT: [[TMP6:%.*]] = extractelement <8 x i1> [[TMP5]], i64 010467; CHECK-NEXT: [[TMP7:%.*]] = select i1 [[TMP6]], i32 0, i32 010468; CHECK-NEXT: [[TMP8:%.*]] = bitcast float [[TMP4]] to i3210469; CHECK-NEXT: [[TMP9:%.*]] = xor i32 [[TMP8]], 010470; CHECK-NEXT: [[TMP10:%.*]] = or i32 [[TMP9]], 010471; CHECK-NEXT: [[TMP11:%.*]] = or i32 [[TMP10]], 010472; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select i1 false, i32 [[TMP11]], i32 [[TMP7]]10473; CHECK-NEXT: [[TMP12:%.*]] = select i1 [[TMP6]], float [[TMP4]], float 0.000000e+0010474; CHECK-NEXT: [[TMP13:%.*]] = insertelement <4 x float> [[X0]], float [[TMP12]], i64 010475; CHECK-NEXT: [[TMP14:%.*]] = extractelement <4 x float> [[X0]], i64 010476; CHECK-NEXT: [[TMP15:%.*]] = extractelement <4 x float> [[X1]], i64 010477; CHECK-NEXT: [[TMP16:%.*]] = extractelement <4 x float> [[X2]], i64 010478; CHECK-NEXT: [[TMP17:%.*]] = call float @llvm.x86.avx512.vfmadd.f32(float [[TMP14]], float [[TMP15]], float [[TMP16]], i32 11)10479; CHECK-NEXT: [[TMP18:%.*]] = bitcast i8 [[X3]] to <8 x i1>10480; CHECK-NEXT: [[TMP19:%.*]] = extractelement <8 x i1> [[TMP18]], i64 010481; CHECK-NEXT: [[TMP20:%.*]] = select i1 [[TMP19]], i32 0, i32 010482; CHECK-NEXT: [[TMP21:%.*]] = bitcast float [[TMP17]] to i3210483; CHECK-NEXT: [[TMP22:%.*]] = xor i32 [[TMP21]], 010484; CHECK-NEXT: [[TMP23:%.*]] = or i32 [[TMP22]], 010485; CHECK-NEXT: [[TMP24:%.*]] = or i32 [[TMP23]], 010486; CHECK-NEXT: [[_MSPROP_SELECT1:%.*]] = select i1 false, i32 [[TMP24]], i32 [[TMP20]]10487; CHECK-NEXT: [[TMP25:%.*]] = select i1 [[TMP19]], float [[TMP17]], float 0.000000e+0010488; CHECK-NEXT: [[TMP26:%.*]] = insertelement <4 x float> [[X0]], float [[TMP25]], i64 010489; CHECK-NEXT: [[RES2:%.*]] = fadd <4 x float> [[TMP13]], [[TMP26]]10490; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 810491; CHECK-NEXT: ret <4 x float> [[RES2]]10492;10493 %1 = extractelement <4 x float> %x0, i64 010494 %2 = extractelement <4 x float> %x1, i64 010495 %3 = extractelement <4 x float> %x2, i64 010496 %4 = call float @llvm.fma.f32(float %1, float %2, float %3)10497 %5 = bitcast i8 %x3 to <8 x i1>10498 %6 = extractelement <8 x i1> %5, i64 010499 %7 = select i1 %6, float %4, float 0.000000e+0010500 %8 = insertelement <4 x float> %x0, float %7, i64 010501 %9 = extractelement <4 x float> %x0, i64 010502 %10 = extractelement <4 x float> %x1, i64 010503 %11 = extractelement <4 x float> %x2, i64 010504 %12 = call float @llvm.x86.avx512.vfmadd.f32(float %9, float %10, float %11, i32 11)10505 %13 = bitcast i8 %x3 to <8 x i1>10506 %14 = extractelement <8 x i1> %13, i64 010507 %15 = select i1 %14, float %12, float 0.000000e+0010508 %16 = insertelement <4 x float> %x0, float %15, i64 010509 %res2 = fadd <4 x float> %8, %1610510 ret <4 x float> %res210511}10512 10513define <4 x float> @test_int_x86_avx512_maskz_vfmadd_ss_load0(i8 zeroext %0, ptr nocapture readonly %1, float %2, float %3) #0 {10514; CHECK-LABEL: @test_int_x86_avx512_maskz_vfmadd_ss_load0(10515; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 810516; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 810517; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 810518; CHECK-NEXT: [[TMP8:%.*]] = load i8, ptr @__msan_param_tls, align 810519; CHECK-NEXT: call void @llvm.donothing()10520; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP5]], 010521; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP9:%.*]], label [[TMP10:%.*]], !prof [[PROF1]]10522; CHECK: 9:10523; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]10524; CHECK-NEXT: unreachable10525; CHECK: 10:10526; CHECK-NEXT: [[TMP11:%.*]] = load <4 x float>, ptr [[TMP1:%.*]], align 1610527; CHECK-NEXT: [[TMP12:%.*]] = ptrtoint ptr [[TMP1]] to i6410528; CHECK-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], 8796093022208010529; CHECK-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP13]] to ptr10530; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP14]], align 1610531; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <4 x i32> [[_MSLD]], i64 010532; CHECK-NEXT: [[TMP15:%.*]] = extractelement <4 x float> [[TMP11]], i64 010533; CHECK-NEXT: [[_MSPROP1:%.*]] = or i32 [[_MSPROP]], [[TMP6]]10534; CHECK-NEXT: [[_MSPROP2:%.*]] = or i32 [[_MSPROP1]], [[TMP7]]10535; CHECK-NEXT: [[TMP16:%.*]] = tail call float @llvm.fma.f32(float [[TMP15]], float [[TMP2:%.*]], float [[TMP3:%.*]])10536; CHECK-NEXT: [[TMP17:%.*]] = bitcast i8 [[TMP8]] to <8 x i1>10537; CHECK-NEXT: [[TMP18:%.*]] = bitcast i8 [[TMP0:%.*]] to <8 x i1>10538; CHECK-NEXT: [[_MSPROP3:%.*]] = extractelement <8 x i1> [[TMP17]], i64 010539; CHECK-NEXT: [[TMP19:%.*]] = extractelement <8 x i1> [[TMP18]], i64 010540; CHECK-NEXT: [[TMP20:%.*]] = select i1 [[TMP19]], i32 [[_MSPROP2]], i32 010541; CHECK-NEXT: [[TMP21:%.*]] = bitcast float [[TMP16]] to i3210542; CHECK-NEXT: [[TMP22:%.*]] = xor i32 [[TMP21]], 010543; CHECK-NEXT: [[TMP23:%.*]] = or i32 [[TMP22]], [[_MSPROP2]]10544; CHECK-NEXT: [[TMP24:%.*]] = or i32 [[TMP23]], 010545; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select i1 [[_MSPROP3]], i32 [[TMP24]], i32 [[TMP20]]10546; CHECK-NEXT: [[TMP25:%.*]] = select i1 [[TMP19]], float [[TMP16]], float 0.000000e+0010547; CHECK-NEXT: [[_MSPROP4:%.*]] = insertelement <4 x i32> [[_MSLD]], i32 [[_MSPROP_SELECT]], i64 010548; CHECK-NEXT: [[TMP26:%.*]] = insertelement <4 x float> [[TMP11]], float [[TMP25]], i64 010549; CHECK-NEXT: store <4 x i32> [[_MSPROP4]], ptr @__msan_retval_tls, align 810550; CHECK-NEXT: ret <4 x float> [[TMP26]]10551;10552 %5 = load <4 x float>, ptr %1, align 1610553 %6 = extractelement <4 x float> %5, i64 010554 %7 = tail call float @llvm.fma.f32(float %6, float %2, float %3) #210555 %8 = bitcast i8 %0 to <8 x i1>10556 %9 = extractelement <8 x i1> %8, i64 010557 %10 = select i1 %9, float %7, float 0.000000e+0010558 %11 = insertelement <4 x float> %5, float %10, i64 010559 ret <4 x float> %1110560}10561 10562define <2 x double> @test_int_x86_avx512_mask3_vfmadd_sd(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3, i32 %x4) #0 {10563; CHECK-LABEL: @test_int_x86_avx512_mask3_vfmadd_sd(10564; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 810565; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 810566; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 810567; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 810568; CHECK-NEXT: call void @llvm.donothing()10569; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <2 x i64> [[TMP1]], i64 010570; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[X0:%.*]], i64 010571; CHECK-NEXT: [[_MSPROP1:%.*]] = extractelement <2 x i64> [[TMP2]], i64 010572; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x double> [[X1:%.*]], i64 010573; CHECK-NEXT: [[_MSPROP2:%.*]] = extractelement <2 x i64> [[TMP3]], i64 010574; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x double> [[X2:%.*]], i64 010575; CHECK-NEXT: [[_MSPROP3:%.*]] = or i64 [[_MSPROP]], [[_MSPROP1]]10576; CHECK-NEXT: [[_MSPROP4:%.*]] = or i64 [[_MSPROP3]], [[_MSPROP2]]10577; CHECK-NEXT: [[TMP8:%.*]] = call double @llvm.fma.f64(double [[TMP5]], double [[TMP6]], double [[TMP7]])10578; CHECK-NEXT: [[TMP9:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>10579; CHECK-NEXT: [[TMP10:%.*]] = bitcast i8 [[X3:%.*]] to <8 x i1>10580; CHECK-NEXT: [[_MSPROP5:%.*]] = extractelement <8 x i1> [[TMP9]], i64 010581; CHECK-NEXT: [[TMP11:%.*]] = extractelement <8 x i1> [[TMP10]], i64 010582; CHECK-NEXT: [[TMP12:%.*]] = select i1 [[TMP11]], i64 [[_MSPROP4]], i64 [[_MSPROP2]]10583; CHECK-NEXT: [[TMP13:%.*]] = bitcast double [[TMP8]] to i6410584; CHECK-NEXT: [[TMP14:%.*]] = bitcast double [[TMP7]] to i6410585; CHECK-NEXT: [[TMP15:%.*]] = xor i64 [[TMP13]], [[TMP14]]10586; CHECK-NEXT: [[TMP16:%.*]] = or i64 [[TMP15]], [[_MSPROP4]]10587; CHECK-NEXT: [[TMP17:%.*]] = or i64 [[TMP16]], [[_MSPROP2]]10588; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select i1 [[_MSPROP5]], i64 [[TMP17]], i64 [[TMP12]]10589; CHECK-NEXT: [[TMP18:%.*]] = select i1 [[TMP11]], double [[TMP8]], double [[TMP7]]10590; CHECK-NEXT: [[_MSPROP6:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[_MSPROP_SELECT]], i64 010591; CHECK-NEXT: [[TMP19:%.*]] = insertelement <2 x double> [[X2]], double [[TMP18]], i64 010592; CHECK-NEXT: [[_MSPROP7:%.*]] = extractelement <2 x i64> [[TMP1]], i64 010593; CHECK-NEXT: [[TMP20:%.*]] = extractelement <2 x double> [[X0]], i64 010594; CHECK-NEXT: [[_MSPROP8:%.*]] = extractelement <2 x i64> [[TMP2]], i64 010595; CHECK-NEXT: [[TMP21:%.*]] = extractelement <2 x double> [[X1]], i64 010596; CHECK-NEXT: [[_MSPROP9:%.*]] = extractelement <2 x i64> [[TMP3]], i64 010597; CHECK-NEXT: [[TMP22:%.*]] = extractelement <2 x double> [[X2]], i64 010598; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[_MSPROP7]], 010599; CHECK-NEXT: [[_MSCMP19:%.*]] = icmp ne i64 [[_MSPROP8]], 010600; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP19]]10601; CHECK-NEXT: [[_MSCMP20:%.*]] = icmp ne i64 [[_MSPROP9]], 010602; CHECK-NEXT: [[_MSOR21:%.*]] = or i1 [[_MSOR]], [[_MSCMP20]]10603; CHECK-NEXT: br i1 [[_MSOR21]], label [[TMP23:%.*]], label [[TMP24:%.*]], !prof [[PROF1]]10604; CHECK: 23:10605; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]10606; CHECK-NEXT: unreachable10607; CHECK: 24:10608; CHECK-NEXT: [[TMP25:%.*]] = call double @llvm.x86.avx512.vfmadd.f64(double [[TMP20]], double [[TMP21]], double [[TMP22]], i32 11)10609; CHECK-NEXT: [[_MSPROP10:%.*]] = insertelement <2 x i64> [[TMP3]], i64 0, i64 010610; CHECK-NEXT: [[TMP26:%.*]] = insertelement <2 x double> [[X2]], double [[TMP25]], i64 010611; CHECK-NEXT: [[_MSPROP11:%.*]] = extractelement <2 x i64> [[TMP1]], i64 010612; CHECK-NEXT: [[TMP27:%.*]] = extractelement <2 x double> [[X0]], i64 010613; CHECK-NEXT: [[_MSPROP12:%.*]] = extractelement <2 x i64> [[TMP2]], i64 010614; CHECK-NEXT: [[TMP28:%.*]] = extractelement <2 x double> [[X1]], i64 010615; CHECK-NEXT: [[_MSPROP13:%.*]] = extractelement <2 x i64> [[TMP3]], i64 010616; CHECK-NEXT: [[TMP29:%.*]] = extractelement <2 x double> [[X2]], i64 010617; CHECK-NEXT: [[_MSCMP22:%.*]] = icmp ne i64 [[_MSPROP11]], 010618; CHECK-NEXT: [[_MSCMP23:%.*]] = icmp ne i64 [[_MSPROP12]], 010619; CHECK-NEXT: [[_MSOR24:%.*]] = or i1 [[_MSCMP22]], [[_MSCMP23]]10620; CHECK-NEXT: [[_MSCMP25:%.*]] = icmp ne i64 [[_MSPROP13]], 010621; CHECK-NEXT: [[_MSOR26:%.*]] = or i1 [[_MSOR24]], [[_MSCMP25]]10622; CHECK-NEXT: br i1 [[_MSOR26]], label [[TMP30:%.*]], label [[TMP31:%.*]], !prof [[PROF1]]10623; CHECK: 30:10624; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]10625; CHECK-NEXT: unreachable10626; CHECK: 31:10627; CHECK-NEXT: [[TMP32:%.*]] = call double @llvm.x86.avx512.vfmadd.f64(double [[TMP27]], double [[TMP28]], double [[TMP29]], i32 10)10628; CHECK-NEXT: [[TMP33:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>10629; CHECK-NEXT: [[TMP34:%.*]] = bitcast i8 [[X3]] to <8 x i1>10630; CHECK-NEXT: [[_MSPROP14:%.*]] = extractelement <8 x i1> [[TMP33]], i64 010631; CHECK-NEXT: [[TMP35:%.*]] = extractelement <8 x i1> [[TMP34]], i64 010632; CHECK-NEXT: [[TMP36:%.*]] = select i1 [[TMP35]], i64 0, i64 [[_MSPROP13]]10633; CHECK-NEXT: [[TMP37:%.*]] = bitcast double [[TMP32]] to i6410634; CHECK-NEXT: [[TMP38:%.*]] = bitcast double [[TMP29]] to i6410635; CHECK-NEXT: [[TMP39:%.*]] = xor i64 [[TMP37]], [[TMP38]]10636; CHECK-NEXT: [[TMP40:%.*]] = or i64 [[TMP39]], 010637; CHECK-NEXT: [[TMP41:%.*]] = or i64 [[TMP40]], [[_MSPROP13]]10638; CHECK-NEXT: [[_MSPROP_SELECT15:%.*]] = select i1 [[_MSPROP14]], i64 [[TMP41]], i64 [[TMP36]]10639; CHECK-NEXT: [[TMP42:%.*]] = select i1 [[TMP35]], double [[TMP32]], double [[TMP29]]10640; CHECK-NEXT: [[_MSPROP16:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[_MSPROP_SELECT15]], i64 010641; CHECK-NEXT: [[TMP43:%.*]] = insertelement <2 x double> [[X2]], double [[TMP42]], i64 010642; CHECK-NEXT: [[_MSPROP17:%.*]] = or <2 x i64> [[_MSPROP6]], [[_MSPROP10]]10643; CHECK-NEXT: [[RES3:%.*]] = fadd <2 x double> [[TMP19]], [[TMP26]]10644; CHECK-NEXT: [[_MSPROP18:%.*]] = or <2 x i64> [[_MSPROP16]], [[_MSPROP17]]10645; CHECK-NEXT: [[RES4:%.*]] = fadd <2 x double> [[TMP43]], [[RES3]]10646; CHECK-NEXT: store <2 x i64> [[_MSPROP18]], ptr @__msan_retval_tls, align 810647; CHECK-NEXT: ret <2 x double> [[RES4]]10648;10649 %1 = extractelement <2 x double> %x0, i64 010650 %2 = extractelement <2 x double> %x1, i64 010651 %3 = extractelement <2 x double> %x2, i64 010652 %4 = call double @llvm.fma.f64(double %1, double %2, double %3)10653 %5 = bitcast i8 %x3 to <8 x i1>10654 %6 = extractelement <8 x i1> %5, i64 010655 %7 = select i1 %6, double %4, double %310656 %8 = insertelement <2 x double> %x2, double %7, i64 010657 %9 = extractelement <2 x double> %x0, i64 010658 %10 = extractelement <2 x double> %x1, i64 010659 %11 = extractelement <2 x double> %x2, i64 010660 %12 = call double @llvm.x86.avx512.vfmadd.f64(double %9, double %10, double %11, i32 11)10661 %13 = insertelement <2 x double> %x2, double %12, i64 010662 %14 = extractelement <2 x double> %x0, i64 010663 %15 = extractelement <2 x double> %x1, i64 010664 %16 = extractelement <2 x double> %x2, i64 010665 %17 = call double @llvm.x86.avx512.vfmadd.f64(double %14, double %15, double %16, i32 10)10666 %18 = bitcast i8 %x3 to <8 x i1>10667 %19 = extractelement <8 x i1> %18, i64 010668 %20 = select i1 %19, double %17, double %1610669 %21 = insertelement <2 x double> %x2, double %20, i64 010670 %res3 = fadd <2 x double> %8, %1310671 %res4 = fadd <2 x double> %21, %res310672 ret <2 x double> %res410673}10674 10675define <4 x float> @test_int_x86_avx512_mask3_vfmadd_ss(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3, i32 %x4) #0 {10676; CHECK-LABEL: @test_int_x86_avx512_mask3_vfmadd_ss(10677; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 810678; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 810679; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 810680; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 810681; CHECK-NEXT: call void @llvm.donothing()10682; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <4 x i32> [[TMP1]], i64 010683; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x float> [[X0:%.*]], i64 010684; CHECK-NEXT: [[_MSPROP1:%.*]] = extractelement <4 x i32> [[TMP2]], i64 010685; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x float> [[X1:%.*]], i64 010686; CHECK-NEXT: [[_MSPROP2:%.*]] = extractelement <4 x i32> [[TMP3]], i64 010687; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x float> [[X2:%.*]], i64 010688; CHECK-NEXT: [[_MSPROP3:%.*]] = or i32 [[_MSPROP]], [[_MSPROP1]]10689; CHECK-NEXT: [[_MSPROP4:%.*]] = or i32 [[_MSPROP3]], [[_MSPROP2]]10690; CHECK-NEXT: [[TMP8:%.*]] = call float @llvm.fma.f32(float [[TMP5]], float [[TMP6]], float [[TMP7]])10691; CHECK-NEXT: [[TMP9:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>10692; CHECK-NEXT: [[TMP10:%.*]] = bitcast i8 [[X3:%.*]] to <8 x i1>10693; CHECK-NEXT: [[_MSPROP5:%.*]] = extractelement <8 x i1> [[TMP9]], i64 010694; CHECK-NEXT: [[TMP11:%.*]] = extractelement <8 x i1> [[TMP10]], i64 010695; CHECK-NEXT: [[TMP12:%.*]] = select i1 [[TMP11]], i32 [[_MSPROP4]], i32 [[_MSPROP2]]10696; CHECK-NEXT: [[TMP13:%.*]] = bitcast float [[TMP8]] to i3210697; CHECK-NEXT: [[TMP14:%.*]] = bitcast float [[TMP7]] to i3210698; CHECK-NEXT: [[TMP15:%.*]] = xor i32 [[TMP13]], [[TMP14]]10699; CHECK-NEXT: [[TMP16:%.*]] = or i32 [[TMP15]], [[_MSPROP4]]10700; CHECK-NEXT: [[TMP17:%.*]] = or i32 [[TMP16]], [[_MSPROP2]]10701; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select i1 [[_MSPROP5]], i32 [[TMP17]], i32 [[TMP12]]10702; CHECK-NEXT: [[TMP18:%.*]] = select i1 [[TMP11]], float [[TMP8]], float [[TMP7]]10703; CHECK-NEXT: [[_MSPROP6:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[_MSPROP_SELECT]], i64 010704; CHECK-NEXT: [[TMP19:%.*]] = insertelement <4 x float> [[X2]], float [[TMP18]], i64 010705; CHECK-NEXT: [[_MSPROP7:%.*]] = extractelement <4 x i32> [[TMP1]], i64 010706; CHECK-NEXT: [[TMP20:%.*]] = extractelement <4 x float> [[X0]], i64 010707; CHECK-NEXT: [[_MSPROP8:%.*]] = extractelement <4 x i32> [[TMP2]], i64 010708; CHECK-NEXT: [[TMP21:%.*]] = extractelement <4 x float> [[X1]], i64 010709; CHECK-NEXT: [[_MSPROP9:%.*]] = extractelement <4 x i32> [[TMP3]], i64 010710; CHECK-NEXT: [[TMP22:%.*]] = extractelement <4 x float> [[X2]], i64 010711; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[_MSPROP7]], 010712; CHECK-NEXT: [[_MSCMP19:%.*]] = icmp ne i32 [[_MSPROP8]], 010713; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP19]]10714; CHECK-NEXT: [[_MSCMP20:%.*]] = icmp ne i32 [[_MSPROP9]], 010715; CHECK-NEXT: [[_MSOR21:%.*]] = or i1 [[_MSOR]], [[_MSCMP20]]10716; CHECK-NEXT: br i1 [[_MSOR21]], label [[TMP23:%.*]], label [[TMP24:%.*]], !prof [[PROF1]]10717; CHECK: 23:10718; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]10719; CHECK-NEXT: unreachable10720; CHECK: 24:10721; CHECK-NEXT: [[TMP25:%.*]] = call float @llvm.x86.avx512.vfmadd.f32(float [[TMP20]], float [[TMP21]], float [[TMP22]], i32 11)10722; CHECK-NEXT: [[_MSPROP10:%.*]] = insertelement <4 x i32> [[TMP3]], i32 0, i64 010723; CHECK-NEXT: [[TMP26:%.*]] = insertelement <4 x float> [[X2]], float [[TMP25]], i64 010724; CHECK-NEXT: [[_MSPROP11:%.*]] = extractelement <4 x i32> [[TMP1]], i64 010725; CHECK-NEXT: [[TMP27:%.*]] = extractelement <4 x float> [[X0]], i64 010726; CHECK-NEXT: [[_MSPROP12:%.*]] = extractelement <4 x i32> [[TMP2]], i64 010727; CHECK-NEXT: [[TMP28:%.*]] = extractelement <4 x float> [[X1]], i64 010728; CHECK-NEXT: [[_MSPROP13:%.*]] = extractelement <4 x i32> [[TMP3]], i64 010729; CHECK-NEXT: [[TMP29:%.*]] = extractelement <4 x float> [[X2]], i64 010730; CHECK-NEXT: [[_MSCMP22:%.*]] = icmp ne i32 [[_MSPROP11]], 010731; CHECK-NEXT: [[_MSCMP23:%.*]] = icmp ne i32 [[_MSPROP12]], 010732; CHECK-NEXT: [[_MSOR24:%.*]] = or i1 [[_MSCMP22]], [[_MSCMP23]]10733; CHECK-NEXT: [[_MSCMP25:%.*]] = icmp ne i32 [[_MSPROP13]], 010734; CHECK-NEXT: [[_MSOR26:%.*]] = or i1 [[_MSOR24]], [[_MSCMP25]]10735; CHECK-NEXT: br i1 [[_MSOR26]], label [[TMP30:%.*]], label [[TMP31:%.*]], !prof [[PROF1]]10736; CHECK: 30:10737; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]10738; CHECK-NEXT: unreachable10739; CHECK: 31:10740; CHECK-NEXT: [[TMP32:%.*]] = call float @llvm.x86.avx512.vfmadd.f32(float [[TMP27]], float [[TMP28]], float [[TMP29]], i32 10)10741; CHECK-NEXT: [[TMP33:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>10742; CHECK-NEXT: [[TMP34:%.*]] = bitcast i8 [[X3]] to <8 x i1>10743; CHECK-NEXT: [[_MSPROP14:%.*]] = extractelement <8 x i1> [[TMP33]], i64 010744; CHECK-NEXT: [[TMP35:%.*]] = extractelement <8 x i1> [[TMP34]], i64 010745; CHECK-NEXT: [[TMP36:%.*]] = select i1 [[TMP35]], i32 0, i32 [[_MSPROP13]]10746; CHECK-NEXT: [[TMP37:%.*]] = bitcast float [[TMP32]] to i3210747; CHECK-NEXT: [[TMP38:%.*]] = bitcast float [[TMP29]] to i3210748; CHECK-NEXT: [[TMP39:%.*]] = xor i32 [[TMP37]], [[TMP38]]10749; CHECK-NEXT: [[TMP40:%.*]] = or i32 [[TMP39]], 010750; CHECK-NEXT: [[TMP41:%.*]] = or i32 [[TMP40]], [[_MSPROP13]]10751; CHECK-NEXT: [[_MSPROP_SELECT15:%.*]] = select i1 [[_MSPROP14]], i32 [[TMP41]], i32 [[TMP36]]10752; CHECK-NEXT: [[TMP42:%.*]] = select i1 [[TMP35]], float [[TMP32]], float [[TMP29]]10753; CHECK-NEXT: [[_MSPROP16:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[_MSPROP_SELECT15]], i64 010754; CHECK-NEXT: [[TMP43:%.*]] = insertelement <4 x float> [[X2]], float [[TMP42]], i64 010755; CHECK-NEXT: [[_MSPROP17:%.*]] = or <4 x i32> [[_MSPROP6]], [[_MSPROP10]]10756; CHECK-NEXT: [[RES3:%.*]] = fadd <4 x float> [[TMP19]], [[TMP26]]10757; CHECK-NEXT: [[_MSPROP18:%.*]] = or <4 x i32> [[_MSPROP16]], [[_MSPROP17]]10758; CHECK-NEXT: [[RES4:%.*]] = fadd <4 x float> [[TMP43]], [[RES3]]10759; CHECK-NEXT: store <4 x i32> [[_MSPROP18]], ptr @__msan_retval_tls, align 810760; CHECK-NEXT: ret <4 x float> [[RES4]]10761;10762 %1 = extractelement <4 x float> %x0, i64 010763 %2 = extractelement <4 x float> %x1, i64 010764 %3 = extractelement <4 x float> %x2, i64 010765 %4 = call float @llvm.fma.f32(float %1, float %2, float %3)10766 %5 = bitcast i8 %x3 to <8 x i1>10767 %6 = extractelement <8 x i1> %5, i64 010768 %7 = select i1 %6, float %4, float %310769 %8 = insertelement <4 x float> %x2, float %7, i64 010770 %9 = extractelement <4 x float> %x0, i64 010771 %10 = extractelement <4 x float> %x1, i64 010772 %11 = extractelement <4 x float> %x2, i64 010773 %12 = call float @llvm.x86.avx512.vfmadd.f32(float %9, float %10, float %11, i32 11)10774 %13 = insertelement <4 x float> %x2, float %12, i64 010775 %14 = extractelement <4 x float> %x0, i64 010776 %15 = extractelement <4 x float> %x1, i64 010777 %16 = extractelement <4 x float> %x2, i64 010778 %17 = call float @llvm.x86.avx512.vfmadd.f32(float %14, float %15, float %16, i32 10)10779 %18 = bitcast i8 %x3 to <8 x i1>10780 %19 = extractelement <8 x i1> %18, i64 010781 %20 = select i1 %19, float %17, float %1610782 %21 = insertelement <4 x float> %x2, float %20, i64 010783 %res3 = fadd <4 x float> %8, %1310784 %res4 = fadd <4 x float> %21, %res310785 ret <4 x float> %res410786}10787 10788define void @fmadd_ss_mask_memfold(ptr %a, ptr %b, i8 %c, <4 x float> %extra_param, <4 x float> %extra_param2) #0 {10789; CHECK-LABEL: @fmadd_ss_mask_memfold(10790; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 810791; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 810792; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 810793; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 810794; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 810795; CHECK-NEXT: call void @llvm.donothing()10796; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 010797; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP9:%.*]], label [[TMP10:%.*]], !prof [[PROF1]]10798; CHECK: 6:10799; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]10800; CHECK-NEXT: unreachable10801; CHECK: 7:10802; CHECK-NEXT: [[A_VAL:%.*]] = load float, ptr [[A:%.*]], align 410803; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[A]] to i6410804; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 8796093022208010805; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr10806; CHECK-NEXT: [[_MSLD:%.*]] = load i32, ptr [[TMP8]], align 410807; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <4 x i32> [[TMP4]], i32 [[_MSLD]], i32 010808; CHECK-NEXT: [[AV0:%.*]] = insertelement <4 x float> [[EXTRA_PARAM:%.*]], float [[A_VAL]], i32 010809; CHECK-NEXT: [[_MSPROP1:%.*]] = insertelement <4 x i32> [[_MSPROP]], i32 0, i32 110810; CHECK-NEXT: [[AV1:%.*]] = insertelement <4 x float> [[AV0]], float 0.000000e+00, i32 110811; CHECK-NEXT: [[_MSPROP2:%.*]] = insertelement <4 x i32> [[_MSPROP1]], i32 0, i32 210812; CHECK-NEXT: [[AV2:%.*]] = insertelement <4 x float> [[AV1]], float 0.000000e+00, i32 210813; CHECK-NEXT: [[_MSPROP3:%.*]] = insertelement <4 x i32> [[_MSPROP2]], i32 0, i32 310814; CHECK-NEXT: [[AV:%.*]] = insertelement <4 x float> [[AV2]], float 0.000000e+00, i32 310815; CHECK-NEXT: [[_MSCMP17:%.*]] = icmp ne i64 [[TMP2]], 010816; CHECK-NEXT: br i1 [[_MSCMP17]], label [[TMP29:%.*]], label [[TMP30:%.*]], !prof [[PROF1]]10817; CHECK: 11:10818; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]10819; CHECK-NEXT: unreachable10820; CHECK: 12:10821; CHECK-NEXT: [[B_VAL:%.*]] = load float, ptr [[B:%.*]], align 410822; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[B]] to i6410823; CHECK-NEXT: [[TMP12:%.*]] = xor i64 [[TMP11]], 8796093022208010824; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to ptr10825; CHECK-NEXT: [[_MSLD4:%.*]] = load i32, ptr [[TMP13]], align 410826; CHECK-NEXT: [[_MSPROP5:%.*]] = insertelement <4 x i32> [[TMP5]], i32 [[_MSLD4]], i32 010827; CHECK-NEXT: [[BV0:%.*]] = insertelement <4 x float> [[EXTRA_PARAM2:%.*]], float [[B_VAL]], i32 010828; CHECK-NEXT: [[_MSPROP6:%.*]] = insertelement <4 x i32> [[_MSPROP5]], i32 0, i32 110829; CHECK-NEXT: [[BV1:%.*]] = insertelement <4 x float> [[BV0]], float 0.000000e+00, i32 110830; CHECK-NEXT: [[_MSPROP7:%.*]] = insertelement <4 x i32> [[_MSPROP6]], i32 0, i32 210831; CHECK-NEXT: [[BV2:%.*]] = insertelement <4 x float> [[BV1]], float 0.000000e+00, i32 210832; CHECK-NEXT: [[_MSPROP8:%.*]] = insertelement <4 x i32> [[_MSPROP7]], i32 0, i32 310833; CHECK-NEXT: [[BV:%.*]] = insertelement <4 x float> [[BV2]], float 0.000000e+00, i32 310834; CHECK-NEXT: [[_MSPROP9:%.*]] = extractelement <4 x i32> [[_MSPROP3]], i64 010835; CHECK-NEXT: [[TMP14:%.*]] = extractelement <4 x float> [[AV]], i64 010836; CHECK-NEXT: [[_MSPROP10:%.*]] = extractelement <4 x i32> [[_MSPROP8]], i64 010837; CHECK-NEXT: [[TMP15:%.*]] = extractelement <4 x float> [[BV]], i64 010838; CHECK-NEXT: [[_MSPROP11:%.*]] = extractelement <4 x i32> [[_MSPROP3]], i64 010839; CHECK-NEXT: [[TMP16:%.*]] = extractelement <4 x float> [[AV]], i64 010840; CHECK-NEXT: [[_MSPROP12:%.*]] = or i32 [[_MSPROP9]], [[_MSPROP10]]10841; CHECK-NEXT: [[_MSPROP13:%.*]] = or i32 [[_MSPROP12]], [[_MSPROP11]]10842; CHECK-NEXT: [[TMP17:%.*]] = call float @llvm.fma.f32(float [[TMP14]], float [[TMP15]], float [[TMP16]])10843; CHECK-NEXT: [[TMP18:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>10844; CHECK-NEXT: [[TMP19:%.*]] = bitcast i8 [[C:%.*]] to <8 x i1>10845; CHECK-NEXT: [[_MSPROP14:%.*]] = extractelement <8 x i1> [[TMP18]], i64 010846; CHECK-NEXT: [[TMP20:%.*]] = extractelement <8 x i1> [[TMP19]], i64 010847; CHECK-NEXT: [[TMP21:%.*]] = select i1 [[TMP20]], i32 [[_MSPROP13]], i32 [[_MSPROP9]]10848; CHECK-NEXT: [[TMP22:%.*]] = bitcast float [[TMP17]] to i3210849; CHECK-NEXT: [[TMP23:%.*]] = bitcast float [[TMP14]] to i3210850; CHECK-NEXT: [[TMP24:%.*]] = xor i32 [[TMP22]], [[TMP23]]10851; CHECK-NEXT: [[TMP25:%.*]] = or i32 [[TMP24]], [[_MSPROP13]]10852; CHECK-NEXT: [[TMP26:%.*]] = or i32 [[TMP25]], [[_MSPROP9]]10853; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select i1 [[_MSPROP14]], i32 [[TMP26]], i32 [[TMP21]]10854; CHECK-NEXT: [[TMP27:%.*]] = select i1 [[TMP20]], float [[TMP17]], float [[TMP14]]10855; CHECK-NEXT: [[_MSPROP15:%.*]] = insertelement <4 x i32> [[_MSPROP3]], i32 [[_MSPROP_SELECT]], i64 010856; CHECK-NEXT: [[TMP28:%.*]] = insertelement <4 x float> [[AV]], float [[TMP27]], i64 010857; CHECK-NEXT: [[_MSPROP16:%.*]] = extractelement <4 x i32> [[_MSPROP15]], i32 010858; CHECK-NEXT: [[SR:%.*]] = extractelement <4 x float> [[TMP28]], i32 010859; CHECK-NEXT: [[_MSCMP18:%.*]] = icmp ne i64 [[TMP1]], 010860; CHECK-NEXT: br i1 [[_MSCMP18]], label [[TMP34:%.*]], label [[TMP35:%.*]], !prof [[PROF1]]10861; CHECK: 31:10862; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]10863; CHECK-NEXT: unreachable10864; CHECK: 32:10865; CHECK-NEXT: [[TMP31:%.*]] = ptrtoint ptr [[A]] to i6410866; CHECK-NEXT: [[TMP32:%.*]] = xor i64 [[TMP31]], 8796093022208010867; CHECK-NEXT: [[TMP33:%.*]] = inttoptr i64 [[TMP32]] to ptr10868; CHECK-NEXT: store i32 [[_MSPROP16]], ptr [[TMP33]], align 410869; CHECK-NEXT: store float [[SR]], ptr [[A]], align 410870; CHECK-NEXT: ret void10871;10872 %a.val = load float, ptr %a10873 %av0 = insertelement <4 x float> %extra_param, float %a.val, i32 010874 %av1 = insertelement <4 x float> %av0, float 0.000000e+00, i32 110875 %av2 = insertelement <4 x float> %av1, float 0.000000e+00, i32 210876 %av = insertelement <4 x float> %av2, float 0.000000e+00, i32 310877 10878 %b.val = load float, ptr %b10879 %bv0 = insertelement <4 x float> %extra_param2, float %b.val, i32 010880 %bv1 = insertelement <4 x float> %bv0, float 0.000000e+00, i32 110881 %bv2 = insertelement <4 x float> %bv1, float 0.000000e+00, i32 210882 %bv = insertelement <4 x float> %bv2, float 0.000000e+00, i32 310883 %1 = extractelement <4 x float> %av, i64 010884 %2 = extractelement <4 x float> %bv, i64 010885 %3 = extractelement <4 x float> %av, i64 010886 %4 = call float @llvm.fma.f32(float %1, float %2, float %3)10887 %5 = bitcast i8 %c to <8 x i1>10888 %6 = extractelement <8 x i1> %5, i64 010889 %7 = select i1 %6, float %4, float %110890 %8 = insertelement <4 x float> %av, float %7, i64 010891 %sr = extractelement <4 x float> %8, i32 010892 store float %sr, ptr %a10893 ret void10894}10895 10896define void @fmadd_ss_maskz_memfold(ptr %a, ptr %b, i8 %c, <4 x float> %extra_param, <4 x float> %extra_param2) #0 {10897; CHECK-LABEL: @fmadd_ss_maskz_memfold(10898; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 810899; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 810900; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 810901; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 810902; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 810903; CHECK-NEXT: call void @llvm.donothing()10904; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 010905; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP9:%.*]], label [[TMP10:%.*]], !prof [[PROF1]]10906; CHECK: 6:10907; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]10908; CHECK-NEXT: unreachable10909; CHECK: 7:10910; CHECK-NEXT: [[A_VAL:%.*]] = load float, ptr [[A:%.*]], align 410911; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[A]] to i6410912; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 8796093022208010913; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr10914; CHECK-NEXT: [[_MSLD:%.*]] = load i32, ptr [[TMP8]], align 410915; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <4 x i32> [[TMP4]], i32 [[_MSLD]], i32 010916; CHECK-NEXT: [[AV0:%.*]] = insertelement <4 x float> [[EXTRA_PARAM:%.*]], float [[A_VAL]], i32 010917; CHECK-NEXT: [[_MSPROP1:%.*]] = insertelement <4 x i32> [[_MSPROP]], i32 0, i32 110918; CHECK-NEXT: [[AV1:%.*]] = insertelement <4 x float> [[AV0]], float 0.000000e+00, i32 110919; CHECK-NEXT: [[_MSPROP2:%.*]] = insertelement <4 x i32> [[_MSPROP1]], i32 0, i32 210920; CHECK-NEXT: [[AV2:%.*]] = insertelement <4 x float> [[AV1]], float 0.000000e+00, i32 210921; CHECK-NEXT: [[_MSPROP3:%.*]] = insertelement <4 x i32> [[_MSPROP2]], i32 0, i32 310922; CHECK-NEXT: [[AV:%.*]] = insertelement <4 x float> [[AV2]], float 0.000000e+00, i32 310923; CHECK-NEXT: [[_MSCMP17:%.*]] = icmp ne i64 [[TMP2]], 010924; CHECK-NEXT: br i1 [[_MSCMP17]], label [[TMP28:%.*]], label [[TMP29:%.*]], !prof [[PROF1]]10925; CHECK: 11:10926; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]10927; CHECK-NEXT: unreachable10928; CHECK: 12:10929; CHECK-NEXT: [[B_VAL:%.*]] = load float, ptr [[B:%.*]], align 410930; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[B]] to i6410931; CHECK-NEXT: [[TMP12:%.*]] = xor i64 [[TMP11]], 8796093022208010932; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to ptr10933; CHECK-NEXT: [[_MSLD4:%.*]] = load i32, ptr [[TMP13]], align 410934; CHECK-NEXT: [[_MSPROP5:%.*]] = insertelement <4 x i32> [[TMP5]], i32 [[_MSLD4]], i32 010935; CHECK-NEXT: [[BV0:%.*]] = insertelement <4 x float> [[EXTRA_PARAM2:%.*]], float [[B_VAL]], i32 010936; CHECK-NEXT: [[_MSPROP6:%.*]] = insertelement <4 x i32> [[_MSPROP5]], i32 0, i32 110937; CHECK-NEXT: [[BV1:%.*]] = insertelement <4 x float> [[BV0]], float 0.000000e+00, i32 110938; CHECK-NEXT: [[_MSPROP7:%.*]] = insertelement <4 x i32> [[_MSPROP6]], i32 0, i32 210939; CHECK-NEXT: [[BV2:%.*]] = insertelement <4 x float> [[BV1]], float 0.000000e+00, i32 210940; CHECK-NEXT: [[_MSPROP8:%.*]] = insertelement <4 x i32> [[_MSPROP7]], i32 0, i32 310941; CHECK-NEXT: [[BV:%.*]] = insertelement <4 x float> [[BV2]], float 0.000000e+00, i32 310942; CHECK-NEXT: [[_MSPROP9:%.*]] = extractelement <4 x i32> [[_MSPROP3]], i64 010943; CHECK-NEXT: [[TMP14:%.*]] = extractelement <4 x float> [[AV]], i64 010944; CHECK-NEXT: [[_MSPROP10:%.*]] = extractelement <4 x i32> [[_MSPROP8]], i64 010945; CHECK-NEXT: [[TMP15:%.*]] = extractelement <4 x float> [[BV]], i64 010946; CHECK-NEXT: [[_MSPROP11:%.*]] = extractelement <4 x i32> [[_MSPROP3]], i64 010947; CHECK-NEXT: [[TMP16:%.*]] = extractelement <4 x float> [[AV]], i64 010948; CHECK-NEXT: [[_MSPROP12:%.*]] = or i32 [[_MSPROP9]], [[_MSPROP10]]10949; CHECK-NEXT: [[_MSPROP13:%.*]] = or i32 [[_MSPROP12]], [[_MSPROP11]]10950; CHECK-NEXT: [[TMP17:%.*]] = call float @llvm.fma.f32(float [[TMP14]], float [[TMP15]], float [[TMP16]])10951; CHECK-NEXT: [[TMP18:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>10952; CHECK-NEXT: [[TMP19:%.*]] = bitcast i8 [[C:%.*]] to <8 x i1>10953; CHECK-NEXT: [[_MSPROP14:%.*]] = extractelement <8 x i1> [[TMP18]], i64 010954; CHECK-NEXT: [[TMP20:%.*]] = extractelement <8 x i1> [[TMP19]], i64 010955; CHECK-NEXT: [[TMP21:%.*]] = select i1 [[TMP20]], i32 [[_MSPROP13]], i32 010956; CHECK-NEXT: [[TMP22:%.*]] = bitcast float [[TMP17]] to i3210957; CHECK-NEXT: [[TMP23:%.*]] = xor i32 [[TMP22]], 010958; CHECK-NEXT: [[TMP24:%.*]] = or i32 [[TMP23]], [[_MSPROP13]]10959; CHECK-NEXT: [[TMP25:%.*]] = or i32 [[TMP24]], 010960; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select i1 [[_MSPROP14]], i32 [[TMP25]], i32 [[TMP21]]10961; CHECK-NEXT: [[TMP26:%.*]] = select i1 [[TMP20]], float [[TMP17]], float 0.000000e+0010962; CHECK-NEXT: [[_MSPROP15:%.*]] = insertelement <4 x i32> [[_MSPROP3]], i32 [[_MSPROP_SELECT]], i64 010963; CHECK-NEXT: [[TMP27:%.*]] = insertelement <4 x float> [[AV]], float [[TMP26]], i64 010964; CHECK-NEXT: [[_MSPROP16:%.*]] = extractelement <4 x i32> [[_MSPROP15]], i32 010965; CHECK-NEXT: [[SR:%.*]] = extractelement <4 x float> [[TMP27]], i32 010966; CHECK-NEXT: [[_MSCMP18:%.*]] = icmp ne i64 [[TMP1]], 010967; CHECK-NEXT: br i1 [[_MSCMP18]], label [[TMP33:%.*]], label [[TMP34:%.*]], !prof [[PROF1]]10968; CHECK: 30:10969; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]10970; CHECK-NEXT: unreachable10971; CHECK: 31:10972; CHECK-NEXT: [[TMP30:%.*]] = ptrtoint ptr [[A]] to i6410973; CHECK-NEXT: [[TMP31:%.*]] = xor i64 [[TMP30]], 8796093022208010974; CHECK-NEXT: [[TMP32:%.*]] = inttoptr i64 [[TMP31]] to ptr10975; CHECK-NEXT: store i32 [[_MSPROP16]], ptr [[TMP32]], align 410976; CHECK-NEXT: store float [[SR]], ptr [[A]], align 410977; CHECK-NEXT: ret void10978;10979 %a.val = load float, ptr %a10980 %av0 = insertelement <4 x float> %extra_param, float %a.val, i32 010981 %av1 = insertelement <4 x float> %av0, float 0.000000e+00, i32 110982 %av2 = insertelement <4 x float> %av1, float 0.000000e+00, i32 210983 %av = insertelement <4 x float> %av2, float 0.000000e+00, i32 310984 10985 %b.val = load float, ptr %b10986 %bv0 = insertelement <4 x float> %extra_param2, float %b.val, i32 010987 %bv1 = insertelement <4 x float> %bv0, float 0.000000e+00, i32 110988 %bv2 = insertelement <4 x float> %bv1, float 0.000000e+00, i32 210989 %bv = insertelement <4 x float> %bv2, float 0.000000e+00, i32 310990 %1 = extractelement <4 x float> %av, i64 010991 %2 = extractelement <4 x float> %bv, i64 010992 %3 = extractelement <4 x float> %av, i64 010993 %4 = call float @llvm.fma.f32(float %1, float %2, float %3)10994 %5 = bitcast i8 %c to <8 x i1>10995 %6 = extractelement <8 x i1> %5, i64 010996 %7 = select i1 %6, float %4, float 0.000000e+0010997 %8 = insertelement <4 x float> %av, float %7, i64 010998 %sr = extractelement <4 x float> %8, i32 010999 store float %sr, ptr %a11000 ret void11001}11002 11003define void @fmadd_sd_mask_memfold(ptr %a, ptr %b, i8 %c, <2 x double> %extra_param, <2 x double> %extra_param2) #0 {11004; CHECK-LABEL: @fmadd_sd_mask_memfold(11005; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 811006; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 811007; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 811008; CHECK-NEXT: [[TMP5:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 811009; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 811010; CHECK-NEXT: call void @llvm.donothing()11011; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 011012; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP9:%.*]], label [[TMP10:%.*]], !prof [[PROF1]]11013; CHECK: 6:11014; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]11015; CHECK-NEXT: unreachable11016; CHECK: 7:11017; CHECK-NEXT: [[A_VAL:%.*]] = load double, ptr [[A:%.*]], align 811018; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[A]] to i6411019; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 8796093022208011020; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr11021; CHECK-NEXT: [[_MSLD:%.*]] = load i64, ptr [[TMP8]], align 811022; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <2 x i64> [[TMP4]], i64 [[_MSLD]], i32 011023; CHECK-NEXT: [[AV0:%.*]] = insertelement <2 x double> [[EXTRA_PARAM:%.*]], double [[A_VAL]], i32 011024; CHECK-NEXT: [[_MSPROP1:%.*]] = insertelement <2 x i64> [[_MSPROP]], i64 0, i32 111025; CHECK-NEXT: [[AV:%.*]] = insertelement <2 x double> [[AV0]], double 0.000000e+00, i32 111026; CHECK-NEXT: [[_MSCMP13:%.*]] = icmp ne i64 [[TMP2]], 011027; CHECK-NEXT: br i1 [[_MSCMP13]], label [[TMP29:%.*]], label [[TMP30:%.*]], !prof [[PROF1]]11028; CHECK: 11:11029; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]11030; CHECK-NEXT: unreachable11031; CHECK: 12:11032; CHECK-NEXT: [[B_VAL:%.*]] = load double, ptr [[B:%.*]], align 811033; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[B]] to i6411034; CHECK-NEXT: [[TMP12:%.*]] = xor i64 [[TMP11]], 8796093022208011035; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to ptr11036; CHECK-NEXT: [[_MSLD2:%.*]] = load i64, ptr [[TMP13]], align 811037; CHECK-NEXT: [[_MSPROP3:%.*]] = insertelement <2 x i64> [[TMP5]], i64 [[_MSLD2]], i32 011038; CHECK-NEXT: [[BV0:%.*]] = insertelement <2 x double> [[EXTRA_PARAM2:%.*]], double [[B_VAL]], i32 011039; CHECK-NEXT: [[_MSPROP4:%.*]] = insertelement <2 x i64> [[_MSPROP3]], i64 0, i32 111040; CHECK-NEXT: [[BV:%.*]] = insertelement <2 x double> [[BV0]], double 0.000000e+00, i32 111041; CHECK-NEXT: [[_MSPROP5:%.*]] = extractelement <2 x i64> [[_MSPROP1]], i64 011042; CHECK-NEXT: [[TMP14:%.*]] = extractelement <2 x double> [[AV]], i64 011043; CHECK-NEXT: [[_MSPROP6:%.*]] = extractelement <2 x i64> [[_MSPROP4]], i64 011044; CHECK-NEXT: [[TMP15:%.*]] = extractelement <2 x double> [[BV]], i64 011045; CHECK-NEXT: [[_MSPROP7:%.*]] = extractelement <2 x i64> [[_MSPROP1]], i64 011046; CHECK-NEXT: [[TMP16:%.*]] = extractelement <2 x double> [[AV]], i64 011047; CHECK-NEXT: [[_MSPROP8:%.*]] = or i64 [[_MSPROP5]], [[_MSPROP6]]11048; CHECK-NEXT: [[_MSPROP9:%.*]] = or i64 [[_MSPROP8]], [[_MSPROP7]]11049; CHECK-NEXT: [[TMP17:%.*]] = call double @llvm.fma.f64(double [[TMP14]], double [[TMP15]], double [[TMP16]])11050; CHECK-NEXT: [[TMP18:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>11051; CHECK-NEXT: [[TMP19:%.*]] = bitcast i8 [[C:%.*]] to <8 x i1>11052; CHECK-NEXT: [[_MSPROP10:%.*]] = extractelement <8 x i1> [[TMP18]], i64 011053; CHECK-NEXT: [[TMP20:%.*]] = extractelement <8 x i1> [[TMP19]], i64 011054; CHECK-NEXT: [[TMP21:%.*]] = select i1 [[TMP20]], i64 [[_MSPROP9]], i64 [[_MSPROP5]]11055; CHECK-NEXT: [[TMP22:%.*]] = bitcast double [[TMP17]] to i6411056; CHECK-NEXT: [[TMP23:%.*]] = bitcast double [[TMP14]] to i6411057; CHECK-NEXT: [[TMP24:%.*]] = xor i64 [[TMP22]], [[TMP23]]11058; CHECK-NEXT: [[TMP25:%.*]] = or i64 [[TMP24]], [[_MSPROP9]]11059; CHECK-NEXT: [[TMP26:%.*]] = or i64 [[TMP25]], [[_MSPROP5]]11060; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select i1 [[_MSPROP10]], i64 [[TMP26]], i64 [[TMP21]]11061; CHECK-NEXT: [[TMP27:%.*]] = select i1 [[TMP20]], double [[TMP17]], double [[TMP14]]11062; CHECK-NEXT: [[_MSPROP11:%.*]] = insertelement <2 x i64> [[_MSPROP1]], i64 [[_MSPROP_SELECT]], i64 011063; CHECK-NEXT: [[TMP28:%.*]] = insertelement <2 x double> [[AV]], double [[TMP27]], i64 011064; CHECK-NEXT: [[_MSPROP12:%.*]] = extractelement <2 x i64> [[_MSPROP11]], i32 011065; CHECK-NEXT: [[SR:%.*]] = extractelement <2 x double> [[TMP28]], i32 011066; CHECK-NEXT: [[_MSCMP14:%.*]] = icmp ne i64 [[TMP1]], 011067; CHECK-NEXT: br i1 [[_MSCMP14]], label [[TMP34:%.*]], label [[TMP35:%.*]], !prof [[PROF1]]11068; CHECK: 31:11069; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]11070; CHECK-NEXT: unreachable11071; CHECK: 32:11072; CHECK-NEXT: [[TMP31:%.*]] = ptrtoint ptr [[A]] to i6411073; CHECK-NEXT: [[TMP32:%.*]] = xor i64 [[TMP31]], 8796093022208011074; CHECK-NEXT: [[TMP33:%.*]] = inttoptr i64 [[TMP32]] to ptr11075; CHECK-NEXT: store i64 [[_MSPROP12]], ptr [[TMP33]], align 811076; CHECK-NEXT: store double [[SR]], ptr [[A]], align 811077; CHECK-NEXT: ret void11078;11079 %a.val = load double, ptr %a11080 %av0 = insertelement <2 x double> %extra_param, double %a.val, i32 011081 %av = insertelement <2 x double> %av0, double 0.000000e+00, i32 111082 11083 %b.val = load double, ptr %b11084 %bv0 = insertelement <2 x double> %extra_param2, double %b.val, i32 011085 %bv = insertelement <2 x double> %bv0, double 0.000000e+00, i32 111086 %1 = extractelement <2 x double> %av, i64 011087 %2 = extractelement <2 x double> %bv, i64 011088 %3 = extractelement <2 x double> %av, i64 011089 %4 = call double @llvm.fma.f64(double %1, double %2, double %3)11090 %5 = bitcast i8 %c to <8 x i1>11091 %6 = extractelement <8 x i1> %5, i64 011092 %7 = select i1 %6, double %4, double %111093 %8 = insertelement <2 x double> %av, double %7, i64 011094 %sr = extractelement <2 x double> %8, i32 011095 store double %sr, ptr %a11096 ret void11097}11098 11099define void @fmadd_sd_maskz_memfold(ptr %a, ptr %b, i8 %c, <2x double> %extra_param, <2x double> %extra_param2) #0 {11100; CHECK-LABEL: @fmadd_sd_maskz_memfold(11101; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 811102; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 811103; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 811104; CHECK-NEXT: [[TMP5:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 811105; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 811106; CHECK-NEXT: call void @llvm.donothing()11107; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 011108; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP9:%.*]], label [[TMP10:%.*]], !prof [[PROF1]]11109; CHECK: 6:11110; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]11111; CHECK-NEXT: unreachable11112; CHECK: 7:11113; CHECK-NEXT: [[A_VAL:%.*]] = load double, ptr [[A:%.*]], align 811114; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[A]] to i6411115; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 8796093022208011116; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr11117; CHECK-NEXT: [[_MSLD:%.*]] = load i64, ptr [[TMP8]], align 811118; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <2 x i64> [[TMP4]], i64 [[_MSLD]], i32 011119; CHECK-NEXT: [[AV0:%.*]] = insertelement <2 x double> [[EXTRA_PARAM:%.*]], double [[A_VAL]], i32 011120; CHECK-NEXT: [[_MSPROP1:%.*]] = insertelement <2 x i64> [[_MSPROP]], i64 0, i32 111121; CHECK-NEXT: [[AV:%.*]] = insertelement <2 x double> [[AV0]], double 0.000000e+00, i32 111122; CHECK-NEXT: [[_MSCMP13:%.*]] = icmp ne i64 [[TMP2]], 011123; CHECK-NEXT: br i1 [[_MSCMP13]], label [[TMP28:%.*]], label [[TMP29:%.*]], !prof [[PROF1]]11124; CHECK: 11:11125; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]11126; CHECK-NEXT: unreachable11127; CHECK: 12:11128; CHECK-NEXT: [[B_VAL:%.*]] = load double, ptr [[B:%.*]], align 811129; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[B]] to i6411130; CHECK-NEXT: [[TMP12:%.*]] = xor i64 [[TMP11]], 8796093022208011131; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to ptr11132; CHECK-NEXT: [[_MSLD2:%.*]] = load i64, ptr [[TMP13]], align 811133; CHECK-NEXT: [[_MSPROP3:%.*]] = insertelement <2 x i64> [[TMP5]], i64 [[_MSLD2]], i32 011134; CHECK-NEXT: [[BV0:%.*]] = insertelement <2 x double> [[EXTRA_PARAM2:%.*]], double [[B_VAL]], i32 011135; CHECK-NEXT: [[_MSPROP4:%.*]] = insertelement <2 x i64> [[_MSPROP3]], i64 0, i32 111136; CHECK-NEXT: [[BV:%.*]] = insertelement <2 x double> [[BV0]], double 0.000000e+00, i32 111137; CHECK-NEXT: [[_MSPROP5:%.*]] = extractelement <2 x i64> [[_MSPROP1]], i64 011138; CHECK-NEXT: [[TMP14:%.*]] = extractelement <2 x double> [[AV]], i64 011139; CHECK-NEXT: [[_MSPROP6:%.*]] = extractelement <2 x i64> [[_MSPROP4]], i64 011140; CHECK-NEXT: [[TMP15:%.*]] = extractelement <2 x double> [[BV]], i64 011141; CHECK-NEXT: [[_MSPROP7:%.*]] = extractelement <2 x i64> [[_MSPROP1]], i64 011142; CHECK-NEXT: [[TMP16:%.*]] = extractelement <2 x double> [[AV]], i64 011143; CHECK-NEXT: [[_MSPROP8:%.*]] = or i64 [[_MSPROP5]], [[_MSPROP6]]11144; CHECK-NEXT: [[_MSPROP9:%.*]] = or i64 [[_MSPROP8]], [[_MSPROP7]]11145; CHECK-NEXT: [[TMP17:%.*]] = call double @llvm.fma.f64(double [[TMP14]], double [[TMP15]], double [[TMP16]])11146; CHECK-NEXT: [[TMP18:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>11147; CHECK-NEXT: [[TMP19:%.*]] = bitcast i8 [[C:%.*]] to <8 x i1>11148; CHECK-NEXT: [[_MSPROP10:%.*]] = extractelement <8 x i1> [[TMP18]], i64 011149; CHECK-NEXT: [[TMP20:%.*]] = extractelement <8 x i1> [[TMP19]], i64 011150; CHECK-NEXT: [[TMP21:%.*]] = select i1 [[TMP20]], i64 [[_MSPROP9]], i64 011151; CHECK-NEXT: [[TMP22:%.*]] = bitcast double [[TMP17]] to i6411152; CHECK-NEXT: [[TMP23:%.*]] = xor i64 [[TMP22]], 011153; CHECK-NEXT: [[TMP24:%.*]] = or i64 [[TMP23]], [[_MSPROP9]]11154; CHECK-NEXT: [[TMP25:%.*]] = or i64 [[TMP24]], 011155; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select i1 [[_MSPROP10]], i64 [[TMP25]], i64 [[TMP21]]11156; CHECK-NEXT: [[TMP26:%.*]] = select i1 [[TMP20]], double [[TMP17]], double 0.000000e+0011157; CHECK-NEXT: [[_MSPROP11:%.*]] = insertelement <2 x i64> [[_MSPROP1]], i64 [[_MSPROP_SELECT]], i64 011158; CHECK-NEXT: [[TMP27:%.*]] = insertelement <2 x double> [[AV]], double [[TMP26]], i64 011159; CHECK-NEXT: [[_MSPROP12:%.*]] = extractelement <2 x i64> [[_MSPROP11]], i32 011160; CHECK-NEXT: [[SR:%.*]] = extractelement <2 x double> [[TMP27]], i32 011161; CHECK-NEXT: [[_MSCMP14:%.*]] = icmp ne i64 [[TMP1]], 011162; CHECK-NEXT: br i1 [[_MSCMP14]], label [[TMP33:%.*]], label [[TMP34:%.*]], !prof [[PROF1]]11163; CHECK: 30:11164; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]11165; CHECK-NEXT: unreachable11166; CHECK: 31:11167; CHECK-NEXT: [[TMP30:%.*]] = ptrtoint ptr [[A]] to i6411168; CHECK-NEXT: [[TMP31:%.*]] = xor i64 [[TMP30]], 8796093022208011169; CHECK-NEXT: [[TMP32:%.*]] = inttoptr i64 [[TMP31]] to ptr11170; CHECK-NEXT: store i64 [[_MSPROP12]], ptr [[TMP32]], align 811171; CHECK-NEXT: store double [[SR]], ptr [[A]], align 811172; CHECK-NEXT: ret void11173;11174 %a.val = load double, ptr %a11175 %av0 = insertelement <2 x double> %extra_param, double %a.val, i32 011176 %av = insertelement <2 x double> %av0, double 0.000000e+00, i32 111177 11178 %b.val = load double, ptr %b11179 %bv0 = insertelement <2 x double> %extra_param2, double %b.val, i32 011180 %bv = insertelement <2 x double> %bv0, double 0.000000e+00, i32 111181 %1 = extractelement <2 x double> %av, i64 011182 %2 = extractelement <2 x double> %bv, i64 011183 %3 = extractelement <2 x double> %av, i64 011184 %4 = call double @llvm.fma.f64(double %1, double %2, double %3)11185 %5 = bitcast i8 %c to <8 x i1>11186 %6 = extractelement <8 x i1> %5, i64 011187 %7 = select i1 %6, double %4, double 0.000000e+0011188 %8 = insertelement <2 x double> %av, double %7, i64 011189 %sr = extractelement <2 x double> %8, i32 011190 store double %sr, ptr %a11191 ret void11192}11193 11194define <2 x double> @test_int_x86_avx512_mask3_vfmsub_sd(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3, i32 %x4) #0 {11195; CHECK-LABEL: @test_int_x86_avx512_mask3_vfmsub_sd(11196; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 811197; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 811198; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 811199; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 811200; CHECK-NEXT: call void @llvm.donothing()11201; CHECK-NEXT: [[TMP5:%.*]] = fneg <2 x double> [[X2:%.*]]11202; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <2 x i64> [[TMP2]], i64 011203; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x double> [[X0:%.*]], i64 011204; CHECK-NEXT: [[_MSPROP1:%.*]] = extractelement <2 x i64> [[TMP3]], i64 011205; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x double> [[X1:%.*]], i64 011206; CHECK-NEXT: [[_MSPROP2:%.*]] = extractelement <2 x i64> [[TMP1]], i64 011207; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x double> [[TMP5]], i64 011208; CHECK-NEXT: [[_MSPROP3:%.*]] = or i64 [[_MSPROP]], [[_MSPROP1]]11209; CHECK-NEXT: [[_MSPROP4:%.*]] = or i64 [[_MSPROP3]], [[_MSPROP2]]11210; CHECK-NEXT: [[TMP9:%.*]] = call double @llvm.fma.f64(double [[TMP6]], double [[TMP7]], double [[TMP8]])11211; CHECK-NEXT: [[_MSPROP5:%.*]] = extractelement <2 x i64> [[TMP1]], i64 011212; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x double> [[X2]], i64 011213; CHECK-NEXT: [[TMP11:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>11214; CHECK-NEXT: [[TMP12:%.*]] = bitcast i8 [[X3:%.*]] to <8 x i1>11215; CHECK-NEXT: [[_MSPROP6:%.*]] = extractelement <8 x i1> [[TMP11]], i64 011216; CHECK-NEXT: [[TMP13:%.*]] = extractelement <8 x i1> [[TMP12]], i64 011217; CHECK-NEXT: [[TMP14:%.*]] = select i1 [[TMP13]], i64 [[_MSPROP4]], i64 [[_MSPROP5]]11218; CHECK-NEXT: [[TMP15:%.*]] = bitcast double [[TMP9]] to i6411219; CHECK-NEXT: [[TMP16:%.*]] = bitcast double [[TMP10]] to i6411220; CHECK-NEXT: [[TMP17:%.*]] = xor i64 [[TMP15]], [[TMP16]]11221; CHECK-NEXT: [[TMP18:%.*]] = or i64 [[TMP17]], [[_MSPROP4]]11222; CHECK-NEXT: [[TMP19:%.*]] = or i64 [[TMP18]], [[_MSPROP5]]11223; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select i1 [[_MSPROP6]], i64 [[TMP19]], i64 [[TMP14]]11224; CHECK-NEXT: [[TMP20:%.*]] = select i1 [[TMP13]], double [[TMP9]], double [[TMP10]]11225; CHECK-NEXT: [[_MSPROP7:%.*]] = insertelement <2 x i64> [[TMP1]], i64 [[_MSPROP_SELECT]], i64 011226; CHECK-NEXT: [[TMP21:%.*]] = insertelement <2 x double> [[X2]], double [[TMP20]], i64 011227; CHECK-NEXT: [[TMP22:%.*]] = fneg <2 x double> [[X2]]11228; CHECK-NEXT: [[_MSPROP8:%.*]] = extractelement <2 x i64> [[TMP2]], i64 011229; CHECK-NEXT: [[TMP23:%.*]] = extractelement <2 x double> [[X0]], i64 011230; CHECK-NEXT: [[_MSPROP9:%.*]] = extractelement <2 x i64> [[TMP3]], i64 011231; CHECK-NEXT: [[TMP24:%.*]] = extractelement <2 x double> [[X1]], i64 011232; CHECK-NEXT: [[_MSPROP10:%.*]] = extractelement <2 x i64> [[TMP1]], i64 011233; CHECK-NEXT: [[TMP25:%.*]] = extractelement <2 x double> [[TMP22]], i64 011234; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[_MSPROP8]], 011235; CHECK-NEXT: [[_MSCMP22:%.*]] = icmp ne i64 [[_MSPROP9]], 011236; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP22]]11237; CHECK-NEXT: [[_MSCMP23:%.*]] = icmp ne i64 [[_MSPROP10]], 011238; CHECK-NEXT: [[_MSOR24:%.*]] = or i1 [[_MSOR]], [[_MSCMP23]]11239; CHECK-NEXT: br i1 [[_MSOR24]], label [[TMP26:%.*]], label [[TMP27:%.*]], !prof [[PROF1]]11240; CHECK: 26:11241; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]11242; CHECK-NEXT: unreachable11243; CHECK: 27:11244; CHECK-NEXT: [[TMP28:%.*]] = call double @llvm.x86.avx512.vfmadd.f64(double [[TMP23]], double [[TMP24]], double [[TMP25]], i32 11)11245; CHECK-NEXT: [[_MSPROP11:%.*]] = extractelement <2 x i64> [[TMP1]], i64 011246; CHECK-NEXT: [[TMP29:%.*]] = extractelement <2 x double> [[X2]], i64 011247; CHECK-NEXT: [[_MSPROP12:%.*]] = insertelement <2 x i64> [[TMP1]], i64 0, i64 011248; CHECK-NEXT: [[TMP30:%.*]] = insertelement <2 x double> [[X2]], double [[TMP28]], i64 011249; CHECK-NEXT: [[TMP31:%.*]] = fneg <2 x double> [[X2]]11250; CHECK-NEXT: [[_MSPROP13:%.*]] = extractelement <2 x i64> [[TMP2]], i64 011251; CHECK-NEXT: [[TMP32:%.*]] = extractelement <2 x double> [[X0]], i64 011252; CHECK-NEXT: [[_MSPROP14:%.*]] = extractelement <2 x i64> [[TMP3]], i64 011253; CHECK-NEXT: [[TMP33:%.*]] = extractelement <2 x double> [[X1]], i64 011254; CHECK-NEXT: [[_MSPROP15:%.*]] = extractelement <2 x i64> [[TMP1]], i64 011255; CHECK-NEXT: [[TMP34:%.*]] = extractelement <2 x double> [[TMP31]], i64 011256; CHECK-NEXT: [[_MSCMP25:%.*]] = icmp ne i64 [[_MSPROP13]], 011257; CHECK-NEXT: [[_MSCMP26:%.*]] = icmp ne i64 [[_MSPROP14]], 011258; CHECK-NEXT: [[_MSOR27:%.*]] = or i1 [[_MSCMP25]], [[_MSCMP26]]11259; CHECK-NEXT: [[_MSCMP28:%.*]] = icmp ne i64 [[_MSPROP15]], 011260; CHECK-NEXT: [[_MSOR29:%.*]] = or i1 [[_MSOR27]], [[_MSCMP28]]11261; CHECK-NEXT: br i1 [[_MSOR29]], label [[TMP35:%.*]], label [[TMP36:%.*]], !prof [[PROF1]]11262; CHECK: 35:11263; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]11264; CHECK-NEXT: unreachable11265; CHECK: 36:11266; CHECK-NEXT: [[TMP37:%.*]] = call double @llvm.x86.avx512.vfmadd.f64(double [[TMP32]], double [[TMP33]], double [[TMP34]], i32 10)11267; CHECK-NEXT: [[_MSPROP16:%.*]] = extractelement <2 x i64> [[TMP1]], i64 011268; CHECK-NEXT: [[TMP38:%.*]] = extractelement <2 x double> [[X2]], i64 011269; CHECK-NEXT: [[TMP39:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>11270; CHECK-NEXT: [[TMP40:%.*]] = bitcast i8 [[X3]] to <8 x i1>11271; CHECK-NEXT: [[_MSPROP17:%.*]] = extractelement <8 x i1> [[TMP39]], i64 011272; CHECK-NEXT: [[TMP41:%.*]] = extractelement <8 x i1> [[TMP40]], i64 011273; CHECK-NEXT: [[TMP42:%.*]] = select i1 [[TMP41]], i64 0, i64 [[_MSPROP16]]11274; CHECK-NEXT: [[TMP43:%.*]] = bitcast double [[TMP37]] to i6411275; CHECK-NEXT: [[TMP44:%.*]] = bitcast double [[TMP38]] to i6411276; CHECK-NEXT: [[TMP45:%.*]] = xor i64 [[TMP43]], [[TMP44]]11277; CHECK-NEXT: [[TMP46:%.*]] = or i64 [[TMP45]], 011278; CHECK-NEXT: [[TMP47:%.*]] = or i64 [[TMP46]], [[_MSPROP16]]11279; CHECK-NEXT: [[_MSPROP_SELECT18:%.*]] = select i1 [[_MSPROP17]], i64 [[TMP47]], i64 [[TMP42]]11280; CHECK-NEXT: [[TMP48:%.*]] = select i1 [[TMP41]], double [[TMP37]], double [[TMP38]]11281; CHECK-NEXT: [[_MSPROP19:%.*]] = insertelement <2 x i64> [[TMP1]], i64 [[_MSPROP_SELECT18]], i64 011282; CHECK-NEXT: [[TMP49:%.*]] = insertelement <2 x double> [[X2]], double [[TMP48]], i64 011283; CHECK-NEXT: [[_MSPROP20:%.*]] = or <2 x i64> [[_MSPROP7]], [[_MSPROP12]]11284; CHECK-NEXT: [[RES3:%.*]] = fadd <2 x double> [[TMP21]], [[TMP30]]11285; CHECK-NEXT: [[_MSPROP21:%.*]] = or <2 x i64> [[_MSPROP19]], [[_MSPROP20]]11286; CHECK-NEXT: [[RES4:%.*]] = fadd <2 x double> [[TMP49]], [[RES3]]11287; CHECK-NEXT: store <2 x i64> [[_MSPROP21]], ptr @__msan_retval_tls, align 811288; CHECK-NEXT: ret <2 x double> [[RES4]]11289;11290 %1 = fneg <2 x double> %x211291 %2 = extractelement <2 x double> %x0, i64 011292 %3 = extractelement <2 x double> %x1, i64 011293 %4 = extractelement <2 x double> %1, i64 011294 %5 = call double @llvm.fma.f64(double %2, double %3, double %4)11295 %6 = extractelement <2 x double> %x2, i64 011296 %7 = bitcast i8 %x3 to <8 x i1>11297 %8 = extractelement <8 x i1> %7, i64 011298 %9 = select i1 %8, double %5, double %611299 %10 = insertelement <2 x double> %x2, double %9, i64 011300 %11 = fneg <2 x double> %x211301 %12 = extractelement <2 x double> %x0, i64 011302 %13 = extractelement <2 x double> %x1, i64 011303 %14 = extractelement <2 x double> %11, i64 011304 %15 = call double @llvm.x86.avx512.vfmadd.f64(double %12, double %13, double %14, i32 11)11305 %16 = extractelement <2 x double> %x2, i64 011306 %17 = insertelement <2 x double> %x2, double %15, i64 011307 %18 = fneg <2 x double> %x211308 %19 = extractelement <2 x double> %x0, i64 011309 %20 = extractelement <2 x double> %x1, i64 011310 %21 = extractelement <2 x double> %18, i64 011311 %22 = call double @llvm.x86.avx512.vfmadd.f64(double %19, double %20, double %21, i32 10)11312 %23 = extractelement <2 x double> %x2, i64 011313 %24 = bitcast i8 %x3 to <8 x i1>11314 %25 = extractelement <8 x i1> %24, i64 011315 %26 = select i1 %25, double %22, double %2311316 %27 = insertelement <2 x double> %x2, double %26, i64 011317 %res3 = fadd <2 x double> %10, %1711318 %res4 = fadd <2 x double> %27, %res311319 ret <2 x double> %res411320}11321 11322define <4 x float> @test_int_x86_avx512_mask3_vfmsub_ss(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3, i32 %x4) #0 {11323; CHECK-LABEL: @test_int_x86_avx512_mask3_vfmsub_ss(11324; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 811325; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 811326; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 811327; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 811328; CHECK-NEXT: call void @llvm.donothing()11329; CHECK-NEXT: [[TMP5:%.*]] = fneg <4 x float> [[X2:%.*]]11330; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <4 x i32> [[TMP2]], i64 011331; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x float> [[X0:%.*]], i64 011332; CHECK-NEXT: [[_MSPROP1:%.*]] = extractelement <4 x i32> [[TMP3]], i64 011333; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x float> [[X1:%.*]], i64 011334; CHECK-NEXT: [[_MSPROP2:%.*]] = extractelement <4 x i32> [[TMP1]], i64 011335; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x float> [[TMP5]], i64 011336; CHECK-NEXT: [[_MSPROP3:%.*]] = or i32 [[_MSPROP]], [[_MSPROP1]]11337; CHECK-NEXT: [[_MSPROP4:%.*]] = or i32 [[_MSPROP3]], [[_MSPROP2]]11338; CHECK-NEXT: [[TMP9:%.*]] = call float @llvm.fma.f32(float [[TMP6]], float [[TMP7]], float [[TMP8]])11339; CHECK-NEXT: [[_MSPROP5:%.*]] = extractelement <4 x i32> [[TMP1]], i64 011340; CHECK-NEXT: [[TMP10:%.*]] = extractelement <4 x float> [[X2]], i64 011341; CHECK-NEXT: [[TMP11:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>11342; CHECK-NEXT: [[TMP12:%.*]] = bitcast i8 [[X3:%.*]] to <8 x i1>11343; CHECK-NEXT: [[_MSPROP6:%.*]] = extractelement <8 x i1> [[TMP11]], i64 011344; CHECK-NEXT: [[TMP13:%.*]] = extractelement <8 x i1> [[TMP12]], i64 011345; CHECK-NEXT: [[TMP14:%.*]] = select i1 [[TMP13]], i32 [[_MSPROP4]], i32 [[_MSPROP5]]11346; CHECK-NEXT: [[TMP15:%.*]] = bitcast float [[TMP9]] to i3211347; CHECK-NEXT: [[TMP16:%.*]] = bitcast float [[TMP10]] to i3211348; CHECK-NEXT: [[TMP17:%.*]] = xor i32 [[TMP15]], [[TMP16]]11349; CHECK-NEXT: [[TMP18:%.*]] = or i32 [[TMP17]], [[_MSPROP4]]11350; CHECK-NEXT: [[TMP19:%.*]] = or i32 [[TMP18]], [[_MSPROP5]]11351; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select i1 [[_MSPROP6]], i32 [[TMP19]], i32 [[TMP14]]11352; CHECK-NEXT: [[TMP20:%.*]] = select i1 [[TMP13]], float [[TMP9]], float [[TMP10]]11353; CHECK-NEXT: [[_MSPROP7:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[_MSPROP_SELECT]], i64 011354; CHECK-NEXT: [[TMP21:%.*]] = insertelement <4 x float> [[X2]], float [[TMP20]], i64 011355; CHECK-NEXT: [[TMP22:%.*]] = fneg <4 x float> [[X2]]11356; CHECK-NEXT: [[_MSPROP8:%.*]] = extractelement <4 x i32> [[TMP2]], i64 011357; CHECK-NEXT: [[TMP23:%.*]] = extractelement <4 x float> [[X0]], i64 011358; CHECK-NEXT: [[_MSPROP9:%.*]] = extractelement <4 x i32> [[TMP3]], i64 011359; CHECK-NEXT: [[TMP24:%.*]] = extractelement <4 x float> [[X1]], i64 011360; CHECK-NEXT: [[_MSPROP10:%.*]] = extractelement <4 x i32> [[TMP1]], i64 011361; CHECK-NEXT: [[TMP25:%.*]] = extractelement <4 x float> [[TMP22]], i64 011362; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[_MSPROP8]], 011363; CHECK-NEXT: [[_MSCMP22:%.*]] = icmp ne i32 [[_MSPROP9]], 011364; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP22]]11365; CHECK-NEXT: [[_MSCMP23:%.*]] = icmp ne i32 [[_MSPROP10]], 011366; CHECK-NEXT: [[_MSOR24:%.*]] = or i1 [[_MSOR]], [[_MSCMP23]]11367; CHECK-NEXT: br i1 [[_MSOR24]], label [[TMP26:%.*]], label [[TMP27:%.*]], !prof [[PROF1]]11368; CHECK: 26:11369; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]11370; CHECK-NEXT: unreachable11371; CHECK: 27:11372; CHECK-NEXT: [[TMP28:%.*]] = call float @llvm.x86.avx512.vfmadd.f32(float [[TMP23]], float [[TMP24]], float [[TMP25]], i32 11)11373; CHECK-NEXT: [[_MSPROP11:%.*]] = extractelement <4 x i32> [[TMP1]], i64 011374; CHECK-NEXT: [[TMP29:%.*]] = extractelement <4 x float> [[X2]], i64 011375; CHECK-NEXT: [[_MSPROP12:%.*]] = insertelement <4 x i32> [[TMP1]], i32 0, i64 011376; CHECK-NEXT: [[TMP30:%.*]] = insertelement <4 x float> [[X2]], float [[TMP28]], i64 011377; CHECK-NEXT: [[TMP31:%.*]] = fneg <4 x float> [[X2]]11378; CHECK-NEXT: [[_MSPROP13:%.*]] = extractelement <4 x i32> [[TMP2]], i64 011379; CHECK-NEXT: [[TMP32:%.*]] = extractelement <4 x float> [[X0]], i64 011380; CHECK-NEXT: [[_MSPROP14:%.*]] = extractelement <4 x i32> [[TMP3]], i64 011381; CHECK-NEXT: [[TMP33:%.*]] = extractelement <4 x float> [[X1]], i64 011382; CHECK-NEXT: [[_MSPROP15:%.*]] = extractelement <4 x i32> [[TMP1]], i64 011383; CHECK-NEXT: [[TMP34:%.*]] = extractelement <4 x float> [[TMP31]], i64 011384; CHECK-NEXT: [[_MSCMP25:%.*]] = icmp ne i32 [[_MSPROP13]], 011385; CHECK-NEXT: [[_MSCMP26:%.*]] = icmp ne i32 [[_MSPROP14]], 011386; CHECK-NEXT: [[_MSOR27:%.*]] = or i1 [[_MSCMP25]], [[_MSCMP26]]11387; CHECK-NEXT: [[_MSCMP28:%.*]] = icmp ne i32 [[_MSPROP15]], 011388; CHECK-NEXT: [[_MSOR29:%.*]] = or i1 [[_MSOR27]], [[_MSCMP28]]11389; CHECK-NEXT: br i1 [[_MSOR29]], label [[TMP35:%.*]], label [[TMP36:%.*]], !prof [[PROF1]]11390; CHECK: 35:11391; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]11392; CHECK-NEXT: unreachable11393; CHECK: 36:11394; CHECK-NEXT: [[TMP37:%.*]] = call float @llvm.x86.avx512.vfmadd.f32(float [[TMP32]], float [[TMP33]], float [[TMP34]], i32 10)11395; CHECK-NEXT: [[_MSPROP16:%.*]] = extractelement <4 x i32> [[TMP1]], i64 011396; CHECK-NEXT: [[TMP38:%.*]] = extractelement <4 x float> [[X2]], i64 011397; CHECK-NEXT: [[TMP39:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>11398; CHECK-NEXT: [[TMP40:%.*]] = bitcast i8 [[X3]] to <8 x i1>11399; CHECK-NEXT: [[_MSPROP17:%.*]] = extractelement <8 x i1> [[TMP39]], i64 011400; CHECK-NEXT: [[TMP41:%.*]] = extractelement <8 x i1> [[TMP40]], i64 011401; CHECK-NEXT: [[TMP42:%.*]] = select i1 [[TMP41]], i32 0, i32 [[_MSPROP16]]11402; CHECK-NEXT: [[TMP43:%.*]] = bitcast float [[TMP37]] to i3211403; CHECK-NEXT: [[TMP44:%.*]] = bitcast float [[TMP38]] to i3211404; CHECK-NEXT: [[TMP45:%.*]] = xor i32 [[TMP43]], [[TMP44]]11405; CHECK-NEXT: [[TMP46:%.*]] = or i32 [[TMP45]], 011406; CHECK-NEXT: [[TMP47:%.*]] = or i32 [[TMP46]], [[_MSPROP16]]11407; CHECK-NEXT: [[_MSPROP_SELECT18:%.*]] = select i1 [[_MSPROP17]], i32 [[TMP47]], i32 [[TMP42]]11408; CHECK-NEXT: [[TMP48:%.*]] = select i1 [[TMP41]], float [[TMP37]], float [[TMP38]]11409; CHECK-NEXT: [[_MSPROP19:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[_MSPROP_SELECT18]], i64 011410; CHECK-NEXT: [[TMP49:%.*]] = insertelement <4 x float> [[X2]], float [[TMP48]], i64 011411; CHECK-NEXT: [[_MSPROP20:%.*]] = or <4 x i32> [[_MSPROP7]], [[_MSPROP12]]11412; CHECK-NEXT: [[RES3:%.*]] = fadd <4 x float> [[TMP21]], [[TMP30]]11413; CHECK-NEXT: [[_MSPROP21:%.*]] = or <4 x i32> [[_MSPROP19]], [[_MSPROP20]]11414; CHECK-NEXT: [[RES4:%.*]] = fadd <4 x float> [[TMP49]], [[RES3]]11415; CHECK-NEXT: store <4 x i32> [[_MSPROP21]], ptr @__msan_retval_tls, align 811416; CHECK-NEXT: ret <4 x float> [[RES4]]11417;11418 %1 = fneg <4 x float> %x211419 %2 = extractelement <4 x float> %x0, i64 011420 %3 = extractelement <4 x float> %x1, i64 011421 %4 = extractelement <4 x float> %1, i64 011422 %5 = call float @llvm.fma.f32(float %2, float %3, float %4)11423 %6 = extractelement <4 x float> %x2, i64 011424 %7 = bitcast i8 %x3 to <8 x i1>11425 %8 = extractelement <8 x i1> %7, i64 011426 %9 = select i1 %8, float %5, float %611427 %10 = insertelement <4 x float> %x2, float %9, i64 011428 %11 = fneg <4 x float> %x211429 %12 = extractelement <4 x float> %x0, i64 011430 %13 = extractelement <4 x float> %x1, i64 011431 %14 = extractelement <4 x float> %11, i64 011432 %15 = call float @llvm.x86.avx512.vfmadd.f32(float %12, float %13, float %14, i32 11)11433 %16 = extractelement <4 x float> %x2, i64 011434 %17 = insertelement <4 x float> %x2, float %15, i64 011435 %18 = fneg <4 x float> %x211436 %19 = extractelement <4 x float> %x0, i64 011437 %20 = extractelement <4 x float> %x1, i64 011438 %21 = extractelement <4 x float> %18, i64 011439 %22 = call float @llvm.x86.avx512.vfmadd.f32(float %19, float %20, float %21, i32 10)11440 %23 = extractelement <4 x float> %x2, i64 011441 %24 = bitcast i8 %x3 to <8 x i1>11442 %25 = extractelement <8 x i1> %24, i64 011443 %26 = select i1 %25, float %22, float %2311444 %27 = insertelement <4 x float> %x2, float %26, i64 011445 %res3 = fadd <4 x float> %10, %1711446 %res4 = fadd <4 x float> %27, %res311447 ret <4 x float> %res411448}11449 11450define <2 x double> @test_int_x86_avx512_mask3_vfnmsub_sd(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3, i32 %x4) #0 {11451; CHECK-LABEL: @test_int_x86_avx512_mask3_vfnmsub_sd(11452; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 811453; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 811454; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 811455; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 811456; CHECK-NEXT: call void @llvm.donothing()11457; CHECK-NEXT: [[TMP5:%.*]] = fneg <2 x double> [[X0:%.*]]11458; CHECK-NEXT: [[TMP6:%.*]] = fneg <2 x double> [[X2:%.*]]11459; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <2 x i64> [[TMP1]], i64 011460; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x double> [[TMP5]], i64 011461; CHECK-NEXT: [[_MSPROP1:%.*]] = extractelement <2 x i64> [[TMP3]], i64 011462; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x double> [[X1:%.*]], i64 011463; CHECK-NEXT: [[_MSPROP2:%.*]] = extractelement <2 x i64> [[TMP2]], i64 011464; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x double> [[TMP6]], i64 011465; CHECK-NEXT: [[_MSPROP3:%.*]] = or i64 [[_MSPROP]], [[_MSPROP1]]11466; CHECK-NEXT: [[_MSPROP4:%.*]] = or i64 [[_MSPROP3]], [[_MSPROP2]]11467; CHECK-NEXT: [[TMP10:%.*]] = call double @llvm.fma.f64(double [[TMP7]], double [[TMP8]], double [[TMP9]])11468; CHECK-NEXT: [[_MSPROP5:%.*]] = extractelement <2 x i64> [[TMP2]], i64 011469; CHECK-NEXT: [[TMP11:%.*]] = extractelement <2 x double> [[X2]], i64 011470; CHECK-NEXT: [[TMP12:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>11471; CHECK-NEXT: [[TMP13:%.*]] = bitcast i8 [[X3:%.*]] to <8 x i1>11472; CHECK-NEXT: [[_MSPROP6:%.*]] = extractelement <8 x i1> [[TMP12]], i64 011473; CHECK-NEXT: [[TMP14:%.*]] = extractelement <8 x i1> [[TMP13]], i64 011474; CHECK-NEXT: [[TMP15:%.*]] = select i1 [[TMP14]], i64 [[_MSPROP4]], i64 [[_MSPROP5]]11475; CHECK-NEXT: [[TMP16:%.*]] = bitcast double [[TMP10]] to i6411476; CHECK-NEXT: [[TMP17:%.*]] = bitcast double [[TMP11]] to i6411477; CHECK-NEXT: [[TMP18:%.*]] = xor i64 [[TMP16]], [[TMP17]]11478; CHECK-NEXT: [[TMP19:%.*]] = or i64 [[TMP18]], [[_MSPROP4]]11479; CHECK-NEXT: [[TMP20:%.*]] = or i64 [[TMP19]], [[_MSPROP5]]11480; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select i1 [[_MSPROP6]], i64 [[TMP20]], i64 [[TMP15]]11481; CHECK-NEXT: [[TMP21:%.*]] = select i1 [[TMP14]], double [[TMP10]], double [[TMP11]]11482; CHECK-NEXT: [[_MSPROP7:%.*]] = insertelement <2 x i64> [[TMP2]], i64 [[_MSPROP_SELECT]], i64 011483; CHECK-NEXT: [[TMP22:%.*]] = insertelement <2 x double> [[X2]], double [[TMP21]], i64 011484; CHECK-NEXT: [[TMP23:%.*]] = fneg <2 x double> [[X0]]11485; CHECK-NEXT: [[TMP24:%.*]] = fneg <2 x double> [[X2]]11486; CHECK-NEXT: [[_MSPROP8:%.*]] = extractelement <2 x i64> [[TMP1]], i64 011487; CHECK-NEXT: [[TMP25:%.*]] = extractelement <2 x double> [[TMP23]], i64 011488; CHECK-NEXT: [[_MSPROP9:%.*]] = extractelement <2 x i64> [[TMP3]], i64 011489; CHECK-NEXT: [[TMP26:%.*]] = extractelement <2 x double> [[X1]], i64 011490; CHECK-NEXT: [[_MSPROP10:%.*]] = extractelement <2 x i64> [[TMP2]], i64 011491; CHECK-NEXT: [[TMP27:%.*]] = extractelement <2 x double> [[TMP24]], i64 011492; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[_MSPROP8]], 011493; CHECK-NEXT: [[_MSCMP22:%.*]] = icmp ne i64 [[_MSPROP9]], 011494; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP22]]11495; CHECK-NEXT: [[_MSCMP23:%.*]] = icmp ne i64 [[_MSPROP10]], 011496; CHECK-NEXT: [[_MSOR24:%.*]] = or i1 [[_MSOR]], [[_MSCMP23]]11497; CHECK-NEXT: br i1 [[_MSOR24]], label [[TMP28:%.*]], label [[TMP29:%.*]], !prof [[PROF1]]11498; CHECK: 28:11499; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]11500; CHECK-NEXT: unreachable11501; CHECK: 29:11502; CHECK-NEXT: [[TMP30:%.*]] = call double @llvm.x86.avx512.vfmadd.f64(double [[TMP25]], double [[TMP26]], double [[TMP27]], i32 11)11503; CHECK-NEXT: [[_MSPROP11:%.*]] = extractelement <2 x i64> [[TMP2]], i64 011504; CHECK-NEXT: [[TMP31:%.*]] = extractelement <2 x double> [[X2]], i64 011505; CHECK-NEXT: [[_MSPROP12:%.*]] = insertelement <2 x i64> [[TMP2]], i64 0, i64 011506; CHECK-NEXT: [[TMP32:%.*]] = insertelement <2 x double> [[X2]], double [[TMP30]], i64 011507; CHECK-NEXT: [[TMP33:%.*]] = fneg <2 x double> [[X0]]11508; CHECK-NEXT: [[TMP34:%.*]] = fneg <2 x double> [[X2]]11509; CHECK-NEXT: [[_MSPROP13:%.*]] = extractelement <2 x i64> [[TMP1]], i64 011510; CHECK-NEXT: [[TMP35:%.*]] = extractelement <2 x double> [[TMP33]], i64 011511; CHECK-NEXT: [[_MSPROP14:%.*]] = extractelement <2 x i64> [[TMP3]], i64 011512; CHECK-NEXT: [[TMP36:%.*]] = extractelement <2 x double> [[X1]], i64 011513; CHECK-NEXT: [[_MSPROP15:%.*]] = extractelement <2 x i64> [[TMP2]], i64 011514; CHECK-NEXT: [[TMP37:%.*]] = extractelement <2 x double> [[TMP34]], i64 011515; CHECK-NEXT: [[_MSCMP25:%.*]] = icmp ne i64 [[_MSPROP13]], 011516; CHECK-NEXT: [[_MSCMP26:%.*]] = icmp ne i64 [[_MSPROP14]], 011517; CHECK-NEXT: [[_MSOR27:%.*]] = or i1 [[_MSCMP25]], [[_MSCMP26]]11518; CHECK-NEXT: [[_MSCMP28:%.*]] = icmp ne i64 [[_MSPROP15]], 011519; CHECK-NEXT: [[_MSOR29:%.*]] = or i1 [[_MSOR27]], [[_MSCMP28]]11520; CHECK-NEXT: br i1 [[_MSOR29]], label [[TMP38:%.*]], label [[TMP39:%.*]], !prof [[PROF1]]11521; CHECK: 38:11522; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]11523; CHECK-NEXT: unreachable11524; CHECK: 39:11525; CHECK-NEXT: [[TMP40:%.*]] = call double @llvm.x86.avx512.vfmadd.f64(double [[TMP35]], double [[TMP36]], double [[TMP37]], i32 10)11526; CHECK-NEXT: [[_MSPROP16:%.*]] = extractelement <2 x i64> [[TMP2]], i64 011527; CHECK-NEXT: [[TMP41:%.*]] = extractelement <2 x double> [[X2]], i64 011528; CHECK-NEXT: [[TMP42:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>11529; CHECK-NEXT: [[TMP43:%.*]] = bitcast i8 [[X3]] to <8 x i1>11530; CHECK-NEXT: [[_MSPROP17:%.*]] = extractelement <8 x i1> [[TMP42]], i64 011531; CHECK-NEXT: [[TMP44:%.*]] = extractelement <8 x i1> [[TMP43]], i64 011532; CHECK-NEXT: [[TMP45:%.*]] = select i1 [[TMP44]], i64 0, i64 [[_MSPROP16]]11533; CHECK-NEXT: [[TMP46:%.*]] = bitcast double [[TMP40]] to i6411534; CHECK-NEXT: [[TMP47:%.*]] = bitcast double [[TMP41]] to i6411535; CHECK-NEXT: [[TMP48:%.*]] = xor i64 [[TMP46]], [[TMP47]]11536; CHECK-NEXT: [[TMP49:%.*]] = or i64 [[TMP48]], 011537; CHECK-NEXT: [[TMP50:%.*]] = or i64 [[TMP49]], [[_MSPROP16]]11538; CHECK-NEXT: [[_MSPROP_SELECT18:%.*]] = select i1 [[_MSPROP17]], i64 [[TMP50]], i64 [[TMP45]]11539; CHECK-NEXT: [[TMP51:%.*]] = select i1 [[TMP44]], double [[TMP40]], double [[TMP41]]11540; CHECK-NEXT: [[_MSPROP19:%.*]] = insertelement <2 x i64> [[TMP2]], i64 [[_MSPROP_SELECT18]], i64 011541; CHECK-NEXT: [[TMP52:%.*]] = insertelement <2 x double> [[X2]], double [[TMP51]], i64 011542; CHECK-NEXT: [[_MSPROP20:%.*]] = or <2 x i64> [[_MSPROP7]], [[_MSPROP12]]11543; CHECK-NEXT: [[RES3:%.*]] = fadd <2 x double> [[TMP22]], [[TMP32]]11544; CHECK-NEXT: [[_MSPROP21:%.*]] = or <2 x i64> [[_MSPROP19]], [[_MSPROP20]]11545; CHECK-NEXT: [[RES4:%.*]] = fadd <2 x double> [[TMP52]], [[RES3]]11546; CHECK-NEXT: store <2 x i64> [[_MSPROP21]], ptr @__msan_retval_tls, align 811547; CHECK-NEXT: ret <2 x double> [[RES4]]11548;11549 %1 = fneg <2 x double> %x011550 %2 = fneg <2 x double> %x211551 %3 = extractelement <2 x double> %1, i64 011552 %4 = extractelement <2 x double> %x1, i64 011553 %5 = extractelement <2 x double> %2, i64 011554 %6 = call double @llvm.fma.f64(double %3, double %4, double %5)11555 %7 = extractelement <2 x double> %x2, i64 011556 %8 = bitcast i8 %x3 to <8 x i1>11557 %9 = extractelement <8 x i1> %8, i64 011558 %10 = select i1 %9, double %6, double %711559 %11 = insertelement <2 x double> %x2, double %10, i64 011560 %12 = fneg <2 x double> %x011561 %13 = fneg <2 x double> %x211562 %14 = extractelement <2 x double> %12, i64 011563 %15 = extractelement <2 x double> %x1, i64 011564 %16 = extractelement <2 x double> %13, i64 011565 %17 = call double @llvm.x86.avx512.vfmadd.f64(double %14, double %15, double %16, i32 11)11566 %18 = extractelement <2 x double> %x2, i64 011567 %19 = insertelement <2 x double> %x2, double %17, i64 011568 %20 = fneg <2 x double> %x011569 %21 = fneg <2 x double> %x211570 %22 = extractelement <2 x double> %20, i64 011571 %23 = extractelement <2 x double> %x1, i64 011572 %24 = extractelement <2 x double> %21, i64 011573 %25 = call double @llvm.x86.avx512.vfmadd.f64(double %22, double %23, double %24, i32 10)11574 %26 = extractelement <2 x double> %x2, i64 011575 %27 = bitcast i8 %x3 to <8 x i1>11576 %28 = extractelement <8 x i1> %27, i64 011577 %29 = select i1 %28, double %25, double %2611578 %30 = insertelement <2 x double> %x2, double %29, i64 011579 %res3 = fadd <2 x double> %11, %1911580 %res4 = fadd <2 x double> %30, %res311581 ret <2 x double> %res411582}11583 11584define <4 x float> @test_int_x86_avx512_mask3_vfnmsub_ss(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3, i32 %x4) #0 {11585; CHECK-LABEL: @test_int_x86_avx512_mask3_vfnmsub_ss(11586; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 811587; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 811588; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 811589; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 811590; CHECK-NEXT: call void @llvm.donothing()11591; CHECK-NEXT: [[TMP5:%.*]] = fneg <4 x float> [[X0:%.*]]11592; CHECK-NEXT: [[TMP6:%.*]] = fneg <4 x float> [[X2:%.*]]11593; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <4 x i32> [[TMP1]], i64 011594; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x float> [[TMP5]], i64 011595; CHECK-NEXT: [[_MSPROP1:%.*]] = extractelement <4 x i32> [[TMP3]], i64 011596; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x float> [[X1:%.*]], i64 011597; CHECK-NEXT: [[_MSPROP2:%.*]] = extractelement <4 x i32> [[TMP2]], i64 011598; CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x float> [[TMP6]], i64 011599; CHECK-NEXT: [[_MSPROP3:%.*]] = or i32 [[_MSPROP]], [[_MSPROP1]]11600; CHECK-NEXT: [[_MSPROP4:%.*]] = or i32 [[_MSPROP3]], [[_MSPROP2]]11601; CHECK-NEXT: [[TMP10:%.*]] = call float @llvm.fma.f32(float [[TMP7]], float [[TMP8]], float [[TMP9]])11602; CHECK-NEXT: [[_MSPROP5:%.*]] = extractelement <4 x i32> [[TMP2]], i64 011603; CHECK-NEXT: [[TMP11:%.*]] = extractelement <4 x float> [[X2]], i64 011604; CHECK-NEXT: [[TMP12:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>11605; CHECK-NEXT: [[TMP13:%.*]] = bitcast i8 [[X3:%.*]] to <8 x i1>11606; CHECK-NEXT: [[_MSPROP6:%.*]] = extractelement <8 x i1> [[TMP12]], i64 011607; CHECK-NEXT: [[TMP14:%.*]] = extractelement <8 x i1> [[TMP13]], i64 011608; CHECK-NEXT: [[TMP15:%.*]] = select i1 [[TMP14]], i32 [[_MSPROP4]], i32 [[_MSPROP5]]11609; CHECK-NEXT: [[TMP16:%.*]] = bitcast float [[TMP10]] to i3211610; CHECK-NEXT: [[TMP17:%.*]] = bitcast float [[TMP11]] to i3211611; CHECK-NEXT: [[TMP18:%.*]] = xor i32 [[TMP16]], [[TMP17]]11612; CHECK-NEXT: [[TMP19:%.*]] = or i32 [[TMP18]], [[_MSPROP4]]11613; CHECK-NEXT: [[TMP20:%.*]] = or i32 [[TMP19]], [[_MSPROP5]]11614; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select i1 [[_MSPROP6]], i32 [[TMP20]], i32 [[TMP15]]11615; CHECK-NEXT: [[TMP21:%.*]] = select i1 [[TMP14]], float [[TMP10]], float [[TMP11]]11616; CHECK-NEXT: [[_MSPROP7:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[_MSPROP_SELECT]], i64 011617; CHECK-NEXT: [[TMP22:%.*]] = insertelement <4 x float> [[X2]], float [[TMP21]], i64 011618; CHECK-NEXT: [[TMP23:%.*]] = fneg <4 x float> [[X0]]11619; CHECK-NEXT: [[TMP24:%.*]] = fneg <4 x float> [[X2]]11620; CHECK-NEXT: [[_MSPROP8:%.*]] = extractelement <4 x i32> [[TMP1]], i64 011621; CHECK-NEXT: [[TMP25:%.*]] = extractelement <4 x float> [[TMP23]], i64 011622; CHECK-NEXT: [[_MSPROP9:%.*]] = extractelement <4 x i32> [[TMP3]], i64 011623; CHECK-NEXT: [[TMP26:%.*]] = extractelement <4 x float> [[X1]], i64 011624; CHECK-NEXT: [[_MSPROP10:%.*]] = extractelement <4 x i32> [[TMP2]], i64 011625; CHECK-NEXT: [[TMP27:%.*]] = extractelement <4 x float> [[TMP24]], i64 011626; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[_MSPROP8]], 011627; CHECK-NEXT: [[_MSCMP22:%.*]] = icmp ne i32 [[_MSPROP9]], 011628; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP22]]11629; CHECK-NEXT: [[_MSCMP23:%.*]] = icmp ne i32 [[_MSPROP10]], 011630; CHECK-NEXT: [[_MSOR24:%.*]] = or i1 [[_MSOR]], [[_MSCMP23]]11631; CHECK-NEXT: br i1 [[_MSOR24]], label [[TMP28:%.*]], label [[TMP29:%.*]], !prof [[PROF1]]11632; CHECK: 28:11633; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]11634; CHECK-NEXT: unreachable11635; CHECK: 29:11636; CHECK-NEXT: [[TMP30:%.*]] = call float @llvm.x86.avx512.vfmadd.f32(float [[TMP25]], float [[TMP26]], float [[TMP27]], i32 11)11637; CHECK-NEXT: [[_MSPROP11:%.*]] = extractelement <4 x i32> [[TMP2]], i64 011638; CHECK-NEXT: [[TMP31:%.*]] = extractelement <4 x float> [[X2]], i64 011639; CHECK-NEXT: [[_MSPROP12:%.*]] = insertelement <4 x i32> [[TMP2]], i32 0, i64 011640; CHECK-NEXT: [[TMP32:%.*]] = insertelement <4 x float> [[X2]], float [[TMP30]], i64 011641; CHECK-NEXT: [[TMP33:%.*]] = fneg <4 x float> [[X0]]11642; CHECK-NEXT: [[TMP34:%.*]] = fneg <4 x float> [[X2]]11643; CHECK-NEXT: [[_MSPROP13:%.*]] = extractelement <4 x i32> [[TMP1]], i64 011644; CHECK-NEXT: [[TMP35:%.*]] = extractelement <4 x float> [[TMP33]], i64 011645; CHECK-NEXT: [[_MSPROP14:%.*]] = extractelement <4 x i32> [[TMP3]], i64 011646; CHECK-NEXT: [[TMP36:%.*]] = extractelement <4 x float> [[X1]], i64 011647; CHECK-NEXT: [[_MSPROP15:%.*]] = extractelement <4 x i32> [[TMP2]], i64 011648; CHECK-NEXT: [[TMP37:%.*]] = extractelement <4 x float> [[TMP34]], i64 011649; CHECK-NEXT: [[_MSCMP25:%.*]] = icmp ne i32 [[_MSPROP13]], 011650; CHECK-NEXT: [[_MSCMP26:%.*]] = icmp ne i32 [[_MSPROP14]], 011651; CHECK-NEXT: [[_MSOR27:%.*]] = or i1 [[_MSCMP25]], [[_MSCMP26]]11652; CHECK-NEXT: [[_MSCMP28:%.*]] = icmp ne i32 [[_MSPROP15]], 011653; CHECK-NEXT: [[_MSOR29:%.*]] = or i1 [[_MSOR27]], [[_MSCMP28]]11654; CHECK-NEXT: br i1 [[_MSOR29]], label [[TMP38:%.*]], label [[TMP39:%.*]], !prof [[PROF1]]11655; CHECK: 38:11656; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]11657; CHECK-NEXT: unreachable11658; CHECK: 39:11659; CHECK-NEXT: [[TMP40:%.*]] = call float @llvm.x86.avx512.vfmadd.f32(float [[TMP35]], float [[TMP36]], float [[TMP37]], i32 10)11660; CHECK-NEXT: [[_MSPROP16:%.*]] = extractelement <4 x i32> [[TMP2]], i64 011661; CHECK-NEXT: [[TMP41:%.*]] = extractelement <4 x float> [[X2]], i64 011662; CHECK-NEXT: [[TMP42:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>11663; CHECK-NEXT: [[TMP43:%.*]] = bitcast i8 [[X3]] to <8 x i1>11664; CHECK-NEXT: [[_MSPROP17:%.*]] = extractelement <8 x i1> [[TMP42]], i64 011665; CHECK-NEXT: [[TMP44:%.*]] = extractelement <8 x i1> [[TMP43]], i64 011666; CHECK-NEXT: [[TMP45:%.*]] = select i1 [[TMP44]], i32 0, i32 [[_MSPROP16]]11667; CHECK-NEXT: [[TMP46:%.*]] = bitcast float [[TMP40]] to i3211668; CHECK-NEXT: [[TMP47:%.*]] = bitcast float [[TMP41]] to i3211669; CHECK-NEXT: [[TMP48:%.*]] = xor i32 [[TMP46]], [[TMP47]]11670; CHECK-NEXT: [[TMP49:%.*]] = or i32 [[TMP48]], 011671; CHECK-NEXT: [[TMP50:%.*]] = or i32 [[TMP49]], [[_MSPROP16]]11672; CHECK-NEXT: [[_MSPROP_SELECT18:%.*]] = select i1 [[_MSPROP17]], i32 [[TMP50]], i32 [[TMP45]]11673; CHECK-NEXT: [[TMP51:%.*]] = select i1 [[TMP44]], float [[TMP40]], float [[TMP41]]11674; CHECK-NEXT: [[_MSPROP19:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[_MSPROP_SELECT18]], i64 011675; CHECK-NEXT: [[TMP52:%.*]] = insertelement <4 x float> [[X2]], float [[TMP51]], i64 011676; CHECK-NEXT: [[_MSPROP20:%.*]] = or <4 x i32> [[_MSPROP7]], [[_MSPROP12]]11677; CHECK-NEXT: [[RES3:%.*]] = fadd <4 x float> [[TMP22]], [[TMP32]]11678; CHECK-NEXT: [[_MSPROP21:%.*]] = or <4 x i32> [[_MSPROP19]], [[_MSPROP20]]11679; CHECK-NEXT: [[RES4:%.*]] = fadd <4 x float> [[TMP52]], [[RES3]]11680; CHECK-NEXT: store <4 x i32> [[_MSPROP21]], ptr @__msan_retval_tls, align 811681; CHECK-NEXT: ret <4 x float> [[RES4]]11682;11683 %1 = fneg <4 x float> %x011684 %2 = fneg <4 x float> %x211685 %3 = extractelement <4 x float> %1, i64 011686 %4 = extractelement <4 x float> %x1, i64 011687 %5 = extractelement <4 x float> %2, i64 011688 %6 = call float @llvm.fma.f32(float %3, float %4, float %5)11689 %7 = extractelement <4 x float> %x2, i64 011690 %8 = bitcast i8 %x3 to <8 x i1>11691 %9 = extractelement <8 x i1> %8, i64 011692 %10 = select i1 %9, float %6, float %711693 %11 = insertelement <4 x float> %x2, float %10, i64 011694 %12 = fneg <4 x float> %x011695 %13 = fneg <4 x float> %x211696 %14 = extractelement <4 x float> %12, i64 011697 %15 = extractelement <4 x float> %x1, i64 011698 %16 = extractelement <4 x float> %13, i64 011699 %17 = call float @llvm.x86.avx512.vfmadd.f32(float %14, float %15, float %16, i32 11)11700 %18 = extractelement <4 x float> %x2, i64 011701 %19 = insertelement <4 x float> %x2, float %17, i64 011702 %20 = fneg <4 x float> %x011703 %21 = fneg <4 x float> %x211704 %22 = extractelement <4 x float> %20, i64 011705 %23 = extractelement <4 x float> %x1, i64 011706 %24 = extractelement <4 x float> %21, i64 011707 %25 = call float @llvm.x86.avx512.vfmadd.f32(float %22, float %23, float %24, i32 10)11708 %26 = extractelement <4 x float> %x2, i64 011709 %27 = bitcast i8 %x3 to <8 x i1>11710 %28 = extractelement <8 x i1> %27, i64 011711 %29 = select i1 %28, float %25, float %2611712 %30 = insertelement <4 x float> %x2, float %29, i64 011713 %res3 = fadd <4 x float> %11, %1911714 %res4 = fadd <4 x float> %30, %res311715 ret <4 x float> %res411716}11717 11718define <4 x float>@test_int_x86_avx512_mask3_vfmadd_ss_rm(<4 x float> %x0, <4 x float> %x1, ptr%ptr_b ,i8 %x3,i32 %x4, <4 x float> %extra_param) #0 {11719; CHECK-LABEL: @test_int_x86_avx512_mask3_vfmadd_ss_rm(11720; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 811721; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 56), align 811722; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 811723; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 811724; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 811725; CHECK-NEXT: call void @llvm.donothing()11726; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 011727; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP6:%.*]], label [[TMP25:%.*]], !prof [[PROF1]]11728; CHECK: 6:11729; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]11730; CHECK-NEXT: unreachable11731; CHECK: 7:11732; CHECK-NEXT: [[Q:%.*]] = load float, ptr [[PTR_B:%.*]], align 411733; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[PTR_B]] to i6411734; CHECK-NEXT: [[TMP8:%.*]] = xor i64 [[TMP7]], 8796093022208011735; CHECK-NEXT: [[TMP9:%.*]] = inttoptr i64 [[TMP8]] to ptr11736; CHECK-NEXT: [[_MSLD:%.*]] = load i32, ptr [[TMP9]], align 411737; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <4 x i32> [[TMP5]], i32 [[_MSLD]], i32 011738; CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x float> [[EXTRA_PARAM:%.*]], float [[Q]], i32 011739; CHECK-NEXT: [[_MSPROP1:%.*]] = extractelement <4 x i32> [[TMP2]], i64 011740; CHECK-NEXT: [[TMP10:%.*]] = extractelement <4 x float> [[X0:%.*]], i64 011741; CHECK-NEXT: [[_MSPROP2:%.*]] = extractelement <4 x i32> [[_MSPROP]], i64 011742; CHECK-NEXT: [[TMP11:%.*]] = extractelement <4 x float> [[VECINIT_I]], i64 011743; CHECK-NEXT: [[_MSPROP3:%.*]] = extractelement <4 x i32> [[TMP3]], i64 011744; CHECK-NEXT: [[TMP12:%.*]] = extractelement <4 x float> [[X1:%.*]], i64 011745; CHECK-NEXT: [[_MSPROP4:%.*]] = or i32 [[_MSPROP1]], [[_MSPROP2]]11746; CHECK-NEXT: [[_MSPROP5:%.*]] = or i32 [[_MSPROP4]], [[_MSPROP3]]11747; CHECK-NEXT: [[TMP13:%.*]] = call float @llvm.fma.f32(float [[TMP10]], float [[TMP11]], float [[TMP12]])11748; CHECK-NEXT: [[TMP14:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>11749; CHECK-NEXT: [[TMP15:%.*]] = bitcast i8 [[X3:%.*]] to <8 x i1>11750; CHECK-NEXT: [[_MSPROP6:%.*]] = extractelement <8 x i1> [[TMP14]], i64 011751; CHECK-NEXT: [[TMP16:%.*]] = extractelement <8 x i1> [[TMP15]], i64 011752; CHECK-NEXT: [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[_MSPROP5]], i32 [[_MSPROP3]]11753; CHECK-NEXT: [[TMP18:%.*]] = bitcast float [[TMP13]] to i3211754; CHECK-NEXT: [[TMP19:%.*]] = bitcast float [[TMP12]] to i3211755; CHECK-NEXT: [[TMP20:%.*]] = xor i32 [[TMP18]], [[TMP19]]11756; CHECK-NEXT: [[TMP21:%.*]] = or i32 [[TMP20]], [[_MSPROP5]]11757; CHECK-NEXT: [[TMP22:%.*]] = or i32 [[TMP21]], [[_MSPROP3]]11758; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select i1 [[_MSPROP6]], i32 [[TMP22]], i32 [[TMP17]]11759; CHECK-NEXT: [[TMP23:%.*]] = select i1 [[TMP16]], float [[TMP13]], float [[TMP12]]11760; CHECK-NEXT: [[_MSPROP7:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[_MSPROP_SELECT]], i64 011761; CHECK-NEXT: [[TMP24:%.*]] = insertelement <4 x float> [[X1]], float [[TMP23]], i64 011762; CHECK-NEXT: store <4 x i32> [[_MSPROP7]], ptr @__msan_retval_tls, align 811763; CHECK-NEXT: ret <4 x float> [[TMP24]]11764;11765 %q = load float, ptr %ptr_b11766 %vecinit.i = insertelement <4 x float> %extra_param, float %q, i32 011767 %1 = extractelement <4 x float> %x0, i64 011768 %2 = extractelement <4 x float> %vecinit.i, i64 011769 %3 = extractelement <4 x float> %x1, i64 011770 %4 = call float @llvm.fma.f32(float %1, float %2, float %3)11771 %5 = bitcast i8 %x3 to <8 x i1>11772 %6 = extractelement <8 x i1> %5, i64 011773 %7 = select i1 %6, float %4, float %311774 %8 = insertelement <4 x float> %x1, float %7, i64 011775 ret <4 x float> %811776}11777 11778define <4 x float>@test_int_x86_avx512_mask_vfmadd_ss_rm(<4 x float> %x0, <4 x float> %x1,ptr%ptr_b ,i8 %x3,i32 %x4, <4 x float> %extra_param) #0 {11779; CHECK-LABEL: @test_int_x86_avx512_mask_vfmadd_ss_rm(11780; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 811781; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 56), align 811782; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 811783; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 811784; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 811785; CHECK-NEXT: call void @llvm.donothing()11786; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 011787; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP6:%.*]], label [[TMP25:%.*]], !prof [[PROF1]]11788; CHECK: 6:11789; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]11790; CHECK-NEXT: unreachable11791; CHECK: 7:11792; CHECK-NEXT: [[Q:%.*]] = load float, ptr [[PTR_B:%.*]], align 411793; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[PTR_B]] to i6411794; CHECK-NEXT: [[TMP8:%.*]] = xor i64 [[TMP7]], 8796093022208011795; CHECK-NEXT: [[TMP9:%.*]] = inttoptr i64 [[TMP8]] to ptr11796; CHECK-NEXT: [[_MSLD:%.*]] = load i32, ptr [[TMP9]], align 411797; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <4 x i32> [[TMP5]], i32 [[_MSLD]], i32 011798; CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x float> [[EXTRA_PARAM:%.*]], float [[Q]], i32 011799; CHECK-NEXT: [[_MSPROP1:%.*]] = extractelement <4 x i32> [[TMP2]], i64 011800; CHECK-NEXT: [[TMP10:%.*]] = extractelement <4 x float> [[X0:%.*]], i64 011801; CHECK-NEXT: [[_MSPROP2:%.*]] = extractelement <4 x i32> [[_MSPROP]], i64 011802; CHECK-NEXT: [[TMP11:%.*]] = extractelement <4 x float> [[VECINIT_I]], i64 011803; CHECK-NEXT: [[_MSPROP3:%.*]] = extractelement <4 x i32> [[TMP3]], i64 011804; CHECK-NEXT: [[TMP12:%.*]] = extractelement <4 x float> [[X1:%.*]], i64 011805; CHECK-NEXT: [[_MSPROP4:%.*]] = or i32 [[_MSPROP1]], [[_MSPROP2]]11806; CHECK-NEXT: [[_MSPROP5:%.*]] = or i32 [[_MSPROP4]], [[_MSPROP3]]11807; CHECK-NEXT: [[TMP13:%.*]] = call float @llvm.fma.f32(float [[TMP10]], float [[TMP11]], float [[TMP12]])11808; CHECK-NEXT: [[TMP14:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>11809; CHECK-NEXT: [[TMP15:%.*]] = bitcast i8 [[X3:%.*]] to <8 x i1>11810; CHECK-NEXT: [[_MSPROP6:%.*]] = extractelement <8 x i1> [[TMP14]], i64 011811; CHECK-NEXT: [[TMP16:%.*]] = extractelement <8 x i1> [[TMP15]], i64 011812; CHECK-NEXT: [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[_MSPROP5]], i32 [[_MSPROP1]]11813; CHECK-NEXT: [[TMP18:%.*]] = bitcast float [[TMP13]] to i3211814; CHECK-NEXT: [[TMP19:%.*]] = bitcast float [[TMP10]] to i3211815; CHECK-NEXT: [[TMP20:%.*]] = xor i32 [[TMP18]], [[TMP19]]11816; CHECK-NEXT: [[TMP21:%.*]] = or i32 [[TMP20]], [[_MSPROP5]]11817; CHECK-NEXT: [[TMP22:%.*]] = or i32 [[TMP21]], [[_MSPROP1]]11818; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select i1 [[_MSPROP6]], i32 [[TMP22]], i32 [[TMP17]]11819; CHECK-NEXT: [[TMP23:%.*]] = select i1 [[TMP16]], float [[TMP13]], float [[TMP10]]11820; CHECK-NEXT: [[_MSPROP7:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[_MSPROP_SELECT]], i64 011821; CHECK-NEXT: [[TMP24:%.*]] = insertelement <4 x float> [[X0]], float [[TMP23]], i64 011822; CHECK-NEXT: store <4 x i32> [[_MSPROP7]], ptr @__msan_retval_tls, align 811823; CHECK-NEXT: ret <4 x float> [[TMP24]]11824;11825 %q = load float, ptr %ptr_b11826 %vecinit.i = insertelement <4 x float> %extra_param, float %q, i32 011827 %1 = extractelement <4 x float> %x0, i64 011828 %2 = extractelement <4 x float> %vecinit.i, i64 011829 %3 = extractelement <4 x float> %x1, i64 011830 %4 = call float @llvm.fma.f32(float %1, float %2, float %3)11831 %5 = bitcast i8 %x3 to <8 x i1>11832 %6 = extractelement <8 x i1> %5, i64 011833 %7 = select i1 %6, float %4, float %111834 %8 = insertelement <4 x float> %x0, float %7, i64 011835 ret <4 x float> %811836}11837 11838 11839define <4 x float>@test_int_x86_avx512_maskz_vfmadd_ss_rm(<4 x float> %x0, <4 x float> %x1,ptr%ptr_b ,i8 %x3,i32 %x4, <4 x float> %extra_param) #0 {11840; CHECK-LABEL: @test_int_x86_avx512_maskz_vfmadd_ss_rm(11841; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 811842; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 56), align 811843; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 811844; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 811845; CHECK-NEXT: call void @llvm.donothing()11846; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 011847; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP5:%.*]], label [[TMP20:%.*]], !prof [[PROF1]]11848; CHECK: 5:11849; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]11850; CHECK-NEXT: unreachable11851; CHECK: 6:11852; CHECK-NEXT: [[Q:%.*]] = load float, ptr [[PTR_B:%.*]], align 411853; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[PTR_B]] to i6411854; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 8796093022208011855; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr11856; CHECK-NEXT: [[_MSLD:%.*]] = load i32, ptr [[TMP8]], align 411857; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <4 x i32> [[TMP4]], i32 [[_MSLD]], i32 011858; CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x float> [[EXTRA_PARAM:%.*]], float [[Q]], i32 011859; CHECK-NEXT: [[_MSPROP1:%.*]] = extractelement <4 x i32> [[TMP2]], i64 011860; CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x float> [[X0:%.*]], i64 011861; CHECK-NEXT: [[_MSPROP2:%.*]] = extractelement <4 x i32> [[TMP3]], i64 011862; CHECK-NEXT: [[TMP10:%.*]] = extractelement <4 x float> [[X1:%.*]], i64 011863; CHECK-NEXT: [[_MSPROP3:%.*]] = extractelement <4 x i32> [[_MSPROP]], i64 011864; CHECK-NEXT: [[TMP11:%.*]] = extractelement <4 x float> [[VECINIT_I]], i64 011865; CHECK-NEXT: [[_MSPROP4:%.*]] = or i32 [[_MSPROP1]], [[_MSPROP2]]11866; CHECK-NEXT: [[_MSPROP5:%.*]] = or i32 [[_MSPROP4]], [[_MSPROP3]]11867; CHECK-NEXT: [[TMP12:%.*]] = call float @llvm.fma.f32(float [[TMP9]], float [[TMP10]], float [[TMP11]])11868; CHECK-NEXT: [[TMP13:%.*]] = select i1 false, i32 [[_MSPROP5]], i32 011869; CHECK-NEXT: [[TMP14:%.*]] = bitcast float [[TMP12]] to i3211870; CHECK-NEXT: [[TMP15:%.*]] = xor i32 [[TMP14]], 011871; CHECK-NEXT: [[TMP16:%.*]] = or i32 [[TMP15]], [[_MSPROP5]]11872; CHECK-NEXT: [[TMP17:%.*]] = or i32 [[TMP16]], 011873; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select i1 false, i32 [[TMP17]], i32 [[TMP13]]11874; CHECK-NEXT: [[TMP18:%.*]] = select i1 false, float [[TMP12]], float 0.000000e+0011875; CHECK-NEXT: [[_MSPROP6:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[_MSPROP_SELECT]], i64 011876; CHECK-NEXT: [[TMP19:%.*]] = insertelement <4 x float> [[X0]], float [[TMP18]], i64 011877; CHECK-NEXT: store <4 x i32> [[_MSPROP6]], ptr @__msan_retval_tls, align 811878; CHECK-NEXT: ret <4 x float> [[TMP19]]11879;11880 %q = load float, ptr %ptr_b11881 %vecinit.i = insertelement <4 x float> %extra_param, float %q, i32 011882 %1 = extractelement <4 x float> %x0, i64 011883 %2 = extractelement <4 x float> %x1, i64 011884 %3 = extractelement <4 x float> %vecinit.i, i64 011885 %4 = call float @llvm.fma.f32(float %1, float %2, float %3)11886 %5 = select i1 false, float %4, float 0.000000e+0011887 %6 = insertelement <4 x float> %x0, float %5, i64 011888 ret <4 x float> %611889}11890 11891define <16 x i32> @test_x86_avx512_psll_d_512(<16 x i32> %a0, <4 x i32> %a1) #0 {11892; CHECK-LABEL: @test_x86_avx512_psll_d_512(11893; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 811894; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 811895; CHECK-NEXT: call void @llvm.donothing()11896; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP2]] to i12811897; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i6411898; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 011899; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i51211900; CHECK-NEXT: [[TMP7:%.*]] = bitcast i512 [[TMP6]] to <16 x i32>11901; CHECK-NEXT: [[TMP8:%.*]] = call <16 x i32> @llvm.x86.avx512.psll.d.512(<16 x i32> [[TMP1]], <4 x i32> [[A1:%.*]])11902; CHECK-NEXT: [[TMP9:%.*]] = or <16 x i32> [[TMP8]], [[TMP7]]11903; CHECK-NEXT: [[RES:%.*]] = call <16 x i32> @llvm.x86.avx512.psll.d.512(<16 x i32> [[A0:%.*]], <4 x i32> [[A1]])11904; CHECK-NEXT: store <16 x i32> [[TMP9]], ptr @__msan_retval_tls, align 811905; CHECK-NEXT: ret <16 x i32> [[RES]]11906;11907 %res = call <16 x i32> @llvm.x86.avx512.psll.d.512(<16 x i32> %a0, <4 x i32> %a1) ; <<16 x i32>> [#uses=1]11908 ret <16 x i32> %res11909}11910define <16 x i32> @test_x86_avx512_mask_psll_d_512(<16 x i32> %a0, <4 x i32> %a1, <16 x i32> %passthru, i16 %mask) #0 {11911; CHECK-LABEL: @test_x86_avx512_mask_psll_d_512(11912; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 811913; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 811914; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 144), align 811915; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 80), align 811916; CHECK-NEXT: call void @llvm.donothing()11917; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP2]] to i12811918; CHECK-NEXT: [[TMP6:%.*]] = trunc i128 [[TMP5]] to i6411919; CHECK-NEXT: [[TMP7:%.*]] = icmp ne i64 [[TMP6]], 011920; CHECK-NEXT: [[TMP8:%.*]] = sext i1 [[TMP7]] to i51211921; CHECK-NEXT: [[TMP9:%.*]] = bitcast i512 [[TMP8]] to <16 x i32>11922; CHECK-NEXT: [[TMP10:%.*]] = call <16 x i32> @llvm.x86.avx512.psll.d.512(<16 x i32> [[TMP1]], <4 x i32> [[A1:%.*]])11923; CHECK-NEXT: [[TMP11:%.*]] = or <16 x i32> [[TMP10]], [[TMP9]]11924; CHECK-NEXT: [[RES:%.*]] = call <16 x i32> @llvm.x86.avx512.psll.d.512(<16 x i32> [[A0:%.*]], <4 x i32> [[A1]])11925; CHECK-NEXT: [[TMP12:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>11926; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>11927; CHECK-NEXT: [[TMP13:%.*]] = select <16 x i1> [[MASK_CAST]], <16 x i32> [[TMP11]], <16 x i32> [[TMP4]]11928; CHECK-NEXT: [[TMP14:%.*]] = xor <16 x i32> [[RES]], [[PASSTHRU:%.*]]11929; CHECK-NEXT: [[TMP15:%.*]] = or <16 x i32> [[TMP14]], [[TMP11]]11930; CHECK-NEXT: [[TMP16:%.*]] = or <16 x i32> [[TMP15]], [[TMP4]]11931; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP12]], <16 x i32> [[TMP16]], <16 x i32> [[TMP13]]11932; CHECK-NEXT: [[RES2:%.*]] = select <16 x i1> [[MASK_CAST]], <16 x i32> [[RES]], <16 x i32> [[PASSTHRU]]11933; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 811934; CHECK-NEXT: ret <16 x i32> [[RES2]]11935;11936 %res = call <16 x i32> @llvm.x86.avx512.psll.d.512(<16 x i32> %a0, <4 x i32> %a1) ; <<16 x i32>> [#uses=1]11937 %mask.cast = bitcast i16 %mask to <16 x i1>11938 %res2 = select <16 x i1> %mask.cast, <16 x i32> %res, <16 x i32> %passthru11939 ret <16 x i32> %res211940}11941define <16 x i32> @test_x86_avx512_maskz_psll_d_512(<16 x i32> %a0, <4 x i32> %a1, i16 %mask) #0 {11942; CHECK-LABEL: @test_x86_avx512_maskz_psll_d_512(11943; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 811944; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 811945; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 80), align 811946; CHECK-NEXT: call void @llvm.donothing()11947; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i12811948; CHECK-NEXT: [[TMP5:%.*]] = trunc i128 [[TMP4]] to i6411949; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i64 [[TMP5]], 011950; CHECK-NEXT: [[TMP7:%.*]] = sext i1 [[TMP6]] to i51211951; CHECK-NEXT: [[TMP8:%.*]] = bitcast i512 [[TMP7]] to <16 x i32>11952; CHECK-NEXT: [[TMP9:%.*]] = call <16 x i32> @llvm.x86.avx512.psll.d.512(<16 x i32> [[TMP1]], <4 x i32> [[A1:%.*]])11953; CHECK-NEXT: [[TMP10:%.*]] = or <16 x i32> [[TMP9]], [[TMP8]]11954; CHECK-NEXT: [[RES:%.*]] = call <16 x i32> @llvm.x86.avx512.psll.d.512(<16 x i32> [[A0:%.*]], <4 x i32> [[A1]])11955; CHECK-NEXT: [[TMP11:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>11956; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>11957; CHECK-NEXT: [[TMP12:%.*]] = select <16 x i1> [[MASK_CAST]], <16 x i32> [[TMP10]], <16 x i32> zeroinitializer11958; CHECK-NEXT: [[TMP13:%.*]] = xor <16 x i32> [[RES]], zeroinitializer11959; CHECK-NEXT: [[TMP14:%.*]] = or <16 x i32> [[TMP13]], [[TMP10]]11960; CHECK-NEXT: [[TMP15:%.*]] = or <16 x i32> [[TMP14]], zeroinitializer11961; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP11]], <16 x i32> [[TMP15]], <16 x i32> [[TMP12]]11962; CHECK-NEXT: [[RES2:%.*]] = select <16 x i1> [[MASK_CAST]], <16 x i32> [[RES]], <16 x i32> zeroinitializer11963; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 811964; CHECK-NEXT: ret <16 x i32> [[RES2]]11965;11966 %res = call <16 x i32> @llvm.x86.avx512.psll.d.512(<16 x i32> %a0, <4 x i32> %a1) ; <<16 x i32>> [#uses=1]11967 %mask.cast = bitcast i16 %mask to <16 x i1>11968 %res2 = select <16 x i1> %mask.cast, <16 x i32> %res, <16 x i32> zeroinitializer11969 ret <16 x i32> %res211970}11971declare <16 x i32> @llvm.x86.avx512.psll.d.512(<16 x i32>, <4 x i32>) nounwind readnone11972 11973 11974define <8 x i64> @test_x86_avx512_psll_q_512(<8 x i64> %a0, <2 x i64> %a1) #0 {11975; CHECK-LABEL: @test_x86_avx512_psll_q_512(11976; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 811977; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 811978; CHECK-NEXT: call void @llvm.donothing()11979; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP2]] to i12811980; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i6411981; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 011982; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i51211983; CHECK-NEXT: [[TMP7:%.*]] = bitcast i512 [[TMP6]] to <8 x i64>11984; CHECK-NEXT: [[TMP8:%.*]] = call <8 x i64> @llvm.x86.avx512.psll.q.512(<8 x i64> [[TMP1]], <2 x i64> [[A1:%.*]])11985; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i64> [[TMP8]], [[TMP7]]11986; CHECK-NEXT: [[RES:%.*]] = call <8 x i64> @llvm.x86.avx512.psll.q.512(<8 x i64> [[A0:%.*]], <2 x i64> [[A1]])11987; CHECK-NEXT: store <8 x i64> [[TMP9]], ptr @__msan_retval_tls, align 811988; CHECK-NEXT: ret <8 x i64> [[RES]]11989;11990 %res = call <8 x i64> @llvm.x86.avx512.psll.q.512(<8 x i64> %a0, <2 x i64> %a1) ; <<8 x i64>> [#uses=1]11991 ret <8 x i64> %res11992}11993define <8 x i64> @test_x86_avx512_mask_psll_q_512(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> %passthru, i8 %mask) #0 {11994; CHECK-LABEL: @test_x86_avx512_mask_psll_q_512(11995; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 811996; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 811997; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 144), align 811998; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 80), align 811999; CHECK-NEXT: call void @llvm.donothing()12000; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP2]] to i12812001; CHECK-NEXT: [[TMP6:%.*]] = trunc i128 [[TMP5]] to i6412002; CHECK-NEXT: [[TMP7:%.*]] = icmp ne i64 [[TMP6]], 012003; CHECK-NEXT: [[TMP8:%.*]] = sext i1 [[TMP7]] to i51212004; CHECK-NEXT: [[TMP9:%.*]] = bitcast i512 [[TMP8]] to <8 x i64>12005; CHECK-NEXT: [[TMP10:%.*]] = call <8 x i64> @llvm.x86.avx512.psll.q.512(<8 x i64> [[TMP1]], <2 x i64> [[A1:%.*]])12006; CHECK-NEXT: [[TMP11:%.*]] = or <8 x i64> [[TMP10]], [[TMP9]]12007; CHECK-NEXT: [[RES:%.*]] = call <8 x i64> @llvm.x86.avx512.psll.q.512(<8 x i64> [[A0:%.*]], <2 x i64> [[A1]])12008; CHECK-NEXT: [[TMP12:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>12009; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>12010; CHECK-NEXT: [[TMP13:%.*]] = select <8 x i1> [[MASK_CAST]], <8 x i64> [[TMP11]], <8 x i64> [[TMP4]]12011; CHECK-NEXT: [[TMP14:%.*]] = xor <8 x i64> [[RES]], [[PASSTHRU:%.*]]12012; CHECK-NEXT: [[TMP15:%.*]] = or <8 x i64> [[TMP14]], [[TMP11]]12013; CHECK-NEXT: [[TMP16:%.*]] = or <8 x i64> [[TMP15]], [[TMP4]]12014; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP12]], <8 x i64> [[TMP16]], <8 x i64> [[TMP13]]12015; CHECK-NEXT: [[RES2:%.*]] = select <8 x i1> [[MASK_CAST]], <8 x i64> [[RES]], <8 x i64> [[PASSTHRU]]12016; CHECK-NEXT: store <8 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 812017; CHECK-NEXT: ret <8 x i64> [[RES2]]12018;12019 %res = call <8 x i64> @llvm.x86.avx512.psll.q.512(<8 x i64> %a0, <2 x i64> %a1) ; <<8 x i64>> [#uses=1]12020 %mask.cast = bitcast i8 %mask to <8 x i1>12021 %res2 = select <8 x i1> %mask.cast, <8 x i64> %res, <8 x i64> %passthru12022 ret <8 x i64> %res212023}12024define <8 x i64> @test_x86_avx512_maskz_psll_q_512(<8 x i64> %a0, <2 x i64> %a1, i8 %mask) #0 {12025; CHECK-LABEL: @test_x86_avx512_maskz_psll_q_512(12026; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 812027; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 812028; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 80), align 812029; CHECK-NEXT: call void @llvm.donothing()12030; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP2]] to i12812031; CHECK-NEXT: [[TMP5:%.*]] = trunc i128 [[TMP4]] to i6412032; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i64 [[TMP5]], 012033; CHECK-NEXT: [[TMP7:%.*]] = sext i1 [[TMP6]] to i51212034; CHECK-NEXT: [[TMP8:%.*]] = bitcast i512 [[TMP7]] to <8 x i64>12035; CHECK-NEXT: [[TMP9:%.*]] = call <8 x i64> @llvm.x86.avx512.psll.q.512(<8 x i64> [[TMP1]], <2 x i64> [[A1:%.*]])12036; CHECK-NEXT: [[TMP10:%.*]] = or <8 x i64> [[TMP9]], [[TMP8]]12037; CHECK-NEXT: [[RES:%.*]] = call <8 x i64> @llvm.x86.avx512.psll.q.512(<8 x i64> [[A0:%.*]], <2 x i64> [[A1]])12038; CHECK-NEXT: [[TMP11:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>12039; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>12040; CHECK-NEXT: [[TMP12:%.*]] = select <8 x i1> [[MASK_CAST]], <8 x i64> [[TMP10]], <8 x i64> zeroinitializer12041; CHECK-NEXT: [[TMP13:%.*]] = xor <8 x i64> [[RES]], zeroinitializer12042; CHECK-NEXT: [[TMP14:%.*]] = or <8 x i64> [[TMP13]], [[TMP10]]12043; CHECK-NEXT: [[TMP15:%.*]] = or <8 x i64> [[TMP14]], zeroinitializer12044; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP11]], <8 x i64> [[TMP15]], <8 x i64> [[TMP12]]12045; CHECK-NEXT: [[RES2:%.*]] = select <8 x i1> [[MASK_CAST]], <8 x i64> [[RES]], <8 x i64> zeroinitializer12046; CHECK-NEXT: store <8 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 812047; CHECK-NEXT: ret <8 x i64> [[RES2]]12048;12049 %res = call <8 x i64> @llvm.x86.avx512.psll.q.512(<8 x i64> %a0, <2 x i64> %a1) ; <<8 x i64>> [#uses=1]12050 %mask.cast = bitcast i8 %mask to <8 x i1>12051 %res2 = select <8 x i1> %mask.cast, <8 x i64> %res, <8 x i64> zeroinitializer12052 ret <8 x i64> %res212053}12054declare <8 x i64> @llvm.x86.avx512.psll.q.512(<8 x i64>, <2 x i64>) nounwind readnone12055 12056 12057define <16 x i32> @test_x86_avx512_pslli_d_512(<16 x i32> %a0) #0 {12058; CHECK-LABEL: @test_x86_avx512_pslli_d_512(12059; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 812060; CHECK-NEXT: call void @llvm.donothing()12061; CHECK-NEXT: [[TMP2:%.*]] = call <16 x i32> @llvm.x86.avx512.pslli.d.512(<16 x i32> [[TMP1]], i32 7)12062; CHECK-NEXT: [[TMP3:%.*]] = or <16 x i32> [[TMP2]], zeroinitializer12063; CHECK-NEXT: [[RES:%.*]] = call <16 x i32> @llvm.x86.avx512.pslli.d.512(<16 x i32> [[A0:%.*]], i32 7)12064; CHECK-NEXT: store <16 x i32> [[TMP3]], ptr @__msan_retval_tls, align 812065; CHECK-NEXT: ret <16 x i32> [[RES]]12066;12067 %res = call <16 x i32> @llvm.x86.avx512.pslli.d.512(<16 x i32> %a0, i32 7) ; <<16 x i32>> [#uses=1]12068 ret <16 x i32> %res12069}12070define <16 x i32> @test_x86_avx512_mask_pslli_d_512(<16 x i32> %a0, <16 x i32> %passthru, i16 %mask) #0 {12071; CHECK-LABEL: @test_x86_avx512_mask_pslli_d_512(12072; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 812073; CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 812074; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 812075; CHECK-NEXT: call void @llvm.donothing()12076; CHECK-NEXT: [[TMP4:%.*]] = call <16 x i32> @llvm.x86.avx512.pslli.d.512(<16 x i32> [[TMP1]], i32 7)12077; CHECK-NEXT: [[TMP5:%.*]] = or <16 x i32> [[TMP4]], zeroinitializer12078; CHECK-NEXT: [[RES:%.*]] = call <16 x i32> @llvm.x86.avx512.pslli.d.512(<16 x i32> [[A0:%.*]], i32 7)12079; CHECK-NEXT: [[TMP6:%.*]] = bitcast i16 [[TMP2]] to <16 x i1>12080; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>12081; CHECK-NEXT: [[TMP7:%.*]] = select <16 x i1> [[MASK_CAST]], <16 x i32> [[TMP5]], <16 x i32> [[TMP3]]12082; CHECK-NEXT: [[TMP8:%.*]] = xor <16 x i32> [[RES]], [[PASSTHRU:%.*]]12083; CHECK-NEXT: [[TMP9:%.*]] = or <16 x i32> [[TMP8]], [[TMP5]]12084; CHECK-NEXT: [[TMP10:%.*]] = or <16 x i32> [[TMP9]], [[TMP3]]12085; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP6]], <16 x i32> [[TMP10]], <16 x i32> [[TMP7]]12086; CHECK-NEXT: [[RES2:%.*]] = select <16 x i1> [[MASK_CAST]], <16 x i32> [[RES]], <16 x i32> [[PASSTHRU]]12087; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 812088; CHECK-NEXT: ret <16 x i32> [[RES2]]12089;12090 %res = call <16 x i32> @llvm.x86.avx512.pslli.d.512(<16 x i32> %a0, i32 7) ; <<16 x i32>> [#uses=1]12091 %mask.cast = bitcast i16 %mask to <16 x i1>12092 %res2 = select <16 x i1> %mask.cast, <16 x i32> %res, <16 x i32> %passthru12093 ret <16 x i32> %res212094}12095define <16 x i32> @test_x86_avx512_maskz_pslli_d_512(<16 x i32> %a0, i16 %mask) #0 {12096; CHECK-LABEL: @test_x86_avx512_maskz_pslli_d_512(12097; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 812098; CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 812099; CHECK-NEXT: call void @llvm.donothing()12100; CHECK-NEXT: [[TMP3:%.*]] = call <16 x i32> @llvm.x86.avx512.pslli.d.512(<16 x i32> [[TMP1]], i32 7)12101; CHECK-NEXT: [[TMP4:%.*]] = or <16 x i32> [[TMP3]], zeroinitializer12102; CHECK-NEXT: [[RES:%.*]] = call <16 x i32> @llvm.x86.avx512.pslli.d.512(<16 x i32> [[A0:%.*]], i32 7)12103; CHECK-NEXT: [[TMP5:%.*]] = bitcast i16 [[TMP2]] to <16 x i1>12104; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>12105; CHECK-NEXT: [[TMP6:%.*]] = select <16 x i1> [[MASK_CAST]], <16 x i32> [[TMP4]], <16 x i32> zeroinitializer12106; CHECK-NEXT: [[TMP7:%.*]] = xor <16 x i32> [[RES]], zeroinitializer12107; CHECK-NEXT: [[TMP8:%.*]] = or <16 x i32> [[TMP7]], [[TMP4]]12108; CHECK-NEXT: [[TMP9:%.*]] = or <16 x i32> [[TMP8]], zeroinitializer12109; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP5]], <16 x i32> [[TMP9]], <16 x i32> [[TMP6]]12110; CHECK-NEXT: [[RES2:%.*]] = select <16 x i1> [[MASK_CAST]], <16 x i32> [[RES]], <16 x i32> zeroinitializer12111; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 812112; CHECK-NEXT: ret <16 x i32> [[RES2]]12113;12114 %res = call <16 x i32> @llvm.x86.avx512.pslli.d.512(<16 x i32> %a0, i32 7) ; <<16 x i32>> [#uses=1]12115 %mask.cast = bitcast i16 %mask to <16 x i1>12116 %res2 = select <16 x i1> %mask.cast, <16 x i32> %res, <16 x i32> zeroinitializer12117 ret <16 x i32> %res212118}12119declare <16 x i32> @llvm.x86.avx512.pslli.d.512(<16 x i32>, i32) nounwind readnone12120 12121 12122define <8 x i64> @test_x86_avx512_pslli_q_512(<8 x i64> %a0) #0 {12123; CHECK-LABEL: @test_x86_avx512_pslli_q_512(12124; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 812125; CHECK-NEXT: call void @llvm.donothing()12126; CHECK-NEXT: [[TMP2:%.*]] = call <8 x i64> @llvm.x86.avx512.pslli.q.512(<8 x i64> [[TMP1]], i32 7)12127; CHECK-NEXT: [[TMP3:%.*]] = or <8 x i64> [[TMP2]], zeroinitializer12128; CHECK-NEXT: [[RES:%.*]] = call <8 x i64> @llvm.x86.avx512.pslli.q.512(<8 x i64> [[A0:%.*]], i32 7)12129; CHECK-NEXT: store <8 x i64> [[TMP3]], ptr @__msan_retval_tls, align 812130; CHECK-NEXT: ret <8 x i64> [[RES]]12131;12132 %res = call <8 x i64> @llvm.x86.avx512.pslli.q.512(<8 x i64> %a0, i32 7) ; <<8 x i64>> [#uses=1]12133 ret <8 x i64> %res12134}12135define <8 x i64> @test_x86_avx512_mask_pslli_q_512(<8 x i64> %a0, <8 x i64> %passthru, i8 %mask) #0 {12136; CHECK-LABEL: @test_x86_avx512_mask_pslli_q_512(12137; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 812138; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 812139; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 812140; CHECK-NEXT: call void @llvm.donothing()12141; CHECK-NEXT: [[TMP4:%.*]] = call <8 x i64> @llvm.x86.avx512.pslli.q.512(<8 x i64> [[TMP1]], i32 7)12142; CHECK-NEXT: [[TMP5:%.*]] = or <8 x i64> [[TMP4]], zeroinitializer12143; CHECK-NEXT: [[RES:%.*]] = call <8 x i64> @llvm.x86.avx512.pslli.q.512(<8 x i64> [[A0:%.*]], i32 7)12144; CHECK-NEXT: [[TMP6:%.*]] = bitcast i8 [[TMP2]] to <8 x i1>12145; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>12146; CHECK-NEXT: [[TMP7:%.*]] = select <8 x i1> [[MASK_CAST]], <8 x i64> [[TMP5]], <8 x i64> [[TMP3]]12147; CHECK-NEXT: [[TMP8:%.*]] = xor <8 x i64> [[RES]], [[PASSTHRU:%.*]]12148; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i64> [[TMP8]], [[TMP5]]12149; CHECK-NEXT: [[TMP10:%.*]] = or <8 x i64> [[TMP9]], [[TMP3]]12150; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP6]], <8 x i64> [[TMP10]], <8 x i64> [[TMP7]]12151; CHECK-NEXT: [[RES2:%.*]] = select <8 x i1> [[MASK_CAST]], <8 x i64> [[RES]], <8 x i64> [[PASSTHRU]]12152; CHECK-NEXT: store <8 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 812153; CHECK-NEXT: ret <8 x i64> [[RES2]]12154;12155 %res = call <8 x i64> @llvm.x86.avx512.pslli.q.512(<8 x i64> %a0, i32 7) ; <<8 x i64>> [#uses=1]12156 %mask.cast = bitcast i8 %mask to <8 x i1>12157 %res2 = select <8 x i1> %mask.cast, <8 x i64> %res, <8 x i64> %passthru12158 ret <8 x i64> %res212159}12160define <8 x i64> @test_x86_avx512_maskz_pslli_q_512(<8 x i64> %a0, <8 x i64> %passthru, i8 %mask) #0 {12161; CHECK-LABEL: @test_x86_avx512_maskz_pslli_q_512(12162; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 812163; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 812164; CHECK-NEXT: call void @llvm.donothing()12165; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i64> @llvm.x86.avx512.pslli.q.512(<8 x i64> [[TMP1]], i32 7)12166; CHECK-NEXT: [[TMP4:%.*]] = or <8 x i64> [[TMP3]], zeroinitializer12167; CHECK-NEXT: [[RES:%.*]] = call <8 x i64> @llvm.x86.avx512.pslli.q.512(<8 x i64> [[A0:%.*]], i32 7)12168; CHECK-NEXT: [[TMP5:%.*]] = bitcast i8 [[TMP2]] to <8 x i1>12169; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>12170; CHECK-NEXT: [[TMP6:%.*]] = select <8 x i1> [[MASK_CAST]], <8 x i64> [[TMP4]], <8 x i64> zeroinitializer12171; CHECK-NEXT: [[TMP7:%.*]] = xor <8 x i64> [[RES]], zeroinitializer12172; CHECK-NEXT: [[TMP8:%.*]] = or <8 x i64> [[TMP7]], [[TMP4]]12173; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i64> [[TMP8]], zeroinitializer12174; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP5]], <8 x i64> [[TMP9]], <8 x i64> [[TMP6]]12175; CHECK-NEXT: [[RES2:%.*]] = select <8 x i1> [[MASK_CAST]], <8 x i64> [[RES]], <8 x i64> zeroinitializer12176; CHECK-NEXT: store <8 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 812177; CHECK-NEXT: ret <8 x i64> [[RES2]]12178;12179 %res = call <8 x i64> @llvm.x86.avx512.pslli.q.512(<8 x i64> %a0, i32 7) ; <<8 x i64>> [#uses=1]12180 %mask.cast = bitcast i8 %mask to <8 x i1>12181 %res2 = select <8 x i1> %mask.cast, <8 x i64> %res, <8 x i64> zeroinitializer12182 ret <8 x i64> %res212183}12184declare <8 x i64> @llvm.x86.avx512.pslli.q.512(<8 x i64>, i32) nounwind readnone12185 12186 12187define <8 x i64> @test_x86_avx512_psra_q_512(<8 x i64> %a0, <2 x i64> %a1) #0 {12188; CHECK-LABEL: @test_x86_avx512_psra_q_512(12189; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 812190; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 812191; CHECK-NEXT: call void @llvm.donothing()12192; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP2]] to i12812193; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i6412194; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 012195; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i51212196; CHECK-NEXT: [[TMP7:%.*]] = bitcast i512 [[TMP6]] to <8 x i64>12197; CHECK-NEXT: [[TMP8:%.*]] = call <8 x i64> @llvm.x86.avx512.psra.q.512(<8 x i64> [[TMP1]], <2 x i64> [[A1:%.*]])12198; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i64> [[TMP8]], [[TMP7]]12199; CHECK-NEXT: [[RES:%.*]] = call <8 x i64> @llvm.x86.avx512.psra.q.512(<8 x i64> [[A0:%.*]], <2 x i64> [[A1]])12200; CHECK-NEXT: store <8 x i64> [[TMP9]], ptr @__msan_retval_tls, align 812201; CHECK-NEXT: ret <8 x i64> [[RES]]12202;12203 %res = call <8 x i64> @llvm.x86.avx512.psra.q.512(<8 x i64> %a0, <2 x i64> %a1) ; <<8 x i64>> [#uses=1]12204 ret <8 x i64> %res12205}12206define <8 x i64> @test_x86_avx512_mask_psra_q_512(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> %passthru, i8 %mask) #0 {12207; CHECK-LABEL: @test_x86_avx512_mask_psra_q_512(12208; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 812209; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 812210; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 144), align 812211; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 80), align 812212; CHECK-NEXT: call void @llvm.donothing()12213; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP2]] to i12812214; CHECK-NEXT: [[TMP6:%.*]] = trunc i128 [[TMP5]] to i6412215; CHECK-NEXT: [[TMP7:%.*]] = icmp ne i64 [[TMP6]], 012216; CHECK-NEXT: [[TMP8:%.*]] = sext i1 [[TMP7]] to i51212217; CHECK-NEXT: [[TMP9:%.*]] = bitcast i512 [[TMP8]] to <8 x i64>12218; CHECK-NEXT: [[TMP10:%.*]] = call <8 x i64> @llvm.x86.avx512.psra.q.512(<8 x i64> [[TMP1]], <2 x i64> [[A1:%.*]])12219; CHECK-NEXT: [[TMP11:%.*]] = or <8 x i64> [[TMP10]], [[TMP9]]12220; CHECK-NEXT: [[RES:%.*]] = call <8 x i64> @llvm.x86.avx512.psra.q.512(<8 x i64> [[A0:%.*]], <2 x i64> [[A1]])12221; CHECK-NEXT: [[TMP12:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>12222; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>12223; CHECK-NEXT: [[TMP13:%.*]] = select <8 x i1> [[MASK_CAST]], <8 x i64> [[TMP11]], <8 x i64> [[TMP4]]12224; CHECK-NEXT: [[TMP14:%.*]] = xor <8 x i64> [[RES]], [[PASSTHRU:%.*]]12225; CHECK-NEXT: [[TMP15:%.*]] = or <8 x i64> [[TMP14]], [[TMP11]]12226; CHECK-NEXT: [[TMP16:%.*]] = or <8 x i64> [[TMP15]], [[TMP4]]12227; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP12]], <8 x i64> [[TMP16]], <8 x i64> [[TMP13]]12228; CHECK-NEXT: [[RES2:%.*]] = select <8 x i1> [[MASK_CAST]], <8 x i64> [[RES]], <8 x i64> [[PASSTHRU]]12229; CHECK-NEXT: store <8 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 812230; CHECK-NEXT: ret <8 x i64> [[RES2]]12231;12232 %res = call <8 x i64> @llvm.x86.avx512.psra.q.512(<8 x i64> %a0, <2 x i64> %a1) ; <<8 x i64>> [#uses=1]12233 %mask.cast = bitcast i8 %mask to <8 x i1>12234 %res2 = select <8 x i1> %mask.cast, <8 x i64> %res, <8 x i64> %passthru12235 ret <8 x i64> %res212236}12237define <8 x i64> @test_x86_avx512_maskz_psra_q_512(<8 x i64> %a0, <2 x i64> %a1, i8 %mask) #0 {12238; CHECK-LABEL: @test_x86_avx512_maskz_psra_q_512(12239; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 812240; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 812241; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 80), align 812242; CHECK-NEXT: call void @llvm.donothing()12243; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP2]] to i12812244; CHECK-NEXT: [[TMP5:%.*]] = trunc i128 [[TMP4]] to i6412245; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i64 [[TMP5]], 012246; CHECK-NEXT: [[TMP7:%.*]] = sext i1 [[TMP6]] to i51212247; CHECK-NEXT: [[TMP8:%.*]] = bitcast i512 [[TMP7]] to <8 x i64>12248; CHECK-NEXT: [[TMP9:%.*]] = call <8 x i64> @llvm.x86.avx512.psra.q.512(<8 x i64> [[TMP1]], <2 x i64> [[A1:%.*]])12249; CHECK-NEXT: [[TMP10:%.*]] = or <8 x i64> [[TMP9]], [[TMP8]]12250; CHECK-NEXT: [[RES:%.*]] = call <8 x i64> @llvm.x86.avx512.psra.q.512(<8 x i64> [[A0:%.*]], <2 x i64> [[A1]])12251; CHECK-NEXT: [[TMP11:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>12252; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>12253; CHECK-NEXT: [[TMP12:%.*]] = select <8 x i1> [[MASK_CAST]], <8 x i64> [[TMP10]], <8 x i64> zeroinitializer12254; CHECK-NEXT: [[TMP13:%.*]] = xor <8 x i64> [[RES]], zeroinitializer12255; CHECK-NEXT: [[TMP14:%.*]] = or <8 x i64> [[TMP13]], [[TMP10]]12256; CHECK-NEXT: [[TMP15:%.*]] = or <8 x i64> [[TMP14]], zeroinitializer12257; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP11]], <8 x i64> [[TMP15]], <8 x i64> [[TMP12]]12258; CHECK-NEXT: [[RES2:%.*]] = select <8 x i1> [[MASK_CAST]], <8 x i64> [[RES]], <8 x i64> zeroinitializer12259; CHECK-NEXT: store <8 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 812260; CHECK-NEXT: ret <8 x i64> [[RES2]]12261;12262 %res = call <8 x i64> @llvm.x86.avx512.psra.q.512(<8 x i64> %a0, <2 x i64> %a1) ; <<8 x i64>> [#uses=1]12263 %mask.cast = bitcast i8 %mask to <8 x i1>12264 %res2 = select <8 x i1> %mask.cast, <8 x i64> %res, <8 x i64> zeroinitializer12265 ret <8 x i64> %res212266}12267declare <8 x i64> @llvm.x86.avx512.psra.q.512(<8 x i64>, <2 x i64>) nounwind readnone12268 12269 12270define <16 x i32> @test_x86_avx512_psra_d_512(<16 x i32> %a0, <4 x i32> %a1) #0 {12271; CHECK-LABEL: @test_x86_avx512_psra_d_512(12272; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 812273; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 812274; CHECK-NEXT: call void @llvm.donothing()12275; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP2]] to i12812276; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i6412277; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 012278; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i51212279; CHECK-NEXT: [[TMP7:%.*]] = bitcast i512 [[TMP6]] to <16 x i32>12280; CHECK-NEXT: [[TMP8:%.*]] = call <16 x i32> @llvm.x86.avx512.psra.d.512(<16 x i32> [[TMP1]], <4 x i32> [[A1:%.*]])12281; CHECK-NEXT: [[TMP9:%.*]] = or <16 x i32> [[TMP8]], [[TMP7]]12282; CHECK-NEXT: [[RES:%.*]] = call <16 x i32> @llvm.x86.avx512.psra.d.512(<16 x i32> [[A0:%.*]], <4 x i32> [[A1]])12283; CHECK-NEXT: store <16 x i32> [[TMP9]], ptr @__msan_retval_tls, align 812284; CHECK-NEXT: ret <16 x i32> [[RES]]12285;12286 %res = call <16 x i32> @llvm.x86.avx512.psra.d.512(<16 x i32> %a0, <4 x i32> %a1) ; <<16 x i32>> [#uses=1]12287 ret <16 x i32> %res12288}12289define <16 x i32> @test_x86_avx512_mask_psra_d_512(<16 x i32> %a0, <4 x i32> %a1, <16 x i32> %passthru, i16 %mask) #0 {12290; CHECK-LABEL: @test_x86_avx512_mask_psra_d_512(12291; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 812292; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 812293; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 144), align 812294; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 80), align 812295; CHECK-NEXT: call void @llvm.donothing()12296; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP2]] to i12812297; CHECK-NEXT: [[TMP6:%.*]] = trunc i128 [[TMP5]] to i6412298; CHECK-NEXT: [[TMP7:%.*]] = icmp ne i64 [[TMP6]], 012299; CHECK-NEXT: [[TMP8:%.*]] = sext i1 [[TMP7]] to i51212300; CHECK-NEXT: [[TMP9:%.*]] = bitcast i512 [[TMP8]] to <16 x i32>12301; CHECK-NEXT: [[TMP10:%.*]] = call <16 x i32> @llvm.x86.avx512.psra.d.512(<16 x i32> [[TMP1]], <4 x i32> [[A1:%.*]])12302; CHECK-NEXT: [[TMP11:%.*]] = or <16 x i32> [[TMP10]], [[TMP9]]12303; CHECK-NEXT: [[RES:%.*]] = call <16 x i32> @llvm.x86.avx512.psra.d.512(<16 x i32> [[A0:%.*]], <4 x i32> [[A1]])12304; CHECK-NEXT: [[TMP12:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>12305; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>12306; CHECK-NEXT: [[TMP13:%.*]] = select <16 x i1> [[MASK_CAST]], <16 x i32> [[TMP11]], <16 x i32> [[TMP4]]12307; CHECK-NEXT: [[TMP14:%.*]] = xor <16 x i32> [[RES]], [[PASSTHRU:%.*]]12308; CHECK-NEXT: [[TMP15:%.*]] = or <16 x i32> [[TMP14]], [[TMP11]]12309; CHECK-NEXT: [[TMP16:%.*]] = or <16 x i32> [[TMP15]], [[TMP4]]12310; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP12]], <16 x i32> [[TMP16]], <16 x i32> [[TMP13]]12311; CHECK-NEXT: [[RES2:%.*]] = select <16 x i1> [[MASK_CAST]], <16 x i32> [[RES]], <16 x i32> [[PASSTHRU]]12312; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 812313; CHECK-NEXT: ret <16 x i32> [[RES2]]12314;12315 %res = call <16 x i32> @llvm.x86.avx512.psra.d.512(<16 x i32> %a0, <4 x i32> %a1) ; <<16 x i32>> [#uses=1]12316 %mask.cast = bitcast i16 %mask to <16 x i1>12317 %res2 = select <16 x i1> %mask.cast, <16 x i32> %res, <16 x i32> %passthru12318 ret <16 x i32> %res212319}12320define <16 x i32> @test_x86_avx512_maskz_psra_d_512(<16 x i32> %a0, <4 x i32> %a1, i16 %mask) #0 {12321; CHECK-LABEL: @test_x86_avx512_maskz_psra_d_512(12322; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 812323; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 812324; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 80), align 812325; CHECK-NEXT: call void @llvm.donothing()12326; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i12812327; CHECK-NEXT: [[TMP5:%.*]] = trunc i128 [[TMP4]] to i6412328; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i64 [[TMP5]], 012329; CHECK-NEXT: [[TMP7:%.*]] = sext i1 [[TMP6]] to i51212330; CHECK-NEXT: [[TMP8:%.*]] = bitcast i512 [[TMP7]] to <16 x i32>12331; CHECK-NEXT: [[TMP9:%.*]] = call <16 x i32> @llvm.x86.avx512.psra.d.512(<16 x i32> [[TMP1]], <4 x i32> [[A1:%.*]])12332; CHECK-NEXT: [[TMP10:%.*]] = or <16 x i32> [[TMP9]], [[TMP8]]12333; CHECK-NEXT: [[RES:%.*]] = call <16 x i32> @llvm.x86.avx512.psra.d.512(<16 x i32> [[A0:%.*]], <4 x i32> [[A1]])12334; CHECK-NEXT: [[TMP11:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>12335; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>12336; CHECK-NEXT: [[TMP12:%.*]] = select <16 x i1> [[MASK_CAST]], <16 x i32> [[TMP10]], <16 x i32> zeroinitializer12337; CHECK-NEXT: [[TMP13:%.*]] = xor <16 x i32> [[RES]], zeroinitializer12338; CHECK-NEXT: [[TMP14:%.*]] = or <16 x i32> [[TMP13]], [[TMP10]]12339; CHECK-NEXT: [[TMP15:%.*]] = or <16 x i32> [[TMP14]], zeroinitializer12340; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP11]], <16 x i32> [[TMP15]], <16 x i32> [[TMP12]]12341; CHECK-NEXT: [[RES2:%.*]] = select <16 x i1> [[MASK_CAST]], <16 x i32> [[RES]], <16 x i32> zeroinitializer12342; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 812343; CHECK-NEXT: ret <16 x i32> [[RES2]]12344;12345 %res = call <16 x i32> @llvm.x86.avx512.psra.d.512(<16 x i32> %a0, <4 x i32> %a1) ; <<16 x i32>> [#uses=1]12346 %mask.cast = bitcast i16 %mask to <16 x i1>12347 %res2 = select <16 x i1> %mask.cast, <16 x i32> %res, <16 x i32> zeroinitializer12348 ret <16 x i32> %res212349}12350declare <16 x i32> @llvm.x86.avx512.psra.d.512(<16 x i32>, <4 x i32>) nounwind readnone12351 12352 12353 12354define <8 x i64> @test_x86_avx512_psrai_q_512(<8 x i64> %a0) #0 {12355; CHECK-LABEL: @test_x86_avx512_psrai_q_512(12356; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 812357; CHECK-NEXT: call void @llvm.donothing()12358; CHECK-NEXT: [[TMP2:%.*]] = call <8 x i64> @llvm.x86.avx512.psrai.q.512(<8 x i64> [[TMP1]], i32 7)12359; CHECK-NEXT: [[TMP3:%.*]] = or <8 x i64> [[TMP2]], zeroinitializer12360; CHECK-NEXT: [[RES:%.*]] = call <8 x i64> @llvm.x86.avx512.psrai.q.512(<8 x i64> [[A0:%.*]], i32 7)12361; CHECK-NEXT: store <8 x i64> [[TMP3]], ptr @__msan_retval_tls, align 812362; CHECK-NEXT: ret <8 x i64> [[RES]]12363;12364 %res = call <8 x i64> @llvm.x86.avx512.psrai.q.512(<8 x i64> %a0, i32 7) ; <<8 x i64>> [#uses=1]12365 ret <8 x i64> %res12366}12367define <8 x i64> @test_x86_avx512_mask_psrai_q_512(<8 x i64> %a0, <8 x i64> %passthru, i8 %mask) #0 {12368; CHECK-LABEL: @test_x86_avx512_mask_psrai_q_512(12369; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 812370; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 812371; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 812372; CHECK-NEXT: call void @llvm.donothing()12373; CHECK-NEXT: [[TMP4:%.*]] = call <8 x i64> @llvm.x86.avx512.psrai.q.512(<8 x i64> [[TMP1]], i32 7)12374; CHECK-NEXT: [[TMP5:%.*]] = or <8 x i64> [[TMP4]], zeroinitializer12375; CHECK-NEXT: [[RES:%.*]] = call <8 x i64> @llvm.x86.avx512.psrai.q.512(<8 x i64> [[A0:%.*]], i32 7)12376; CHECK-NEXT: [[TMP6:%.*]] = bitcast i8 [[TMP2]] to <8 x i1>12377; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>12378; CHECK-NEXT: [[TMP7:%.*]] = select <8 x i1> [[MASK_CAST]], <8 x i64> [[TMP5]], <8 x i64> [[TMP3]]12379; CHECK-NEXT: [[TMP8:%.*]] = xor <8 x i64> [[RES]], [[PASSTHRU:%.*]]12380; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i64> [[TMP8]], [[TMP5]]12381; CHECK-NEXT: [[TMP10:%.*]] = or <8 x i64> [[TMP9]], [[TMP3]]12382; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP6]], <8 x i64> [[TMP10]], <8 x i64> [[TMP7]]12383; CHECK-NEXT: [[RES2:%.*]] = select <8 x i1> [[MASK_CAST]], <8 x i64> [[RES]], <8 x i64> [[PASSTHRU]]12384; CHECK-NEXT: store <8 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 812385; CHECK-NEXT: ret <8 x i64> [[RES2]]12386;12387 %res = call <8 x i64> @llvm.x86.avx512.psrai.q.512(<8 x i64> %a0, i32 7) ; <<8 x i64>> [#uses=1]12388 %mask.cast = bitcast i8 %mask to <8 x i1>12389 %res2 = select <8 x i1> %mask.cast, <8 x i64> %res, <8 x i64> %passthru12390 ret <8 x i64> %res212391}12392define <8 x i64> @test_x86_avx512_maskz_psrai_q_512(<8 x i64> %a0, i8 %mask) #0 {12393; CHECK-LABEL: @test_x86_avx512_maskz_psrai_q_512(12394; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 812395; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 812396; CHECK-NEXT: call void @llvm.donothing()12397; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i64> @llvm.x86.avx512.psrai.q.512(<8 x i64> [[TMP1]], i32 7)12398; CHECK-NEXT: [[TMP4:%.*]] = or <8 x i64> [[TMP3]], zeroinitializer12399; CHECK-NEXT: [[RES:%.*]] = call <8 x i64> @llvm.x86.avx512.psrai.q.512(<8 x i64> [[A0:%.*]], i32 7)12400; CHECK-NEXT: [[TMP5:%.*]] = bitcast i8 [[TMP2]] to <8 x i1>12401; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>12402; CHECK-NEXT: [[TMP6:%.*]] = select <8 x i1> [[MASK_CAST]], <8 x i64> [[TMP4]], <8 x i64> zeroinitializer12403; CHECK-NEXT: [[TMP7:%.*]] = xor <8 x i64> [[RES]], zeroinitializer12404; CHECK-NEXT: [[TMP8:%.*]] = or <8 x i64> [[TMP7]], [[TMP4]]12405; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i64> [[TMP8]], zeroinitializer12406; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP5]], <8 x i64> [[TMP9]], <8 x i64> [[TMP6]]12407; CHECK-NEXT: [[RES2:%.*]] = select <8 x i1> [[MASK_CAST]], <8 x i64> [[RES]], <8 x i64> zeroinitializer12408; CHECK-NEXT: store <8 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 812409; CHECK-NEXT: ret <8 x i64> [[RES2]]12410;12411 %res = call <8 x i64> @llvm.x86.avx512.psrai.q.512(<8 x i64> %a0, i32 7) ; <<8 x i64>> [#uses=1]12412 %mask.cast = bitcast i8 %mask to <8 x i1>12413 %res2 = select <8 x i1> %mask.cast, <8 x i64> %res, <8 x i64> zeroinitializer12414 ret <8 x i64> %res212415}12416declare <8 x i64> @llvm.x86.avx512.psrai.q.512(<8 x i64>, i32) nounwind readnone12417 12418 12419define <16 x i32> @test_x86_avx512_psrai_d_512(<16 x i32> %a0) #0 {12420; CHECK-LABEL: @test_x86_avx512_psrai_d_512(12421; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 812422; CHECK-NEXT: call void @llvm.donothing()12423; CHECK-NEXT: [[TMP2:%.*]] = call <16 x i32> @llvm.x86.avx512.psrai.d.512(<16 x i32> [[TMP1]], i32 7)12424; CHECK-NEXT: [[TMP3:%.*]] = or <16 x i32> [[TMP2]], zeroinitializer12425; CHECK-NEXT: [[RES:%.*]] = call <16 x i32> @llvm.x86.avx512.psrai.d.512(<16 x i32> [[A0:%.*]], i32 7)12426; CHECK-NEXT: store <16 x i32> [[TMP3]], ptr @__msan_retval_tls, align 812427; CHECK-NEXT: ret <16 x i32> [[RES]]12428;12429 %res = call <16 x i32> @llvm.x86.avx512.psrai.d.512(<16 x i32> %a0, i32 7) ; <<16 x i32>> [#uses=1]12430 ret <16 x i32> %res12431}12432define <16 x i32> @test_x86_avx512_mask_psrai_d_512(<16 x i32> %a0, <16 x i32> %passthru, i16 %mask) #0 {12433; CHECK-LABEL: @test_x86_avx512_mask_psrai_d_512(12434; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 812435; CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 812436; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 812437; CHECK-NEXT: call void @llvm.donothing()12438; CHECK-NEXT: [[TMP4:%.*]] = call <16 x i32> @llvm.x86.avx512.psrai.d.512(<16 x i32> [[TMP1]], i32 7)12439; CHECK-NEXT: [[TMP5:%.*]] = or <16 x i32> [[TMP4]], zeroinitializer12440; CHECK-NEXT: [[RES:%.*]] = call <16 x i32> @llvm.x86.avx512.psrai.d.512(<16 x i32> [[A0:%.*]], i32 7)12441; CHECK-NEXT: [[TMP6:%.*]] = bitcast i16 [[TMP2]] to <16 x i1>12442; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>12443; CHECK-NEXT: [[TMP7:%.*]] = select <16 x i1> [[MASK_CAST]], <16 x i32> [[TMP5]], <16 x i32> [[TMP3]]12444; CHECK-NEXT: [[TMP8:%.*]] = xor <16 x i32> [[RES]], [[PASSTHRU:%.*]]12445; CHECK-NEXT: [[TMP9:%.*]] = or <16 x i32> [[TMP8]], [[TMP5]]12446; CHECK-NEXT: [[TMP10:%.*]] = or <16 x i32> [[TMP9]], [[TMP3]]12447; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP6]], <16 x i32> [[TMP10]], <16 x i32> [[TMP7]]12448; CHECK-NEXT: [[RES2:%.*]] = select <16 x i1> [[MASK_CAST]], <16 x i32> [[RES]], <16 x i32> [[PASSTHRU]]12449; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 812450; CHECK-NEXT: ret <16 x i32> [[RES2]]12451;12452 %res = call <16 x i32> @llvm.x86.avx512.psrai.d.512(<16 x i32> %a0, i32 7) ; <<16 x i32>> [#uses=1]12453 %mask.cast = bitcast i16 %mask to <16 x i1>12454 %res2 = select <16 x i1> %mask.cast, <16 x i32> %res, <16 x i32> %passthru12455 ret <16 x i32> %res212456}12457define <16 x i32> @test_x86_avx512_maskz_psrai_d_512(<16 x i32> %a0, i16 %mask) #0 {12458; CHECK-LABEL: @test_x86_avx512_maskz_psrai_d_512(12459; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 812460; CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 812461; CHECK-NEXT: call void @llvm.donothing()12462; CHECK-NEXT: [[TMP3:%.*]] = call <16 x i32> @llvm.x86.avx512.psrai.d.512(<16 x i32> [[TMP1]], i32 7)12463; CHECK-NEXT: [[TMP4:%.*]] = or <16 x i32> [[TMP3]], zeroinitializer12464; CHECK-NEXT: [[RES:%.*]] = call <16 x i32> @llvm.x86.avx512.psrai.d.512(<16 x i32> [[A0:%.*]], i32 7)12465; CHECK-NEXT: [[TMP5:%.*]] = bitcast i16 [[TMP2]] to <16 x i1>12466; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>12467; CHECK-NEXT: [[TMP6:%.*]] = select <16 x i1> [[MASK_CAST]], <16 x i32> [[TMP4]], <16 x i32> zeroinitializer12468; CHECK-NEXT: [[TMP7:%.*]] = xor <16 x i32> [[RES]], zeroinitializer12469; CHECK-NEXT: [[TMP8:%.*]] = or <16 x i32> [[TMP7]], [[TMP4]]12470; CHECK-NEXT: [[TMP9:%.*]] = or <16 x i32> [[TMP8]], zeroinitializer12471; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP5]], <16 x i32> [[TMP9]], <16 x i32> [[TMP6]]12472; CHECK-NEXT: [[RES2:%.*]] = select <16 x i1> [[MASK_CAST]], <16 x i32> [[RES]], <16 x i32> zeroinitializer12473; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 812474; CHECK-NEXT: ret <16 x i32> [[RES2]]12475;12476 %res = call <16 x i32> @llvm.x86.avx512.psrai.d.512(<16 x i32> %a0, i32 7) ; <<16 x i32>> [#uses=1]12477 %mask.cast = bitcast i16 %mask to <16 x i1>12478 %res2 = select <16 x i1> %mask.cast, <16 x i32> %res, <16 x i32> zeroinitializer12479 ret <16 x i32> %res212480}12481declare <16 x i32> @llvm.x86.avx512.psrai.d.512(<16 x i32>, i32) nounwind readnone12482 12483 12484 12485define <16 x i32> @test_x86_avx512_psrl_d_512(<16 x i32> %a0, <4 x i32> %a1) #0 {12486; CHECK-LABEL: @test_x86_avx512_psrl_d_512(12487; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 812488; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 812489; CHECK-NEXT: call void @llvm.donothing()12490; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP2]] to i12812491; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i6412492; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 012493; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i51212494; CHECK-NEXT: [[TMP7:%.*]] = bitcast i512 [[TMP6]] to <16 x i32>12495; CHECK-NEXT: [[TMP8:%.*]] = call <16 x i32> @llvm.x86.avx512.psrl.d.512(<16 x i32> [[TMP1]], <4 x i32> [[A1:%.*]])12496; CHECK-NEXT: [[TMP9:%.*]] = or <16 x i32> [[TMP8]], [[TMP7]]12497; CHECK-NEXT: [[RES:%.*]] = call <16 x i32> @llvm.x86.avx512.psrl.d.512(<16 x i32> [[A0:%.*]], <4 x i32> [[A1]])12498; CHECK-NEXT: store <16 x i32> [[TMP9]], ptr @__msan_retval_tls, align 812499; CHECK-NEXT: ret <16 x i32> [[RES]]12500;12501 %res = call <16 x i32> @llvm.x86.avx512.psrl.d.512(<16 x i32> %a0, <4 x i32> %a1) ; <<16 x i32>> [#uses=1]12502 ret <16 x i32> %res12503}12504define <16 x i32> @test_x86_avx512_mask_psrl_d_512(<16 x i32> %a0, <4 x i32> %a1, <16 x i32> %passthru, i16 %mask) #0 {12505; CHECK-LABEL: @test_x86_avx512_mask_psrl_d_512(12506; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 812507; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 812508; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 144), align 812509; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 80), align 812510; CHECK-NEXT: call void @llvm.donothing()12511; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP2]] to i12812512; CHECK-NEXT: [[TMP6:%.*]] = trunc i128 [[TMP5]] to i6412513; CHECK-NEXT: [[TMP7:%.*]] = icmp ne i64 [[TMP6]], 012514; CHECK-NEXT: [[TMP8:%.*]] = sext i1 [[TMP7]] to i51212515; CHECK-NEXT: [[TMP9:%.*]] = bitcast i512 [[TMP8]] to <16 x i32>12516; CHECK-NEXT: [[TMP10:%.*]] = call <16 x i32> @llvm.x86.avx512.psrl.d.512(<16 x i32> [[TMP1]], <4 x i32> [[A1:%.*]])12517; CHECK-NEXT: [[TMP11:%.*]] = or <16 x i32> [[TMP10]], [[TMP9]]12518; CHECK-NEXT: [[RES:%.*]] = call <16 x i32> @llvm.x86.avx512.psrl.d.512(<16 x i32> [[A0:%.*]], <4 x i32> [[A1]])12519; CHECK-NEXT: [[TMP12:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>12520; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>12521; CHECK-NEXT: [[TMP13:%.*]] = select <16 x i1> [[MASK_CAST]], <16 x i32> [[TMP11]], <16 x i32> [[TMP4]]12522; CHECK-NEXT: [[TMP14:%.*]] = xor <16 x i32> [[RES]], [[PASSTHRU:%.*]]12523; CHECK-NEXT: [[TMP15:%.*]] = or <16 x i32> [[TMP14]], [[TMP11]]12524; CHECK-NEXT: [[TMP16:%.*]] = or <16 x i32> [[TMP15]], [[TMP4]]12525; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP12]], <16 x i32> [[TMP16]], <16 x i32> [[TMP13]]12526; CHECK-NEXT: [[RES2:%.*]] = select <16 x i1> [[MASK_CAST]], <16 x i32> [[RES]], <16 x i32> [[PASSTHRU]]12527; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 812528; CHECK-NEXT: ret <16 x i32> [[RES2]]12529;12530 %res = call <16 x i32> @llvm.x86.avx512.psrl.d.512(<16 x i32> %a0, <4 x i32> %a1) ; <<16 x i32>> [#uses=1]12531 %mask.cast = bitcast i16 %mask to <16 x i1>12532 %res2 = select <16 x i1> %mask.cast, <16 x i32> %res, <16 x i32> %passthru12533 ret <16 x i32> %res212534}12535define <16 x i32> @test_x86_avx512_maskz_psrl_d_512(<16 x i32> %a0, <4 x i32> %a1, i16 %mask) #0 {12536; CHECK-LABEL: @test_x86_avx512_maskz_psrl_d_512(12537; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 812538; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 812539; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 80), align 812540; CHECK-NEXT: call void @llvm.donothing()12541; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i12812542; CHECK-NEXT: [[TMP5:%.*]] = trunc i128 [[TMP4]] to i6412543; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i64 [[TMP5]], 012544; CHECK-NEXT: [[TMP7:%.*]] = sext i1 [[TMP6]] to i51212545; CHECK-NEXT: [[TMP8:%.*]] = bitcast i512 [[TMP7]] to <16 x i32>12546; CHECK-NEXT: [[TMP9:%.*]] = call <16 x i32> @llvm.x86.avx512.psrl.d.512(<16 x i32> [[TMP1]], <4 x i32> [[A1:%.*]])12547; CHECK-NEXT: [[TMP10:%.*]] = or <16 x i32> [[TMP9]], [[TMP8]]12548; CHECK-NEXT: [[RES:%.*]] = call <16 x i32> @llvm.x86.avx512.psrl.d.512(<16 x i32> [[A0:%.*]], <4 x i32> [[A1]])12549; CHECK-NEXT: [[TMP11:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>12550; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>12551; CHECK-NEXT: [[TMP12:%.*]] = select <16 x i1> [[MASK_CAST]], <16 x i32> [[TMP10]], <16 x i32> zeroinitializer12552; CHECK-NEXT: [[TMP13:%.*]] = xor <16 x i32> [[RES]], zeroinitializer12553; CHECK-NEXT: [[TMP14:%.*]] = or <16 x i32> [[TMP13]], [[TMP10]]12554; CHECK-NEXT: [[TMP15:%.*]] = or <16 x i32> [[TMP14]], zeroinitializer12555; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP11]], <16 x i32> [[TMP15]], <16 x i32> [[TMP12]]12556; CHECK-NEXT: [[RES2:%.*]] = select <16 x i1> [[MASK_CAST]], <16 x i32> [[RES]], <16 x i32> zeroinitializer12557; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 812558; CHECK-NEXT: ret <16 x i32> [[RES2]]12559;12560 %res = call <16 x i32> @llvm.x86.avx512.psrl.d.512(<16 x i32> %a0, <4 x i32> %a1) ; <<16 x i32>> [#uses=1]12561 %mask.cast = bitcast i16 %mask to <16 x i1>12562 %res2 = select <16 x i1> %mask.cast, <16 x i32> %res, <16 x i32> zeroinitializer12563 ret <16 x i32> %res212564}12565declare <16 x i32> @llvm.x86.avx512.psrl.d.512(<16 x i32>, <4 x i32>) nounwind readnone12566 12567 12568define <8 x i64> @test_x86_avx512_psrl_q_512(<8 x i64> %a0, <2 x i64> %a1) #0 {12569; CHECK-LABEL: @test_x86_avx512_psrl_q_512(12570; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 812571; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 812572; CHECK-NEXT: call void @llvm.donothing()12573; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP2]] to i12812574; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i6412575; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 012576; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i51212577; CHECK-NEXT: [[TMP7:%.*]] = bitcast i512 [[TMP6]] to <8 x i64>12578; CHECK-NEXT: [[TMP8:%.*]] = call <8 x i64> @llvm.x86.avx512.psrl.q.512(<8 x i64> [[TMP1]], <2 x i64> [[A1:%.*]])12579; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i64> [[TMP8]], [[TMP7]]12580; CHECK-NEXT: [[RES:%.*]] = call <8 x i64> @llvm.x86.avx512.psrl.q.512(<8 x i64> [[A0:%.*]], <2 x i64> [[A1]])12581; CHECK-NEXT: store <8 x i64> [[TMP9]], ptr @__msan_retval_tls, align 812582; CHECK-NEXT: ret <8 x i64> [[RES]]12583;12584 %res = call <8 x i64> @llvm.x86.avx512.psrl.q.512(<8 x i64> %a0, <2 x i64> %a1) ; <<8 x i64>> [#uses=1]12585 ret <8 x i64> %res12586}12587define <8 x i64> @test_x86_avx512_mask_psrl_q_512(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> %passthru, i8 %mask) #0 {12588; CHECK-LABEL: @test_x86_avx512_mask_psrl_q_512(12589; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 812590; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 812591; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 144), align 812592; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 80), align 812593; CHECK-NEXT: call void @llvm.donothing()12594; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP2]] to i12812595; CHECK-NEXT: [[TMP6:%.*]] = trunc i128 [[TMP5]] to i6412596; CHECK-NEXT: [[TMP7:%.*]] = icmp ne i64 [[TMP6]], 012597; CHECK-NEXT: [[TMP8:%.*]] = sext i1 [[TMP7]] to i51212598; CHECK-NEXT: [[TMP9:%.*]] = bitcast i512 [[TMP8]] to <8 x i64>12599; CHECK-NEXT: [[TMP10:%.*]] = call <8 x i64> @llvm.x86.avx512.psrl.q.512(<8 x i64> [[TMP1]], <2 x i64> [[A1:%.*]])12600; CHECK-NEXT: [[TMP11:%.*]] = or <8 x i64> [[TMP10]], [[TMP9]]12601; CHECK-NEXT: [[RES:%.*]] = call <8 x i64> @llvm.x86.avx512.psrl.q.512(<8 x i64> [[A0:%.*]], <2 x i64> [[A1]])12602; CHECK-NEXT: [[TMP12:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>12603; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>12604; CHECK-NEXT: [[TMP13:%.*]] = select <8 x i1> [[MASK_CAST]], <8 x i64> [[TMP11]], <8 x i64> [[TMP4]]12605; CHECK-NEXT: [[TMP14:%.*]] = xor <8 x i64> [[RES]], [[PASSTHRU:%.*]]12606; CHECK-NEXT: [[TMP15:%.*]] = or <8 x i64> [[TMP14]], [[TMP11]]12607; CHECK-NEXT: [[TMP16:%.*]] = or <8 x i64> [[TMP15]], [[TMP4]]12608; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP12]], <8 x i64> [[TMP16]], <8 x i64> [[TMP13]]12609; CHECK-NEXT: [[RES2:%.*]] = select <8 x i1> [[MASK_CAST]], <8 x i64> [[RES]], <8 x i64> [[PASSTHRU]]12610; CHECK-NEXT: store <8 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 812611; CHECK-NEXT: ret <8 x i64> [[RES2]]12612;12613 %res = call <8 x i64> @llvm.x86.avx512.psrl.q.512(<8 x i64> %a0, <2 x i64> %a1) ; <<8 x i64>> [#uses=1]12614 %mask.cast = bitcast i8 %mask to <8 x i1>12615 %res2 = select <8 x i1> %mask.cast, <8 x i64> %res, <8 x i64> %passthru12616 ret <8 x i64> %res212617}12618define <8 x i64> @test_x86_avx512_maskz_psrl_q_512(<8 x i64> %a0, <2 x i64> %a1, i8 %mask) #0 {12619; CHECK-LABEL: @test_x86_avx512_maskz_psrl_q_512(12620; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 812621; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 812622; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 80), align 812623; CHECK-NEXT: call void @llvm.donothing()12624; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP2]] to i12812625; CHECK-NEXT: [[TMP5:%.*]] = trunc i128 [[TMP4]] to i6412626; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i64 [[TMP5]], 012627; CHECK-NEXT: [[TMP7:%.*]] = sext i1 [[TMP6]] to i51212628; CHECK-NEXT: [[TMP8:%.*]] = bitcast i512 [[TMP7]] to <8 x i64>12629; CHECK-NEXT: [[TMP9:%.*]] = call <8 x i64> @llvm.x86.avx512.psrl.q.512(<8 x i64> [[TMP1]], <2 x i64> [[A1:%.*]])12630; CHECK-NEXT: [[TMP10:%.*]] = or <8 x i64> [[TMP9]], [[TMP8]]12631; CHECK-NEXT: [[RES:%.*]] = call <8 x i64> @llvm.x86.avx512.psrl.q.512(<8 x i64> [[A0:%.*]], <2 x i64> [[A1]])12632; CHECK-NEXT: [[TMP11:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>12633; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>12634; CHECK-NEXT: [[TMP12:%.*]] = select <8 x i1> [[MASK_CAST]], <8 x i64> [[TMP10]], <8 x i64> zeroinitializer12635; CHECK-NEXT: [[TMP13:%.*]] = xor <8 x i64> [[RES]], zeroinitializer12636; CHECK-NEXT: [[TMP14:%.*]] = or <8 x i64> [[TMP13]], [[TMP10]]12637; CHECK-NEXT: [[TMP15:%.*]] = or <8 x i64> [[TMP14]], zeroinitializer12638; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP11]], <8 x i64> [[TMP15]], <8 x i64> [[TMP12]]12639; CHECK-NEXT: [[RES2:%.*]] = select <8 x i1> [[MASK_CAST]], <8 x i64> [[RES]], <8 x i64> zeroinitializer12640; CHECK-NEXT: store <8 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 812641; CHECK-NEXT: ret <8 x i64> [[RES2]]12642;12643 %res = call <8 x i64> @llvm.x86.avx512.psrl.q.512(<8 x i64> %a0, <2 x i64> %a1) ; <<8 x i64>> [#uses=1]12644 %mask.cast = bitcast i8 %mask to <8 x i1>12645 %res2 = select <8 x i1> %mask.cast, <8 x i64> %res, <8 x i64> zeroinitializer12646 ret <8 x i64> %res212647}12648declare <8 x i64> @llvm.x86.avx512.psrl.q.512(<8 x i64>, <2 x i64>) nounwind readnone12649 12650 12651define <16 x i32> @test_x86_avx512_psrli_d_512(<16 x i32> %a0) #0 {12652; CHECK-LABEL: @test_x86_avx512_psrli_d_512(12653; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 812654; CHECK-NEXT: call void @llvm.donothing()12655; CHECK-NEXT: [[TMP2:%.*]] = call <16 x i32> @llvm.x86.avx512.psrli.d.512(<16 x i32> [[TMP1]], i32 7)12656; CHECK-NEXT: [[TMP3:%.*]] = or <16 x i32> [[TMP2]], zeroinitializer12657; CHECK-NEXT: [[RES:%.*]] = call <16 x i32> @llvm.x86.avx512.psrli.d.512(<16 x i32> [[A0:%.*]], i32 7)12658; CHECK-NEXT: store <16 x i32> [[TMP3]], ptr @__msan_retval_tls, align 812659; CHECK-NEXT: ret <16 x i32> [[RES]]12660;12661 %res = call <16 x i32> @llvm.x86.avx512.psrli.d.512(<16 x i32> %a0, i32 7) ; <<16 x i32>> [#uses=1]12662 ret <16 x i32> %res12663}12664define <16 x i32> @test_x86_avx512_mask_psrli_d_512(<16 x i32> %a0, <16 x i32> %passthru, i16 %mask) #0 {12665; CHECK-LABEL: @test_x86_avx512_mask_psrli_d_512(12666; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 812667; CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 812668; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 812669; CHECK-NEXT: call void @llvm.donothing()12670; CHECK-NEXT: [[TMP4:%.*]] = call <16 x i32> @llvm.x86.avx512.psrli.d.512(<16 x i32> [[TMP1]], i32 7)12671; CHECK-NEXT: [[TMP5:%.*]] = or <16 x i32> [[TMP4]], zeroinitializer12672; CHECK-NEXT: [[RES:%.*]] = call <16 x i32> @llvm.x86.avx512.psrli.d.512(<16 x i32> [[A0:%.*]], i32 7)12673; CHECK-NEXT: [[TMP6:%.*]] = bitcast i16 [[TMP2]] to <16 x i1>12674; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>12675; CHECK-NEXT: [[TMP7:%.*]] = select <16 x i1> [[MASK_CAST]], <16 x i32> [[TMP5]], <16 x i32> [[TMP3]]12676; CHECK-NEXT: [[TMP8:%.*]] = xor <16 x i32> [[RES]], [[PASSTHRU:%.*]]12677; CHECK-NEXT: [[TMP9:%.*]] = or <16 x i32> [[TMP8]], [[TMP5]]12678; CHECK-NEXT: [[TMP10:%.*]] = or <16 x i32> [[TMP9]], [[TMP3]]12679; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP6]], <16 x i32> [[TMP10]], <16 x i32> [[TMP7]]12680; CHECK-NEXT: [[RES2:%.*]] = select <16 x i1> [[MASK_CAST]], <16 x i32> [[RES]], <16 x i32> [[PASSTHRU]]12681; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 812682; CHECK-NEXT: ret <16 x i32> [[RES2]]12683;12684 %res = call <16 x i32> @llvm.x86.avx512.psrli.d.512(<16 x i32> %a0, i32 7) ; <<16 x i32>> [#uses=1]12685 %mask.cast = bitcast i16 %mask to <16 x i1>12686 %res2 = select <16 x i1> %mask.cast, <16 x i32> %res, <16 x i32> %passthru12687 ret <16 x i32> %res212688}12689define <16 x i32> @test_x86_avx512_maskz_psrli_d_512(<16 x i32> %a0, i16 %mask) #0 {12690; CHECK-LABEL: @test_x86_avx512_maskz_psrli_d_512(12691; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 812692; CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 812693; CHECK-NEXT: call void @llvm.donothing()12694; CHECK-NEXT: [[TMP3:%.*]] = call <16 x i32> @llvm.x86.avx512.psrli.d.512(<16 x i32> [[TMP1]], i32 7)12695; CHECK-NEXT: [[TMP4:%.*]] = or <16 x i32> [[TMP3]], zeroinitializer12696; CHECK-NEXT: [[RES:%.*]] = call <16 x i32> @llvm.x86.avx512.psrli.d.512(<16 x i32> [[A0:%.*]], i32 7)12697; CHECK-NEXT: [[TMP5:%.*]] = bitcast i16 [[TMP2]] to <16 x i1>12698; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>12699; CHECK-NEXT: [[TMP6:%.*]] = select <16 x i1> [[MASK_CAST]], <16 x i32> [[TMP4]], <16 x i32> zeroinitializer12700; CHECK-NEXT: [[TMP7:%.*]] = xor <16 x i32> [[RES]], zeroinitializer12701; CHECK-NEXT: [[TMP8:%.*]] = or <16 x i32> [[TMP7]], [[TMP4]]12702; CHECK-NEXT: [[TMP9:%.*]] = or <16 x i32> [[TMP8]], zeroinitializer12703; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP5]], <16 x i32> [[TMP9]], <16 x i32> [[TMP6]]12704; CHECK-NEXT: [[RES2:%.*]] = select <16 x i1> [[MASK_CAST]], <16 x i32> [[RES]], <16 x i32> zeroinitializer12705; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 812706; CHECK-NEXT: ret <16 x i32> [[RES2]]12707;12708 %res = call <16 x i32> @llvm.x86.avx512.psrli.d.512(<16 x i32> %a0, i32 7) ; <<16 x i32>> [#uses=1]12709 %mask.cast = bitcast i16 %mask to <16 x i1>12710 %res2 = select <16 x i1> %mask.cast, <16 x i32> %res, <16 x i32> zeroinitializer12711 ret <16 x i32> %res212712}12713declare <16 x i32> @llvm.x86.avx512.psrli.d.512(<16 x i32>, i32) nounwind readnone12714 12715 12716define <8 x i64> @test_x86_avx512_psrli_q_512(<8 x i64> %a0) #0 {12717; CHECK-LABEL: @test_x86_avx512_psrli_q_512(12718; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 812719; CHECK-NEXT: call void @llvm.donothing()12720; CHECK-NEXT: [[TMP2:%.*]] = call <8 x i64> @llvm.x86.avx512.psrli.q.512(<8 x i64> [[TMP1]], i32 7)12721; CHECK-NEXT: [[TMP3:%.*]] = or <8 x i64> [[TMP2]], zeroinitializer12722; CHECK-NEXT: [[RES:%.*]] = call <8 x i64> @llvm.x86.avx512.psrli.q.512(<8 x i64> [[A0:%.*]], i32 7)12723; CHECK-NEXT: store <8 x i64> [[TMP3]], ptr @__msan_retval_tls, align 812724; CHECK-NEXT: ret <8 x i64> [[RES]]12725;12726 %res = call <8 x i64> @llvm.x86.avx512.psrli.q.512(<8 x i64> %a0, i32 7) ; <<8 x i64>> [#uses=1]12727 ret <8 x i64> %res12728}12729define <8 x i64> @test_x86_avx512_mask_psrli_q_512(<8 x i64> %a0, <8 x i64> %passthru, i8 %mask) #0 {12730; CHECK-LABEL: @test_x86_avx512_mask_psrli_q_512(12731; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 812732; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 812733; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 812734; CHECK-NEXT: call void @llvm.donothing()12735; CHECK-NEXT: [[TMP4:%.*]] = call <8 x i64> @llvm.x86.avx512.psrli.q.512(<8 x i64> [[TMP1]], i32 7)12736; CHECK-NEXT: [[TMP5:%.*]] = or <8 x i64> [[TMP4]], zeroinitializer12737; CHECK-NEXT: [[RES:%.*]] = call <8 x i64> @llvm.x86.avx512.psrli.q.512(<8 x i64> [[A0:%.*]], i32 7)12738; CHECK-NEXT: [[TMP6:%.*]] = bitcast i8 [[TMP2]] to <8 x i1>12739; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>12740; CHECK-NEXT: [[TMP7:%.*]] = select <8 x i1> [[MASK_CAST]], <8 x i64> [[TMP5]], <8 x i64> [[TMP3]]12741; CHECK-NEXT: [[TMP8:%.*]] = xor <8 x i64> [[RES]], [[PASSTHRU:%.*]]12742; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i64> [[TMP8]], [[TMP5]]12743; CHECK-NEXT: [[TMP10:%.*]] = or <8 x i64> [[TMP9]], [[TMP3]]12744; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP6]], <8 x i64> [[TMP10]], <8 x i64> [[TMP7]]12745; CHECK-NEXT: [[RES2:%.*]] = select <8 x i1> [[MASK_CAST]], <8 x i64> [[RES]], <8 x i64> [[PASSTHRU]]12746; CHECK-NEXT: store <8 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 812747; CHECK-NEXT: ret <8 x i64> [[RES2]]12748;12749 %res = call <8 x i64> @llvm.x86.avx512.psrli.q.512(<8 x i64> %a0, i32 7) ; <<8 x i64>> [#uses=1]12750 %mask.cast = bitcast i8 %mask to <8 x i1>12751 %res2 = select <8 x i1> %mask.cast, <8 x i64> %res, <8 x i64> %passthru12752 ret <8 x i64> %res212753}12754define <8 x i64> @test_x86_avx512_maskz_psrli_q_512(<8 x i64> %a0, i8 %mask) #0 {12755; CHECK-LABEL: @test_x86_avx512_maskz_psrli_q_512(12756; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 812757; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 812758; CHECK-NEXT: call void @llvm.donothing()12759; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i64> @llvm.x86.avx512.psrli.q.512(<8 x i64> [[TMP1]], i32 7)12760; CHECK-NEXT: [[TMP4:%.*]] = or <8 x i64> [[TMP3]], zeroinitializer12761; CHECK-NEXT: [[RES:%.*]] = call <8 x i64> @llvm.x86.avx512.psrli.q.512(<8 x i64> [[A0:%.*]], i32 7)12762; CHECK-NEXT: [[TMP5:%.*]] = bitcast i8 [[TMP2]] to <8 x i1>12763; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>12764; CHECK-NEXT: [[TMP6:%.*]] = select <8 x i1> [[MASK_CAST]], <8 x i64> [[TMP4]], <8 x i64> zeroinitializer12765; CHECK-NEXT: [[TMP7:%.*]] = xor <8 x i64> [[RES]], zeroinitializer12766; CHECK-NEXT: [[TMP8:%.*]] = or <8 x i64> [[TMP7]], [[TMP4]]12767; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i64> [[TMP8]], zeroinitializer12768; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP5]], <8 x i64> [[TMP9]], <8 x i64> [[TMP6]]12769; CHECK-NEXT: [[RES2:%.*]] = select <8 x i1> [[MASK_CAST]], <8 x i64> [[RES]], <8 x i64> zeroinitializer12770; CHECK-NEXT: store <8 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 812771; CHECK-NEXT: ret <8 x i64> [[RES2]]12772;12773 %res = call <8 x i64> @llvm.x86.avx512.psrli.q.512(<8 x i64> %a0, i32 7) ; <<8 x i64>> [#uses=1]12774 %mask.cast = bitcast i8 %mask to <8 x i1>12775 %res2 = select <8 x i1> %mask.cast, <8 x i64> %res, <8 x i64> zeroinitializer12776 ret <8 x i64> %res212777}12778declare <8 x i64> @llvm.x86.avx512.psrli.q.512(<8 x i64>, i32) nounwind readnone12779 12780define <16 x i32> @test_x86_avx512_psllv_d_512(<16 x i32> %a0, <16 x i32> %a1) #0 {12781; CHECK-LABEL: @test_x86_avx512_psllv_d_512(12782; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 812783; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 812784; CHECK-NEXT: call void @llvm.donothing()12785; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <16 x i32> [[TMP2]], zeroinitializer12786; CHECK-NEXT: [[TMP4:%.*]] = sext <16 x i1> [[TMP3]] to <16 x i32>12787; CHECK-NEXT: [[TMP5:%.*]] = call <16 x i32> @llvm.x86.avx512.psllv.d.512(<16 x i32> [[TMP1]], <16 x i32> [[A1:%.*]])12788; CHECK-NEXT: [[TMP6:%.*]] = or <16 x i32> [[TMP5]], [[TMP4]]12789; CHECK-NEXT: [[RES:%.*]] = call <16 x i32> @llvm.x86.avx512.psllv.d.512(<16 x i32> [[A0:%.*]], <16 x i32> [[A1]])12790; CHECK-NEXT: store <16 x i32> [[TMP6]], ptr @__msan_retval_tls, align 812791; CHECK-NEXT: ret <16 x i32> [[RES]]12792;12793 %res = call <16 x i32> @llvm.x86.avx512.psllv.d.512(<16 x i32> %a0, <16 x i32> %a1)12794 ret <16 x i32> %res12795}12796 12797define <16 x i32> @test_x86_avx512_psllv_d_512_const() #0 {12798; CHECK-LABEL: @test_x86_avx512_psllv_d_512_const(12799; CHECK-NEXT: call void @llvm.donothing()12800; CHECK-NEXT: [[TMP1:%.*]] = call <16 x i32> @llvm.x86.avx512.psllv.d.512(<16 x i32> zeroinitializer, <16 x i32> <i32 1, i32 0, i32 33, i32 -1, i32 2, i32 0, i32 34, i32 -2, i32 3, i32 0, i32 35, i32 -1, i32 4, i32 0, i32 36, i32 -3>)12801; CHECK-NEXT: [[TMP2:%.*]] = or <16 x i32> [[TMP1]], zeroinitializer12802; CHECK-NEXT: [[RES0:%.*]] = call <16 x i32> @llvm.x86.avx512.psllv.d.512(<16 x i32> <i32 2, i32 9, i32 0, i32 -1, i32 3, i32 7, i32 -1, i32 0, i32 4, i32 5, i32 -2, i32 0, i32 5, i32 3, i32 -3, i32 0>, <16 x i32> <i32 1, i32 0, i32 33, i32 -1, i32 2, i32 0, i32 34, i32 -2, i32 3, i32 0, i32 35, i32 -1, i32 4, i32 0, i32 36, i32 -3>)12803; CHECK-NEXT: [[TMP3:%.*]] = call <16 x i32> @llvm.x86.avx512.psllv.d.512(<16 x i32> zeroinitializer, <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 -1>)12804; CHECK-NEXT: [[TMP4:%.*]] = or <16 x i32> [[TMP3]], zeroinitializer12805; CHECK-NEXT: [[RES1:%.*]] = call <16 x i32> @llvm.x86.avx512.psllv.d.512(<16 x i32> <i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 -1>, <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 -1>)12806; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i32> [[TMP2]], [[TMP4]]12807; CHECK-NEXT: [[RES2:%.*]] = add <16 x i32> [[RES0]], [[RES1]]12808; CHECK-NEXT: store <16 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 812809; CHECK-NEXT: ret <16 x i32> [[RES2]]12810;12811 %res0 = call <16 x i32> @llvm.x86.avx512.psllv.d.512(<16 x i32> <i32 2, i32 9, i32 0, i32 -1, i32 3, i32 7, i32 -1, i32 0, i32 4, i32 5, i32 -2, i32 0, i32 5, i32 3, i32 -3, i32 0>, <16 x i32> <i32 1, i32 0, i32 33, i32 -1,i32 2, i32 0, i32 34, i32 -2, i32 3, i32 0, i32 35, i32 -1, i32 4, i32 0, i32 36, i32 -3>)12812 %res1 = call <16 x i32> @llvm.x86.avx512.psllv.d.512(<16 x i32> <i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 -1>, <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 -1>)12813 %res2 = add <16 x i32> %res0, %res112814 ret <16 x i32> %res212815}12816 12817define <16 x i32> @test_x86_avx512_mask_psllv_d_512(<16 x i32> %a0, <16 x i32> %a1, <16 x i32> %a2, i16 %mask) #0 {12818; CHECK-LABEL: @test_x86_avx512_mask_psllv_d_512(12819; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 812820; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 812821; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 812822; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 812823; CHECK-NEXT: call void @llvm.donothing()12824; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <16 x i32> [[TMP2]], zeroinitializer12825; CHECK-NEXT: [[TMP6:%.*]] = sext <16 x i1> [[TMP5]] to <16 x i32>12826; CHECK-NEXT: [[TMP7:%.*]] = call <16 x i32> @llvm.x86.avx512.psllv.d.512(<16 x i32> [[TMP1]], <16 x i32> [[A1:%.*]])12827; CHECK-NEXT: [[TMP8:%.*]] = or <16 x i32> [[TMP7]], [[TMP6]]12828; CHECK-NEXT: [[RES:%.*]] = call <16 x i32> @llvm.x86.avx512.psllv.d.512(<16 x i32> [[A0:%.*]], <16 x i32> [[A1]])12829; CHECK-NEXT: [[TMP9:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>12830; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>12831; CHECK-NEXT: [[TMP10:%.*]] = select <16 x i1> [[MASK_CAST]], <16 x i32> [[TMP8]], <16 x i32> [[TMP4]]12832; CHECK-NEXT: [[TMP11:%.*]] = xor <16 x i32> [[RES]], [[A2:%.*]]12833; CHECK-NEXT: [[TMP12:%.*]] = or <16 x i32> [[TMP11]], [[TMP8]]12834; CHECK-NEXT: [[TMP13:%.*]] = or <16 x i32> [[TMP12]], [[TMP4]]12835; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP9]], <16 x i32> [[TMP13]], <16 x i32> [[TMP10]]12836; CHECK-NEXT: [[RES2:%.*]] = select <16 x i1> [[MASK_CAST]], <16 x i32> [[RES]], <16 x i32> [[A2]]12837; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 812838; CHECK-NEXT: ret <16 x i32> [[RES2]]12839;12840 %res = call <16 x i32> @llvm.x86.avx512.psllv.d.512(<16 x i32> %a0, <16 x i32> %a1)12841 %mask.cast = bitcast i16 %mask to <16 x i1>12842 %res2 = select <16 x i1> %mask.cast, <16 x i32> %res, <16 x i32> %a212843 ret <16 x i32> %res212844}12845 12846define <16 x i32> @test_x86_avx512_maskz_psllv_d_512(<16 x i32> %a0, <16 x i32> %a1, i16 %mask) #0 {12847; CHECK-LABEL: @test_x86_avx512_maskz_psllv_d_512(12848; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 812849; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 812850; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 812851; CHECK-NEXT: call void @llvm.donothing()12852; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <16 x i32> [[TMP2]], zeroinitializer12853; CHECK-NEXT: [[TMP5:%.*]] = sext <16 x i1> [[TMP4]] to <16 x i32>12854; CHECK-NEXT: [[TMP6:%.*]] = call <16 x i32> @llvm.x86.avx512.psllv.d.512(<16 x i32> [[TMP1]], <16 x i32> [[A1:%.*]])12855; CHECK-NEXT: [[TMP7:%.*]] = or <16 x i32> [[TMP6]], [[TMP5]]12856; CHECK-NEXT: [[RES:%.*]] = call <16 x i32> @llvm.x86.avx512.psllv.d.512(<16 x i32> [[A0:%.*]], <16 x i32> [[A1]])12857; CHECK-NEXT: [[TMP8:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>12858; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>12859; CHECK-NEXT: [[TMP9:%.*]] = select <16 x i1> [[MASK_CAST]], <16 x i32> [[TMP7]], <16 x i32> zeroinitializer12860; CHECK-NEXT: [[TMP10:%.*]] = xor <16 x i32> [[RES]], zeroinitializer12861; CHECK-NEXT: [[TMP11:%.*]] = or <16 x i32> [[TMP10]], [[TMP7]]12862; CHECK-NEXT: [[TMP12:%.*]] = or <16 x i32> [[TMP11]], zeroinitializer12863; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP8]], <16 x i32> [[TMP12]], <16 x i32> [[TMP9]]12864; CHECK-NEXT: [[RES2:%.*]] = select <16 x i1> [[MASK_CAST]], <16 x i32> [[RES]], <16 x i32> zeroinitializer12865; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 812866; CHECK-NEXT: ret <16 x i32> [[RES2]]12867;12868 %res = call <16 x i32> @llvm.x86.avx512.psllv.d.512(<16 x i32> %a0, <16 x i32> %a1)12869 %mask.cast = bitcast i16 %mask to <16 x i1>12870 %res2 = select <16 x i1> %mask.cast, <16 x i32> %res, <16 x i32> zeroinitializer12871 ret <16 x i32> %res212872}12873 12874declare <16 x i32> @llvm.x86.avx512.psllv.d.512(<16 x i32>, <16 x i32>) nounwind readnone12875 12876define <8 x i64> @test_x86_avx512_psllv_q_512(<8 x i64> %a0, <8 x i64> %a1) #0 {12877; CHECK-LABEL: @test_x86_avx512_psllv_q_512(12878; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 812879; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 812880; CHECK-NEXT: call void @llvm.donothing()12881; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <8 x i64> [[TMP2]], zeroinitializer12882; CHECK-NEXT: [[TMP4:%.*]] = sext <8 x i1> [[TMP3]] to <8 x i64>12883; CHECK-NEXT: [[TMP5:%.*]] = call <8 x i64> @llvm.x86.avx512.psllv.q.512(<8 x i64> [[TMP1]], <8 x i64> [[A1:%.*]])12884; CHECK-NEXT: [[TMP6:%.*]] = or <8 x i64> [[TMP5]], [[TMP4]]12885; CHECK-NEXT: [[RES:%.*]] = call <8 x i64> @llvm.x86.avx512.psllv.q.512(<8 x i64> [[A0:%.*]], <8 x i64> [[A1]])12886; CHECK-NEXT: store <8 x i64> [[TMP6]], ptr @__msan_retval_tls, align 812887; CHECK-NEXT: ret <8 x i64> [[RES]]12888;12889 %res = call <8 x i64> @llvm.x86.avx512.psllv.q.512(<8 x i64> %a0, <8 x i64> %a1)12890 ret <8 x i64> %res12891}12892 12893define <8 x i64> @test_x86_avx512_psllv_q_512_const() #0 {12894; CHECK-LABEL: @test_x86_avx512_psllv_q_512_const(12895; CHECK-NEXT: call void @llvm.donothing()12896; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i64> @llvm.x86.avx512.psllv.q.512(<8 x i64> zeroinitializer, <8 x i64> <i64 1, i64 0, i64 33, i64 -1, i64 2, i64 0, i64 34, i64 -2>)12897; CHECK-NEXT: [[TMP2:%.*]] = or <8 x i64> [[TMP1]], zeroinitializer12898; CHECK-NEXT: [[RES0:%.*]] = call <8 x i64> @llvm.x86.avx512.psllv.q.512(<8 x i64> <i64 2, i64 9, i64 0, i64 -1, i64 3, i64 7, i64 -1, i64 0>, <8 x i64> <i64 1, i64 0, i64 33, i64 -1, i64 2, i64 0, i64 34, i64 -2>)12899; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i64> @llvm.x86.avx512.psllv.q.512(<8 x i64> zeroinitializer, <8 x i64> <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 -1>)12900; CHECK-NEXT: [[TMP4:%.*]] = or <8 x i64> [[TMP3]], zeroinitializer12901; CHECK-NEXT: [[RES1:%.*]] = call <8 x i64> @llvm.x86.avx512.psllv.q.512(<8 x i64> <i64 4, i64 4, i64 4, i64 4, i64 4, i64 4, i64 4, i64 -1>, <8 x i64> <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 -1>)12902; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i64> [[TMP2]], [[TMP4]]12903; CHECK-NEXT: [[RES2:%.*]] = add <8 x i64> [[RES0]], [[RES1]]12904; CHECK-NEXT: store <8 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 812905; CHECK-NEXT: ret <8 x i64> [[RES2]]12906;12907 %res0 = call <8 x i64> @llvm.x86.avx512.psllv.q.512(<8 x i64> <i64 2, i64 9, i64 0, i64 -1, i64 3, i64 7, i64 -1, i64 0>, <8 x i64> <i64 1, i64 0, i64 33, i64 -1,i64 2, i64 0, i64 34, i64 -2>)12908 %res1 = call <8 x i64> @llvm.x86.avx512.psllv.q.512(<8 x i64> <i64 4, i64 4, i64 4, i64 4, i64 4, i64 4, i64 4, i64 -1>, <8 x i64> <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 -1>)12909 %res2 = add <8 x i64> %res0, %res112910 ret <8 x i64> %res212911}12912 12913define <8 x i64> @test_x86_avx512_mask_psllv_q_512(<8 x i64> %a0, <8 x i64> %a1, <8 x i64> %a2, i8 %mask) #0 {12914; CHECK-LABEL: @test_x86_avx512_mask_psllv_q_512(12915; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 812916; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 812917; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 812918; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 812919; CHECK-NEXT: call void @llvm.donothing()12920; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <8 x i64> [[TMP2]], zeroinitializer12921; CHECK-NEXT: [[TMP6:%.*]] = sext <8 x i1> [[TMP5]] to <8 x i64>12922; CHECK-NEXT: [[TMP7:%.*]] = call <8 x i64> @llvm.x86.avx512.psllv.q.512(<8 x i64> [[TMP1]], <8 x i64> [[A1:%.*]])12923; CHECK-NEXT: [[TMP8:%.*]] = or <8 x i64> [[TMP7]], [[TMP6]]12924; CHECK-NEXT: [[RES:%.*]] = call <8 x i64> @llvm.x86.avx512.psllv.q.512(<8 x i64> [[A0:%.*]], <8 x i64> [[A1]])12925; CHECK-NEXT: [[TMP9:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>12926; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>12927; CHECK-NEXT: [[TMP10:%.*]] = select <8 x i1> [[MASK_CAST]], <8 x i64> [[TMP8]], <8 x i64> [[TMP4]]12928; CHECK-NEXT: [[TMP11:%.*]] = xor <8 x i64> [[RES]], [[A2:%.*]]12929; CHECK-NEXT: [[TMP12:%.*]] = or <8 x i64> [[TMP11]], [[TMP8]]12930; CHECK-NEXT: [[TMP13:%.*]] = or <8 x i64> [[TMP12]], [[TMP4]]12931; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP9]], <8 x i64> [[TMP13]], <8 x i64> [[TMP10]]12932; CHECK-NEXT: [[RES2:%.*]] = select <8 x i1> [[MASK_CAST]], <8 x i64> [[RES]], <8 x i64> [[A2]]12933; CHECK-NEXT: store <8 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 812934; CHECK-NEXT: ret <8 x i64> [[RES2]]12935;12936 %res = call <8 x i64> @llvm.x86.avx512.psllv.q.512(<8 x i64> %a0, <8 x i64> %a1)12937 %mask.cast = bitcast i8 %mask to <8 x i1>12938 %res2 = select <8 x i1> %mask.cast, <8 x i64> %res, <8 x i64> %a212939 ret <8 x i64> %res212940}12941 12942define <8 x i64> @test_x86_avx512_maskz_psllv_q_512(<8 x i64> %a0, <8 x i64> %a1, i8 %mask) #0 {12943; CHECK-LABEL: @test_x86_avx512_maskz_psllv_q_512(12944; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 812945; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 812946; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 812947; CHECK-NEXT: call void @llvm.donothing()12948; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <8 x i64> [[TMP2]], zeroinitializer12949; CHECK-NEXT: [[TMP5:%.*]] = sext <8 x i1> [[TMP4]] to <8 x i64>12950; CHECK-NEXT: [[TMP6:%.*]] = call <8 x i64> @llvm.x86.avx512.psllv.q.512(<8 x i64> [[TMP1]], <8 x i64> [[A1:%.*]])12951; CHECK-NEXT: [[TMP7:%.*]] = or <8 x i64> [[TMP6]], [[TMP5]]12952; CHECK-NEXT: [[RES:%.*]] = call <8 x i64> @llvm.x86.avx512.psllv.q.512(<8 x i64> [[A0:%.*]], <8 x i64> [[A1]])12953; CHECK-NEXT: [[TMP8:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>12954; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>12955; CHECK-NEXT: [[TMP9:%.*]] = select <8 x i1> [[MASK_CAST]], <8 x i64> [[TMP7]], <8 x i64> zeroinitializer12956; CHECK-NEXT: [[TMP10:%.*]] = xor <8 x i64> [[RES]], zeroinitializer12957; CHECK-NEXT: [[TMP11:%.*]] = or <8 x i64> [[TMP10]], [[TMP7]]12958; CHECK-NEXT: [[TMP12:%.*]] = or <8 x i64> [[TMP11]], zeroinitializer12959; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP8]], <8 x i64> [[TMP12]], <8 x i64> [[TMP9]]12960; CHECK-NEXT: [[RES2:%.*]] = select <8 x i1> [[MASK_CAST]], <8 x i64> [[RES]], <8 x i64> zeroinitializer12961; CHECK-NEXT: store <8 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 812962; CHECK-NEXT: ret <8 x i64> [[RES2]]12963;12964 %res = call <8 x i64> @llvm.x86.avx512.psllv.q.512(<8 x i64> %a0, <8 x i64> %a1)12965 %mask.cast = bitcast i8 %mask to <8 x i1>12966 %res2 = select <8 x i1> %mask.cast, <8 x i64> %res, <8 x i64> zeroinitializer12967 ret <8 x i64> %res212968}12969 12970declare <8 x i64> @llvm.x86.avx512.psllv.q.512(<8 x i64>, <8 x i64>) nounwind readnone12971 12972define <16 x i32> @test_x86_avx512_psrav_d_512(<16 x i32> %a0, <16 x i32> %a1) #0 {12973; CHECK-LABEL: @test_x86_avx512_psrav_d_512(12974; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 812975; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 812976; CHECK-NEXT: call void @llvm.donothing()12977; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <16 x i32> [[TMP2]], zeroinitializer12978; CHECK-NEXT: [[TMP4:%.*]] = sext <16 x i1> [[TMP3]] to <16 x i32>12979; CHECK-NEXT: [[TMP5:%.*]] = call <16 x i32> @llvm.x86.avx512.psrav.d.512(<16 x i32> [[TMP1]], <16 x i32> [[A1:%.*]])12980; CHECK-NEXT: [[TMP6:%.*]] = or <16 x i32> [[TMP5]], [[TMP4]]12981; CHECK-NEXT: [[RES:%.*]] = call <16 x i32> @llvm.x86.avx512.psrav.d.512(<16 x i32> [[A0:%.*]], <16 x i32> [[A1]])12982; CHECK-NEXT: store <16 x i32> [[TMP6]], ptr @__msan_retval_tls, align 812983; CHECK-NEXT: ret <16 x i32> [[RES]]12984;12985 %res = call <16 x i32> @llvm.x86.avx512.psrav.d.512(<16 x i32> %a0, <16 x i32> %a1)12986 ret <16 x i32> %res12987}12988 12989define <16 x i32> @test_x86_avx512_mask_psrav_d_512(<16 x i32> %a0, <16 x i32> %a1, <16 x i32> %a2, i16 %mask) #0 {12990; CHECK-LABEL: @test_x86_avx512_mask_psrav_d_512(12991; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 812992; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 812993; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 812994; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 812995; CHECK-NEXT: call void @llvm.donothing()12996; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <16 x i32> [[TMP2]], zeroinitializer12997; CHECK-NEXT: [[TMP6:%.*]] = sext <16 x i1> [[TMP5]] to <16 x i32>12998; CHECK-NEXT: [[TMP7:%.*]] = call <16 x i32> @llvm.x86.avx512.psrav.d.512(<16 x i32> [[TMP1]], <16 x i32> [[A1:%.*]])12999; CHECK-NEXT: [[TMP8:%.*]] = or <16 x i32> [[TMP7]], [[TMP6]]13000; CHECK-NEXT: [[RES:%.*]] = call <16 x i32> @llvm.x86.avx512.psrav.d.512(<16 x i32> [[A0:%.*]], <16 x i32> [[A1]])13001; CHECK-NEXT: [[TMP9:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>13002; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>13003; CHECK-NEXT: [[TMP10:%.*]] = select <16 x i1> [[MASK_CAST]], <16 x i32> [[TMP8]], <16 x i32> [[TMP4]]13004; CHECK-NEXT: [[TMP11:%.*]] = xor <16 x i32> [[RES]], [[A2:%.*]]13005; CHECK-NEXT: [[TMP12:%.*]] = or <16 x i32> [[TMP11]], [[TMP8]]13006; CHECK-NEXT: [[TMP13:%.*]] = or <16 x i32> [[TMP12]], [[TMP4]]13007; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP9]], <16 x i32> [[TMP13]], <16 x i32> [[TMP10]]13008; CHECK-NEXT: [[RES2:%.*]] = select <16 x i1> [[MASK_CAST]], <16 x i32> [[RES]], <16 x i32> [[A2]]13009; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 813010; CHECK-NEXT: ret <16 x i32> [[RES2]]13011;13012 %res = call <16 x i32> @llvm.x86.avx512.psrav.d.512(<16 x i32> %a0, <16 x i32> %a1)13013 %mask.cast = bitcast i16 %mask to <16 x i1>13014 %res2 = select <16 x i1> %mask.cast, <16 x i32> %res, <16 x i32> %a213015 ret <16 x i32> %res213016}13017 13018define <16 x i32> @test_x86_avx512_maskz_psrav_d_512(<16 x i32> %a0, <16 x i32> %a1, i16 %mask) #0 {13019; CHECK-LABEL: @test_x86_avx512_maskz_psrav_d_512(13020; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 813021; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 813022; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 813023; CHECK-NEXT: call void @llvm.donothing()13024; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <16 x i32> [[TMP2]], zeroinitializer13025; CHECK-NEXT: [[TMP5:%.*]] = sext <16 x i1> [[TMP4]] to <16 x i32>13026; CHECK-NEXT: [[TMP6:%.*]] = call <16 x i32> @llvm.x86.avx512.psrav.d.512(<16 x i32> [[TMP1]], <16 x i32> [[A1:%.*]])13027; CHECK-NEXT: [[TMP7:%.*]] = or <16 x i32> [[TMP6]], [[TMP5]]13028; CHECK-NEXT: [[RES:%.*]] = call <16 x i32> @llvm.x86.avx512.psrav.d.512(<16 x i32> [[A0:%.*]], <16 x i32> [[A1]])13029; CHECK-NEXT: [[TMP8:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>13030; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>13031; CHECK-NEXT: [[TMP9:%.*]] = select <16 x i1> [[MASK_CAST]], <16 x i32> [[TMP7]], <16 x i32> zeroinitializer13032; CHECK-NEXT: [[TMP10:%.*]] = xor <16 x i32> [[RES]], zeroinitializer13033; CHECK-NEXT: [[TMP11:%.*]] = or <16 x i32> [[TMP10]], [[TMP7]]13034; CHECK-NEXT: [[TMP12:%.*]] = or <16 x i32> [[TMP11]], zeroinitializer13035; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP8]], <16 x i32> [[TMP12]], <16 x i32> [[TMP9]]13036; CHECK-NEXT: [[RES2:%.*]] = select <16 x i1> [[MASK_CAST]], <16 x i32> [[RES]], <16 x i32> zeroinitializer13037; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 813038; CHECK-NEXT: ret <16 x i32> [[RES2]]13039;13040 %res = call <16 x i32> @llvm.x86.avx512.psrav.d.512(<16 x i32> %a0, <16 x i32> %a1)13041 %mask.cast = bitcast i16 %mask to <16 x i1>13042 %res2 = select <16 x i1> %mask.cast, <16 x i32> %res, <16 x i32> zeroinitializer13043 ret <16 x i32> %res213044}13045 13046declare <16 x i32> @llvm.x86.avx512.psrav.d.512(<16 x i32>, <16 x i32>) nounwind readnone13047 13048define <8 x i64> @test_x86_avx512_psrav_q_512(<8 x i64> %a0, <8 x i64> %a1) #0 {13049; CHECK-LABEL: @test_x86_avx512_psrav_q_512(13050; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 813051; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 813052; CHECK-NEXT: call void @llvm.donothing()13053; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <8 x i64> [[TMP2]], zeroinitializer13054; CHECK-NEXT: [[TMP4:%.*]] = sext <8 x i1> [[TMP3]] to <8 x i64>13055; CHECK-NEXT: [[TMP5:%.*]] = call <8 x i64> @llvm.x86.avx512.psrav.q.512(<8 x i64> [[TMP1]], <8 x i64> [[A1:%.*]])13056; CHECK-NEXT: [[TMP6:%.*]] = or <8 x i64> [[TMP5]], [[TMP4]]13057; CHECK-NEXT: [[RES:%.*]] = call <8 x i64> @llvm.x86.avx512.psrav.q.512(<8 x i64> [[A0:%.*]], <8 x i64> [[A1]])13058; CHECK-NEXT: store <8 x i64> [[TMP6]], ptr @__msan_retval_tls, align 813059; CHECK-NEXT: ret <8 x i64> [[RES]]13060;13061 %res = call <8 x i64> @llvm.x86.avx512.psrav.q.512(<8 x i64> %a0, <8 x i64> %a1)13062 ret <8 x i64> %res13063}13064 13065define <8 x i64> @test_x86_avx512_mask_psrav_q_512(<8 x i64> %a0, <8 x i64> %a1, <8 x i64> %a2, i8 %mask) #0 {13066; CHECK-LABEL: @test_x86_avx512_mask_psrav_q_512(13067; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 813068; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 813069; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 813070; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 813071; CHECK-NEXT: call void @llvm.donothing()13072; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <8 x i64> [[TMP2]], zeroinitializer13073; CHECK-NEXT: [[TMP6:%.*]] = sext <8 x i1> [[TMP5]] to <8 x i64>13074; CHECK-NEXT: [[TMP7:%.*]] = call <8 x i64> @llvm.x86.avx512.psrav.q.512(<8 x i64> [[TMP1]], <8 x i64> [[A1:%.*]])13075; CHECK-NEXT: [[TMP8:%.*]] = or <8 x i64> [[TMP7]], [[TMP6]]13076; CHECK-NEXT: [[RES:%.*]] = call <8 x i64> @llvm.x86.avx512.psrav.q.512(<8 x i64> [[A0:%.*]], <8 x i64> [[A1]])13077; CHECK-NEXT: [[TMP9:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>13078; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>13079; CHECK-NEXT: [[TMP10:%.*]] = select <8 x i1> [[MASK_CAST]], <8 x i64> [[TMP8]], <8 x i64> [[TMP4]]13080; CHECK-NEXT: [[TMP11:%.*]] = xor <8 x i64> [[RES]], [[A2:%.*]]13081; CHECK-NEXT: [[TMP12:%.*]] = or <8 x i64> [[TMP11]], [[TMP8]]13082; CHECK-NEXT: [[TMP13:%.*]] = or <8 x i64> [[TMP12]], [[TMP4]]13083; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP9]], <8 x i64> [[TMP13]], <8 x i64> [[TMP10]]13084; CHECK-NEXT: [[RES2:%.*]] = select <8 x i1> [[MASK_CAST]], <8 x i64> [[RES]], <8 x i64> [[A2]]13085; CHECK-NEXT: store <8 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 813086; CHECK-NEXT: ret <8 x i64> [[RES2]]13087;13088 %res = call <8 x i64> @llvm.x86.avx512.psrav.q.512(<8 x i64> %a0, <8 x i64> %a1)13089 %mask.cast = bitcast i8 %mask to <8 x i1>13090 %res2 = select <8 x i1> %mask.cast, <8 x i64> %res, <8 x i64> %a213091 ret <8 x i64> %res213092}13093 13094define <8 x i64> @test_x86_avx512_maskz_psrav_q_512(<8 x i64> %a0, <8 x i64> %a1, i8 %mask) #0 {13095; CHECK-LABEL: @test_x86_avx512_maskz_psrav_q_512(13096; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 813097; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 813098; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 813099; CHECK-NEXT: call void @llvm.donothing()13100; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <8 x i64> [[TMP2]], zeroinitializer13101; CHECK-NEXT: [[TMP5:%.*]] = sext <8 x i1> [[TMP4]] to <8 x i64>13102; CHECK-NEXT: [[TMP6:%.*]] = call <8 x i64> @llvm.x86.avx512.psrav.q.512(<8 x i64> [[TMP1]], <8 x i64> [[A1:%.*]])13103; CHECK-NEXT: [[TMP7:%.*]] = or <8 x i64> [[TMP6]], [[TMP5]]13104; CHECK-NEXT: [[RES:%.*]] = call <8 x i64> @llvm.x86.avx512.psrav.q.512(<8 x i64> [[A0:%.*]], <8 x i64> [[A1]])13105; CHECK-NEXT: [[TMP8:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>13106; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>13107; CHECK-NEXT: [[TMP9:%.*]] = select <8 x i1> [[MASK_CAST]], <8 x i64> [[TMP7]], <8 x i64> zeroinitializer13108; CHECK-NEXT: [[TMP10:%.*]] = xor <8 x i64> [[RES]], zeroinitializer13109; CHECK-NEXT: [[TMP11:%.*]] = or <8 x i64> [[TMP10]], [[TMP7]]13110; CHECK-NEXT: [[TMP12:%.*]] = or <8 x i64> [[TMP11]], zeroinitializer13111; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP8]], <8 x i64> [[TMP12]], <8 x i64> [[TMP9]]13112; CHECK-NEXT: [[RES2:%.*]] = select <8 x i1> [[MASK_CAST]], <8 x i64> [[RES]], <8 x i64> zeroinitializer13113; CHECK-NEXT: store <8 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 813114; CHECK-NEXT: ret <8 x i64> [[RES2]]13115;13116 %res = call <8 x i64> @llvm.x86.avx512.psrav.q.512(<8 x i64> %a0, <8 x i64> %a1)13117 %mask.cast = bitcast i8 %mask to <8 x i1>13118 %res2 = select <8 x i1> %mask.cast, <8 x i64> %res, <8 x i64> zeroinitializer13119 ret <8 x i64> %res213120}13121 13122declare <8 x i64> @llvm.x86.avx512.psrav.q.512(<8 x i64>, <8 x i64>) nounwind readnone13123 13124define <16 x i32> @test_x86_avx512_psrlv_d_512(<16 x i32> %a0, <16 x i32> %a1) #0 {13125; CHECK-LABEL: @test_x86_avx512_psrlv_d_512(13126; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 813127; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 813128; CHECK-NEXT: call void @llvm.donothing()13129; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <16 x i32> [[TMP2]], zeroinitializer13130; CHECK-NEXT: [[TMP4:%.*]] = sext <16 x i1> [[TMP3]] to <16 x i32>13131; CHECK-NEXT: [[TMP5:%.*]] = call <16 x i32> @llvm.x86.avx512.psrlv.d.512(<16 x i32> [[TMP1]], <16 x i32> [[A1:%.*]])13132; CHECK-NEXT: [[TMP6:%.*]] = or <16 x i32> [[TMP5]], [[TMP4]]13133; CHECK-NEXT: [[RES:%.*]] = call <16 x i32> @llvm.x86.avx512.psrlv.d.512(<16 x i32> [[A0:%.*]], <16 x i32> [[A1]])13134; CHECK-NEXT: store <16 x i32> [[TMP6]], ptr @__msan_retval_tls, align 813135; CHECK-NEXT: ret <16 x i32> [[RES]]13136;13137 %res = call <16 x i32> @llvm.x86.avx512.psrlv.d.512(<16 x i32> %a0, <16 x i32> %a1)13138 ret <16 x i32> %res13139}13140 13141define <16 x i32> @test_x86_avx512_psrlv_d_512_const() #0 {13142; CHECK-LABEL: @test_x86_avx512_psrlv_d_512_const(13143; CHECK-NEXT: call void @llvm.donothing()13144; CHECK-NEXT: [[TMP1:%.*]] = call <16 x i32> @llvm.x86.avx512.psrlv.d.512(<16 x i32> zeroinitializer, <16 x i32> <i32 1, i32 0, i32 33, i32 -1, i32 2, i32 0, i32 34, i32 -2, i32 3, i32 0, i32 35, i32 -1, i32 4, i32 0, i32 36, i32 -3>)13145; CHECK-NEXT: [[TMP2:%.*]] = or <16 x i32> [[TMP1]], zeroinitializer13146; CHECK-NEXT: [[RES0:%.*]] = call <16 x i32> @llvm.x86.avx512.psrlv.d.512(<16 x i32> <i32 2, i32 9, i32 0, i32 -1, i32 3, i32 7, i32 -1, i32 0, i32 4, i32 5, i32 -2, i32 0, i32 5, i32 3, i32 -3, i32 0>, <16 x i32> <i32 1, i32 0, i32 33, i32 -1, i32 2, i32 0, i32 34, i32 -2, i32 3, i32 0, i32 35, i32 -1, i32 4, i32 0, i32 36, i32 -3>)13147; CHECK-NEXT: [[TMP3:%.*]] = call <16 x i32> @llvm.x86.avx512.psrlv.d.512(<16 x i32> zeroinitializer, <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 -1>)13148; CHECK-NEXT: [[TMP4:%.*]] = or <16 x i32> [[TMP3]], zeroinitializer13149; CHECK-NEXT: [[RES1:%.*]] = call <16 x i32> @llvm.x86.avx512.psrlv.d.512(<16 x i32> <i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 -1>, <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 -1>)13150; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i32> [[TMP2]], [[TMP4]]13151; CHECK-NEXT: [[RES2:%.*]] = add <16 x i32> [[RES0]], [[RES1]]13152; CHECK-NEXT: store <16 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 813153; CHECK-NEXT: ret <16 x i32> [[RES2]]13154;13155 %res0 = call <16 x i32> @llvm.x86.avx512.psrlv.d.512(<16 x i32> <i32 2, i32 9, i32 0, i32 -1, i32 3, i32 7, i32 -1, i32 0, i32 4, i32 5, i32 -2, i32 0, i32 5, i32 3, i32 -3, i32 0>, <16 x i32> <i32 1, i32 0, i32 33, i32 -1,i32 2, i32 0, i32 34, i32 -2, i32 3, i32 0, i32 35, i32 -1, i32 4, i32 0, i32 36, i32 -3>)13156 %res1 = call <16 x i32> @llvm.x86.avx512.psrlv.d.512(<16 x i32> <i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 -1>, <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 -1 >)13157 %res2 = add <16 x i32> %res0, %res113158 ret <16 x i32> %res213159}13160 13161define <16 x i32> @test_x86_avx512_mask_psrlv_d_512(<16 x i32> %a0, <16 x i32> %a1, <16 x i32> %a2, i16 %mask) #0 {13162; CHECK-LABEL: @test_x86_avx512_mask_psrlv_d_512(13163; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 813164; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 813165; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 813166; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 813167; CHECK-NEXT: call void @llvm.donothing()13168; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <16 x i32> [[TMP2]], zeroinitializer13169; CHECK-NEXT: [[TMP6:%.*]] = sext <16 x i1> [[TMP5]] to <16 x i32>13170; CHECK-NEXT: [[TMP7:%.*]] = call <16 x i32> @llvm.x86.avx512.psrlv.d.512(<16 x i32> [[TMP1]], <16 x i32> [[A1:%.*]])13171; CHECK-NEXT: [[TMP8:%.*]] = or <16 x i32> [[TMP7]], [[TMP6]]13172; CHECK-NEXT: [[RES:%.*]] = call <16 x i32> @llvm.x86.avx512.psrlv.d.512(<16 x i32> [[A0:%.*]], <16 x i32> [[A1]])13173; CHECK-NEXT: [[TMP9:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>13174; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>13175; CHECK-NEXT: [[TMP10:%.*]] = select <16 x i1> [[MASK_CAST]], <16 x i32> [[TMP8]], <16 x i32> [[TMP4]]13176; CHECK-NEXT: [[TMP11:%.*]] = xor <16 x i32> [[RES]], [[A2:%.*]]13177; CHECK-NEXT: [[TMP12:%.*]] = or <16 x i32> [[TMP11]], [[TMP8]]13178; CHECK-NEXT: [[TMP13:%.*]] = or <16 x i32> [[TMP12]], [[TMP4]]13179; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP9]], <16 x i32> [[TMP13]], <16 x i32> [[TMP10]]13180; CHECK-NEXT: [[RES2:%.*]] = select <16 x i1> [[MASK_CAST]], <16 x i32> [[RES]], <16 x i32> [[A2]]13181; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 813182; CHECK-NEXT: ret <16 x i32> [[RES2]]13183;13184 %res = call <16 x i32> @llvm.x86.avx512.psrlv.d.512(<16 x i32> %a0, <16 x i32> %a1)13185 %mask.cast = bitcast i16 %mask to <16 x i1>13186 %res2 = select <16 x i1> %mask.cast, <16 x i32> %res, <16 x i32> %a213187 ret <16 x i32> %res213188}13189 13190define <16 x i32> @test_x86_avx512_maskz_psrlv_d_512(<16 x i32> %a0, <16 x i32> %a1, i16 %mask) #0 {13191; CHECK-LABEL: @test_x86_avx512_maskz_psrlv_d_512(13192; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 813193; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 813194; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 813195; CHECK-NEXT: call void @llvm.donothing()13196; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <16 x i32> [[TMP2]], zeroinitializer13197; CHECK-NEXT: [[TMP5:%.*]] = sext <16 x i1> [[TMP4]] to <16 x i32>13198; CHECK-NEXT: [[TMP6:%.*]] = call <16 x i32> @llvm.x86.avx512.psrlv.d.512(<16 x i32> [[TMP1]], <16 x i32> [[A1:%.*]])13199; CHECK-NEXT: [[TMP7:%.*]] = or <16 x i32> [[TMP6]], [[TMP5]]13200; CHECK-NEXT: [[RES:%.*]] = call <16 x i32> @llvm.x86.avx512.psrlv.d.512(<16 x i32> [[A0:%.*]], <16 x i32> [[A1]])13201; CHECK-NEXT: [[TMP8:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>13202; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>13203; CHECK-NEXT: [[TMP9:%.*]] = select <16 x i1> [[MASK_CAST]], <16 x i32> [[TMP7]], <16 x i32> zeroinitializer13204; CHECK-NEXT: [[TMP10:%.*]] = xor <16 x i32> [[RES]], zeroinitializer13205; CHECK-NEXT: [[TMP11:%.*]] = or <16 x i32> [[TMP10]], [[TMP7]]13206; CHECK-NEXT: [[TMP12:%.*]] = or <16 x i32> [[TMP11]], zeroinitializer13207; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP8]], <16 x i32> [[TMP12]], <16 x i32> [[TMP9]]13208; CHECK-NEXT: [[RES2:%.*]] = select <16 x i1> [[MASK_CAST]], <16 x i32> [[RES]], <16 x i32> zeroinitializer13209; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 813210; CHECK-NEXT: ret <16 x i32> [[RES2]]13211;13212 %res = call <16 x i32> @llvm.x86.avx512.psrlv.d.512(<16 x i32> %a0, <16 x i32> %a1)13213 %mask.cast = bitcast i16 %mask to <16 x i1>13214 %res2 = select <16 x i1> %mask.cast, <16 x i32> %res, <16 x i32> zeroinitializer13215 ret <16 x i32> %res213216}13217 13218declare <16 x i32> @llvm.x86.avx512.psrlv.d.512(<16 x i32>, <16 x i32>) nounwind readnone13219 13220define <8 x i64> @test_x86_avx512_psrlv_q_512(<8 x i64> %a0, <8 x i64> %a1) #0 {13221; CHECK-LABEL: @test_x86_avx512_psrlv_q_512(13222; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 813223; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 813224; CHECK-NEXT: call void @llvm.donothing()13225; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <8 x i64> [[TMP2]], zeroinitializer13226; CHECK-NEXT: [[TMP4:%.*]] = sext <8 x i1> [[TMP3]] to <8 x i64>13227; CHECK-NEXT: [[TMP5:%.*]] = call <8 x i64> @llvm.x86.avx512.psrlv.q.512(<8 x i64> [[TMP1]], <8 x i64> [[A1:%.*]])13228; CHECK-NEXT: [[TMP6:%.*]] = or <8 x i64> [[TMP5]], [[TMP4]]13229; CHECK-NEXT: [[RES:%.*]] = call <8 x i64> @llvm.x86.avx512.psrlv.q.512(<8 x i64> [[A0:%.*]], <8 x i64> [[A1]])13230; CHECK-NEXT: store <8 x i64> [[TMP6]], ptr @__msan_retval_tls, align 813231; CHECK-NEXT: ret <8 x i64> [[RES]]13232;13233 %res = call <8 x i64> @llvm.x86.avx512.psrlv.q.512(<8 x i64> %a0, <8 x i64> %a1)13234 ret <8 x i64> %res13235}13236 13237define <8 x i64> @test_x86_avx512_psrlv_q_512_const() #0 {13238; CHECK-LABEL: @test_x86_avx512_psrlv_q_512_const(13239; CHECK-NEXT: call void @llvm.donothing()13240; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i64> @llvm.x86.avx512.psrlv.q.512(<8 x i64> zeroinitializer, <8 x i64> <i64 1, i64 0, i64 33, i64 -1, i64 2, i64 0, i64 34, i64 -2>)13241; CHECK-NEXT: [[TMP2:%.*]] = or <8 x i64> [[TMP1]], zeroinitializer13242; CHECK-NEXT: [[RES0:%.*]] = call <8 x i64> @llvm.x86.avx512.psrlv.q.512(<8 x i64> <i64 2, i64 9, i64 0, i64 -1, i64 3, i64 7, i64 -1, i64 0>, <8 x i64> <i64 1, i64 0, i64 33, i64 -1, i64 2, i64 0, i64 34, i64 -2>)13243; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i64> @llvm.x86.avx512.psrlv.q.512(<8 x i64> zeroinitializer, <8 x i64> <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 -1>)13244; CHECK-NEXT: [[TMP4:%.*]] = or <8 x i64> [[TMP3]], zeroinitializer13245; CHECK-NEXT: [[RES1:%.*]] = call <8 x i64> @llvm.x86.avx512.psrlv.q.512(<8 x i64> <i64 4, i64 4, i64 4, i64 4, i64 4, i64 4, i64 4, i64 -1>, <8 x i64> <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 -1>)13246; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i64> [[TMP2]], [[TMP4]]13247; CHECK-NEXT: [[RES2:%.*]] = add <8 x i64> [[RES0]], [[RES1]]13248; CHECK-NEXT: store <8 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 813249; CHECK-NEXT: ret <8 x i64> [[RES2]]13250;13251 %res0 = call <8 x i64> @llvm.x86.avx512.psrlv.q.512(<8 x i64> <i64 2, i64 9, i64 0, i64 -1, i64 3, i64 7, i64 -1, i64 0>, <8 x i64> <i64 1, i64 0, i64 33, i64 -1,i64 2, i64 0, i64 34, i64 -2>)13252 %res1 = call <8 x i64> @llvm.x86.avx512.psrlv.q.512(<8 x i64> <i64 4, i64 4, i64 4, i64 4, i64 4, i64 4, i64 4, i64 -1>, <8 x i64> <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 -1>)13253 %res2 = add <8 x i64> %res0, %res113254 ret <8 x i64> %res213255}13256 13257define <8 x i64> @test_x86_avx512_mask_psrlv_q_512(<8 x i64> %a0, <8 x i64> %a1, <8 x i64> %a2, i8 %mask) #0 {13258; CHECK-LABEL: @test_x86_avx512_mask_psrlv_q_512(13259; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 813260; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 813261; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 813262; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 813263; CHECK-NEXT: call void @llvm.donothing()13264; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <8 x i64> [[TMP2]], zeroinitializer13265; CHECK-NEXT: [[TMP6:%.*]] = sext <8 x i1> [[TMP5]] to <8 x i64>13266; CHECK-NEXT: [[TMP7:%.*]] = call <8 x i64> @llvm.x86.avx512.psrlv.q.512(<8 x i64> [[TMP1]], <8 x i64> [[A1:%.*]])13267; CHECK-NEXT: [[TMP8:%.*]] = or <8 x i64> [[TMP7]], [[TMP6]]13268; CHECK-NEXT: [[RES:%.*]] = call <8 x i64> @llvm.x86.avx512.psrlv.q.512(<8 x i64> [[A0:%.*]], <8 x i64> [[A1]])13269; CHECK-NEXT: [[TMP9:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>13270; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>13271; CHECK-NEXT: [[TMP10:%.*]] = select <8 x i1> [[MASK_CAST]], <8 x i64> [[TMP8]], <8 x i64> [[TMP4]]13272; CHECK-NEXT: [[TMP11:%.*]] = xor <8 x i64> [[RES]], [[A2:%.*]]13273; CHECK-NEXT: [[TMP12:%.*]] = or <8 x i64> [[TMP11]], [[TMP8]]13274; CHECK-NEXT: [[TMP13:%.*]] = or <8 x i64> [[TMP12]], [[TMP4]]13275; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP9]], <8 x i64> [[TMP13]], <8 x i64> [[TMP10]]13276; CHECK-NEXT: [[RES2:%.*]] = select <8 x i1> [[MASK_CAST]], <8 x i64> [[RES]], <8 x i64> [[A2]]13277; CHECK-NEXT: store <8 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 813278; CHECK-NEXT: ret <8 x i64> [[RES2]]13279;13280 %res = call <8 x i64> @llvm.x86.avx512.psrlv.q.512(<8 x i64> %a0, <8 x i64> %a1)13281 %mask.cast = bitcast i8 %mask to <8 x i1>13282 %res2 = select <8 x i1> %mask.cast, <8 x i64> %res, <8 x i64> %a213283 ret <8 x i64> %res213284}13285 13286define <8 x i64> @test_x86_avx512_maskz_psrlv_q_512(<8 x i64> %a0, <8 x i64> %a1, i8 %mask) #0 {13287; CHECK-LABEL: @test_x86_avx512_maskz_psrlv_q_512(13288; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 813289; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 813290; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 813291; CHECK-NEXT: call void @llvm.donothing()13292; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <8 x i64> [[TMP2]], zeroinitializer13293; CHECK-NEXT: [[TMP5:%.*]] = sext <8 x i1> [[TMP4]] to <8 x i64>13294; CHECK-NEXT: [[TMP6:%.*]] = call <8 x i64> @llvm.x86.avx512.psrlv.q.512(<8 x i64> [[TMP1]], <8 x i64> [[A1:%.*]])13295; CHECK-NEXT: [[TMP7:%.*]] = or <8 x i64> [[TMP6]], [[TMP5]]13296; CHECK-NEXT: [[RES:%.*]] = call <8 x i64> @llvm.x86.avx512.psrlv.q.512(<8 x i64> [[A0:%.*]], <8 x i64> [[A1]])13297; CHECK-NEXT: [[TMP8:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>13298; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>13299; CHECK-NEXT: [[TMP9:%.*]] = select <8 x i1> [[MASK_CAST]], <8 x i64> [[TMP7]], <8 x i64> zeroinitializer13300; CHECK-NEXT: [[TMP10:%.*]] = xor <8 x i64> [[RES]], zeroinitializer13301; CHECK-NEXT: [[TMP11:%.*]] = or <8 x i64> [[TMP10]], [[TMP7]]13302; CHECK-NEXT: [[TMP12:%.*]] = or <8 x i64> [[TMP11]], zeroinitializer13303; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP8]], <8 x i64> [[TMP12]], <8 x i64> [[TMP9]]13304; CHECK-NEXT: [[RES2:%.*]] = select <8 x i1> [[MASK_CAST]], <8 x i64> [[RES]], <8 x i64> zeroinitializer13305; CHECK-NEXT: store <8 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 813306; CHECK-NEXT: ret <8 x i64> [[RES2]]13307;13308 %res = call <8 x i64> @llvm.x86.avx512.psrlv.q.512(<8 x i64> %a0, <8 x i64> %a1)13309 %mask.cast = bitcast i8 %mask to <8 x i1>13310 %res2 = select <8 x i1> %mask.cast, <8 x i64> %res, <8 x i64> zeroinitializer13311 ret <8 x i64> %res213312}13313 13314declare <8 x i64> @llvm.x86.avx512.psrlv.q.512(<8 x i64>, <8 x i64>) nounwind readnone13315 13316 13317define <8 x double> @test_mm256_castpd128_pd256_freeze(<2 x double> %a0) nounwind #0 {13318; CHECK-LABEL: @test_mm256_castpd128_pd256_freeze(13319; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 813320; CHECK-NEXT: call void @llvm.donothing()13321; CHECK-NEXT: [[A1:%.*]] = freeze <2 x double> poison13322; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>13323; CHECK-NEXT: [[RES:%.*]] = shufflevector <2 x double> [[A0:%.*]], <2 x double> [[A1]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>13324; CHECK-NEXT: store <8 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 813325; CHECK-NEXT: ret <8 x double> [[RES]]13326;13327 %a1 = freeze <2 x double> poison13328 %res = shufflevector <2 x double> %a0, <2 x double> %a1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>13329 ret <8 x double> %res13330}13331 13332 13333define <8 x double> @test_mm256_castpd256_pd256_freeze(<4 x double> %a0) nounwind #0 {13334; CHECK-LABEL: @test_mm256_castpd256_pd256_freeze(13335; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 813336; CHECK-NEXT: call void @llvm.donothing()13337; CHECK-NEXT: [[A1:%.*]] = freeze <4 x double> poison13338; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i64> [[TMP1]], <4 x i64> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>13339; CHECK-NEXT: [[RES:%.*]] = shufflevector <4 x double> [[A0:%.*]], <4 x double> [[A1]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>13340; CHECK-NEXT: store <8 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 813341; CHECK-NEXT: ret <8 x double> [[RES]]13342;13343 %a1 = freeze <4 x double> poison13344 %res = shufflevector <4 x double> %a0, <4 x double> %a1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>13345 ret <8 x double> %res13346}13347 13348 13349define <16 x float> @test_mm256_castps128_ps512_freeze(<4 x float> %a0) nounwind #0 {13350; CHECK-LABEL: @test_mm256_castps128_ps512_freeze(13351; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 813352; CHECK-NEXT: call void @llvm.donothing()13353; CHECK-NEXT: [[A1:%.*]] = freeze <4 x float> poison13354; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7>13355; CHECK-NEXT: [[RES:%.*]] = shufflevector <4 x float> [[A0:%.*]], <4 x float> [[A1]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7>13356; CHECK-NEXT: store <16 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 813357; CHECK-NEXT: ret <16 x float> [[RES]]13358;13359 %a1 = freeze <4 x float> poison13360 %res = shufflevector <4 x float> %a0, <4 x float> %a1, <16x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7>13361 ret <16 x float> %res13362}13363 13364 13365define <16 x float> @test_mm256_castps256_ps512_freeze(<8 x float> %a0) nounwind #0 {13366; CHECK-LABEL: @test_mm256_castps256_ps512_freeze(13367; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 813368; CHECK-NEXT: call void @llvm.donothing()13369; CHECK-NEXT: [[A1:%.*]] = freeze <8 x float> poison13370; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>13371; CHECK-NEXT: [[RES:%.*]] = shufflevector <8 x float> [[A0:%.*]], <8 x float> [[A1]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>13372; CHECK-NEXT: store <16 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 813373; CHECK-NEXT: ret <16 x float> [[RES]]13374;13375 %a1 = freeze <8 x float> poison13376 %res = shufflevector <8 x float> %a0, <8 x float> %a1, <16x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>13377 ret <16 x float> %res13378}13379 13380 13381define <8 x i64> @test_mm512_castsi128_si512_freeze(<2 x i64> %a0) nounwind #0 {13382; CHECK-LABEL: @test_mm512_castsi128_si512_freeze(13383; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 813384; CHECK-NEXT: call void @llvm.donothing()13385; CHECK-NEXT: [[A1:%.*]] = freeze <2 x i64> poison13386; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>13387; CHECK-NEXT: [[RES:%.*]] = shufflevector <2 x i64> [[A0:%.*]], <2 x i64> [[A1]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>13388; CHECK-NEXT: store <8 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 813389; CHECK-NEXT: ret <8 x i64> [[RES]]13390;13391 %a1 = freeze <2 x i64> poison13392 %res = shufflevector <2 x i64> %a0, <2 x i64> %a1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>13393 ret <8 x i64> %res13394}13395 13396 13397define <8 x i64> @test_mm512_castsi256_si512_pd256_freeze(<4 x i64> %a0) nounwind #0 {13398; CHECK-LABEL: @test_mm512_castsi256_si512_pd256_freeze(13399; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 813400; CHECK-NEXT: call void @llvm.donothing()13401; CHECK-NEXT: [[A1:%.*]] = freeze <4 x i64> poison13402; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i64> [[TMP1]], <4 x i64> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>13403; CHECK-NEXT: [[RES:%.*]] = shufflevector <4 x i64> [[A0:%.*]], <4 x i64> [[A1]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>13404; CHECK-NEXT: store <8 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 813405; CHECK-NEXT: ret <8 x i64> [[RES]]13406;13407 %a1 = freeze <4 x i64> poison13408 %res = shufflevector <4 x i64> %a0, <4 x i64> %a1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>13409 ret <8 x i64> %res13410}13411 13412 13413define <16 x float> @bad_mask_transition(<8 x double> %a, <8 x double> %b, <8 x double> %c, <8 x double> %d, <16 x float> %e, <16 x float> %f, <16 x i1> %extra_param, <16 x i1> %extra_param2) #0 {13414; CHECK-LABEL: @bad_mask_transition(13415; CHECK-NEXT: entry:13416; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 813417; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 813418; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 813419; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 813420; CHECK-NEXT: [[TMP8:%.*]] = load <16 x i1>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 384), align 813421; CHECK-NEXT: [[TMP9:%.*]] = load <16 x i1>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 392), align 813422; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 320), align 813423; CHECK-NEXT: [[TMP5:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 256), align 813424; CHECK-NEXT: call void @llvm.donothing()13425; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i64> [[TMP0]] to i51213426; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP6]], 013427; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i64> [[TMP1]] to i51213428; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP7]], 013429; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]13430; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP14:%.*]], label [[TMP15:%.*]], !prof [[PROF1]]13431; CHECK: 10:13432; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]13433; CHECK-NEXT: unreachable13434; CHECK: 11:13435; CHECK-NEXT: [[TMP10:%.*]] = call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> [[A:%.*]], <8 x double> [[B:%.*]], i32 17, <8 x i1> splat (i1 true), i32 4)13436; CHECK-NEXT: [[TMP11:%.*]] = bitcast <8 x i1> [[TMP10]] to i813437; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x i64> [[TMP2]] to i51213438; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i512 [[TMP12]], 013439; CHECK-NEXT: [[TMP13:%.*]] = bitcast <8 x i64> [[TMP3]] to i51213440; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i512 [[TMP13]], 013441; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]13442; CHECK-NEXT: br i1 [[_MSOR4]], label [[TMP30:%.*]], label [[TMP34:%.*]], !prof [[PROF1]]13443; CHECK: 16:13444; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]13445; CHECK-NEXT: unreachable13446; CHECK: 17:13447; CHECK-NEXT: [[TMP16:%.*]] = call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> [[C:%.*]], <8 x double> [[D:%.*]], i32 17, <8 x i1> splat (i1 true), i32 4)13448; CHECK-NEXT: [[TMP17:%.*]] = bitcast <8 x i1> [[TMP16]] to i813449; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[TMP11]] to i1613450; CHECK-NEXT: [[CONV2:%.*]] = zext i8 [[TMP17]] to i1613451; CHECK-NEXT: [[TMP18:%.*]] = bitcast i16 [[CONV]] to <16 x i1>13452; CHECK-NEXT: [[TMP19:%.*]] = bitcast i16 [[CONV2]] to <16 x i1>13453; CHECK-NEXT: [[TMP20:%.*]] = shufflevector <16 x i1> zeroinitializer, <16 x i1> [[TMP8]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>13454; CHECK-NEXT: [[TMP31:%.*]] = shufflevector <16 x i1> [[TMP18]], <16 x i1> [[EXTRA_PARAM:%.*]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>13455; CHECK-NEXT: [[TMP21:%.*]] = shufflevector <16 x i1> zeroinitializer, <16 x i1> [[TMP9]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>13456; CHECK-NEXT: [[TMP32:%.*]] = shufflevector <16 x i1> [[TMP19]], <16 x i1> [[EXTRA_PARAM2:%.*]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>13457; CHECK-NEXT: [[TMP22:%.*]] = shufflevector <8 x i1> [[TMP20]], <8 x i1> [[TMP21]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>13458; CHECK-NEXT: [[TMP23:%.*]] = shufflevector <8 x i1> [[TMP31]], <8 x i1> [[TMP32]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>13459; CHECK-NEXT: [[TMP33:%.*]] = select <16 x i1> [[TMP23]], <16 x i32> [[TMP4]], <16 x i32> [[TMP5]]13460; CHECK-NEXT: [[TMP24:%.*]] = bitcast <16 x float> [[F:%.*]] to <16 x i32>13461; CHECK-NEXT: [[TMP25:%.*]] = bitcast <16 x float> [[E:%.*]] to <16 x i32>13462; CHECK-NEXT: [[TMP26:%.*]] = xor <16 x i32> [[TMP24]], [[TMP25]]13463; CHECK-NEXT: [[TMP27:%.*]] = or <16 x i32> [[TMP26]], [[TMP4]]13464; CHECK-NEXT: [[TMP28:%.*]] = or <16 x i32> [[TMP27]], [[TMP5]]13465; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP22]], <16 x i32> [[TMP28]], <16 x i32> [[TMP33]]13466; CHECK-NEXT: [[TMP29:%.*]] = select <16 x i1> [[TMP23]], <16 x float> [[F]], <16 x float> [[E]]13467; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 813468; CHECK-NEXT: ret <16 x float> [[TMP29]]13469;13470entry:13471 %0 = call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %a, <8 x double> %b, i32 17, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i32 4)13472 %1 = bitcast <8 x i1> %0 to i813473 %2 = call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %c, <8 x double> %d, i32 17, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i32 4)13474 %3 = bitcast <8 x i1> %2 to i813475 %conv = zext i8 %1 to i1613476 %conv2 = zext i8 %3 to i1613477 %4 = bitcast i16 %conv to <16 x i1>13478 %5 = bitcast i16 %conv2 to <16 x i1>13479 %6 = shufflevector <16 x i1> %4, <16 x i1> %extra_param, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>13480 %7 = shufflevector <16 x i1> %5, <16 x i1> %extra_param2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>13481 %8 = shufflevector <8 x i1> %6, <8 x i1> %7, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>13482 %9 = select <16 x i1> %8, <16 x float> %f, <16 x float> %e13483 ret <16 x float> %913484}13485 13486define <16 x float> @bad_mask_transition_2(<8 x double> %a, <8 x double> %b, <8 x double> %c, <8 x double> %d, <16 x float> %e, <16 x float> %f) #0 {13487; CHECK-LABEL: @bad_mask_transition_2(13488; CHECK-NEXT: entry:13489; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 813490; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 813491; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 320), align 813492; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 256), align 813493; CHECK-NEXT: call void @llvm.donothing()13494; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i64> [[TMP0]] to i51213495; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP4]], 013496; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i64> [[TMP1]] to i51213497; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP5]], 013498; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]13499; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]13500; CHECK: 6:13501; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR10]]13502; CHECK-NEXT: unreachable13503; CHECK: 7:13504; CHECK-NEXT: [[TMP8:%.*]] = call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> [[A:%.*]], <8 x double> [[B:%.*]], i32 17, <8 x i1> splat (i1 true), i32 4)13505; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i1> [[TMP8]] to i813506; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[TMP9]] to i1613507; CHECK-NEXT: [[TMP10:%.*]] = bitcast i16 [[CONV]] to <16 x i1>13508; CHECK-NEXT: [[TMP11:%.*]] = select <16 x i1> [[TMP10]], <16 x i32> [[TMP2]], <16 x i32> [[TMP3]]13509; CHECK-NEXT: [[TMP12:%.*]] = bitcast <16 x float> [[F:%.*]] to <16 x i32>13510; CHECK-NEXT: [[TMP13:%.*]] = bitcast <16 x float> [[E:%.*]] to <16 x i32>13511; CHECK-NEXT: [[TMP14:%.*]] = xor <16 x i32> [[TMP12]], [[TMP13]]13512; CHECK-NEXT: [[TMP15:%.*]] = or <16 x i32> [[TMP14]], [[TMP2]]13513; CHECK-NEXT: [[TMP16:%.*]] = or <16 x i32> [[TMP15]], [[TMP3]]13514; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> zeroinitializer, <16 x i32> [[TMP16]], <16 x i32> [[TMP11]]13515; CHECK-NEXT: [[TMP17:%.*]] = select <16 x i1> [[TMP10]], <16 x float> [[F]], <16 x float> [[E]]13516; CHECK-NEXT: store <16 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 813517; CHECK-NEXT: ret <16 x float> [[TMP17]]13518;13519entry:13520 %0 = call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %a, <8 x double> %b, i32 17, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i32 4)13521 %1 = bitcast <8 x i1> %0 to i813522 %conv = zext i8 %1 to i1613523 %2 = bitcast i16 %conv to <16 x i1>13524 %3 = select <16 x i1> %2, <16 x float> %f, <16 x float> %e13525 ret <16 x float> %313526}13527 13528declare <8 x double> @llvm.x86.avx512.mask.compress.v8f64(<8 x double>, <8 x double>, <8 x i1>)13529declare <16 x float> @llvm.x86.avx512.mask.compress.v16f32(<16 x float>, <16 x float>, <16 x i1>)13530declare <8 x i64> @llvm.x86.avx512.mask.compress.v8i64(<8 x i64>, <8 x i64>, <8 x i1>)13531declare <16 x i32> @llvm.x86.avx512.mask.compress.v16i32(<16 x i32>, <16 x i32>, <16 x i1>)13532declare <8 x double> @llvm.x86.avx512.mask.expand.v8f64(<8 x double>, <8 x double>, <8 x i1>)13533declare <16 x float> @llvm.x86.avx512.mask.expand.v16f32(<16 x float>, <16 x float>, <16 x i1>)13534declare <8 x i64> @llvm.x86.avx512.mask.expand.v8i64(<8 x i64>, <8 x i64>, <8 x i1>)13535declare <16 x i32> @llvm.x86.avx512.mask.expand.v16i32(<16 x i32>, <16 x i32>, <16 x i1>)13536 13537attributes #0 = { sanitize_memory }13538