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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 62; RUN: opt -S -passes=msan -mattr=+avx512bf16 < %s | FileCheck %s3;4; Forked from llvm/test/CodeGen/X86/avx512bf16-mov.ll5;6; Strictly handled: (none)7;8; Heuristically handled: (none)9 10target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"11target triple = "x86_64-unknown-linux-gnu"12 13define dso_local void @funbf16(ptr readonly %src, ptr writeonly %dst) sanitize_memory {14; CHECK-LABEL: define dso_local void @funbf16(15; CHECK-SAME: ptr readonly [[SRC:%.*]], ptr writeonly [[DST:%.*]]) #[[ATTR0:[0-9]+]] {16; CHECK-NEXT: [[ENTRY:.*:]]17; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__msan_param_tls, align 818; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 819; CHECK-NEXT: call void @llvm.donothing()20; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP0]], 021; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB2:.*]], label %[[BB3:.*]], !prof [[PROF1:![0-9]+]]22; CHECK: [[BB2]]:23; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3:[0-9]+]]24; CHECK-NEXT: unreachable25; CHECK: [[BB3]]:26; CHECK-NEXT: [[TMP4:%.*]] = load <8 x bfloat>, ptr [[SRC]], align 127; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[SRC]] to i6428; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 8796093022208029; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr30; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP7]], align 131; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i64 [[TMP1]], 032; CHECK-NEXT: br i1 [[_MSCMP4]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]33; CHECK: [[BB8]]:34; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]35; CHECK-NEXT: unreachable36; CHECK: [[BB9]]:37; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[DST]] to i6438; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 8796093022208039; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr40; CHECK-NEXT: store <8 x i16> [[_MSLD]], ptr [[TMP12]], align 141; CHECK-NEXT: store <8 x bfloat> [[TMP4]], ptr [[DST]], align 142; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i64 [[TMP0]], 043; CHECK-NEXT: br i1 [[_MSCMP5]], label %[[BB13:.*]], label %[[BB14:.*]], !prof [[PROF1]]44; CHECK: [[BB13]]:45; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]46; CHECK-NEXT: unreachable47; CHECK: [[BB14]]:48; CHECK-NEXT: [[TMP15:%.*]] = load <8 x bfloat>, ptr [[SRC]], align 3249; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[SRC]] to i6450; CHECK-NEXT: [[TMP17:%.*]] = xor i64 [[TMP16]], 8796093022208051; CHECK-NEXT: [[TMP18:%.*]] = inttoptr i64 [[TMP17]] to ptr52; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP18]], align 3253; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i64 [[TMP1]], 054; CHECK-NEXT: br i1 [[_MSCMP6]], label %[[BB19:.*]], label %[[BB20:.*]], !prof [[PROF1]]55; CHECK: [[BB19]]:56; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]57; CHECK-NEXT: unreachable58; CHECK: [[BB20]]:59; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[DST]] to i6460; CHECK-NEXT: [[TMP22:%.*]] = xor i64 [[TMP21]], 8796093022208061; CHECK-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP22]] to ptr62; CHECK-NEXT: store <8 x i16> [[_MSLD1]], ptr [[TMP23]], align 3263; CHECK-NEXT: store <8 x bfloat> [[TMP15]], ptr [[DST]], align 3264; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i64 [[TMP0]], 065; CHECK-NEXT: br i1 [[_MSCMP7]], label %[[BB24:.*]], label %[[BB25:.*]], !prof [[PROF1]]66; CHECK: [[BB24]]:67; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]68; CHECK-NEXT: unreachable69; CHECK: [[BB25]]:70; CHECK-NEXT: [[TMP26:%.*]] = load <16 x bfloat>, ptr [[SRC]], align 171; CHECK-NEXT: [[TMP27:%.*]] = ptrtoint ptr [[SRC]] to i6472; CHECK-NEXT: [[TMP28:%.*]] = xor i64 [[TMP27]], 8796093022208073; CHECK-NEXT: [[TMP29:%.*]] = inttoptr i64 [[TMP28]] to ptr74; CHECK-NEXT: [[_MSLD2:%.*]] = load <16 x i16>, ptr [[TMP29]], align 175; CHECK-NEXT: [[_MSCMP8:%.*]] = icmp ne i64 [[TMP1]], 076; CHECK-NEXT: br i1 [[_MSCMP8]], label %[[BB30:.*]], label %[[BB31:.*]], !prof [[PROF1]]77; CHECK: [[BB30]]:78; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]79; CHECK-NEXT: unreachable80; CHECK: [[BB31]]:81; CHECK-NEXT: [[TMP32:%.*]] = ptrtoint ptr [[DST]] to i6482; CHECK-NEXT: [[TMP33:%.*]] = xor i64 [[TMP32]], 8796093022208083; CHECK-NEXT: [[TMP34:%.*]] = inttoptr i64 [[TMP33]] to ptr84; CHECK-NEXT: store <16 x i16> [[_MSLD2]], ptr [[TMP34]], align 185; CHECK-NEXT: store <16 x bfloat> [[TMP26]], ptr [[DST]], align 186; CHECK-NEXT: [[_MSCMP9:%.*]] = icmp ne i64 [[TMP0]], 087; CHECK-NEXT: br i1 [[_MSCMP9]], label %[[BB35:.*]], label %[[BB36:.*]], !prof [[PROF1]]88; CHECK: [[BB35]]:89; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]90; CHECK-NEXT: unreachable91; CHECK: [[BB36]]:92; CHECK-NEXT: [[TMP37:%.*]] = load <16 x bfloat>, ptr [[SRC]], align 3293; CHECK-NEXT: [[TMP38:%.*]] = ptrtoint ptr [[SRC]] to i6494; CHECK-NEXT: [[TMP39:%.*]] = xor i64 [[TMP38]], 8796093022208095; CHECK-NEXT: [[TMP40:%.*]] = inttoptr i64 [[TMP39]] to ptr96; CHECK-NEXT: [[_MSLD3:%.*]] = load <16 x i16>, ptr [[TMP40]], align 3297; CHECK-NEXT: [[_MSCMP10:%.*]] = icmp ne i64 [[TMP1]], 098; CHECK-NEXT: br i1 [[_MSCMP10]], label %[[BB41:.*]], label %[[BB42:.*]], !prof [[PROF1]]99; CHECK: [[BB41]]:100; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]101; CHECK-NEXT: unreachable102; CHECK: [[BB42]]:103; CHECK-NEXT: [[TMP43:%.*]] = ptrtoint ptr [[DST]] to i64104; CHECK-NEXT: [[TMP44:%.*]] = xor i64 [[TMP43]], 87960930222080105; CHECK-NEXT: [[TMP45:%.*]] = inttoptr i64 [[TMP44]] to ptr106; CHECK-NEXT: store <16 x i16> [[_MSLD3]], ptr [[TMP45]], align 32107; CHECK-NEXT: store <16 x bfloat> [[TMP37]], ptr [[DST]], align 32108; CHECK-NEXT: ret void109;110entry:111 %0 = load <8 x bfloat>, ptr %src, align 1112 store <8 x bfloat> %0, ptr %dst, align 1113 %1 = load <8 x bfloat>, ptr %src, align 32114 store <8 x bfloat> %1, ptr %dst, align 32115 %2 = load <16 x bfloat>, ptr %src, align 1116 store <16 x bfloat> %2, ptr %dst, align 1117 %3 = load <16 x bfloat>, ptr %src, align 32118 store <16 x bfloat> %3, ptr %dst, align 32119 ret void120}121;.122; CHECK: [[PROF1]] = !{!"branch_weights", i32 1, i32 1048575}123;.124