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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt %s -S -mattr=+avx512f -passes=msan 2>&1 | FileCheck %s3;4; Forked from llvm/test/CodeGen/X86/avx512fp16-arith-vl-intrinsics.ll5;6; Handled suboptimally (visitInstruction):7; - llvm.x86.avx512fp16.mask.vcvtpd2ph.1288; - llvm.x86.avx512fp16.mask.vcvtpd2ph.2569; - llvm.x86.avx512fp16.mask.vcvtph2pd.12810; - llvm.x86.avx512fp16.mask.vcvtph2pd.25611; - llvm.x86.avx512fp16.mask.vcvtph2psx.12812; - llvm.x86.avx512fp16.mask.vcvtph2psx.25613; - llvm.x86.avx512fp16.mask.vcvtph2udq.12814; - llvm.x86.avx512fp16.mask.vcvtph2udq.25615; - llvm.x86.avx512fp16.mask.vcvtps2phx.12816; - llvm.x86.avx512fp16.mask.vcvtps2phx.25617; - llvm.x86.avx512fp16.mask.vcvttph2dq.12818; - llvm.x86.avx512fp16.mask.vcvttph2dq.25619; - llvm.x86.avx512fp16.mask.vcvttph2udq.12820; - llvm.x86.avx512fp16.mask.vcvttph2udq.25621;22; Handled heuristically:23; - llvm.x86.avx512fp16.max.ph.12824; - llvm.x86.avx512fp16.max.ph.25625; - llvm.x86.avx512fp16.min.ph.12826; - llvm.x86.avx512fp16.min.ph.25627 28target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"29target triple = "x86_64-unknown-linux-gnu"30 31define <16 x half> @test_int_x86_avx512fp16_add_ph_256(<16 x half> %x1, <16 x half> %x2) #0 {32; CHECK-LABEL: define <16 x half> @test_int_x86_avx512fp16_add_ph_256(33; CHECK-SAME: <16 x half> [[X1:%.*]], <16 x half> [[X2:%.*]]) #[[ATTR0:[0-9]+]] {34; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 835; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 836; CHECK-NEXT: call void @llvm.donothing()37; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i16> [[TMP1]], [[TMP2]]38; CHECK-NEXT: [[RES:%.*]] = fadd <16 x half> [[X1]], [[X2]]39; CHECK-NEXT: store <16 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 840; CHECK-NEXT: ret <16 x half> [[RES]]41;42 %res = fadd <16 x half> %x1, %x243 ret <16 x half> %res44}45 46define <16 x half> @test_int_x86_avx512fp16_mask_add_ph_256(<16 x half> %x1, <16 x half> %x2, <16 x half> %src, i16 %mask, ptr %ptr) #0 {47; CHECK-LABEL: define <16 x half> @test_int_x86_avx512fp16_mask_add_ph_256(48; CHECK-SAME: <16 x half> [[X1:%.*]], <16 x half> [[X2:%.*]], <16 x half> [[SRC:%.*]], i16 [[MASK:%.*]], ptr [[PTR:%.*]]) #[[ATTR0]] {49; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 850; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 104), align 851; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 852; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 853; CHECK-NEXT: [[TMP5:%.*]] = load <16 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 854; CHECK-NEXT: call void @llvm.donothing()55; CHECK-NEXT: [[TMP6:%.*]] = bitcast i16 [[TMP1]] to <16 x i1>56; CHECK-NEXT: [[MSK:%.*]] = bitcast i16 [[MASK]] to <16 x i1>57; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 058; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1:![0-9]+]]59; CHECK: [[BB7]]:60; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4:[0-9]+]]61; CHECK-NEXT: unreachable62; CHECK: [[BB8]]:63; CHECK-NEXT: [[VAL:%.*]] = load <16 x half>, ptr [[PTR]], align 3264; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[PTR]] to i6465; CHECK-NEXT: [[TMP10:%.*]] = xor i64 [[TMP9]], 8796093022208066; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to ptr67; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i16>, ptr [[TMP11]], align 3268; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i16> [[TMP3]], [[TMP4]]69; CHECK-NEXT: [[RES0:%.*]] = fadd <16 x half> [[X1]], [[X2]]70; CHECK-NEXT: [[TMP12:%.*]] = select <16 x i1> [[MSK]], <16 x i16> [[_MSPROP]], <16 x i16> [[TMP5]]71; CHECK-NEXT: [[TMP13:%.*]] = bitcast <16 x half> [[RES0]] to <16 x i16>72; CHECK-NEXT: [[TMP14:%.*]] = bitcast <16 x half> [[SRC]] to <16 x i16>73; CHECK-NEXT: [[TMP15:%.*]] = xor <16 x i16> [[TMP13]], [[TMP14]]74; CHECK-NEXT: [[TMP16:%.*]] = or <16 x i16> [[TMP15]], [[_MSPROP]]75; CHECK-NEXT: [[TMP17:%.*]] = or <16 x i16> [[TMP16]], [[TMP5]]76; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP6]], <16 x i16> [[TMP17]], <16 x i16> [[TMP12]]77; CHECK-NEXT: [[RES1:%.*]] = select <16 x i1> [[MSK]], <16 x half> [[RES0]], <16 x half> [[SRC]]78; CHECK-NEXT: [[_MSPROP1:%.*]] = or <16 x i16> [[TMP3]], [[_MSLD]]79; CHECK-NEXT: [[T3:%.*]] = fadd <16 x half> [[X1]], [[VAL]]80; CHECK-NEXT: [[TMP18:%.*]] = select <16 x i1> [[MSK]], <16 x i16> [[_MSPROP1]], <16 x i16> [[TMP5]]81; CHECK-NEXT: [[TMP19:%.*]] = bitcast <16 x half> [[T3]] to <16 x i16>82; CHECK-NEXT: [[TMP20:%.*]] = bitcast <16 x half> [[SRC]] to <16 x i16>83; CHECK-NEXT: [[TMP21:%.*]] = xor <16 x i16> [[TMP19]], [[TMP20]]84; CHECK-NEXT: [[TMP22:%.*]] = or <16 x i16> [[TMP21]], [[_MSPROP1]]85; CHECK-NEXT: [[TMP23:%.*]] = or <16 x i16> [[TMP22]], [[TMP5]]86; CHECK-NEXT: [[_MSPROP_SELECT2:%.*]] = select <16 x i1> [[TMP6]], <16 x i16> [[TMP23]], <16 x i16> [[TMP18]]87; CHECK-NEXT: [[RES2:%.*]] = select <16 x i1> [[MSK]], <16 x half> [[T3]], <16 x half> [[SRC]]88; CHECK-NEXT: [[_MSPROP3:%.*]] = or <16 x i16> [[_MSPROP_SELECT]], [[_MSPROP_SELECT2]]89; CHECK-NEXT: [[RES:%.*]] = fadd <16 x half> [[RES1]], [[RES2]]90; CHECK-NEXT: store <16 x i16> [[_MSPROP3]], ptr @__msan_retval_tls, align 891; CHECK-NEXT: ret <16 x half> [[RES]]92;93 %msk = bitcast i16 %mask to <16 x i1>94 %val = load <16 x half>, ptr %ptr95 %res0 = fadd <16 x half> %x1, %x296 %res1 = select <16 x i1> %msk, <16 x half> %res0, <16 x half> %src97 %t3 = fadd <16 x half> %x1, %val98 %res2 = select <16 x i1> %msk, <16 x half> %t3, <16 x half> %src99 %res = fadd <16 x half> %res1 , %res2100 ret <16 x half> %res101}102 103define <16 x half> @test_int_x86_avx512fp16_maskz_add_ph_256(<16 x half> %x1, <16 x half> %x2, i16 %mask, ptr %ptr) #0 {104; CHECK-LABEL: define <16 x half> @test_int_x86_avx512fp16_maskz_add_ph_256(105; CHECK-SAME: <16 x half> [[X1:%.*]], <16 x half> [[X2:%.*]], i16 [[MASK:%.*]], ptr [[PTR:%.*]]) #[[ATTR0]] {106; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 8107; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8108; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8109; CHECK-NEXT: call void @llvm.donothing()110; CHECK-NEXT: [[TMP4:%.*]] = bitcast i16 [[TMP1]] to <16 x i1>111; CHECK-NEXT: [[MSK:%.*]] = bitcast i16 [[MASK]] to <16 x i1>112; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i16> [[TMP2]], [[TMP3]]113; CHECK-NEXT: [[RES0:%.*]] = fadd <16 x half> [[X1]], [[X2]]114; CHECK-NEXT: [[TMP5:%.*]] = select <16 x i1> [[MSK]], <16 x i16> [[_MSPROP]], <16 x i16> zeroinitializer115; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x half> [[RES0]] to <16 x i16>116; CHECK-NEXT: [[TMP7:%.*]] = xor <16 x i16> [[TMP6]], zeroinitializer117; CHECK-NEXT: [[TMP8:%.*]] = or <16 x i16> [[TMP7]], [[_MSPROP]]118; CHECK-NEXT: [[TMP9:%.*]] = or <16 x i16> [[TMP8]], zeroinitializer119; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP4]], <16 x i16> [[TMP9]], <16 x i16> [[TMP5]]120; CHECK-NEXT: [[RES1:%.*]] = select <16 x i1> [[MSK]], <16 x half> [[RES0]], <16 x half> zeroinitializer121; CHECK-NEXT: store <16 x i16> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 8122; CHECK-NEXT: ret <16 x half> [[RES1]]123;124 %msk = bitcast i16 %mask to <16 x i1>125 %res0 = fadd <16 x half> %x1, %x2126 %res1 = select <16 x i1> %msk, <16 x half> %res0, <16 x half> zeroinitializer127 ret <16 x half> %res1128}129 130define <8 x half> @test_int_x86_avx512fp16_add_ph_128(<8 x half> %x1, <8 x half> %x2) #0 {131; CHECK-LABEL: define <8 x half> @test_int_x86_avx512fp16_add_ph_128(132; CHECK-SAME: <8 x half> [[X1:%.*]], <8 x half> [[X2:%.*]]) #[[ATTR0]] {133; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8134; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8135; CHECK-NEXT: call void @llvm.donothing()136; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP1]], [[TMP2]]137; CHECK-NEXT: [[RES:%.*]] = fadd <8 x half> [[X1]], [[X2]]138; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8139; CHECK-NEXT: ret <8 x half> [[RES]]140;141 %res = fadd <8 x half> %x1, %x2142 ret <8 x half> %res143}144 145define <8 x half> @test_int_x86_avx512fp16_mask_add_ph_128(<8 x half> %x1, <8 x half> %x2, <8 x half> %src, i8 %mask, ptr %ptr) #0 {146; CHECK-LABEL: define <8 x half> @test_int_x86_avx512fp16_mask_add_ph_128(147; CHECK-SAME: <8 x half> [[X1:%.*]], <8 x half> [[X2:%.*]], <8 x half> [[SRC:%.*]], i8 [[MASK:%.*]], ptr [[PTR:%.*]]) #[[ATTR0]] {148; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 8149; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 56), align 8150; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8151; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8152; CHECK-NEXT: [[TMP5:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8153; CHECK-NEXT: call void @llvm.donothing()154; CHECK-NEXT: [[TMP6:%.*]] = bitcast i8 [[TMP1]] to <8 x i1>155; CHECK-NEXT: [[MSK:%.*]] = bitcast i8 [[MASK]] to <8 x i1>156; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0157; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]158; CHECK: [[BB7]]:159; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]160; CHECK-NEXT: unreachable161; CHECK: [[BB8]]:162; CHECK-NEXT: [[VAL:%.*]] = load <8 x half>, ptr [[PTR]], align 16163; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[PTR]] to i64164; CHECK-NEXT: [[TMP10:%.*]] = xor i64 [[TMP9]], 87960930222080165; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to ptr166; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP11]], align 16167; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP3]], [[TMP4]]168; CHECK-NEXT: [[RES0:%.*]] = fadd <8 x half> [[X1]], [[X2]]169; CHECK-NEXT: [[TMP12:%.*]] = select <8 x i1> [[MSK]], <8 x i16> [[_MSPROP]], <8 x i16> [[TMP5]]170; CHECK-NEXT: [[TMP13:%.*]] = bitcast <8 x half> [[RES0]] to <8 x i16>171; CHECK-NEXT: [[TMP14:%.*]] = bitcast <8 x half> [[SRC]] to <8 x i16>172; CHECK-NEXT: [[TMP15:%.*]] = xor <8 x i16> [[TMP13]], [[TMP14]]173; CHECK-NEXT: [[TMP16:%.*]] = or <8 x i16> [[TMP15]], [[_MSPROP]]174; CHECK-NEXT: [[TMP17:%.*]] = or <8 x i16> [[TMP16]], [[TMP5]]175; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP6]], <8 x i16> [[TMP17]], <8 x i16> [[TMP12]]176; CHECK-NEXT: [[RES1:%.*]] = select <8 x i1> [[MSK]], <8 x half> [[RES0]], <8 x half> [[SRC]]177; CHECK-NEXT: [[_MSPROP1:%.*]] = or <8 x i16> [[TMP3]], [[_MSLD]]178; CHECK-NEXT: [[T3:%.*]] = fadd <8 x half> [[X1]], [[VAL]]179; CHECK-NEXT: [[TMP18:%.*]] = select <8 x i1> [[MSK]], <8 x i16> [[_MSPROP1]], <8 x i16> [[TMP5]]180; CHECK-NEXT: [[TMP19:%.*]] = bitcast <8 x half> [[T3]] to <8 x i16>181; CHECK-NEXT: [[TMP20:%.*]] = bitcast <8 x half> [[SRC]] to <8 x i16>182; CHECK-NEXT: [[TMP21:%.*]] = xor <8 x i16> [[TMP19]], [[TMP20]]183; CHECK-NEXT: [[TMP22:%.*]] = or <8 x i16> [[TMP21]], [[_MSPROP1]]184; CHECK-NEXT: [[TMP23:%.*]] = or <8 x i16> [[TMP22]], [[TMP5]]185; CHECK-NEXT: [[_MSPROP_SELECT2:%.*]] = select <8 x i1> [[TMP6]], <8 x i16> [[TMP23]], <8 x i16> [[TMP18]]186; CHECK-NEXT: [[RES2:%.*]] = select <8 x i1> [[MSK]], <8 x half> [[T3]], <8 x half> [[SRC]]187; CHECK-NEXT: [[_MSPROP3:%.*]] = or <8 x i16> [[_MSPROP_SELECT]], [[_MSPROP_SELECT2]]188; CHECK-NEXT: [[RES:%.*]] = fadd <8 x half> [[RES1]], [[RES2]]189; CHECK-NEXT: store <8 x i16> [[_MSPROP3]], ptr @__msan_retval_tls, align 8190; CHECK-NEXT: ret <8 x half> [[RES]]191;192 %msk = bitcast i8 %mask to <8 x i1>193 %val = load <8 x half>, ptr %ptr194 %res0 = fadd <8 x half> %x1, %x2195 %res1 = select <8 x i1> %msk, <8 x half> %res0, <8 x half> %src196 %t3 = fadd <8 x half> %x1, %val197 %res2 = select <8 x i1> %msk, <8 x half> %t3, <8 x half> %src198 %res = fadd <8 x half> %res1 , %res2199 ret <8 x half> %res200}201 202define <8 x half> @test_int_x86_avx512fp16_maskz_add_ph_128(<8 x half> %x1, <8 x half> %x2, i8 %mask, ptr %ptr) #0 {203; CHECK-LABEL: define <8 x half> @test_int_x86_avx512fp16_maskz_add_ph_128(204; CHECK-SAME: <8 x half> [[X1:%.*]], <8 x half> [[X2:%.*]], i8 [[MASK:%.*]], ptr [[PTR:%.*]]) #[[ATTR0]] {205; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8206; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8207; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8208; CHECK-NEXT: call void @llvm.donothing()209; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8 [[TMP1]] to <8 x i1>210; CHECK-NEXT: [[MSK:%.*]] = bitcast i8 [[MASK]] to <8 x i1>211; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP2]], [[TMP3]]212; CHECK-NEXT: [[RES0:%.*]] = fadd <8 x half> [[X1]], [[X2]]213; CHECK-NEXT: [[TMP5:%.*]] = select <8 x i1> [[MSK]], <8 x i16> [[_MSPROP]], <8 x i16> zeroinitializer214; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x half> [[RES0]] to <8 x i16>215; CHECK-NEXT: [[TMP7:%.*]] = xor <8 x i16> [[TMP6]], zeroinitializer216; CHECK-NEXT: [[TMP8:%.*]] = or <8 x i16> [[TMP7]], [[_MSPROP]]217; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i16> [[TMP8]], zeroinitializer218; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP4]], <8 x i16> [[TMP9]], <8 x i16> [[TMP5]]219; CHECK-NEXT: [[RES1:%.*]] = select <8 x i1> [[MSK]], <8 x half> [[RES0]], <8 x half> zeroinitializer220; CHECK-NEXT: store <8 x i16> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 8221; CHECK-NEXT: ret <8 x half> [[RES1]]222;223 %msk = bitcast i8 %mask to <8 x i1>224 %res0 = fadd <8 x half> %x1, %x2225 %res1 = select <8 x i1> %msk, <8 x half> %res0, <8 x half> zeroinitializer226 ret <8 x half> %res1227}228 229define <16 x half> @test_int_x86_avx512fp16_sub_ph_256(<16 x half> %x1, <16 x half> %x2) #0 {230; CHECK-LABEL: define <16 x half> @test_int_x86_avx512fp16_sub_ph_256(231; CHECK-SAME: <16 x half> [[X1:%.*]], <16 x half> [[X2:%.*]]) #[[ATTR0]] {232; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8233; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8234; CHECK-NEXT: call void @llvm.donothing()235; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i16> [[TMP1]], [[TMP2]]236; CHECK-NEXT: [[RES:%.*]] = fsub <16 x half> [[X1]], [[X2]]237; CHECK-NEXT: store <16 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8238; CHECK-NEXT: ret <16 x half> [[RES]]239;240 %res = fsub <16 x half> %x1, %x2241 ret <16 x half> %res242}243 244define <16 x half> @test_int_x86_avx512fp16_mask_sub_ph_256(<16 x half> %x1, <16 x half> %x2, <16 x half> %src, i16 %mask, ptr %ptr) #0 {245; CHECK-LABEL: define <16 x half> @test_int_x86_avx512fp16_mask_sub_ph_256(246; CHECK-SAME: <16 x half> [[X1:%.*]], <16 x half> [[X2:%.*]], <16 x half> [[SRC:%.*]], i16 [[MASK:%.*]], ptr [[PTR:%.*]]) #[[ATTR0]] {247; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 8248; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 104), align 8249; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8250; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8251; CHECK-NEXT: [[TMP5:%.*]] = load <16 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 8252; CHECK-NEXT: call void @llvm.donothing()253; CHECK-NEXT: [[TMP6:%.*]] = bitcast i16 [[TMP1]] to <16 x i1>254; CHECK-NEXT: [[MSK:%.*]] = bitcast i16 [[MASK]] to <16 x i1>255; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0256; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]257; CHECK: [[BB7]]:258; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]259; CHECK-NEXT: unreachable260; CHECK: [[BB8]]:261; CHECK-NEXT: [[VAL:%.*]] = load <16 x half>, ptr [[PTR]], align 32262; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[PTR]] to i64263; CHECK-NEXT: [[TMP10:%.*]] = xor i64 [[TMP9]], 87960930222080264; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to ptr265; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i16>, ptr [[TMP11]], align 32266; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i16> [[TMP3]], [[TMP4]]267; CHECK-NEXT: [[RES0:%.*]] = fsub <16 x half> [[X1]], [[X2]]268; CHECK-NEXT: [[TMP12:%.*]] = select <16 x i1> [[MSK]], <16 x i16> [[_MSPROP]], <16 x i16> [[TMP5]]269; CHECK-NEXT: [[TMP13:%.*]] = bitcast <16 x half> [[RES0]] to <16 x i16>270; CHECK-NEXT: [[TMP14:%.*]] = bitcast <16 x half> [[SRC]] to <16 x i16>271; CHECK-NEXT: [[TMP15:%.*]] = xor <16 x i16> [[TMP13]], [[TMP14]]272; CHECK-NEXT: [[TMP16:%.*]] = or <16 x i16> [[TMP15]], [[_MSPROP]]273; CHECK-NEXT: [[TMP17:%.*]] = or <16 x i16> [[TMP16]], [[TMP5]]274; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP6]], <16 x i16> [[TMP17]], <16 x i16> [[TMP12]]275; CHECK-NEXT: [[RES1:%.*]] = select <16 x i1> [[MSK]], <16 x half> [[RES0]], <16 x half> [[SRC]]276; CHECK-NEXT: [[_MSPROP1:%.*]] = or <16 x i16> [[TMP3]], [[_MSLD]]277; CHECK-NEXT: [[T3:%.*]] = fsub <16 x half> [[X1]], [[VAL]]278; CHECK-NEXT: [[TMP18:%.*]] = select <16 x i1> [[MSK]], <16 x i16> [[_MSPROP1]], <16 x i16> [[TMP5]]279; CHECK-NEXT: [[TMP19:%.*]] = bitcast <16 x half> [[T3]] to <16 x i16>280; CHECK-NEXT: [[TMP20:%.*]] = bitcast <16 x half> [[SRC]] to <16 x i16>281; CHECK-NEXT: [[TMP21:%.*]] = xor <16 x i16> [[TMP19]], [[TMP20]]282; CHECK-NEXT: [[TMP22:%.*]] = or <16 x i16> [[TMP21]], [[_MSPROP1]]283; CHECK-NEXT: [[TMP23:%.*]] = or <16 x i16> [[TMP22]], [[TMP5]]284; CHECK-NEXT: [[_MSPROP_SELECT2:%.*]] = select <16 x i1> [[TMP6]], <16 x i16> [[TMP23]], <16 x i16> [[TMP18]]285; CHECK-NEXT: [[RES2:%.*]] = select <16 x i1> [[MSK]], <16 x half> [[T3]], <16 x half> [[SRC]]286; CHECK-NEXT: [[_MSPROP3:%.*]] = or <16 x i16> [[_MSPROP_SELECT]], [[_MSPROP_SELECT2]]287; CHECK-NEXT: [[RES:%.*]] = fsub <16 x half> [[RES1]], [[RES2]]288; CHECK-NEXT: store <16 x i16> [[_MSPROP3]], ptr @__msan_retval_tls, align 8289; CHECK-NEXT: ret <16 x half> [[RES]]290;291 %msk = bitcast i16 %mask to <16 x i1>292 %val = load <16 x half>, ptr %ptr293 %res0 = fsub <16 x half> %x1, %x2294 %res1 = select <16 x i1> %msk, <16 x half> %res0, <16 x half> %src295 %t3 = fsub <16 x half> %x1, %val296 %res2 = select <16 x i1> %msk, <16 x half> %t3, <16 x half> %src297 %res = fsub <16 x half> %res1 , %res2298 ret <16 x half> %res299}300 301define <16 x half> @test_int_x86_avx512fp16_maskz_sub_ph_256(<16 x half> %x1, <16 x half> %x2, i16 %mask, ptr %ptr) #0 {302; CHECK-LABEL: define <16 x half> @test_int_x86_avx512fp16_maskz_sub_ph_256(303; CHECK-SAME: <16 x half> [[X1:%.*]], <16 x half> [[X2:%.*]], i16 [[MASK:%.*]], ptr [[PTR:%.*]]) #[[ATTR0]] {304; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 8305; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8306; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8307; CHECK-NEXT: call void @llvm.donothing()308; CHECK-NEXT: [[TMP4:%.*]] = bitcast i16 [[TMP1]] to <16 x i1>309; CHECK-NEXT: [[MSK:%.*]] = bitcast i16 [[MASK]] to <16 x i1>310; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i16> [[TMP2]], [[TMP3]]311; CHECK-NEXT: [[RES0:%.*]] = fsub <16 x half> [[X1]], [[X2]]312; CHECK-NEXT: [[TMP5:%.*]] = select <16 x i1> [[MSK]], <16 x i16> [[_MSPROP]], <16 x i16> zeroinitializer313; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x half> [[RES0]] to <16 x i16>314; CHECK-NEXT: [[TMP7:%.*]] = xor <16 x i16> [[TMP6]], zeroinitializer315; CHECK-NEXT: [[TMP8:%.*]] = or <16 x i16> [[TMP7]], [[_MSPROP]]316; CHECK-NEXT: [[TMP9:%.*]] = or <16 x i16> [[TMP8]], zeroinitializer317; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP4]], <16 x i16> [[TMP9]], <16 x i16> [[TMP5]]318; CHECK-NEXT: [[RES1:%.*]] = select <16 x i1> [[MSK]], <16 x half> [[RES0]], <16 x half> zeroinitializer319; CHECK-NEXT: store <16 x i16> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 8320; CHECK-NEXT: ret <16 x half> [[RES1]]321;322 %msk = bitcast i16 %mask to <16 x i1>323 %res0 = fsub <16 x half> %x1, %x2324 %res1 = select <16 x i1> %msk, <16 x half> %res0, <16 x half> zeroinitializer325 ret <16 x half> %res1326}327 328define <8 x half> @test_int_x86_avx512fp16_sub_ph_128(<8 x half> %x1, <8 x half> %x2) #0 {329; CHECK-LABEL: define <8 x half> @test_int_x86_avx512fp16_sub_ph_128(330; CHECK-SAME: <8 x half> [[X1:%.*]], <8 x half> [[X2:%.*]]) #[[ATTR0]] {331; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8332; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8333; CHECK-NEXT: call void @llvm.donothing()334; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP1]], [[TMP2]]335; CHECK-NEXT: [[RES:%.*]] = fsub <8 x half> [[X1]], [[X2]]336; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8337; CHECK-NEXT: ret <8 x half> [[RES]]338;339 %res = fsub <8 x half> %x1, %x2340 ret <8 x half> %res341}342 343define <8 x half> @test_int_x86_avx512fp16_mask_sub_ph_128(<8 x half> %x1, <8 x half> %x2, <8 x half> %src, i8 %mask, ptr %ptr) #0 {344; CHECK-LABEL: define <8 x half> @test_int_x86_avx512fp16_mask_sub_ph_128(345; CHECK-SAME: <8 x half> [[X1:%.*]], <8 x half> [[X2:%.*]], <8 x half> [[SRC:%.*]], i8 [[MASK:%.*]], ptr [[PTR:%.*]]) #[[ATTR0]] {346; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 8347; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 56), align 8348; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8349; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8350; CHECK-NEXT: [[TMP5:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8351; CHECK-NEXT: call void @llvm.donothing()352; CHECK-NEXT: [[TMP6:%.*]] = bitcast i8 [[TMP1]] to <8 x i1>353; CHECK-NEXT: [[MSK:%.*]] = bitcast i8 [[MASK]] to <8 x i1>354; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0355; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]356; CHECK: [[BB7]]:357; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]358; CHECK-NEXT: unreachable359; CHECK: [[BB8]]:360; CHECK-NEXT: [[VAL:%.*]] = load <8 x half>, ptr [[PTR]], align 16361; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[PTR]] to i64362; CHECK-NEXT: [[TMP10:%.*]] = xor i64 [[TMP9]], 87960930222080363; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to ptr364; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP11]], align 16365; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP3]], [[TMP4]]366; CHECK-NEXT: [[RES0:%.*]] = fsub <8 x half> [[X1]], [[X2]]367; CHECK-NEXT: [[TMP12:%.*]] = select <8 x i1> [[MSK]], <8 x i16> [[_MSPROP]], <8 x i16> [[TMP5]]368; CHECK-NEXT: [[TMP13:%.*]] = bitcast <8 x half> [[RES0]] to <8 x i16>369; CHECK-NEXT: [[TMP14:%.*]] = bitcast <8 x half> [[SRC]] to <8 x i16>370; CHECK-NEXT: [[TMP15:%.*]] = xor <8 x i16> [[TMP13]], [[TMP14]]371; CHECK-NEXT: [[TMP16:%.*]] = or <8 x i16> [[TMP15]], [[_MSPROP]]372; CHECK-NEXT: [[TMP17:%.*]] = or <8 x i16> [[TMP16]], [[TMP5]]373; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP6]], <8 x i16> [[TMP17]], <8 x i16> [[TMP12]]374; CHECK-NEXT: [[RES1:%.*]] = select <8 x i1> [[MSK]], <8 x half> [[RES0]], <8 x half> [[SRC]]375; CHECK-NEXT: [[_MSPROP1:%.*]] = or <8 x i16> [[TMP3]], [[_MSLD]]376; CHECK-NEXT: [[T3:%.*]] = fsub <8 x half> [[X1]], [[VAL]]377; CHECK-NEXT: [[TMP18:%.*]] = select <8 x i1> [[MSK]], <8 x i16> [[_MSPROP1]], <8 x i16> [[TMP5]]378; CHECK-NEXT: [[TMP19:%.*]] = bitcast <8 x half> [[T3]] to <8 x i16>379; CHECK-NEXT: [[TMP20:%.*]] = bitcast <8 x half> [[SRC]] to <8 x i16>380; CHECK-NEXT: [[TMP21:%.*]] = xor <8 x i16> [[TMP19]], [[TMP20]]381; CHECK-NEXT: [[TMP22:%.*]] = or <8 x i16> [[TMP21]], [[_MSPROP1]]382; CHECK-NEXT: [[TMP23:%.*]] = or <8 x i16> [[TMP22]], [[TMP5]]383; CHECK-NEXT: [[_MSPROP_SELECT2:%.*]] = select <8 x i1> [[TMP6]], <8 x i16> [[TMP23]], <8 x i16> [[TMP18]]384; CHECK-NEXT: [[RES2:%.*]] = select <8 x i1> [[MSK]], <8 x half> [[T3]], <8 x half> [[SRC]]385; CHECK-NEXT: [[_MSPROP3:%.*]] = or <8 x i16> [[_MSPROP_SELECT]], [[_MSPROP_SELECT2]]386; CHECK-NEXT: [[RES:%.*]] = fsub <8 x half> [[RES1]], [[RES2]]387; CHECK-NEXT: store <8 x i16> [[_MSPROP3]], ptr @__msan_retval_tls, align 8388; CHECK-NEXT: ret <8 x half> [[RES]]389;390 %msk = bitcast i8 %mask to <8 x i1>391 %val = load <8 x half>, ptr %ptr392 %res0 = fsub <8 x half> %x1, %x2393 %res1 = select <8 x i1> %msk, <8 x half> %res0, <8 x half> %src394 %t3 = fsub <8 x half> %x1, %val395 %res2 = select <8 x i1> %msk, <8 x half> %t3, <8 x half> %src396 %res = fsub <8 x half> %res1 , %res2397 ret <8 x half> %res398}399 400define <8 x half> @test_int_x86_avx512fp16_maskz_sub_ph_128(<8 x half> %x1, <8 x half> %x2, i8 %mask, ptr %ptr) #0 {401; CHECK-LABEL: define <8 x half> @test_int_x86_avx512fp16_maskz_sub_ph_128(402; CHECK-SAME: <8 x half> [[X1:%.*]], <8 x half> [[X2:%.*]], i8 [[MASK:%.*]], ptr [[PTR:%.*]]) #[[ATTR0]] {403; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8404; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8405; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8406; CHECK-NEXT: call void @llvm.donothing()407; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8 [[TMP1]] to <8 x i1>408; CHECK-NEXT: [[MSK:%.*]] = bitcast i8 [[MASK]] to <8 x i1>409; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP2]], [[TMP3]]410; CHECK-NEXT: [[RES0:%.*]] = fsub <8 x half> [[X1]], [[X2]]411; CHECK-NEXT: [[TMP5:%.*]] = select <8 x i1> [[MSK]], <8 x i16> [[_MSPROP]], <8 x i16> zeroinitializer412; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x half> [[RES0]] to <8 x i16>413; CHECK-NEXT: [[TMP7:%.*]] = xor <8 x i16> [[TMP6]], zeroinitializer414; CHECK-NEXT: [[TMP8:%.*]] = or <8 x i16> [[TMP7]], [[_MSPROP]]415; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i16> [[TMP8]], zeroinitializer416; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP4]], <8 x i16> [[TMP9]], <8 x i16> [[TMP5]]417; CHECK-NEXT: [[RES1:%.*]] = select <8 x i1> [[MSK]], <8 x half> [[RES0]], <8 x half> zeroinitializer418; CHECK-NEXT: store <8 x i16> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 8419; CHECK-NEXT: ret <8 x half> [[RES1]]420;421 %msk = bitcast i8 %mask to <8 x i1>422 %res0 = fsub <8 x half> %x1, %x2423 %res1 = select <8 x i1> %msk, <8 x half> %res0, <8 x half> zeroinitializer424 ret <8 x half> %res1425}426 427define <16 x half> @test_int_x86_avx512fp16_mul_ph_256(<16 x half> %x1, <16 x half> %x2) #0 {428; CHECK-LABEL: define <16 x half> @test_int_x86_avx512fp16_mul_ph_256(429; CHECK-SAME: <16 x half> [[X1:%.*]], <16 x half> [[X2:%.*]]) #[[ATTR0]] {430; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8431; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8432; CHECK-NEXT: call void @llvm.donothing()433; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i16> [[TMP1]], [[TMP2]]434; CHECK-NEXT: [[RES:%.*]] = fmul <16 x half> [[X1]], [[X2]]435; CHECK-NEXT: store <16 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8436; CHECK-NEXT: ret <16 x half> [[RES]]437;438 %res = fmul <16 x half> %x1, %x2439 ret <16 x half> %res440}441 442define <16 x half> @test_int_x86_avx512fp16_mask_mul_ph_256(<16 x half> %x1, <16 x half> %x2, <16 x half> %src, i16 %mask, ptr %ptr) #0 {443; CHECK-LABEL: define <16 x half> @test_int_x86_avx512fp16_mask_mul_ph_256(444; CHECK-SAME: <16 x half> [[X1:%.*]], <16 x half> [[X2:%.*]], <16 x half> [[SRC:%.*]], i16 [[MASK:%.*]], ptr [[PTR:%.*]]) #[[ATTR0]] {445; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 8446; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 104), align 8447; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8448; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8449; CHECK-NEXT: [[TMP5:%.*]] = load <16 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 8450; CHECK-NEXT: call void @llvm.donothing()451; CHECK-NEXT: [[TMP6:%.*]] = bitcast i16 [[TMP1]] to <16 x i1>452; CHECK-NEXT: [[MSK:%.*]] = bitcast i16 [[MASK]] to <16 x i1>453; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0454; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]455; CHECK: [[BB7]]:456; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]457; CHECK-NEXT: unreachable458; CHECK: [[BB8]]:459; CHECK-NEXT: [[VAL:%.*]] = load <16 x half>, ptr [[PTR]], align 32460; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[PTR]] to i64461; CHECK-NEXT: [[TMP10:%.*]] = xor i64 [[TMP9]], 87960930222080462; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to ptr463; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i16>, ptr [[TMP11]], align 32464; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i16> [[TMP3]], [[TMP4]]465; CHECK-NEXT: [[RES0:%.*]] = fmul <16 x half> [[X1]], [[X2]]466; CHECK-NEXT: [[TMP12:%.*]] = select <16 x i1> [[MSK]], <16 x i16> [[_MSPROP]], <16 x i16> [[TMP5]]467; CHECK-NEXT: [[TMP13:%.*]] = bitcast <16 x half> [[RES0]] to <16 x i16>468; CHECK-NEXT: [[TMP14:%.*]] = bitcast <16 x half> [[SRC]] to <16 x i16>469; CHECK-NEXT: [[TMP15:%.*]] = xor <16 x i16> [[TMP13]], [[TMP14]]470; CHECK-NEXT: [[TMP16:%.*]] = or <16 x i16> [[TMP15]], [[_MSPROP]]471; CHECK-NEXT: [[TMP17:%.*]] = or <16 x i16> [[TMP16]], [[TMP5]]472; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP6]], <16 x i16> [[TMP17]], <16 x i16> [[TMP12]]473; CHECK-NEXT: [[RES1:%.*]] = select <16 x i1> [[MSK]], <16 x half> [[RES0]], <16 x half> [[SRC]]474; CHECK-NEXT: [[_MSPROP1:%.*]] = or <16 x i16> [[TMP3]], [[_MSLD]]475; CHECK-NEXT: [[T3:%.*]] = fmul <16 x half> [[X1]], [[VAL]]476; CHECK-NEXT: [[TMP18:%.*]] = select <16 x i1> [[MSK]], <16 x i16> [[_MSPROP1]], <16 x i16> [[TMP5]]477; CHECK-NEXT: [[TMP19:%.*]] = bitcast <16 x half> [[T3]] to <16 x i16>478; CHECK-NEXT: [[TMP20:%.*]] = bitcast <16 x half> [[SRC]] to <16 x i16>479; CHECK-NEXT: [[TMP21:%.*]] = xor <16 x i16> [[TMP19]], [[TMP20]]480; CHECK-NEXT: [[TMP22:%.*]] = or <16 x i16> [[TMP21]], [[_MSPROP1]]481; CHECK-NEXT: [[TMP23:%.*]] = or <16 x i16> [[TMP22]], [[TMP5]]482; CHECK-NEXT: [[_MSPROP_SELECT2:%.*]] = select <16 x i1> [[TMP6]], <16 x i16> [[TMP23]], <16 x i16> [[TMP18]]483; CHECK-NEXT: [[RES2:%.*]] = select <16 x i1> [[MSK]], <16 x half> [[T3]], <16 x half> [[SRC]]484; CHECK-NEXT: [[_MSPROP3:%.*]] = or <16 x i16> [[_MSPROP_SELECT]], [[_MSPROP_SELECT2]]485; CHECK-NEXT: [[RES:%.*]] = fmul <16 x half> [[RES1]], [[RES2]]486; CHECK-NEXT: store <16 x i16> [[_MSPROP3]], ptr @__msan_retval_tls, align 8487; CHECK-NEXT: ret <16 x half> [[RES]]488;489 %msk = bitcast i16 %mask to <16 x i1>490 %val = load <16 x half>, ptr %ptr491 %res0 = fmul <16 x half> %x1, %x2492 %res1 = select <16 x i1> %msk, <16 x half> %res0, <16 x half> %src493 %t3 = fmul <16 x half> %x1, %val494 %res2 = select <16 x i1> %msk, <16 x half> %t3, <16 x half> %src495 %res = fmul <16 x half> %res1 , %res2496 ret <16 x half> %res497}498 499define <16 x half> @test_int_x86_avx512fp16_maskz_mul_ph_256(<16 x half> %x1, <16 x half> %x2, i16 %mask, ptr %ptr) #0 {500; CHECK-LABEL: define <16 x half> @test_int_x86_avx512fp16_maskz_mul_ph_256(501; CHECK-SAME: <16 x half> [[X1:%.*]], <16 x half> [[X2:%.*]], i16 [[MASK:%.*]], ptr [[PTR:%.*]]) #[[ATTR0]] {502; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 8503; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8504; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8505; CHECK-NEXT: call void @llvm.donothing()506; CHECK-NEXT: [[TMP4:%.*]] = bitcast i16 [[TMP1]] to <16 x i1>507; CHECK-NEXT: [[MSK:%.*]] = bitcast i16 [[MASK]] to <16 x i1>508; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i16> [[TMP2]], [[TMP3]]509; CHECK-NEXT: [[RES0:%.*]] = fmul <16 x half> [[X1]], [[X2]]510; CHECK-NEXT: [[TMP5:%.*]] = select <16 x i1> [[MSK]], <16 x i16> [[_MSPROP]], <16 x i16> zeroinitializer511; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x half> [[RES0]] to <16 x i16>512; CHECK-NEXT: [[TMP7:%.*]] = xor <16 x i16> [[TMP6]], zeroinitializer513; CHECK-NEXT: [[TMP8:%.*]] = or <16 x i16> [[TMP7]], [[_MSPROP]]514; CHECK-NEXT: [[TMP9:%.*]] = or <16 x i16> [[TMP8]], zeroinitializer515; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP4]], <16 x i16> [[TMP9]], <16 x i16> [[TMP5]]516; CHECK-NEXT: [[RES1:%.*]] = select <16 x i1> [[MSK]], <16 x half> [[RES0]], <16 x half> zeroinitializer517; CHECK-NEXT: store <16 x i16> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 8518; CHECK-NEXT: ret <16 x half> [[RES1]]519;520 %msk = bitcast i16 %mask to <16 x i1>521 %res0 = fmul <16 x half> %x1, %x2522 %res1 = select <16 x i1> %msk, <16 x half> %res0, <16 x half> zeroinitializer523 ret <16 x half> %res1524}525 526define <8 x half> @test_int_x86_avx512fp16_mul_ph_128(<8 x half> %x1, <8 x half> %x2) #0 {527; CHECK-LABEL: define <8 x half> @test_int_x86_avx512fp16_mul_ph_128(528; CHECK-SAME: <8 x half> [[X1:%.*]], <8 x half> [[X2:%.*]]) #[[ATTR0]] {529; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8530; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8531; CHECK-NEXT: call void @llvm.donothing()532; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP1]], [[TMP2]]533; CHECK-NEXT: [[RES:%.*]] = fmul <8 x half> [[X1]], [[X2]]534; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8535; CHECK-NEXT: ret <8 x half> [[RES]]536;537 %res = fmul <8 x half> %x1, %x2538 ret <8 x half> %res539}540 541define <8 x half> @test_int_x86_avx512fp16_mask_mul_ph_128(<8 x half> %x1, <8 x half> %x2, <8 x half> %src, i8 %mask, ptr %ptr) #0 {542; CHECK-LABEL: define <8 x half> @test_int_x86_avx512fp16_mask_mul_ph_128(543; CHECK-SAME: <8 x half> [[X1:%.*]], <8 x half> [[X2:%.*]], <8 x half> [[SRC:%.*]], i8 [[MASK:%.*]], ptr [[PTR:%.*]]) #[[ATTR0]] {544; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 8545; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 56), align 8546; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8547; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8548; CHECK-NEXT: [[TMP5:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8549; CHECK-NEXT: call void @llvm.donothing()550; CHECK-NEXT: [[TMP6:%.*]] = bitcast i8 [[TMP1]] to <8 x i1>551; CHECK-NEXT: [[MSK:%.*]] = bitcast i8 [[MASK]] to <8 x i1>552; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0553; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]554; CHECK: [[BB7]]:555; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]556; CHECK-NEXT: unreachable557; CHECK: [[BB8]]:558; CHECK-NEXT: [[VAL:%.*]] = load <8 x half>, ptr [[PTR]], align 16559; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[PTR]] to i64560; CHECK-NEXT: [[TMP10:%.*]] = xor i64 [[TMP9]], 87960930222080561; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to ptr562; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP11]], align 16563; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP3]], [[TMP4]]564; CHECK-NEXT: [[RES0:%.*]] = fmul <8 x half> [[X1]], [[X2]]565; CHECK-NEXT: [[TMP12:%.*]] = select <8 x i1> [[MSK]], <8 x i16> [[_MSPROP]], <8 x i16> [[TMP5]]566; CHECK-NEXT: [[TMP13:%.*]] = bitcast <8 x half> [[RES0]] to <8 x i16>567; CHECK-NEXT: [[TMP14:%.*]] = bitcast <8 x half> [[SRC]] to <8 x i16>568; CHECK-NEXT: [[TMP15:%.*]] = xor <8 x i16> [[TMP13]], [[TMP14]]569; CHECK-NEXT: [[TMP16:%.*]] = or <8 x i16> [[TMP15]], [[_MSPROP]]570; CHECK-NEXT: [[TMP17:%.*]] = or <8 x i16> [[TMP16]], [[TMP5]]571; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP6]], <8 x i16> [[TMP17]], <8 x i16> [[TMP12]]572; CHECK-NEXT: [[RES1:%.*]] = select <8 x i1> [[MSK]], <8 x half> [[RES0]], <8 x half> [[SRC]]573; CHECK-NEXT: [[_MSPROP1:%.*]] = or <8 x i16> [[TMP3]], [[_MSLD]]574; CHECK-NEXT: [[T3:%.*]] = fmul <8 x half> [[X1]], [[VAL]]575; CHECK-NEXT: [[TMP18:%.*]] = select <8 x i1> [[MSK]], <8 x i16> [[_MSPROP1]], <8 x i16> [[TMP5]]576; CHECK-NEXT: [[TMP19:%.*]] = bitcast <8 x half> [[T3]] to <8 x i16>577; CHECK-NEXT: [[TMP20:%.*]] = bitcast <8 x half> [[SRC]] to <8 x i16>578; CHECK-NEXT: [[TMP21:%.*]] = xor <8 x i16> [[TMP19]], [[TMP20]]579; CHECK-NEXT: [[TMP22:%.*]] = or <8 x i16> [[TMP21]], [[_MSPROP1]]580; CHECK-NEXT: [[TMP23:%.*]] = or <8 x i16> [[TMP22]], [[TMP5]]581; CHECK-NEXT: [[_MSPROP_SELECT2:%.*]] = select <8 x i1> [[TMP6]], <8 x i16> [[TMP23]], <8 x i16> [[TMP18]]582; CHECK-NEXT: [[RES2:%.*]] = select <8 x i1> [[MSK]], <8 x half> [[T3]], <8 x half> [[SRC]]583; CHECK-NEXT: [[_MSPROP3:%.*]] = or <8 x i16> [[_MSPROP_SELECT]], [[_MSPROP_SELECT2]]584; CHECK-NEXT: [[RES:%.*]] = fmul <8 x half> [[RES1]], [[RES2]]585; CHECK-NEXT: store <8 x i16> [[_MSPROP3]], ptr @__msan_retval_tls, align 8586; CHECK-NEXT: ret <8 x half> [[RES]]587;588 %msk = bitcast i8 %mask to <8 x i1>589 %val = load <8 x half>, ptr %ptr590 %res0 = fmul <8 x half> %x1, %x2591 %res1 = select <8 x i1> %msk, <8 x half> %res0, <8 x half> %src592 %t3 = fmul <8 x half> %x1, %val593 %res2 = select <8 x i1> %msk, <8 x half> %t3, <8 x half> %src594 %res = fmul <8 x half> %res1 , %res2595 ret <8 x half> %res596}597 598define <8 x half> @test_int_x86_avx512fp16_maskz_mul_ph_128(<8 x half> %x1, <8 x half> %x2, i8 %mask, ptr %ptr) #0 {599; CHECK-LABEL: define <8 x half> @test_int_x86_avx512fp16_maskz_mul_ph_128(600; CHECK-SAME: <8 x half> [[X1:%.*]], <8 x half> [[X2:%.*]], i8 [[MASK:%.*]], ptr [[PTR:%.*]]) #[[ATTR0]] {601; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8602; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8603; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8604; CHECK-NEXT: call void @llvm.donothing()605; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8 [[TMP1]] to <8 x i1>606; CHECK-NEXT: [[MSK:%.*]] = bitcast i8 [[MASK]] to <8 x i1>607; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP2]], [[TMP3]]608; CHECK-NEXT: [[RES0:%.*]] = fmul <8 x half> [[X1]], [[X2]]609; CHECK-NEXT: [[TMP5:%.*]] = select <8 x i1> [[MSK]], <8 x i16> [[_MSPROP]], <8 x i16> zeroinitializer610; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x half> [[RES0]] to <8 x i16>611; CHECK-NEXT: [[TMP7:%.*]] = xor <8 x i16> [[TMP6]], zeroinitializer612; CHECK-NEXT: [[TMP8:%.*]] = or <8 x i16> [[TMP7]], [[_MSPROP]]613; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i16> [[TMP8]], zeroinitializer614; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP4]], <8 x i16> [[TMP9]], <8 x i16> [[TMP5]]615; CHECK-NEXT: [[RES1:%.*]] = select <8 x i1> [[MSK]], <8 x half> [[RES0]], <8 x half> zeroinitializer616; CHECK-NEXT: store <8 x i16> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 8617; CHECK-NEXT: ret <8 x half> [[RES1]]618;619 %msk = bitcast i8 %mask to <8 x i1>620 %res0 = fmul <8 x half> %x1, %x2621 %res1 = select <8 x i1> %msk, <8 x half> %res0, <8 x half> zeroinitializer622 ret <8 x half> %res1623}624 625define <16 x half> @test_int_x86_avx512fp16_div_ph_256(<16 x half> %x1, <16 x half> %x2) #0 {626; CHECK-LABEL: define <16 x half> @test_int_x86_avx512fp16_div_ph_256(627; CHECK-SAME: <16 x half> [[X1:%.*]], <16 x half> [[X2:%.*]]) #[[ATTR0]] {628; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8629; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8630; CHECK-NEXT: call void @llvm.donothing()631; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i16> [[TMP1]], [[TMP2]]632; CHECK-NEXT: [[RES:%.*]] = fdiv <16 x half> [[X1]], [[X2]]633; CHECK-NEXT: store <16 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8634; CHECK-NEXT: ret <16 x half> [[RES]]635;636 %res = fdiv <16 x half> %x1, %x2637 ret <16 x half> %res638}639 640define <16 x half> @test_int_x86_avx512fp16_div_ph_256_fast(<16 x half> %x1, <16 x half> %x2) #0 {641; CHECK-LABEL: define <16 x half> @test_int_x86_avx512fp16_div_ph_256_fast(642; CHECK-SAME: <16 x half> [[X1:%.*]], <16 x half> [[X2:%.*]]) #[[ATTR0]] {643; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8644; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8645; CHECK-NEXT: call void @llvm.donothing()646; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i16> [[TMP1]], [[TMP2]]647; CHECK-NEXT: [[RES:%.*]] = fdiv fast <16 x half> [[X1]], [[X2]]648; CHECK-NEXT: store <16 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8649; CHECK-NEXT: ret <16 x half> [[RES]]650;651 %res = fdiv fast <16 x half> %x1, %x2652 ret <16 x half> %res653}654 655define <16 x half> @test_int_x86_avx512fp16_mask_div_ph_256(<16 x half> %x1, <16 x half> %x2, <16 x half> %src, i16 %mask, ptr %ptr) #0 {656; CHECK-LABEL: define <16 x half> @test_int_x86_avx512fp16_mask_div_ph_256(657; CHECK-SAME: <16 x half> [[X1:%.*]], <16 x half> [[X2:%.*]], <16 x half> [[SRC:%.*]], i16 [[MASK:%.*]], ptr [[PTR:%.*]]) #[[ATTR0]] {658; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 8659; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 104), align 8660; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8661; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8662; CHECK-NEXT: [[TMP5:%.*]] = load <16 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 8663; CHECK-NEXT: call void @llvm.donothing()664; CHECK-NEXT: [[TMP6:%.*]] = bitcast i16 [[TMP1]] to <16 x i1>665; CHECK-NEXT: [[MSK:%.*]] = bitcast i16 [[MASK]] to <16 x i1>666; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0667; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]668; CHECK: [[BB7]]:669; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]670; CHECK-NEXT: unreachable671; CHECK: [[BB8]]:672; CHECK-NEXT: [[VAL:%.*]] = load <16 x half>, ptr [[PTR]], align 32673; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[PTR]] to i64674; CHECK-NEXT: [[TMP10:%.*]] = xor i64 [[TMP9]], 87960930222080675; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to ptr676; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i16>, ptr [[TMP11]], align 32677; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i16> [[TMP3]], [[TMP4]]678; CHECK-NEXT: [[RES0:%.*]] = fdiv <16 x half> [[X1]], [[X2]]679; CHECK-NEXT: [[TMP12:%.*]] = select <16 x i1> [[MSK]], <16 x i16> [[_MSPROP]], <16 x i16> [[TMP5]]680; CHECK-NEXT: [[TMP13:%.*]] = bitcast <16 x half> [[RES0]] to <16 x i16>681; CHECK-NEXT: [[TMP14:%.*]] = bitcast <16 x half> [[SRC]] to <16 x i16>682; CHECK-NEXT: [[TMP15:%.*]] = xor <16 x i16> [[TMP13]], [[TMP14]]683; CHECK-NEXT: [[TMP16:%.*]] = or <16 x i16> [[TMP15]], [[_MSPROP]]684; CHECK-NEXT: [[TMP17:%.*]] = or <16 x i16> [[TMP16]], [[TMP5]]685; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP6]], <16 x i16> [[TMP17]], <16 x i16> [[TMP12]]686; CHECK-NEXT: [[RES1:%.*]] = select <16 x i1> [[MSK]], <16 x half> [[RES0]], <16 x half> [[SRC]]687; CHECK-NEXT: [[_MSPROP1:%.*]] = or <16 x i16> [[TMP3]], [[_MSLD]]688; CHECK-NEXT: [[T3:%.*]] = fdiv <16 x half> [[X1]], [[VAL]]689; CHECK-NEXT: [[TMP18:%.*]] = select <16 x i1> [[MSK]], <16 x i16> [[_MSPROP1]], <16 x i16> [[TMP5]]690; CHECK-NEXT: [[TMP19:%.*]] = bitcast <16 x half> [[T3]] to <16 x i16>691; CHECK-NEXT: [[TMP20:%.*]] = bitcast <16 x half> [[SRC]] to <16 x i16>692; CHECK-NEXT: [[TMP21:%.*]] = xor <16 x i16> [[TMP19]], [[TMP20]]693; CHECK-NEXT: [[TMP22:%.*]] = or <16 x i16> [[TMP21]], [[_MSPROP1]]694; CHECK-NEXT: [[TMP23:%.*]] = or <16 x i16> [[TMP22]], [[TMP5]]695; CHECK-NEXT: [[_MSPROP_SELECT2:%.*]] = select <16 x i1> [[TMP6]], <16 x i16> [[TMP23]], <16 x i16> [[TMP18]]696; CHECK-NEXT: [[RES2:%.*]] = select <16 x i1> [[MSK]], <16 x half> [[T3]], <16 x half> [[SRC]]697; CHECK-NEXT: [[_MSPROP3:%.*]] = or <16 x i16> [[_MSPROP_SELECT]], [[_MSPROP_SELECT2]]698; CHECK-NEXT: [[RES:%.*]] = fdiv <16 x half> [[RES1]], [[RES2]]699; CHECK-NEXT: store <16 x i16> [[_MSPROP3]], ptr @__msan_retval_tls, align 8700; CHECK-NEXT: ret <16 x half> [[RES]]701;702 %msk = bitcast i16 %mask to <16 x i1>703 %val = load <16 x half>, ptr %ptr704 %res0 = fdiv <16 x half> %x1, %x2705 %res1 = select <16 x i1> %msk, <16 x half> %res0, <16 x half> %src706 %t3 = fdiv <16 x half> %x1, %val707 %res2 = select <16 x i1> %msk, <16 x half> %t3, <16 x half> %src708 %res = fdiv <16 x half> %res1 , %res2709 ret <16 x half> %res710}711 712define <16 x half> @test_int_x86_avx512fp16_maskz_div_ph_256(<16 x half> %x1, <16 x half> %x2, i16 %mask, ptr %ptr) #0 {713; CHECK-LABEL: define <16 x half> @test_int_x86_avx512fp16_maskz_div_ph_256(714; CHECK-SAME: <16 x half> [[X1:%.*]], <16 x half> [[X2:%.*]], i16 [[MASK:%.*]], ptr [[PTR:%.*]]) #[[ATTR0]] {715; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 8716; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8717; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8718; CHECK-NEXT: call void @llvm.donothing()719; CHECK-NEXT: [[TMP4:%.*]] = bitcast i16 [[TMP1]] to <16 x i1>720; CHECK-NEXT: [[MSK:%.*]] = bitcast i16 [[MASK]] to <16 x i1>721; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i16> [[TMP2]], [[TMP3]]722; CHECK-NEXT: [[RES0:%.*]] = fdiv <16 x half> [[X1]], [[X2]]723; CHECK-NEXT: [[TMP5:%.*]] = select <16 x i1> [[MSK]], <16 x i16> [[_MSPROP]], <16 x i16> zeroinitializer724; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x half> [[RES0]] to <16 x i16>725; CHECK-NEXT: [[TMP7:%.*]] = xor <16 x i16> [[TMP6]], zeroinitializer726; CHECK-NEXT: [[TMP8:%.*]] = or <16 x i16> [[TMP7]], [[_MSPROP]]727; CHECK-NEXT: [[TMP9:%.*]] = or <16 x i16> [[TMP8]], zeroinitializer728; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP4]], <16 x i16> [[TMP9]], <16 x i16> [[TMP5]]729; CHECK-NEXT: [[RES1:%.*]] = select <16 x i1> [[MSK]], <16 x half> [[RES0]], <16 x half> zeroinitializer730; CHECK-NEXT: store <16 x i16> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 8731; CHECK-NEXT: ret <16 x half> [[RES1]]732;733 %msk = bitcast i16 %mask to <16 x i1>734 %res0 = fdiv <16 x half> %x1, %x2735 %res1 = select <16 x i1> %msk, <16 x half> %res0, <16 x half> zeroinitializer736 ret <16 x half> %res1737}738 739define <8 x half> @test_int_x86_avx512fp16_div_ph_128(<8 x half> %x1, <8 x half> %x2) #0 {740; CHECK-LABEL: define <8 x half> @test_int_x86_avx512fp16_div_ph_128(741; CHECK-SAME: <8 x half> [[X1:%.*]], <8 x half> [[X2:%.*]]) #[[ATTR0]] {742; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8743; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8744; CHECK-NEXT: call void @llvm.donothing()745; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP1]], [[TMP2]]746; CHECK-NEXT: [[RES:%.*]] = fdiv <8 x half> [[X1]], [[X2]]747; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8748; CHECK-NEXT: ret <8 x half> [[RES]]749;750 %res = fdiv <8 x half> %x1, %x2751 ret <8 x half> %res752}753 754define <8 x half> @test_int_x86_avx512fp16_div_ph_128_fast(<8 x half> %x1, <8 x half> %x2) #0 {755; CHECK-LABEL: define <8 x half> @test_int_x86_avx512fp16_div_ph_128_fast(756; CHECK-SAME: <8 x half> [[X1:%.*]], <8 x half> [[X2:%.*]]) #[[ATTR0]] {757; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8758; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8759; CHECK-NEXT: call void @llvm.donothing()760; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP1]], [[TMP2]]761; CHECK-NEXT: [[RES:%.*]] = fdiv fast <8 x half> [[X1]], [[X2]]762; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8763; CHECK-NEXT: ret <8 x half> [[RES]]764;765 %res = fdiv fast <8 x half> %x1, %x2766 ret <8 x half> %res767}768 769define <8 x half> @test_int_x86_avx512fp16_mask_div_ph_128(<8 x half> %x1, <8 x half> %x2, <8 x half> %src, i8 %mask, ptr %ptr) #0 {770; CHECK-LABEL: define <8 x half> @test_int_x86_avx512fp16_mask_div_ph_128(771; CHECK-SAME: <8 x half> [[X1:%.*]], <8 x half> [[X2:%.*]], <8 x half> [[SRC:%.*]], i8 [[MASK:%.*]], ptr [[PTR:%.*]]) #[[ATTR0]] {772; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 8773; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 56), align 8774; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8775; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8776; CHECK-NEXT: [[TMP5:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8777; CHECK-NEXT: call void @llvm.donothing()778; CHECK-NEXT: [[TMP6:%.*]] = bitcast i8 [[TMP1]] to <8 x i1>779; CHECK-NEXT: [[MSK:%.*]] = bitcast i8 [[MASK]] to <8 x i1>780; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0781; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]782; CHECK: [[BB7]]:783; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]784; CHECK-NEXT: unreachable785; CHECK: [[BB8]]:786; CHECK-NEXT: [[VAL:%.*]] = load <8 x half>, ptr [[PTR]], align 16787; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[PTR]] to i64788; CHECK-NEXT: [[TMP10:%.*]] = xor i64 [[TMP9]], 87960930222080789; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to ptr790; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP11]], align 16791; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP3]], [[TMP4]]792; CHECK-NEXT: [[RES0:%.*]] = fdiv <8 x half> [[X1]], [[X2]]793; CHECK-NEXT: [[TMP12:%.*]] = select <8 x i1> [[MSK]], <8 x i16> [[_MSPROP]], <8 x i16> [[TMP5]]794; CHECK-NEXT: [[TMP13:%.*]] = bitcast <8 x half> [[RES0]] to <8 x i16>795; CHECK-NEXT: [[TMP14:%.*]] = bitcast <8 x half> [[SRC]] to <8 x i16>796; CHECK-NEXT: [[TMP15:%.*]] = xor <8 x i16> [[TMP13]], [[TMP14]]797; CHECK-NEXT: [[TMP16:%.*]] = or <8 x i16> [[TMP15]], [[_MSPROP]]798; CHECK-NEXT: [[TMP17:%.*]] = or <8 x i16> [[TMP16]], [[TMP5]]799; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP6]], <8 x i16> [[TMP17]], <8 x i16> [[TMP12]]800; CHECK-NEXT: [[RES1:%.*]] = select <8 x i1> [[MSK]], <8 x half> [[RES0]], <8 x half> [[SRC]]801; CHECK-NEXT: [[_MSPROP1:%.*]] = or <8 x i16> [[TMP3]], [[_MSLD]]802; CHECK-NEXT: [[T3:%.*]] = fdiv <8 x half> [[X1]], [[VAL]]803; CHECK-NEXT: [[TMP18:%.*]] = select <8 x i1> [[MSK]], <8 x i16> [[_MSPROP1]], <8 x i16> [[TMP5]]804; CHECK-NEXT: [[TMP19:%.*]] = bitcast <8 x half> [[T3]] to <8 x i16>805; CHECK-NEXT: [[TMP20:%.*]] = bitcast <8 x half> [[SRC]] to <8 x i16>806; CHECK-NEXT: [[TMP21:%.*]] = xor <8 x i16> [[TMP19]], [[TMP20]]807; CHECK-NEXT: [[TMP22:%.*]] = or <8 x i16> [[TMP21]], [[_MSPROP1]]808; CHECK-NEXT: [[TMP23:%.*]] = or <8 x i16> [[TMP22]], [[TMP5]]809; CHECK-NEXT: [[_MSPROP_SELECT2:%.*]] = select <8 x i1> [[TMP6]], <8 x i16> [[TMP23]], <8 x i16> [[TMP18]]810; CHECK-NEXT: [[RES2:%.*]] = select <8 x i1> [[MSK]], <8 x half> [[T3]], <8 x half> [[SRC]]811; CHECK-NEXT: [[_MSPROP3:%.*]] = or <8 x i16> [[_MSPROP_SELECT]], [[_MSPROP_SELECT2]]812; CHECK-NEXT: [[RES:%.*]] = fdiv <8 x half> [[RES1]], [[RES2]]813; CHECK-NEXT: store <8 x i16> [[_MSPROP3]], ptr @__msan_retval_tls, align 8814; CHECK-NEXT: ret <8 x half> [[RES]]815;816 %msk = bitcast i8 %mask to <8 x i1>817 %val = load <8 x half>, ptr %ptr818 %res0 = fdiv <8 x half> %x1, %x2819 %res1 = select <8 x i1> %msk, <8 x half> %res0, <8 x half> %src820 %t3 = fdiv <8 x half> %x1, %val821 %res2 = select <8 x i1> %msk, <8 x half> %t3, <8 x half> %src822 %res = fdiv <8 x half> %res1 , %res2823 ret <8 x half> %res824}825 826define <8 x half> @test_int_x86_avx512fp16_maskz_div_ph_128(<8 x half> %x1, <8 x half> %x2, i8 %mask, ptr %ptr) #0 {827; CHECK-LABEL: define <8 x half> @test_int_x86_avx512fp16_maskz_div_ph_128(828; CHECK-SAME: <8 x half> [[X1:%.*]], <8 x half> [[X2:%.*]], i8 [[MASK:%.*]], ptr [[PTR:%.*]]) #[[ATTR0]] {829; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8830; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8831; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8832; CHECK-NEXT: call void @llvm.donothing()833; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8 [[TMP1]] to <8 x i1>834; CHECK-NEXT: [[MSK:%.*]] = bitcast i8 [[MASK]] to <8 x i1>835; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP2]], [[TMP3]]836; CHECK-NEXT: [[RES0:%.*]] = fdiv <8 x half> [[X1]], [[X2]]837; CHECK-NEXT: [[TMP5:%.*]] = select <8 x i1> [[MSK]], <8 x i16> [[_MSPROP]], <8 x i16> zeroinitializer838; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x half> [[RES0]] to <8 x i16>839; CHECK-NEXT: [[TMP7:%.*]] = xor <8 x i16> [[TMP6]], zeroinitializer840; CHECK-NEXT: [[TMP8:%.*]] = or <8 x i16> [[TMP7]], [[_MSPROP]]841; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i16> [[TMP8]], zeroinitializer842; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP4]], <8 x i16> [[TMP9]], <8 x i16> [[TMP5]]843; CHECK-NEXT: [[RES1:%.*]] = select <8 x i1> [[MSK]], <8 x half> [[RES0]], <8 x half> zeroinitializer844; CHECK-NEXT: store <8 x i16> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 8845; CHECK-NEXT: ret <8 x half> [[RES1]]846;847 %msk = bitcast i8 %mask to <8 x i1>848 %res0 = fdiv <8 x half> %x1, %x2849 %res1 = select <8 x i1> %msk, <8 x half> %res0, <8 x half> zeroinitializer850 ret <8 x half> %res1851}852 853define <16 x half> @test_min_ph_256(<16 x half> %x1, <16 x half> %x2) #0 {854; CHECK-LABEL: define <16 x half> @test_min_ph_256(855; CHECK-SAME: <16 x half> [[X1:%.*]], <16 x half> [[X2:%.*]]) #[[ATTR0]] {856; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8857; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8858; CHECK-NEXT: call void @llvm.donothing()859; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i16> [[TMP1]], [[TMP2]]860; CHECK-NEXT: [[TMP3:%.*]] = trunc <16 x i16> [[_MSPROP]] to <16 x i1>861; CHECK-NEXT: [[RES0:%.*]] = fcmp olt <16 x half> [[X1]], [[X2]]862; CHECK-NEXT: [[TMP4:%.*]] = select <16 x i1> [[RES0]], <16 x i16> [[TMP1]], <16 x i16> [[TMP2]]863; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x half> [[X1]] to <16 x i16>864; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x half> [[X2]] to <16 x i16>865; CHECK-NEXT: [[TMP7:%.*]] = xor <16 x i16> [[TMP5]], [[TMP6]]866; CHECK-NEXT: [[TMP8:%.*]] = or <16 x i16> [[TMP7]], [[TMP1]]867; CHECK-NEXT: [[TMP9:%.*]] = or <16 x i16> [[TMP8]], [[TMP2]]868; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP3]], <16 x i16> [[TMP9]], <16 x i16> [[TMP4]]869; CHECK-NEXT: [[RES1:%.*]] = select <16 x i1> [[RES0]], <16 x half> [[X1]], <16 x half> [[X2]]870; CHECK-NEXT: store <16 x i16> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 8871; CHECK-NEXT: ret <16 x half> [[RES1]]872;873 %res0 = fcmp olt <16 x half> %x1, %x2874 %res1 = select <16 x i1> %res0, <16 x half> %x1, <16 x half> %x2875 ret <16 x half> %res1876}877 878define <16 x half> @test_max_ph_256(<16 x half> %x1, <16 x half> %x2) #0 {879; CHECK-LABEL: define <16 x half> @test_max_ph_256(880; CHECK-SAME: <16 x half> [[X1:%.*]], <16 x half> [[X2:%.*]]) #[[ATTR0]] {881; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8882; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8883; CHECK-NEXT: call void @llvm.donothing()884; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i16> [[TMP1]], [[TMP2]]885; CHECK-NEXT: [[TMP3:%.*]] = trunc <16 x i16> [[_MSPROP]] to <16 x i1>886; CHECK-NEXT: [[RES0:%.*]] = fcmp ogt <16 x half> [[X1]], [[X2]]887; CHECK-NEXT: [[TMP4:%.*]] = select <16 x i1> [[RES0]], <16 x i16> [[TMP1]], <16 x i16> [[TMP2]]888; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x half> [[X1]] to <16 x i16>889; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x half> [[X2]] to <16 x i16>890; CHECK-NEXT: [[TMP7:%.*]] = xor <16 x i16> [[TMP5]], [[TMP6]]891; CHECK-NEXT: [[TMP8:%.*]] = or <16 x i16> [[TMP7]], [[TMP1]]892; CHECK-NEXT: [[TMP9:%.*]] = or <16 x i16> [[TMP8]], [[TMP2]]893; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP3]], <16 x i16> [[TMP9]], <16 x i16> [[TMP4]]894; CHECK-NEXT: [[RES1:%.*]] = select <16 x i1> [[RES0]], <16 x half> [[X1]], <16 x half> [[X2]]895; CHECK-NEXT: store <16 x i16> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 8896; CHECK-NEXT: ret <16 x half> [[RES1]]897;898 %res0 = fcmp ogt <16 x half> %x1, %x2899 %res1 = select <16 x i1> %res0, <16 x half> %x1, <16 x half> %x2900 ret <16 x half> %res1901}902 903define <8 x half> @test_min_ph_128(<8 x half> %x1, <8 x half> %x2) #0 {904; CHECK-LABEL: define <8 x half> @test_min_ph_128(905; CHECK-SAME: <8 x half> [[X1:%.*]], <8 x half> [[X2:%.*]]) #[[ATTR0]] {906; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8907; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8908; CHECK-NEXT: call void @llvm.donothing()909; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP1]], [[TMP2]]910; CHECK-NEXT: [[TMP3:%.*]] = trunc <8 x i16> [[_MSPROP]] to <8 x i1>911; CHECK-NEXT: [[RES0:%.*]] = fcmp olt <8 x half> [[X1]], [[X2]]912; CHECK-NEXT: [[TMP4:%.*]] = select <8 x i1> [[RES0]], <8 x i16> [[TMP1]], <8 x i16> [[TMP2]]913; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x half> [[X1]] to <8 x i16>914; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x half> [[X2]] to <8 x i16>915; CHECK-NEXT: [[TMP7:%.*]] = xor <8 x i16> [[TMP5]], [[TMP6]]916; CHECK-NEXT: [[TMP8:%.*]] = or <8 x i16> [[TMP7]], [[TMP1]]917; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i16> [[TMP8]], [[TMP2]]918; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP3]], <8 x i16> [[TMP9]], <8 x i16> [[TMP4]]919; CHECK-NEXT: [[RES1:%.*]] = select <8 x i1> [[RES0]], <8 x half> [[X1]], <8 x half> [[X2]]920; CHECK-NEXT: store <8 x i16> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 8921; CHECK-NEXT: ret <8 x half> [[RES1]]922;923 %res0 = fcmp olt <8 x half> %x1, %x2924 %res1 = select <8 x i1> %res0, <8 x half> %x1, <8 x half> %x2925 ret <8 x half> %res1926}927 928define <8 x half> @test_max_ph_128(<8 x half> %x1, <8 x half> %x2) #0 {929; CHECK-LABEL: define <8 x half> @test_max_ph_128(930; CHECK-SAME: <8 x half> [[X1:%.*]], <8 x half> [[X2:%.*]]) #[[ATTR0]] {931; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8932; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8933; CHECK-NEXT: call void @llvm.donothing()934; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP1]], [[TMP2]]935; CHECK-NEXT: [[TMP3:%.*]] = trunc <8 x i16> [[_MSPROP]] to <8 x i1>936; CHECK-NEXT: [[RES0:%.*]] = fcmp ogt <8 x half> [[X1]], [[X2]]937; CHECK-NEXT: [[TMP4:%.*]] = select <8 x i1> [[RES0]], <8 x i16> [[TMP1]], <8 x i16> [[TMP2]]938; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x half> [[X1]] to <8 x i16>939; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x half> [[X2]] to <8 x i16>940; CHECK-NEXT: [[TMP7:%.*]] = xor <8 x i16> [[TMP5]], [[TMP6]]941; CHECK-NEXT: [[TMP8:%.*]] = or <8 x i16> [[TMP7]], [[TMP1]]942; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i16> [[TMP8]], [[TMP2]]943; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP3]], <8 x i16> [[TMP9]], <8 x i16> [[TMP4]]944; CHECK-NEXT: [[RES1:%.*]] = select <8 x i1> [[RES0]], <8 x half> [[X1]], <8 x half> [[X2]]945; CHECK-NEXT: store <8 x i16> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 8946; CHECK-NEXT: ret <8 x half> [[RES1]]947;948 %res0 = fcmp ogt <8 x half> %x1, %x2949 %res1 = select <8 x i1> %res0, <8 x half> %x1, <8 x half> %x2950 ret <8 x half> %res1951}952 953declare <8 x half> @llvm.x86.avx512fp16.max.ph.128(<8 x half>, <8 x half>)954declare <16 x half> @llvm.x86.avx512fp16.max.ph.256(<16 x half>, <16 x half>)955 956define <8 x half> @test_max_ph_128_2(<8 x half> %x1, <8 x half> %x2) #0 {957; CHECK-LABEL: define <8 x half> @test_max_ph_128_2(958; CHECK-SAME: <8 x half> [[X1:%.*]], <8 x half> [[X2:%.*]]) #[[ATTR0]] {959; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8960; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8961; CHECK-NEXT: call void @llvm.donothing()962; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP1]], [[TMP2]]963; CHECK-NEXT: [[RES0:%.*]] = call <8 x half> @llvm.x86.avx512fp16.max.ph.128(<8 x half> [[X1]], <8 x half> [[X2]])964; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8965; CHECK-NEXT: ret <8 x half> [[RES0]]966;967 %res0 = call <8 x half> @llvm.x86.avx512fp16.max.ph.128(<8 x half> %x1, <8 x half> %x2)968 ret <8 x half> %res0969}970 971define <16 x half> @test_max_ph_256_2(<16 x half> %x1, <16 x half> %x2) #0 {972; CHECK-LABEL: define <16 x half> @test_max_ph_256_2(973; CHECK-SAME: <16 x half> [[X1:%.*]], <16 x half> [[X2:%.*]]) #[[ATTR0]] {974; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8975; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8976; CHECK-NEXT: call void @llvm.donothing()977; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i16> [[TMP1]], [[TMP2]]978; CHECK-NEXT: [[RES0:%.*]] = call <16 x half> @llvm.x86.avx512fp16.max.ph.256(<16 x half> [[X1]], <16 x half> [[X2]])979; CHECK-NEXT: store <16 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8980; CHECK-NEXT: ret <16 x half> [[RES0]]981;982 %res0 = call <16 x half> @llvm.x86.avx512fp16.max.ph.256(<16 x half> %x1, <16 x half> %x2)983 ret <16 x half> %res0984}985 986declare <8 x half> @llvm.x86.avx512fp16.min.ph.128(<8 x half>, <8 x half>)987declare <16 x half> @llvm.x86.avx512fp16.min.ph.256(<16 x half>, <16 x half>)988 989define <8 x half> @test_min_ph_128_2(<8 x half> %x1, <8 x half> %x2) #0 {990; CHECK-LABEL: define <8 x half> @test_min_ph_128_2(991; CHECK-SAME: <8 x half> [[X1:%.*]], <8 x half> [[X2:%.*]]) #[[ATTR0]] {992; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8993; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8994; CHECK-NEXT: call void @llvm.donothing()995; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP1]], [[TMP2]]996; CHECK-NEXT: [[RES0:%.*]] = call <8 x half> @llvm.x86.avx512fp16.min.ph.128(<8 x half> [[X1]], <8 x half> [[X2]])997; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8998; CHECK-NEXT: ret <8 x half> [[RES0]]999;1000 %res0 = call <8 x half> @llvm.x86.avx512fp16.min.ph.128(<8 x half> %x1, <8 x half> %x2)1001 ret <8 x half> %res01002}1003 1004define <16 x half> @test_min_ph_256_2(<16 x half> %x1, <16 x half> %x2) #0 {1005; CHECK-LABEL: define <16 x half> @test_min_ph_256_2(1006; CHECK-SAME: <16 x half> [[X1:%.*]], <16 x half> [[X2:%.*]]) #[[ATTR0]] {1007; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 81008; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81009; CHECK-NEXT: call void @llvm.donothing()1010; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i16> [[TMP1]], [[TMP2]]1011; CHECK-NEXT: [[RES0:%.*]] = call <16 x half> @llvm.x86.avx512fp16.min.ph.256(<16 x half> [[X1]], <16 x half> [[X2]])1012; CHECK-NEXT: store <16 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 81013; CHECK-NEXT: ret <16 x half> [[RES0]]1014;1015 %res0 = call <16 x half> @llvm.x86.avx512fp16.min.ph.256(<16 x half> %x1, <16 x half> %x2)1016 ret <16 x half> %res01017}1018 1019declare <4 x double> @llvm.x86.avx512fp16.mask.vcvtph2pd.256(<8 x half>, <4 x double>, i8)1020 1021define <4 x double> @test_int_x86_avx512_mask_vcvt_ph2pd_256(<8 x half> %x0, <4 x double> %x1, i8 %x2) #0 {1022; CHECK-LABEL: define <4 x double> @test_int_x86_avx512_mask_vcvt_ph2pd_256(1023; CHECK-SAME: <8 x half> [[X0:%.*]], <4 x double> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {1024; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81025; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81026; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 81027; CHECK-NEXT: call void @llvm.donothing()1028; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i16> [[TMP1]] to i1281029; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 01030; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i64> [[TMP2]] to i2561031; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP5]], 01032; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1033; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 01034; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]1035; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]1036; CHECK: [[BB6]]:1037; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1038; CHECK-NEXT: unreachable1039; CHECK: [[BB7]]:1040; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.x86.avx512fp16.mask.vcvtph2pd.256(<8 x half> [[X0]], <4 x double> [[X1]], i8 [[X2]])1041; CHECK-NEXT: store <4 x i64> zeroinitializer, ptr @__msan_retval_tls, align 81042; CHECK-NEXT: ret <4 x double> [[RES]]1043;1044 %res = call <4 x double> @llvm.x86.avx512fp16.mask.vcvtph2pd.256(<8 x half> %x0, <4 x double> %x1, i8 %x2)1045 ret <4 x double> %res1046}1047 1048define <4 x double> @test_int_x86_avx512_mask_vcvt_ph2pd_256_nomask(<8 x half> %x0, <4 x double> %x1) #0 {1049; CHECK-LABEL: define <4 x double> @test_int_x86_avx512_mask_vcvt_ph2pd_256_nomask(1050; CHECK-SAME: <8 x half> [[X0:%.*]], <4 x double> [[X1:%.*]]) #[[ATTR0]] {1051; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81052; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81053; CHECK-NEXT: call void @llvm.donothing()1054; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP1]] to i1281055; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 01056; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i64> [[TMP2]] to i2561057; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP4]], 01058; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1059; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]1060; CHECK: [[BB5]]:1061; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1062; CHECK-NEXT: unreachable1063; CHECK: [[BB6]]:1064; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.x86.avx512fp16.mask.vcvtph2pd.256(<8 x half> [[X0]], <4 x double> [[X1]], i8 -1)1065; CHECK-NEXT: store <4 x i64> zeroinitializer, ptr @__msan_retval_tls, align 81066; CHECK-NEXT: ret <4 x double> [[RES]]1067;1068 %res = call <4 x double> @llvm.x86.avx512fp16.mask.vcvtph2pd.256(<8 x half> %x0, <4 x double> %x1, i8 -1)1069 ret <4 x double> %res1070}1071 1072declare <2 x double> @llvm.x86.avx512fp16.mask.vcvtph2pd.128(<8 x half>, <2 x double>, i8)1073 1074define <2 x double> @test_int_x86_avx512_mask_vcvt_ph2pd_128(<8 x half> %x0, <2 x double> %x1, i8 %x2) #0 {1075; CHECK-LABEL: define <2 x double> @test_int_x86_avx512_mask_vcvt_ph2pd_128(1076; CHECK-SAME: <8 x half> [[X0:%.*]], <2 x double> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {1077; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81078; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81079; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81080; CHECK-NEXT: call void @llvm.donothing()1081; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i16> [[TMP1]] to i1281082; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 01083; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP2]] to i1281084; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 01085; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1086; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 01087; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]1088; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]1089; CHECK: [[BB6]]:1090; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1091; CHECK-NEXT: unreachable1092; CHECK: [[BB7]]:1093; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx512fp16.mask.vcvtph2pd.128(<8 x half> [[X0]], <2 x double> [[X1]], i8 [[X2]])1094; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 81095; CHECK-NEXT: ret <2 x double> [[RES]]1096;1097 %res = call <2 x double> @llvm.x86.avx512fp16.mask.vcvtph2pd.128(<8 x half> %x0, <2 x double> %x1, i8 %x2)1098 ret <2 x double> %res1099}1100 1101define <2 x double> @test_int_x86_avx512_mask_vcvt_ph2pd_128_nomask(<8 x half> %x0, <2 x double> %x1) #0 {1102; CHECK-LABEL: define <2 x double> @test_int_x86_avx512_mask_vcvt_ph2pd_128_nomask(1103; CHECK-SAME: <8 x half> [[X0:%.*]], <2 x double> [[X1:%.*]]) #[[ATTR0]] {1104; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81105; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81106; CHECK-NEXT: call void @llvm.donothing()1107; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP1]] to i1281108; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 01109; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP2]] to i1281110; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 01111; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1112; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]1113; CHECK: [[BB5]]:1114; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1115; CHECK-NEXT: unreachable1116; CHECK: [[BB6]]:1117; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx512fp16.mask.vcvtph2pd.128(<8 x half> [[X0]], <2 x double> [[X1]], i8 -1)1118; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 81119; CHECK-NEXT: ret <2 x double> [[RES]]1120;1121 %res = call <2 x double> @llvm.x86.avx512fp16.mask.vcvtph2pd.128(<8 x half> %x0, <2 x double> %x1, i8 -1)1122 ret <2 x double> %res1123}1124 1125declare <8 x half> @llvm.x86.avx512fp16.mask.vcvtpd2ph.256(<4 x double>, <8 x half>, i8)1126 1127define <8 x half> @test_int_x86_avx512_mask_vcvt_pd2ph_256(<4 x double> %x0, <8 x half> %x1, i8 %x2) #0 {1128; CHECK-LABEL: define <8 x half> @test_int_x86_avx512_mask_vcvt_pd2ph_256(1129; CHECK-SAME: <4 x double> [[X0:%.*]], <8 x half> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {1130; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 81131; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81132; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 81133; CHECK-NEXT: call void @llvm.donothing()1134; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i64> [[TMP1]] to i2561135; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP4]], 01136; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP2]] to i1281137; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 01138; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1139; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 01140; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]1141; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]1142; CHECK: [[BB6]]:1143; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1144; CHECK-NEXT: unreachable1145; CHECK: [[BB7]]:1146; CHECK-NEXT: [[RES:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.vcvtpd2ph.256(<4 x double> [[X0]], <8 x half> [[X1]], i8 [[X2]])1147; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 81148; CHECK-NEXT: ret <8 x half> [[RES]]1149;1150 %res = call <8 x half> @llvm.x86.avx512fp16.mask.vcvtpd2ph.256(<4 x double> %x0, <8 x half> %x1, i8 %x2)1151 ret <8 x half> %res1152}1153 1154define <8 x half> @test_int_x86_avx512_mask_vcvt_pd2ph_256_load(ptr %px0, <8 x half> %x1, i8 %x2) #0 {1155; CHECK-LABEL: define <8 x half> @test_int_x86_avx512_mask_vcvt_pd2ph_256_load(1156; CHECK-SAME: ptr [[PX0:%.*]], <8 x half> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {1157; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81158; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81159; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 81160; CHECK-NEXT: call void @llvm.donothing()1161; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01162; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]1163; CHECK: [[BB4]]:1164; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1165; CHECK-NEXT: unreachable1166; CHECK: [[BB5]]:1167; CHECK-NEXT: [[X0:%.*]] = load <4 x double>, ptr [[PX0]], align 321168; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[PX0]] to i641169; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 879609302220801170; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr1171; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i64>, ptr [[TMP8]], align 321172; CHECK-NEXT: [[TMP9:%.*]] = bitcast <4 x i64> [[_MSLD]] to i2561173; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP9]], 01174; CHECK-NEXT: [[TMP10:%.*]] = bitcast <8 x i16> [[TMP2]] to i1281175; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP10]], 01176; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP1]], [[_MSCMP2]]1177; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i8 [[TMP3]], 01178; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSOR]], [[_MSCMP3]]1179; CHECK-NEXT: br i1 [[_MSOR4]], label %[[BB11:.*]], label %[[BB12:.*]], !prof [[PROF1]]1180; CHECK: [[BB11]]:1181; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1182; CHECK-NEXT: unreachable1183; CHECK: [[BB12]]:1184; CHECK-NEXT: [[RES:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.vcvtpd2ph.256(<4 x double> [[X0]], <8 x half> [[X1]], i8 [[X2]])1185; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 81186; CHECK-NEXT: ret <8 x half> [[RES]]1187;1188 %x0 = load <4 x double>, ptr %px0, align 321189 %res = call <8 x half> @llvm.x86.avx512fp16.mask.vcvtpd2ph.256(<4 x double> %x0, <8 x half> %x1, i8 %x2)1190 ret <8 x half> %res1191}1192 1193declare <8 x half> @llvm.x86.avx512fp16.mask.vcvtpd2ph.128(<2 x double>, <8 x half>, i8)1194 1195define <8 x half> @test_int_x86_avx512_mask_vcvt_pd2ph_128(<2 x double> %x0, <8 x half> %x1, i8 %x2) #0 {1196; CHECK-LABEL: define <8 x half> @test_int_x86_avx512_mask_vcvt_pd2ph_128(1197; CHECK-SAME: <2 x double> [[X0:%.*]], <8 x half> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {1198; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 81199; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81200; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81201; CHECK-NEXT: call void @llvm.donothing()1202; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP1]] to i1281203; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 01204; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP2]] to i1281205; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 01206; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1207; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 01208; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]1209; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]1210; CHECK: [[BB6]]:1211; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1212; CHECK-NEXT: unreachable1213; CHECK: [[BB7]]:1214; CHECK-NEXT: [[RES:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.vcvtpd2ph.128(<2 x double> [[X0]], <8 x half> [[X1]], i8 [[X2]])1215; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 81216; CHECK-NEXT: ret <8 x half> [[RES]]1217;1218 %res = call <8 x half> @llvm.x86.avx512fp16.mask.vcvtpd2ph.128(<2 x double> %x0, <8 x half> %x1, i8 %x2)1219 ret <8 x half> %res1220}1221 1222define <8 x half> @test_int_x86_avx512_mask_vcvt_pd2ph_128_load(ptr %px0, <8 x half> %x1, i8 %x2) #0 {1223; CHECK-LABEL: define <8 x half> @test_int_x86_avx512_mask_vcvt_pd2ph_128_load(1224; CHECK-SAME: ptr [[PX0:%.*]], <8 x half> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {1225; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81226; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81227; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 81228; CHECK-NEXT: call void @llvm.donothing()1229; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01230; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]1231; CHECK: [[BB4]]:1232; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1233; CHECK-NEXT: unreachable1234; CHECK: [[BB5]]:1235; CHECK-NEXT: [[X0:%.*]] = load <2 x double>, ptr [[PX0]], align 161236; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[PX0]] to i641237; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 879609302220801238; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr1239; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP8]], align 161240; CHECK-NEXT: [[TMP9:%.*]] = bitcast <2 x i64> [[_MSLD]] to i1281241; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP9]], 01242; CHECK-NEXT: [[TMP10:%.*]] = bitcast <8 x i16> [[TMP2]] to i1281243; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP10]], 01244; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP1]], [[_MSCMP2]]1245; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i8 [[TMP3]], 01246; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSOR]], [[_MSCMP3]]1247; CHECK-NEXT: br i1 [[_MSOR4]], label %[[BB11:.*]], label %[[BB12:.*]], !prof [[PROF1]]1248; CHECK: [[BB11]]:1249; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1250; CHECK-NEXT: unreachable1251; CHECK: [[BB12]]:1252; CHECK-NEXT: [[RES:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.vcvtpd2ph.128(<2 x double> [[X0]], <8 x half> [[X1]], i8 [[X2]])1253; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 81254; CHECK-NEXT: ret <8 x half> [[RES]]1255;1256 %x0 = load <2 x double>, ptr %px0, align 161257 %res = call <8 x half> @llvm.x86.avx512fp16.mask.vcvtpd2ph.128(<2 x double> %x0, <8 x half> %x1, i8 %x2)1258 ret <8 x half> %res1259}1260 1261declare <4 x i32> @llvm.x86.avx512fp16.mask.vcvtph2udq.128(<8 x half>, <4 x i32>, i8)1262 1263define <4 x i32> @test_int_x86_avx512_cvt_ph2udq_128(<8 x half> %x0) #0 {1264; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_cvt_ph2udq_128(1265; CHECK-SAME: <8 x half> [[X0:%.*]]) #[[ATTR0]] {1266; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81267; CHECK-NEXT: call void @llvm.donothing()1268; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1269; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx512fp16.mask.vcvtph2udq.128(<8 x half> [[X0]], <4 x i32> poison, i8 -1)1270; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81271; CHECK-NEXT: ret <4 x i32> [[RES]]1272;1273 %res = call <4 x i32> @llvm.x86.avx512fp16.mask.vcvtph2udq.128(<8 x half> %x0, <4 x i32> poison, i8 -1)1274 ret <4 x i32> %res1275}1276 1277define <4 x i32> @test_int_x86_avx512_mask_cvt_ph2udq_128(<8 x half> %x0, <4 x i32> %x1, i8 %x2) #0 {1278; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_mask_cvt_ph2udq_128(1279; CHECK-SAME: <8 x half> [[X0:%.*]], <4 x i32> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {1280; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81281; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81282; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81283; CHECK-NEXT: call void @llvm.donothing()1284; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i16> [[TMP1]] to i1281285; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 01286; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP2]] to i1281287; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 01288; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1289; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 01290; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]1291; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]1292; CHECK: [[BB6]]:1293; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1294; CHECK-NEXT: unreachable1295; CHECK: [[BB7]]:1296; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx512fp16.mask.vcvtph2udq.128(<8 x half> [[X0]], <4 x i32> [[X1]], i8 [[X2]])1297; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81298; CHECK-NEXT: ret <4 x i32> [[RES]]1299;1300 %res = call <4 x i32> @llvm.x86.avx512fp16.mask.vcvtph2udq.128(<8 x half> %x0, <4 x i32> %x1, i8 %x2)1301 ret <4 x i32> %res1302}1303 1304define <4 x i32> @test_int_x86_avx512_maskz_cvt_ph2udq_128(<8 x half> %x0, i8 %x2) #0 {1305; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_maskz_cvt_ph2udq_128(1306; CHECK-SAME: <8 x half> [[X0:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {1307; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81308; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81309; CHECK-NEXT: call void @llvm.donothing()1310; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP1]] to i1281311; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 01312; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i8 [[TMP2]], 01313; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1314; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]1315; CHECK: [[BB4]]:1316; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1317; CHECK-NEXT: unreachable1318; CHECK: [[BB5]]:1319; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx512fp16.mask.vcvtph2udq.128(<8 x half> [[X0]], <4 x i32> zeroinitializer, i8 [[X2]])1320; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81321; CHECK-NEXT: ret <4 x i32> [[RES]]1322;1323 %res = call <4 x i32> @llvm.x86.avx512fp16.mask.vcvtph2udq.128(<8 x half> %x0, <4 x i32> zeroinitializer, i8 %x2)1324 ret <4 x i32> %res1325}1326 1327declare <8 x i32> @llvm.x86.avx512fp16.mask.vcvtph2udq.256(<8 x half>, <8 x i32>, i8)1328 1329define <8 x i32> @test_int_x86_avx512_cvt_ph2udq_256(<8 x half> %x0) #0 {1330; CHECK-LABEL: define <8 x i32> @test_int_x86_avx512_cvt_ph2udq_256(1331; CHECK-SAME: <8 x half> [[X0:%.*]]) #[[ATTR0]] {1332; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81333; CHECK-NEXT: call void @llvm.donothing()1334; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1335; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx512fp16.mask.vcvtph2udq.256(<8 x half> [[X0]], <8 x i32> poison, i8 -1)1336; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81337; CHECK-NEXT: ret <8 x i32> [[RES]]1338;1339 %res = call <8 x i32> @llvm.x86.avx512fp16.mask.vcvtph2udq.256(<8 x half> %x0, <8 x i32> poison, i8 -1)1340 ret <8 x i32> %res1341}1342 1343define <8 x i32> @test_int_x86_avx512_mask_cvt_ph2udq_256(<8 x half> %x0, <8 x i32> %x1, i8 %x2) #0 {1344; CHECK-LABEL: define <8 x i32> @test_int_x86_avx512_mask_cvt_ph2udq_256(1345; CHECK-SAME: <8 x half> [[X0:%.*]], <8 x i32> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {1346; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81347; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81348; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 81349; CHECK-NEXT: call void @llvm.donothing()1350; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i16> [[TMP1]] to i1281351; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 01352; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i32> [[TMP2]] to i2561353; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP5]], 01354; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1355; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 01356; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]1357; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]1358; CHECK: [[BB6]]:1359; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1360; CHECK-NEXT: unreachable1361; CHECK: [[BB7]]:1362; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx512fp16.mask.vcvtph2udq.256(<8 x half> [[X0]], <8 x i32> [[X1]], i8 [[X2]])1363; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81364; CHECK-NEXT: ret <8 x i32> [[RES]]1365;1366 %res = call <8 x i32> @llvm.x86.avx512fp16.mask.vcvtph2udq.256(<8 x half> %x0, <8 x i32> %x1, i8 %x2)1367 ret <8 x i32> %res1368}1369 1370define <8 x i32> @test_int_x86_avx512_maskz_cvt_ph2udq_256(<8 x half> %x0, i8 %x2) #0 {1371; CHECK-LABEL: define <8 x i32> @test_int_x86_avx512_maskz_cvt_ph2udq_256(1372; CHECK-SAME: <8 x half> [[X0:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {1373; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81374; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81375; CHECK-NEXT: call void @llvm.donothing()1376; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP1]] to i1281377; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 01378; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i8 [[TMP2]], 01379; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1380; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]1381; CHECK: [[BB4]]:1382; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1383; CHECK-NEXT: unreachable1384; CHECK: [[BB5]]:1385; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx512fp16.mask.vcvtph2udq.256(<8 x half> [[X0]], <8 x i32> zeroinitializer, i8 [[X2]])1386; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81387; CHECK-NEXT: ret <8 x i32> [[RES]]1388;1389 %res = call <8 x i32> @llvm.x86.avx512fp16.mask.vcvtph2udq.256(<8 x half> %x0, <8 x i32> zeroinitializer, i8 %x2)1390 ret <8 x i32> %res1391}1392 1393declare <4 x i32> @llvm.x86.avx512fp16.mask.vcvttph2dq.128(<8 x half>, <4 x i32>, i8)1394 1395define <4 x i32> @test_int_x86_avx512_cvtt_ph2dq_128(<8 x half> %x0) #0 {1396; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_cvtt_ph2dq_128(1397; CHECK-SAME: <8 x half> [[X0:%.*]]) #[[ATTR0]] {1398; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81399; CHECK-NEXT: call void @llvm.donothing()1400; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1401; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx512fp16.mask.vcvttph2dq.128(<8 x half> [[X0]], <4 x i32> poison, i8 -1)1402; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81403; CHECK-NEXT: ret <4 x i32> [[RES]]1404;1405 %res = call <4 x i32> @llvm.x86.avx512fp16.mask.vcvttph2dq.128(<8 x half> %x0, <4 x i32> poison, i8 -1)1406 ret <4 x i32> %res1407}1408 1409define <4 x i32> @test_int_x86_avx512_mask_cvtt_ph2dq_128(<8 x half> %x0, <4 x i32> %x1, i8 %x2) #0 {1410; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_mask_cvtt_ph2dq_128(1411; CHECK-SAME: <8 x half> [[X0:%.*]], <4 x i32> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {1412; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81413; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81414; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81415; CHECK-NEXT: call void @llvm.donothing()1416; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i16> [[TMP1]] to i1281417; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 01418; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP2]] to i1281419; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 01420; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1421; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 01422; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]1423; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]1424; CHECK: [[BB6]]:1425; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1426; CHECK-NEXT: unreachable1427; CHECK: [[BB7]]:1428; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx512fp16.mask.vcvttph2dq.128(<8 x half> [[X0]], <4 x i32> [[X1]], i8 [[X2]])1429; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81430; CHECK-NEXT: ret <4 x i32> [[RES]]1431;1432 %res = call <4 x i32> @llvm.x86.avx512fp16.mask.vcvttph2dq.128(<8 x half> %x0, <4 x i32> %x1, i8 %x2)1433 ret <4 x i32> %res1434}1435 1436define <4 x i32> @test_int_x86_avx512_maskz_cvtt_ph2dq_128(<8 x half> %x0, i8 %x2) #0 {1437; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_maskz_cvtt_ph2dq_128(1438; CHECK-SAME: <8 x half> [[X0:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {1439; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81440; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81441; CHECK-NEXT: call void @llvm.donothing()1442; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP1]] to i1281443; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 01444; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i8 [[TMP2]], 01445; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1446; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]1447; CHECK: [[BB4]]:1448; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1449; CHECK-NEXT: unreachable1450; CHECK: [[BB5]]:1451; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx512fp16.mask.vcvttph2dq.128(<8 x half> [[X0]], <4 x i32> zeroinitializer, i8 [[X2]])1452; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81453; CHECK-NEXT: ret <4 x i32> [[RES]]1454;1455 %res = call <4 x i32> @llvm.x86.avx512fp16.mask.vcvttph2dq.128(<8 x half> %x0, <4 x i32> zeroinitializer, i8 %x2)1456 ret <4 x i32> %res1457}1458 1459declare <8 x i32> @llvm.x86.avx512fp16.mask.vcvttph2dq.256(<8 x half>, <8 x i32>, i8)1460 1461define <8 x i32> @test_int_x86_avx512_cvtt_ph2dq_256(<8 x half> %x0) #0 {1462; CHECK-LABEL: define <8 x i32> @test_int_x86_avx512_cvtt_ph2dq_256(1463; CHECK-SAME: <8 x half> [[X0:%.*]]) #[[ATTR0]] {1464; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81465; CHECK-NEXT: call void @llvm.donothing()1466; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1467; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx512fp16.mask.vcvttph2dq.256(<8 x half> [[X0]], <8 x i32> poison, i8 -1)1468; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81469; CHECK-NEXT: ret <8 x i32> [[RES]]1470;1471 %res = call <8 x i32> @llvm.x86.avx512fp16.mask.vcvttph2dq.256(<8 x half> %x0, <8 x i32> poison, i8 -1)1472 ret <8 x i32> %res1473}1474 1475define <8 x i32> @test_int_x86_avx512_mask_cvtt_ph2dq_256(<8 x half> %x0, <8 x i32> %x1, i8 %x2) #0 {1476; CHECK-LABEL: define <8 x i32> @test_int_x86_avx512_mask_cvtt_ph2dq_256(1477; CHECK-SAME: <8 x half> [[X0:%.*]], <8 x i32> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {1478; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81479; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81480; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 81481; CHECK-NEXT: call void @llvm.donothing()1482; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i16> [[TMP1]] to i1281483; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 01484; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i32> [[TMP2]] to i2561485; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP5]], 01486; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1487; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 01488; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]1489; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]1490; CHECK: [[BB6]]:1491; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1492; CHECK-NEXT: unreachable1493; CHECK: [[BB7]]:1494; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx512fp16.mask.vcvttph2dq.256(<8 x half> [[X0]], <8 x i32> [[X1]], i8 [[X2]])1495; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81496; CHECK-NEXT: ret <8 x i32> [[RES]]1497;1498 %res = call <8 x i32> @llvm.x86.avx512fp16.mask.vcvttph2dq.256(<8 x half> %x0, <8 x i32> %x1, i8 %x2)1499 ret <8 x i32> %res1500}1501 1502define <8 x i32> @test_int_x86_avx512_maskz_cvtt_ph2dq_256(<8 x half> %x0, i8 %x2) #0 {1503; CHECK-LABEL: define <8 x i32> @test_int_x86_avx512_maskz_cvtt_ph2dq_256(1504; CHECK-SAME: <8 x half> [[X0:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {1505; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81506; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81507; CHECK-NEXT: call void @llvm.donothing()1508; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP1]] to i1281509; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 01510; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i8 [[TMP2]], 01511; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1512; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]1513; CHECK: [[BB4]]:1514; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1515; CHECK-NEXT: unreachable1516; CHECK: [[BB5]]:1517; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx512fp16.mask.vcvttph2dq.256(<8 x half> [[X0]], <8 x i32> zeroinitializer, i8 [[X2]])1518; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81519; CHECK-NEXT: ret <8 x i32> [[RES]]1520;1521 %res = call <8 x i32> @llvm.x86.avx512fp16.mask.vcvttph2dq.256(<8 x half> %x0, <8 x i32> zeroinitializer, i8 %x2)1522 ret <8 x i32> %res1523}1524 1525declare <4 x i32> @llvm.x86.avx512fp16.mask.vcvttph2udq.128(<8 x half>, <4 x i32>, i8)1526 1527define <4 x i32> @test_int_x86_avx512_cvtt_ph2udq_128(<8 x half> %x0) #0 {1528; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_cvtt_ph2udq_128(1529; CHECK-SAME: <8 x half> [[X0:%.*]]) #[[ATTR0]] {1530; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81531; CHECK-NEXT: call void @llvm.donothing()1532; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1533; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx512fp16.mask.vcvttph2udq.128(<8 x half> [[X0]], <4 x i32> poison, i8 -1)1534; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81535; CHECK-NEXT: ret <4 x i32> [[RES]]1536;1537 %res = call <4 x i32> @llvm.x86.avx512fp16.mask.vcvttph2udq.128(<8 x half> %x0, <4 x i32> poison, i8 -1)1538 ret <4 x i32> %res1539}1540 1541define <4 x i32> @test_int_x86_avx512_mask_cvtt_ph2udq_128(<8 x half> %x0, <4 x i32> %x1, i8 %x2) #0 {1542; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_mask_cvtt_ph2udq_128(1543; CHECK-SAME: <8 x half> [[X0:%.*]], <4 x i32> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {1544; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81545; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81546; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81547; CHECK-NEXT: call void @llvm.donothing()1548; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i16> [[TMP1]] to i1281549; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 01550; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP2]] to i1281551; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 01552; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1553; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 01554; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]1555; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]1556; CHECK: [[BB6]]:1557; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1558; CHECK-NEXT: unreachable1559; CHECK: [[BB7]]:1560; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx512fp16.mask.vcvttph2udq.128(<8 x half> [[X0]], <4 x i32> [[X1]], i8 [[X2]])1561; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81562; CHECK-NEXT: ret <4 x i32> [[RES]]1563;1564 %res = call <4 x i32> @llvm.x86.avx512fp16.mask.vcvttph2udq.128(<8 x half> %x0, <4 x i32> %x1, i8 %x2)1565 ret <4 x i32> %res1566}1567 1568define <4 x i32> @test_int_x86_avx512_maskz_cvtt_ph2udq_128(<8 x half> %x0, i8 %x2) #0 {1569; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_maskz_cvtt_ph2udq_128(1570; CHECK-SAME: <8 x half> [[X0:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {1571; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81572; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81573; CHECK-NEXT: call void @llvm.donothing()1574; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP1]] to i1281575; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 01576; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i8 [[TMP2]], 01577; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1578; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]1579; CHECK: [[BB4]]:1580; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1581; CHECK-NEXT: unreachable1582; CHECK: [[BB5]]:1583; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx512fp16.mask.vcvttph2udq.128(<8 x half> [[X0]], <4 x i32> zeroinitializer, i8 [[X2]])1584; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81585; CHECK-NEXT: ret <4 x i32> [[RES]]1586;1587 %res = call <4 x i32> @llvm.x86.avx512fp16.mask.vcvttph2udq.128(<8 x half> %x0, <4 x i32> zeroinitializer, i8 %x2)1588 ret <4 x i32> %res1589}1590 1591declare <8 x i32> @llvm.x86.avx512fp16.mask.vcvttph2udq.256(<8 x half>, <8 x i32>, i8)1592 1593define <8 x i32> @test_int_x86_avx512_cvtt_ph2udq_256(<8 x half> %x0) #0 {1594; CHECK-LABEL: define <8 x i32> @test_int_x86_avx512_cvtt_ph2udq_256(1595; CHECK-SAME: <8 x half> [[X0:%.*]]) #[[ATTR0]] {1596; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81597; CHECK-NEXT: call void @llvm.donothing()1598; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1599; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx512fp16.mask.vcvttph2udq.256(<8 x half> [[X0]], <8 x i32> poison, i8 -1)1600; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81601; CHECK-NEXT: ret <8 x i32> [[RES]]1602;1603 %res = call <8 x i32> @llvm.x86.avx512fp16.mask.vcvttph2udq.256(<8 x half> %x0, <8 x i32> poison, i8 -1)1604 ret <8 x i32> %res1605}1606 1607define <8 x i32> @test_int_x86_avx512_mask_cvtt_ph2udq_256(<8 x half> %x0, <8 x i32> %x1, i8 %x2) #0 {1608; CHECK-LABEL: define <8 x i32> @test_int_x86_avx512_mask_cvtt_ph2udq_256(1609; CHECK-SAME: <8 x half> [[X0:%.*]], <8 x i32> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {1610; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81611; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81612; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 81613; CHECK-NEXT: call void @llvm.donothing()1614; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i16> [[TMP1]] to i1281615; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 01616; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i32> [[TMP2]] to i2561617; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP5]], 01618; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1619; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 01620; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]1621; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]1622; CHECK: [[BB6]]:1623; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1624; CHECK-NEXT: unreachable1625; CHECK: [[BB7]]:1626; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx512fp16.mask.vcvttph2udq.256(<8 x half> [[X0]], <8 x i32> [[X1]], i8 [[X2]])1627; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81628; CHECK-NEXT: ret <8 x i32> [[RES]]1629;1630 %res = call <8 x i32> @llvm.x86.avx512fp16.mask.vcvttph2udq.256(<8 x half> %x0, <8 x i32> %x1, i8 %x2)1631 ret <8 x i32> %res1632}1633 1634define <8 x i32> @test_int_x86_avx512_maskz_cvtt_ph2udq_256(<8 x half> %x0, i8 %x2) #0 {1635; CHECK-LABEL: define <8 x i32> @test_int_x86_avx512_maskz_cvtt_ph2udq_256(1636; CHECK-SAME: <8 x half> [[X0:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {1637; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81638; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81639; CHECK-NEXT: call void @llvm.donothing()1640; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP1]] to i1281641; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 01642; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i8 [[TMP2]], 01643; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1644; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]1645; CHECK: [[BB4]]:1646; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1647; CHECK-NEXT: unreachable1648; CHECK: [[BB5]]:1649; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx512fp16.mask.vcvttph2udq.256(<8 x half> [[X0]], <8 x i32> zeroinitializer, i8 [[X2]])1650; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81651; CHECK-NEXT: ret <8 x i32> [[RES]]1652;1653 %res = call <8 x i32> @llvm.x86.avx512fp16.mask.vcvttph2udq.256(<8 x half> %x0, <8 x i32> zeroinitializer, i8 %x2)1654 ret <8 x i32> %res1655}1656 1657declare <4 x float> @llvm.x86.avx512fp16.mask.vcvtph2psx.128(<8 x half>, <4 x float>, i8)1658 1659define <4 x float> @test_int_x86_avx512_cvt_ph2psx_128(<8 x half> %x0) #0 {1660; CHECK-LABEL: define <4 x float> @test_int_x86_avx512_cvt_ph2psx_128(1661; CHECK-SAME: <8 x half> [[X0:%.*]]) #[[ATTR0]] {1662; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81663; CHECK-NEXT: call void @llvm.donothing()1664; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1665; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512fp16.mask.vcvtph2psx.128(<8 x half> [[X0]], <4 x float> poison, i8 -1)1666; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81667; CHECK-NEXT: ret <4 x float> [[RES]]1668;1669 %res = call <4 x float> @llvm.x86.avx512fp16.mask.vcvtph2psx.128(<8 x half> %x0, <4 x float> poison, i8 -1)1670 ret <4 x float> %res1671}1672 1673define <4 x float> @test_int_x86_avx512_mask_cvt_ph2psx_128(<8 x half> %x0, <4 x float> %x1, i8 %x2) #0 {1674; CHECK-LABEL: define <4 x float> @test_int_x86_avx512_mask_cvt_ph2psx_128(1675; CHECK-SAME: <8 x half> [[X0:%.*]], <4 x float> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {1676; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81677; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81678; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81679; CHECK-NEXT: call void @llvm.donothing()1680; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i16> [[TMP1]] to i1281681; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 01682; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP2]] to i1281683; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 01684; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1685; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 01686; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]1687; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]1688; CHECK: [[BB6]]:1689; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1690; CHECK-NEXT: unreachable1691; CHECK: [[BB7]]:1692; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512fp16.mask.vcvtph2psx.128(<8 x half> [[X0]], <4 x float> [[X1]], i8 [[X2]])1693; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81694; CHECK-NEXT: ret <4 x float> [[RES]]1695;1696 %res = call <4 x float> @llvm.x86.avx512fp16.mask.vcvtph2psx.128(<8 x half> %x0, <4 x float> %x1, i8 %x2)1697 ret <4 x float> %res1698}1699 1700define <4 x float> @test_int_x86_avx512_maskz_cvt_ph2psx_128(<8 x half> %x0, i8 %x2) #0 {1701; CHECK-LABEL: define <4 x float> @test_int_x86_avx512_maskz_cvt_ph2psx_128(1702; CHECK-SAME: <8 x half> [[X0:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {1703; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81704; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81705; CHECK-NEXT: call void @llvm.donothing()1706; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP1]] to i1281707; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 01708; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i8 [[TMP2]], 01709; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1710; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]1711; CHECK: [[BB4]]:1712; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1713; CHECK-NEXT: unreachable1714; CHECK: [[BB5]]:1715; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512fp16.mask.vcvtph2psx.128(<8 x half> [[X0]], <4 x float> zeroinitializer, i8 [[X2]])1716; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81717; CHECK-NEXT: ret <4 x float> [[RES]]1718;1719 %res = call <4 x float> @llvm.x86.avx512fp16.mask.vcvtph2psx.128(<8 x half> %x0, <4 x float> zeroinitializer, i8 %x2)1720 ret <4 x float> %res1721}1722 1723declare <8 x float> @llvm.x86.avx512fp16.mask.vcvtph2psx.256(<8 x half>, <8 x float>, i8)1724 1725define <8 x float> @test_int_x86_avx512_cvt_ph2psx_256(<8 x half> %x0) #0 {1726; CHECK-LABEL: define <8 x float> @test_int_x86_avx512_cvt_ph2psx_256(1727; CHECK-SAME: <8 x half> [[X0:%.*]]) #[[ATTR0]] {1728; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81729; CHECK-NEXT: call void @llvm.donothing()1730; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1731; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx512fp16.mask.vcvtph2psx.256(<8 x half> [[X0]], <8 x float> poison, i8 -1)1732; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81733; CHECK-NEXT: ret <8 x float> [[RES]]1734;1735 %res = call <8 x float> @llvm.x86.avx512fp16.mask.vcvtph2psx.256(<8 x half> %x0, <8 x float> poison, i8 -1)1736 ret <8 x float> %res1737}1738 1739define <8 x float> @test_int_x86_avx512_mask_cvt_ph2psx_256(<8 x half> %x0, <8 x float> %x1, i8 %x2) #0 {1740; CHECK-LABEL: define <8 x float> @test_int_x86_avx512_mask_cvt_ph2psx_256(1741; CHECK-SAME: <8 x half> [[X0:%.*]], <8 x float> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {1742; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81743; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81744; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 81745; CHECK-NEXT: call void @llvm.donothing()1746; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i16> [[TMP1]] to i1281747; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 01748; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i32> [[TMP2]] to i2561749; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP5]], 01750; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1751; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 01752; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]1753; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]1754; CHECK: [[BB6]]:1755; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1756; CHECK-NEXT: unreachable1757; CHECK: [[BB7]]:1758; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx512fp16.mask.vcvtph2psx.256(<8 x half> [[X0]], <8 x float> [[X1]], i8 [[X2]])1759; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81760; CHECK-NEXT: ret <8 x float> [[RES]]1761;1762 %res = call <8 x float> @llvm.x86.avx512fp16.mask.vcvtph2psx.256(<8 x half> %x0, <8 x float> %x1, i8 %x2)1763 ret <8 x float> %res1764}1765 1766define <8 x float> @test_int_x86_avx512_maskz_cvt_ph2psx_256(<8 x half> %x0, i8 %x2) #0 {1767; CHECK-LABEL: define <8 x float> @test_int_x86_avx512_maskz_cvt_ph2psx_256(1768; CHECK-SAME: <8 x half> [[X0:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {1769; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81770; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81771; CHECK-NEXT: call void @llvm.donothing()1772; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP1]] to i1281773; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 01774; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i8 [[TMP2]], 01775; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1776; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]1777; CHECK: [[BB4]]:1778; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1779; CHECK-NEXT: unreachable1780; CHECK: [[BB5]]:1781; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx512fp16.mask.vcvtph2psx.256(<8 x half> [[X0]], <8 x float> zeroinitializer, i8 [[X2]])1782; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81783; CHECK-NEXT: ret <8 x float> [[RES]]1784;1785 %res = call <8 x float> @llvm.x86.avx512fp16.mask.vcvtph2psx.256(<8 x half> %x0, <8 x float> zeroinitializer, i8 %x2)1786 ret <8 x float> %res1787}1788 1789declare <8 x half> @llvm.x86.avx512fp16.mask.vcvtps2phx.128(<4 x float>, <8 x half>, i8)1790 1791define <8 x half> @test_int_x86_avx512_mask_cvt_ps2phx_128(<4 x float> %x0, <8 x half> %x1, i8 %x2) #0 {1792; CHECK-LABEL: define <8 x half> @test_int_x86_avx512_mask_cvt_ps2phx_128(1793; CHECK-SAME: <4 x float> [[X0:%.*]], <8 x half> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {1794; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 81795; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81796; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81797; CHECK-NEXT: call void @llvm.donothing()1798; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP1]] to i1281799; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 01800; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP2]] to i1281801; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 01802; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1803; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 01804; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]1805; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]1806; CHECK: [[BB6]]:1807; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1808; CHECK-NEXT: unreachable1809; CHECK: [[BB7]]:1810; CHECK-NEXT: [[RES:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.vcvtps2phx.128(<4 x float> [[X0]], <8 x half> [[X1]], i8 [[X2]])1811; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x i32> [[TMP1]] to i1281812; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i128 [[TMP8]], 01813; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i16> [[TMP2]] to i1281814; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i128 [[TMP9]], 01815; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSCMP4]], [[_MSCMP5]]1816; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB10:.*]], label %[[BB11:.*]], !prof [[PROF1]]1817; CHECK: [[BB10]]:1818; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1819; CHECK-NEXT: unreachable1820; CHECK: [[BB11]]:1821; CHECK-NEXT: [[RES1:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.vcvtps2phx.128(<4 x float> [[X0]], <8 x half> [[X1]], i8 -1)1822; CHECK-NEXT: [[RES2:%.*]] = fadd <8 x half> [[RES]], [[RES1]]1823; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 81824; CHECK-NEXT: ret <8 x half> [[RES2]]1825;1826 %res = call <8 x half> @llvm.x86.avx512fp16.mask.vcvtps2phx.128(<4 x float> %x0, <8 x half> %x1, i8 %x2)1827 %res1 = call <8 x half> @llvm.x86.avx512fp16.mask.vcvtps2phx.128(<4 x float> %x0, <8 x half> %x1, i8 -1)1828 %res2 = fadd <8 x half> %res, %res11829 ret <8 x half> %res21830}1831 1832declare <8 x half> @llvm.x86.avx512fp16.mask.vcvtps2phx.256(<8 x float>, <8 x half>, i8)1833 1834define <8 x half> @test_int_x86_avx512_cvt_ps2phx_256(<8 x float> %x0) #0 {1835; CHECK-LABEL: define <8 x half> @test_int_x86_avx512_cvt_ps2phx_256(1836; CHECK-SAME: <8 x float> [[X0:%.*]]) #[[ATTR0]] {1837; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 81838; CHECK-NEXT: call void @llvm.donothing()1839; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1840; CHECK-NEXT: [[RES:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.vcvtps2phx.256(<8 x float> [[X0]], <8 x half> poison, i8 -1)1841; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 81842; CHECK-NEXT: ret <8 x half> [[RES]]1843;1844 %res = call <8 x half> @llvm.x86.avx512fp16.mask.vcvtps2phx.256(<8 x float> %x0, <8 x half> poison, i8 -1)1845 ret <8 x half> %res1846}1847 1848define <8 x half> @test_int_x86_avx512_mask_cvt_ps2phx_256(<8 x float> %x0, <8 x half> %x1, i8 %x2) #0 {1849; CHECK-LABEL: define <8 x half> @test_int_x86_avx512_mask_cvt_ps2phx_256(1850; CHECK-SAME: <8 x float> [[X0:%.*]], <8 x half> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {1851; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 81852; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81853; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 81854; CHECK-NEXT: call void @llvm.donothing()1855; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i32> [[TMP1]] to i2561856; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP4]], 01857; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP2]] to i1281858; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 01859; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1860; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 01861; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]1862; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]1863; CHECK: [[BB6]]:1864; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1865; CHECK-NEXT: unreachable1866; CHECK: [[BB7]]:1867; CHECK-NEXT: [[RES:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.vcvtps2phx.256(<8 x float> [[X0]], <8 x half> [[X1]], i8 [[X2]])1868; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 81869; CHECK-NEXT: ret <8 x half> [[RES]]1870;1871 %res = call <8 x half> @llvm.x86.avx512fp16.mask.vcvtps2phx.256(<8 x float> %x0, <8 x half> %x1, i8 %x2)1872 ret <8 x half> %res1873}1874 1875define <8 x half> @test_int_x86_avx512_maskz_cvt_ps2phx_256(<8 x float> %x0, i8 %x2) #0 {1876; CHECK-LABEL: define <8 x half> @test_int_x86_avx512_maskz_cvt_ps2phx_256(1877; CHECK-SAME: <8 x float> [[X0:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {1878; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 81879; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81880; CHECK-NEXT: call void @llvm.donothing()1881; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i32> [[TMP1]] to i2561882; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP3]], 01883; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i8 [[TMP2]], 01884; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1885; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]1886; CHECK: [[BB4]]:1887; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1888; CHECK-NEXT: unreachable1889; CHECK: [[BB5]]:1890; CHECK-NEXT: [[RES:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.vcvtps2phx.256(<8 x float> [[X0]], <8 x half> zeroinitializer, i8 [[X2]])1891; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 81892; CHECK-NEXT: ret <8 x half> [[RES]]1893;1894 %res = call <8 x half> @llvm.x86.avx512fp16.mask.vcvtps2phx.256(<8 x float> %x0, <8 x half> zeroinitializer, i8 %x2)1895 ret <8 x half> %res1896}1897 1898attributes #0 = { sanitize_memory }1899;.1900; CHECK: [[PROF1]] = !{!"branch_weights", i32 1, i32 1048575}1901;.1902