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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt %s -S -mattr=+avx512f -passes=msan 2>&1 | FileCheck %s3;4; Forked from llvm/test/CodeGen/X86/avx512fp16-intrinsics.ll5;6; Handled suboptimally (visitInstruction):7; - llvm.x86.avx512fp16.fpclass.ph.5128; - llvm.x86.avx512fp16.mask.add.sh.round9; - llvm.x86.avx512fp16.mask.cmp.sh10; - llvm.x86.avx512fp16.mask.div.sh.round11; - llvm.x86.avx512fp16.mask.fpclass.sh12; - llvm.x86.avx512fp16.mask.getexp.ph.51213; - llvm.x86.avx512fp16.mask.getexp.sh14; - llvm.x86.avx512fp16.mask.getmant.ph.51215; - llvm.x86.avx512fp16.mask.getmant.sh16; - llvm.x86.avx512fp16.mask.rcp.ph.51217; - llvm.x86.avx512fp16.mask.rcp.sh18; - llvm.x86.avx512fp16.mask.reduce.ph.51219; - llvm.x86.avx512fp16.mask.reduce.sh20; - llvm.x86.avx512fp16.mask.rndscale.sh21; - llvm.x86.avx512fp16.mask.rsqrt.sh22; - llvm.x86.avx512fp16.mask.scalef.ph.51223; - llvm.x86.avx512fp16.mask.scalef.sh24; - llvm.x86.avx512fp16.mask.sqrt.sh25; - llvm.x86.avx512fp16.mask.vcvtph2dq.51226; - llvm.x86.avx512fp16.mask.vcvtph2qq.51227; - llvm.x86.avx512fp16.mask.vcvtph2udq.51228; - llvm.x86.avx512fp16.mask.vcvtph2uqq.51229; - llvm.x86.avx512fp16.mask.vcvttph2dq.51230; - llvm.x86.avx512fp16.mask.vcvttph2udq.51231; - llvm.x86.avx512fp16.mask.vcvttph2uqq.51232; - llvm.x86.avx512fp16.sqrt.ph.51233; - llvm.x86.avx512fp16.vcomi.sh34; - llvm.x86.avx512fp16.vcvtsh2si3235; - llvm.x86.avx512fp16.vcvtsh2si6436; - llvm.x86.avx512fp16.vcvtsh2usi3237; - llvm.x86.avx512fp16.vcvtsh2usi6438; - llvm.x86.avx512fp16.vcvtsi2sh39; - llvm.x86.avx512fp16.vcvtsi642sh40; - llvm.x86.avx512fp16.vcvttsh2si3241; - llvm.x86.avx512fp16.vcvttsh2si6442; - llvm.x86.avx512fp16.vcvttsh2usi3243; - llvm.x86.avx512fp16.vcvttsh2usi6444; - llvm.x86.avx512fp16.vcvtusi2sh45; - llvm.x86.avx512fp16.vcvtusi642sh46; - llvm.x86.avx512.sitofp.round.v16f16.v16i3247; - llvm.x86.avx512.sitofp.round.v8f16.v8i6448; - llvm.x86.avx512.uitofp.round.v16f16.v16i3249; - llvm.x86.avx512.uitofp.round.v8f16.v8i6450;51; Handled heuristically:52; - llvm.sqrt.f1653; - llvm.sqrt.v32f1654 55target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"56target triple = "x86_64-unknown-linux-gnu"57 58declare i32 @llvm.x86.avx512fp16.vcomi.sh(<8 x half>, <8 x half>, i32, i32)59 60define i32 @test_x86_avx512fp16_ucomi_sh_lt(<8 x half> %a0, <8 x half> %a1) #0 {61; CHECK-LABEL: define i32 @test_x86_avx512fp16_ucomi_sh_lt(62; CHECK-SAME: <8 x half> [[A0:%.*]], <8 x half> [[A1:%.*]]) #[[ATTR1:[0-9]+]] {63; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 864; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 865; CHECK-NEXT: call void @llvm.donothing()66; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP1]] to i12867; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 068; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i16> [[TMP2]] to i12869; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 070; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]71; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1:![0-9]+]]72; CHECK: [[BB5]]:73; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8:[0-9]+]]74; CHECK-NEXT: unreachable75; CHECK: [[BB6]]:76; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx512fp16.vcomi.sh(<8 x half> [[A0]], <8 x half> [[A1]], i32 9, i32 4)77; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 878; CHECK-NEXT: ret i32 [[RES]]79;80 %res = call i32 @llvm.x86.avx512fp16.vcomi.sh(<8 x half> %a0, <8 x half> %a1, i32 9, i32 4)81 ret i32 %res82}83 84declare <32 x half> @llvm.x86.avx512fp16.sqrt.ph.512(<32 x half>, i32) nounwind readnone85 86define <32 x half> @test_sqrt_ph_512(<32 x half> %a0) #0 {87; CHECK-LABEL: define <32 x half> @test_sqrt_ph_512(88; CHECK-SAME: <32 x half> [[A0:%.*]]) #[[ATTR1]] {89; CHECK-NEXT: [[TMP1:%.*]] = load <32 x i16>, ptr @__msan_param_tls, align 890; CHECK-NEXT: call void @llvm.donothing()91; CHECK-NEXT: [[TMP2:%.*]] = call <32 x half> @llvm.sqrt.v32f16(<32 x half> [[A0]])92; CHECK-NEXT: store <32 x i16> [[TMP1]], ptr @__msan_retval_tls, align 893; CHECK-NEXT: ret <32 x half> [[TMP2]]94;95 %1 = call <32 x half> @llvm.sqrt.v32f16(<32 x half> %a0)96 ret <32 x half> %197}98 99define <32 x half> @test_sqrt_ph_512_fast(<32 x half> %a0, <32 x half> %a1) #0 {100; CHECK-LABEL: define <32 x half> @test_sqrt_ph_512_fast(101; CHECK-SAME: <32 x half> [[A0:%.*]], <32 x half> [[A1:%.*]]) #[[ATTR1]] {102; CHECK-NEXT: [[TMP1:%.*]] = load <32 x i16>, ptr @__msan_param_tls, align 8103; CHECK-NEXT: [[TMP2:%.*]] = load <32 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 8104; CHECK-NEXT: call void @llvm.donothing()105; CHECK-NEXT: [[TMP3:%.*]] = call fast <32 x half> @llvm.sqrt.v32f16(<32 x half> [[A0]])106; CHECK-NEXT: [[_MSPROP:%.*]] = or <32 x i16> [[TMP2]], [[TMP1]]107; CHECK-NEXT: [[TMP4:%.*]] = fdiv fast <32 x half> [[A1]], [[TMP3]]108; CHECK-NEXT: store <32 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8109; CHECK-NEXT: ret <32 x half> [[TMP4]]110;111 %1 = call fast <32 x half> @llvm.sqrt.v32f16(<32 x half> %a0)112 %2 = fdiv fast <32 x half> %a1, %1113 ret <32 x half> %2114}115 116define <32 x half> @test_sqrt_ph_512_fast_estimate_attribute(<32 x half> %a0, <32 x half> %a1) "reciprocal-estimates"="vec-sqrt" {117; CHECK-LABEL: define <32 x half> @test_sqrt_ph_512_fast_estimate_attribute(118; CHECK-SAME: <32 x half> [[A0:%.*]], <32 x half> [[A1:%.*]]) #[[ATTR2:[0-9]+]] {119; CHECK-NEXT: call void @llvm.donothing()120; CHECK-NEXT: [[TMP1:%.*]] = call fast <32 x half> @llvm.sqrt.v32f16(<32 x half> [[A0]])121; CHECK-NEXT: [[TMP2:%.*]] = fdiv fast <32 x half> [[A1]], [[TMP1]]122; CHECK-NEXT: store <32 x i16> zeroinitializer, ptr @__msan_retval_tls, align 8123; CHECK-NEXT: ret <32 x half> [[TMP2]]124;125 %1 = call fast <32 x half> @llvm.sqrt.v32f16(<32 x half> %a0)126 %2 = fdiv fast <32 x half> %a1, %1127 ret <32 x half> %2128}129 130define <32 x half> @test_sqrt_ph_512_fast_estimate_attribute_2(<32 x half> %a0, <32 x half> %a1) "reciprocal-estimates"="vec-sqrth:1" {131; CHECK-LABEL: define <32 x half> @test_sqrt_ph_512_fast_estimate_attribute_2(132; CHECK-SAME: <32 x half> [[A0:%.*]], <32 x half> [[A1:%.*]]) #[[ATTR3:[0-9]+]] {133; CHECK-NEXT: call void @llvm.donothing()134; CHECK-NEXT: [[TMP1:%.*]] = call fast <32 x half> @llvm.sqrt.v32f16(<32 x half> [[A0]])135; CHECK-NEXT: [[TMP2:%.*]] = fdiv fast <32 x half> [[A1]], [[TMP1]]136; CHECK-NEXT: store <32 x i16> zeroinitializer, ptr @__msan_retval_tls, align 8137; CHECK-NEXT: ret <32 x half> [[TMP2]]138;139 %1 = call fast <32 x half> @llvm.sqrt.v32f16(<32 x half> %a0)140 %2 = fdiv fast <32 x half> %a1, %1141 ret <32 x half> %2142}143 144define <32 x half> @test_mask_sqrt_ph_512(<32 x half> %a0, <32 x half> %passthru, i32 %mask) #0 {145; CHECK-LABEL: define <32 x half> @test_mask_sqrt_ph_512(146; CHECK-SAME: <32 x half> [[A0:%.*]], <32 x half> [[PASSTHRU:%.*]], i32 [[MASK:%.*]]) #[[ATTR1]] {147; CHECK-NEXT: [[TMP1:%.*]] = load <32 x i16>, ptr @__msan_param_tls, align 8148; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 8149; CHECK-NEXT: [[TMP3:%.*]] = load <32 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 8150; CHECK-NEXT: call void @llvm.donothing()151; CHECK-NEXT: [[TMP4:%.*]] = call <32 x half> @llvm.sqrt.v32f16(<32 x half> [[A0]])152; CHECK-NEXT: [[TMP5:%.*]] = bitcast i32 [[TMP2]] to <32 x i1>153; CHECK-NEXT: [[TMP6:%.*]] = bitcast i32 [[MASK]] to <32 x i1>154; CHECK-NEXT: [[TMP7:%.*]] = select <32 x i1> [[TMP6]], <32 x i16> [[TMP1]], <32 x i16> [[TMP3]]155; CHECK-NEXT: [[TMP8:%.*]] = bitcast <32 x half> [[TMP4]] to <32 x i16>156; CHECK-NEXT: [[TMP9:%.*]] = bitcast <32 x half> [[PASSTHRU]] to <32 x i16>157; CHECK-NEXT: [[TMP10:%.*]] = xor <32 x i16> [[TMP8]], [[TMP9]]158; CHECK-NEXT: [[TMP11:%.*]] = or <32 x i16> [[TMP10]], [[TMP1]]159; CHECK-NEXT: [[TMP12:%.*]] = or <32 x i16> [[TMP11]], [[TMP3]]160; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <32 x i1> [[TMP5]], <32 x i16> [[TMP12]], <32 x i16> [[TMP7]]161; CHECK-NEXT: [[TMP13:%.*]] = select <32 x i1> [[TMP6]], <32 x half> [[TMP4]], <32 x half> [[PASSTHRU]]162; CHECK-NEXT: store <32 x i16> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 8163; CHECK-NEXT: ret <32 x half> [[TMP13]]164;165 %1 = call <32 x half> @llvm.sqrt.v32f16(<32 x half> %a0)166 %2 = bitcast i32 %mask to <32 x i1>167 %3 = select <32 x i1> %2, <32 x half> %1, <32 x half> %passthru168 ret <32 x half> %3169}170 171define <32 x half> @test_maskz_sqrt_ph_512(<32 x half> %a0, i32 %mask) #0 {172; CHECK-LABEL: define <32 x half> @test_maskz_sqrt_ph_512(173; CHECK-SAME: <32 x half> [[A0:%.*]], i32 [[MASK:%.*]]) #[[ATTR1]] {174; CHECK-NEXT: [[TMP1:%.*]] = load <32 x i16>, ptr @__msan_param_tls, align 8175; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 8176; CHECK-NEXT: call void @llvm.donothing()177; CHECK-NEXT: [[TMP3:%.*]] = call <32 x half> @llvm.sqrt.v32f16(<32 x half> [[A0]])178; CHECK-NEXT: [[TMP4:%.*]] = bitcast i32 [[TMP2]] to <32 x i1>179; CHECK-NEXT: [[TMP5:%.*]] = bitcast i32 [[MASK]] to <32 x i1>180; CHECK-NEXT: [[TMP6:%.*]] = select <32 x i1> [[TMP5]], <32 x i16> [[TMP1]], <32 x i16> zeroinitializer181; CHECK-NEXT: [[TMP7:%.*]] = bitcast <32 x half> [[TMP3]] to <32 x i16>182; CHECK-NEXT: [[TMP8:%.*]] = xor <32 x i16> [[TMP7]], zeroinitializer183; CHECK-NEXT: [[TMP9:%.*]] = or <32 x i16> [[TMP8]], [[TMP1]]184; CHECK-NEXT: [[TMP10:%.*]] = or <32 x i16> [[TMP9]], zeroinitializer185; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <32 x i1> [[TMP4]], <32 x i16> [[TMP10]], <32 x i16> [[TMP6]]186; CHECK-NEXT: [[TMP11:%.*]] = select <32 x i1> [[TMP5]], <32 x half> [[TMP3]], <32 x half> zeroinitializer187; CHECK-NEXT: store <32 x i16> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 8188; CHECK-NEXT: ret <32 x half> [[TMP11]]189;190 %1 = call <32 x half> @llvm.sqrt.v32f16(<32 x half> %a0)191 %2 = bitcast i32 %mask to <32 x i1>192 %3 = select <32 x i1> %2, <32 x half> %1, <32 x half> zeroinitializer193 ret <32 x half> %3194}195 196declare <32 x half> @llvm.sqrt.v32f16(<32 x half>)197 198define <32 x half> @test_sqrt_round_ph_512(<32 x half> %a0) #0 {199; CHECK-LABEL: define <32 x half> @test_sqrt_round_ph_512(200; CHECK-SAME: <32 x half> [[A0:%.*]]) #[[ATTR1]] {201; CHECK-NEXT: [[TMP1:%.*]] = load <32 x i16>, ptr @__msan_param_tls, align 8202; CHECK-NEXT: call void @llvm.donothing()203; CHECK-NEXT: [[TMP2:%.*]] = bitcast <32 x i16> [[TMP1]] to i512204; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP2]], 0205; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]206; CHECK: [[BB3]]:207; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]208; CHECK-NEXT: unreachable209; CHECK: [[BB4]]:210; CHECK-NEXT: [[TMP5:%.*]] = call <32 x half> @llvm.x86.avx512fp16.sqrt.ph.512(<32 x half> [[A0]], i32 11)211; CHECK-NEXT: store <32 x i16> zeroinitializer, ptr @__msan_retval_tls, align 8212; CHECK-NEXT: ret <32 x half> [[TMP5]]213;214 %1 = call <32 x half> @llvm.x86.avx512fp16.sqrt.ph.512(<32 x half> %a0, i32 11)215 ret <32 x half> %1216}217 218define <32 x half> @test_mask_sqrt_round_ph_512(<32 x half> %a0, <32 x half> %passthru, i32 %mask) #0 {219; CHECK-LABEL: define <32 x half> @test_mask_sqrt_round_ph_512(220; CHECK-SAME: <32 x half> [[A0:%.*]], <32 x half> [[PASSTHRU:%.*]], i32 [[MASK:%.*]]) #[[ATTR1]] {221; CHECK-NEXT: [[TMP1:%.*]] = load <32 x i16>, ptr @__msan_param_tls, align 8222; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 8223; CHECK-NEXT: [[TMP3:%.*]] = load <32 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 8224; CHECK-NEXT: call void @llvm.donothing()225; CHECK-NEXT: [[TMP4:%.*]] = bitcast <32 x i16> [[TMP1]] to i512226; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP4]], 0227; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]228; CHECK: [[BB5]]:229; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]230; CHECK-NEXT: unreachable231; CHECK: [[BB6]]:232; CHECK-NEXT: [[TMP7:%.*]] = call <32 x half> @llvm.x86.avx512fp16.sqrt.ph.512(<32 x half> [[A0]], i32 11)233; CHECK-NEXT: [[TMP8:%.*]] = bitcast i32 [[TMP2]] to <32 x i1>234; CHECK-NEXT: [[TMP9:%.*]] = bitcast i32 [[MASK]] to <32 x i1>235; CHECK-NEXT: [[TMP10:%.*]] = select <32 x i1> [[TMP9]], <32 x i16> zeroinitializer, <32 x i16> [[TMP3]]236; CHECK-NEXT: [[TMP11:%.*]] = bitcast <32 x half> [[TMP7]] to <32 x i16>237; CHECK-NEXT: [[TMP12:%.*]] = bitcast <32 x half> [[PASSTHRU]] to <32 x i16>238; CHECK-NEXT: [[TMP13:%.*]] = xor <32 x i16> [[TMP11]], [[TMP12]]239; CHECK-NEXT: [[TMP14:%.*]] = or <32 x i16> [[TMP13]], zeroinitializer240; CHECK-NEXT: [[TMP15:%.*]] = or <32 x i16> [[TMP14]], [[TMP3]]241; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <32 x i1> [[TMP8]], <32 x i16> [[TMP15]], <32 x i16> [[TMP10]]242; CHECK-NEXT: [[TMP16:%.*]] = select <32 x i1> [[TMP9]], <32 x half> [[TMP7]], <32 x half> [[PASSTHRU]]243; CHECK-NEXT: store <32 x i16> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 8244; CHECK-NEXT: ret <32 x half> [[TMP16]]245;246 %1 = call <32 x half> @llvm.x86.avx512fp16.sqrt.ph.512(<32 x half> %a0, i32 11)247 %2 = bitcast i32 %mask to <32 x i1>248 %3 = select <32 x i1> %2, <32 x half> %1, <32 x half> %passthru249 ret <32 x half> %3250}251 252define <32 x half> @test_maskz_sqrt_round_ph_512(<32 x half> %a0, i32 %mask) #0 {253; CHECK-LABEL: define <32 x half> @test_maskz_sqrt_round_ph_512(254; CHECK-SAME: <32 x half> [[A0:%.*]], i32 [[MASK:%.*]]) #[[ATTR1]] {255; CHECK-NEXT: [[TMP1:%.*]] = load <32 x i16>, ptr @__msan_param_tls, align 8256; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 8257; CHECK-NEXT: call void @llvm.donothing()258; CHECK-NEXT: [[TMP3:%.*]] = bitcast <32 x i16> [[TMP1]] to i512259; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP3]], 0260; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]261; CHECK: [[BB4]]:262; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]263; CHECK-NEXT: unreachable264; CHECK: [[BB5]]:265; CHECK-NEXT: [[TMP6:%.*]] = call <32 x half> @llvm.x86.avx512fp16.sqrt.ph.512(<32 x half> [[A0]], i32 11)266; CHECK-NEXT: [[TMP7:%.*]] = bitcast i32 [[TMP2]] to <32 x i1>267; CHECK-NEXT: [[TMP8:%.*]] = bitcast i32 [[MASK]] to <32 x i1>268; CHECK-NEXT: [[TMP9:%.*]] = select <32 x i1> [[TMP8]], <32 x i16> zeroinitializer, <32 x i16> zeroinitializer269; CHECK-NEXT: [[TMP10:%.*]] = bitcast <32 x half> [[TMP6]] to <32 x i16>270; CHECK-NEXT: [[TMP11:%.*]] = xor <32 x i16> [[TMP10]], zeroinitializer271; CHECK-NEXT: [[TMP12:%.*]] = or <32 x i16> [[TMP11]], zeroinitializer272; CHECK-NEXT: [[TMP13:%.*]] = or <32 x i16> [[TMP12]], zeroinitializer273; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <32 x i1> [[TMP7]], <32 x i16> [[TMP13]], <32 x i16> [[TMP9]]274; CHECK-NEXT: [[TMP14:%.*]] = select <32 x i1> [[TMP8]], <32 x half> [[TMP6]], <32 x half> zeroinitializer275; CHECK-NEXT: store <32 x i16> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 8276; CHECK-NEXT: ret <32 x half> [[TMP14]]277;278 %1 = call <32 x half> @llvm.x86.avx512fp16.sqrt.ph.512(<32 x half> %a0, i32 11)279 %2 = bitcast i32 %mask to <32 x i1>280 %3 = select <32 x i1> %2, <32 x half> %1, <32 x half> zeroinitializer281 ret <32 x half> %3282}283 284declare <8 x half> @llvm.x86.avx512fp16.mask.sqrt.sh(<8 x half>, <8 x half>, <8 x half>, i8, i32) nounwind readnone285 286define <8 x half> @test_sqrt_sh(<8 x half> %a0, <8 x half> %a1, <8 x half> %a2, i8 %mask) #0 {287; CHECK-LABEL: define <8 x half> @test_sqrt_sh(288; CHECK-SAME: <8 x half> [[A0:%.*]], <8 x half> [[A1:%.*]], <8 x half> [[A2:%.*]], i8 [[MASK:%.*]]) #[[ATTR1]] {289; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8290; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8291; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8292; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 8293; CHECK-NEXT: call void @llvm.donothing()294; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP1]] to i128295; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 0296; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i16> [[TMP2]] to i128297; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP6]], 0298; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]299; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i16> [[TMP3]] to i128300; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 0301; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]302; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 0303; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]304; CHECK-NEXT: br i1 [[_MSOR5]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]305; CHECK: [[BB8]]:306; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]307; CHECK-NEXT: unreachable308; CHECK: [[BB9]]:309; CHECK-NEXT: [[RES:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.sqrt.sh(<8 x half> [[A0]], <8 x half> [[A1]], <8 x half> [[A2]], i8 [[MASK]], i32 4)310; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 8311; CHECK-NEXT: ret <8 x half> [[RES]]312;313 %res = call <8 x half> @llvm.x86.avx512fp16.mask.sqrt.sh(<8 x half> %a0, <8 x half> %a1, <8 x half> %a2, i8 %mask, i32 4)314 ret <8 x half> %res315}316 317define half @test_sqrt_sh2(half %a0, half %a1) #0 {318; CHECK-LABEL: define half @test_sqrt_sh2(319; CHECK-SAME: half [[A0:%.*]], half [[A1:%.*]]) #[[ATTR1]] {320; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8321; CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8322; CHECK-NEXT: call void @llvm.donothing()323; CHECK-NEXT: [[TMP3:%.*]] = call fast half @llvm.sqrt.f16(half [[A0]])324; CHECK-NEXT: [[_MSPROP:%.*]] = or i16 [[TMP2]], [[TMP1]]325; CHECK-NEXT: [[TMP4:%.*]] = fdiv fast half [[A1]], [[TMP3]]326; CHECK-NEXT: store i16 [[_MSPROP]], ptr @__msan_retval_tls, align 8327; CHECK-NEXT: ret half [[TMP4]]328;329 %1 = call fast half @llvm.sqrt.f16(half %a0)330 %2 = fdiv fast half %a1, %1331 ret half %2332}333 334define half @test_sqrt_sh3(half %a0, half %a1) #0 {335; CHECK-LABEL: define half @test_sqrt_sh3(336; CHECK-SAME: half [[A0:%.*]], half [[A1:%.*]]) #[[ATTR1]] {337; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8338; CHECK-NEXT: call void @llvm.donothing()339; CHECK-NEXT: [[TMP2:%.*]] = call fast half @llvm.sqrt.f16(half [[A0]])340; CHECK-NEXT: store i16 [[TMP1]], ptr @__msan_retval_tls, align 8341; CHECK-NEXT: ret half [[TMP2]]342;343 %1 = call fast half @llvm.sqrt.f16(half %a0)344 ret half %1345}346 347declare half @llvm.sqrt.f16(half)348 349define <8 x half> @test_sqrt_sh_r(<8 x half> %a0, <8 x half> %a1, <8 x half> %a2, i8 %mask) #0 {350; CHECK-LABEL: define <8 x half> @test_sqrt_sh_r(351; CHECK-SAME: <8 x half> [[A0:%.*]], <8 x half> [[A1:%.*]], <8 x half> [[A2:%.*]], i8 [[MASK:%.*]]) #[[ATTR1]] {352; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8353; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8354; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8355; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 8356; CHECK-NEXT: call void @llvm.donothing()357; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP1]] to i128358; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 0359; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i16> [[TMP2]] to i128360; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP6]], 0361; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]362; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i16> [[TMP3]] to i128363; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 0364; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]365; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 0366; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]367; CHECK-NEXT: br i1 [[_MSOR5]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]368; CHECK: [[BB8]]:369; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]370; CHECK-NEXT: unreachable371; CHECK: [[BB9]]:372; CHECK-NEXT: [[RES:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.sqrt.sh(<8 x half> [[A0]], <8 x half> [[A1]], <8 x half> [[A2]], i8 [[MASK]], i32 10)373; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 8374; CHECK-NEXT: ret <8 x half> [[RES]]375;376 %res = call <8 x half> @llvm.x86.avx512fp16.mask.sqrt.sh(<8 x half> %a0, <8 x half> %a1, <8 x half> %a2, i8 %mask, i32 10)377 ret <8 x half> %res378}379 380define <8 x half> @test_sqrt_sh_nomask(<8 x half> %a0, <8 x half> %a1, <8 x half> %a2) #0 {381; CHECK-LABEL: define <8 x half> @test_sqrt_sh_nomask(382; CHECK-SAME: <8 x half> [[A0:%.*]], <8 x half> [[A1:%.*]], <8 x half> [[A2:%.*]]) #[[ATTR1]] {383; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8384; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8385; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8386; CHECK-NEXT: call void @llvm.donothing()387; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i16> [[TMP1]] to i128388; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 0389; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP2]] to i128390; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 0391; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]392; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i16> [[TMP3]] to i128393; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP6]], 0394; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]395; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]396; CHECK: [[BB7]]:397; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]398; CHECK-NEXT: unreachable399; CHECK: [[BB8]]:400; CHECK-NEXT: [[RES:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.sqrt.sh(<8 x half> [[A0]], <8 x half> [[A1]], <8 x half> [[A2]], i8 -1, i32 4)401; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 8402; CHECK-NEXT: ret <8 x half> [[RES]]403;404 %res = call <8 x half> @llvm.x86.avx512fp16.mask.sqrt.sh(<8 x half> %a0, <8 x half> %a1, <8 x half> %a2, i8 -1, i32 4)405 ret <8 x half> %res406}407 408define <8 x half> @test_sqrt_sh_z(<8 x half> %a0, <8 x half> %a1, <8 x half> %a2, i8 %mask) #0 {409; CHECK-LABEL: define <8 x half> @test_sqrt_sh_z(410; CHECK-SAME: <8 x half> [[A0:%.*]], <8 x half> [[A1:%.*]], <8 x half> [[A2:%.*]], i8 [[MASK:%.*]]) #[[ATTR1]] {411; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8412; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8413; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 8414; CHECK-NEXT: call void @llvm.donothing()415; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i16> [[TMP1]] to i128416; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 0417; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP2]] to i128418; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 0419; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]420; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 0421; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]422; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]423; CHECK: [[BB6]]:424; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]425; CHECK-NEXT: unreachable426; CHECK: [[BB7]]:427; CHECK-NEXT: [[RES:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.sqrt.sh(<8 x half> [[A0]], <8 x half> [[A1]], <8 x half> zeroinitializer, i8 [[MASK]], i32 10)428; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 8429; CHECK-NEXT: ret <8 x half> [[RES]]430;431 %res = call <8 x half> @llvm.x86.avx512fp16.mask.sqrt.sh(<8 x half> %a0, <8 x half> %a1, <8 x half> zeroinitializer, i8 %mask, i32 10)432 ret <8 x half> %res433}434 435declare <32 x half> @llvm.x86.avx512fp16.mask.rsqrt.ph.512(<32 x half>, <32 x half>, i32)436declare <8 x half> @llvm.x86.avx512fp16.mask.rsqrt.sh(<8 x half>, <8 x half>, <8 x half>, i8)437 438define <32 x half> @test_rsqrt_ph_512(<32 x half> %a0) #0 {439; CHECK-LABEL: define <32 x half> @test_rsqrt_ph_512(440; CHECK-SAME: <32 x half> [[A0:%.*]]) #[[ATTR1]] {441; CHECK-NEXT: [[TMP1:%.*]] = load <32 x i16>, ptr @__msan_param_tls, align 8442; CHECK-NEXT: call void @llvm.donothing()443; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <32 x i16> [[TMP1]], zeroinitializer444; CHECK-NEXT: [[TMP3:%.*]] = sext <32 x i1> [[TMP2]] to <32 x i16>445; CHECK-NEXT: [[TMP4:%.*]] = select <32 x i1> splat (i1 true), <32 x i16> [[TMP3]], <32 x i16> zeroinitializer446; CHECK-NEXT: [[RES:%.*]] = call <32 x half> @llvm.x86.avx512fp16.mask.rsqrt.ph.512(<32 x half> [[A0]], <32 x half> zeroinitializer, i32 -1)447; CHECK-NEXT: store <32 x i16> [[TMP4]], ptr @__msan_retval_tls, align 8448; CHECK-NEXT: ret <32 x half> [[RES]]449;450 %res = call <32 x half> @llvm.x86.avx512fp16.mask.rsqrt.ph.512(<32 x half> %a0, <32 x half> zeroinitializer, i32 -1)451 ret <32 x half> %res452}453 454define <8 x half> @test_rsqrt_sh(<8 x half> %a0, <8 x half> %a1, <8 x half> %a2) #0 {455; CHECK-LABEL: define <8 x half> @test_rsqrt_sh(456; CHECK-SAME: <8 x half> [[A0:%.*]], <8 x half> [[A1:%.*]], <8 x half> [[A2:%.*]]) #[[ATTR1]] {457; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8458; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8459; CHECK-NEXT: call void @llvm.donothing()460; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP1]] to i128461; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 0462; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i16> [[TMP1]] to i128463; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 0464; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]465; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP2]] to i128466; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP5]], 0467; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]468; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]469; CHECK: [[BB6]]:470; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]471; CHECK-NEXT: unreachable472; CHECK: [[BB7]]:473; CHECK-NEXT: [[RES:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.rsqrt.sh(<8 x half> [[A0]], <8 x half> [[A0]], <8 x half> [[A2]], i8 -1)474; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 8475; CHECK-NEXT: ret <8 x half> [[RES]]476;477 %res = call <8 x half> @llvm.x86.avx512fp16.mask.rsqrt.sh(<8 x half> %a0, <8 x half> %a0, <8 x half> %a2, i8 -1)478 ret <8 x half> %res479}480 481define <8 x half> @test_rsqrt_sh_load(<8 x half> %a0, ptr %a1ptr) #0 {482; CHECK-LABEL: define <8 x half> @test_rsqrt_sh_load(483; CHECK-SAME: <8 x half> [[A0:%.*]], ptr [[A1PTR:%.*]]) #[[ATTR1]] {484; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8485; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8486; CHECK-NEXT: call void @llvm.donothing()487; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0488; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]489; CHECK: [[BB3]]:490; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]491; CHECK-NEXT: unreachable492; CHECK: [[BB4]]:493; CHECK-NEXT: [[A1:%.*]] = load <8 x half>, ptr [[A1PTR]], align 16494; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A1PTR]] to i64495; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 87960930222080496; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr497; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP7]], align 16498; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i16> [[TMP2]] to i128499; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP8]], 0500; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i16> [[_MSLD]] to i128501; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP9]], 0502; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP1]], [[_MSCMP2]]503; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]504; CHECK-NEXT: [[RES:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.rsqrt.sh(<8 x half> [[A0]], <8 x half> [[A1]], <8 x half> poison, i8 -1)505; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 8506; CHECK-NEXT: ret <8 x half> [[RES]]507;508 %a1 = load <8 x half>, ptr %a1ptr509 %res = call <8 x half> @llvm.x86.avx512fp16.mask.rsqrt.sh(<8 x half> %a0, <8 x half> %a1, <8 x half> poison, i8 -1)510 ret <8 x half> %res511}512 513define <8 x half> @test_rsqrt_sh_maskz(<8 x half> %a0, i8 %mask) #0 {514; CHECK-LABEL: define <8 x half> @test_rsqrt_sh_maskz(515; CHECK-SAME: <8 x half> [[A0:%.*]], i8 [[MASK:%.*]]) #[[ATTR1]] {516; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8517; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8518; CHECK-NEXT: call void @llvm.donothing()519; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP1]] to i128520; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 0521; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i16> [[TMP1]] to i128522; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 0523; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]524; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP2]], 0525; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]526; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]527; CHECK: [[BB5]]:528; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]529; CHECK-NEXT: unreachable530; CHECK: [[BB6]]:531; CHECK-NEXT: [[RES:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.rsqrt.sh(<8 x half> [[A0]], <8 x half> [[A0]], <8 x half> zeroinitializer, i8 [[MASK]])532; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 8533; CHECK-NEXT: ret <8 x half> [[RES]]534;535 %res = call <8 x half> @llvm.x86.avx512fp16.mask.rsqrt.sh(<8 x half> %a0, <8 x half> %a0, <8 x half> zeroinitializer, i8 %mask)536 ret <8 x half> %res537}538 539define <8 x half> @test_rsqrt_sh_mask(<8 x half> %a0, <8 x half> %b0, <8 x half> %c0, i8 %mask) #0 {540; CHECK-LABEL: define <8 x half> @test_rsqrt_sh_mask(541; CHECK-SAME: <8 x half> [[A0:%.*]], <8 x half> [[B0:%.*]], <8 x half> [[C0:%.*]], i8 [[MASK:%.*]]) #[[ATTR1]] {542; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8543; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8544; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8545; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 8546; CHECK-NEXT: call void @llvm.donothing()547; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP1]] to i128548; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 0549; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i16> [[TMP2]] to i128550; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP6]], 0551; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]552; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i16> [[TMP3]] to i128553; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 0554; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]555; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 0556; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]557; CHECK-NEXT: br i1 [[_MSOR5]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]558; CHECK: [[BB8]]:559; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]560; CHECK-NEXT: unreachable561; CHECK: [[BB9]]:562; CHECK-NEXT: [[RES:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.rsqrt.sh(<8 x half> [[A0]], <8 x half> [[B0]], <8 x half> [[C0]], i8 [[MASK]])563; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 8564; CHECK-NEXT: ret <8 x half> [[RES]]565;566 %res = call <8 x half> @llvm.x86.avx512fp16.mask.rsqrt.sh(<8 x half> %a0, <8 x half> %b0, <8 x half> %c0, i8 %mask)567 ret <8 x half> %res568}569 570declare <32 x i1> @llvm.x86.avx512fp16.fpclass.ph.512(<32 x half>, i32)571 572define i32 @test_int_x86_avx512_fpclass_ph_512(<32 x half> %x0) #0 {573; CHECK-LABEL: define i32 @test_int_x86_avx512_fpclass_ph_512(574; CHECK-SAME: <32 x half> [[X0:%.*]]) #[[ATTR1]] {575; CHECK-NEXT: [[TMP1:%.*]] = load <32 x i16>, ptr @__msan_param_tls, align 8576; CHECK-NEXT: call void @llvm.donothing()577; CHECK-NEXT: [[TMP2:%.*]] = bitcast <32 x i16> [[TMP1]] to i512578; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP2]], 0579; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]580; CHECK: [[BB3]]:581; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]582; CHECK-NEXT: unreachable583; CHECK: [[BB4]]:584; CHECK-NEXT: [[RES:%.*]] = call <32 x i1> @llvm.x86.avx512fp16.fpclass.ph.512(<32 x half> [[X0]], i32 4)585; CHECK-NEXT: [[TMP5:%.*]] = bitcast <32 x i16> [[TMP1]] to i512586; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP5]], 0587; CHECK-NEXT: br i1 [[_MSCMP1]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]588; CHECK: [[BB6]]:589; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]590; CHECK-NEXT: unreachable591; CHECK: [[BB7]]:592; CHECK-NEXT: [[RES1:%.*]] = call <32 x i1> @llvm.x86.avx512fp16.fpclass.ph.512(<32 x half> [[X0]], i32 2)593; CHECK-NEXT: [[TMP8:%.*]] = and <32 x i1> [[RES1]], zeroinitializer594; CHECK-NEXT: [[TMP9:%.*]] = and <32 x i1> zeroinitializer, [[RES]]595; CHECK-NEXT: [[TMP10:%.*]] = or <32 x i1> zeroinitializer, [[TMP8]]596; CHECK-NEXT: [[TMP11:%.*]] = or <32 x i1> [[TMP10]], [[TMP9]]597; CHECK-NEXT: [[TMP12:%.*]] = and <32 x i1> [[RES1]], [[RES]]598; CHECK-NEXT: [[TMP13:%.*]] = bitcast <32 x i1> [[TMP11]] to i32599; CHECK-NEXT: [[TMP14:%.*]] = bitcast <32 x i1> [[TMP12]] to i32600; CHECK-NEXT: store i32 [[TMP13]], ptr @__msan_retval_tls, align 8601; CHECK-NEXT: ret i32 [[TMP14]]602;603 %res = call <32 x i1> @llvm.x86.avx512fp16.fpclass.ph.512(<32 x half> %x0, i32 4)604 %res1 = call <32 x i1> @llvm.x86.avx512fp16.fpclass.ph.512(<32 x half> %x0, i32 2)605 %1 = and <32 x i1> %res1, %res606 %2 = bitcast <32 x i1> %1 to i32607 ret i32 %2608}609 610declare i8 @llvm.x86.avx512fp16.mask.fpclass.sh(<8 x half>, i32, i8)611 612define i8 @test_int_x86_avx512_mask_fpclass_sh(<8 x half> %x0) #0 {613; CHECK-LABEL: define i8 @test_int_x86_avx512_mask_fpclass_sh(614; CHECK-SAME: <8 x half> [[X0:%.*]]) #[[ATTR1]] {615; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8616; CHECK-NEXT: call void @llvm.donothing()617; CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i16> [[TMP1]] to i128618; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 0619; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]620; CHECK: [[BB3]]:621; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]622; CHECK-NEXT: unreachable623; CHECK: [[BB4]]:624; CHECK-NEXT: [[RES:%.*]] = call i8 @llvm.x86.avx512fp16.mask.fpclass.sh(<8 x half> [[X0]], i32 2, i8 -1)625; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP1]] to i128626; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 0627; CHECK-NEXT: br i1 [[_MSCMP1]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]628; CHECK: [[BB6]]:629; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]630; CHECK-NEXT: unreachable631; CHECK: [[BB7]]:632; CHECK-NEXT: [[RES1:%.*]] = call i8 @llvm.x86.avx512fp16.mask.fpclass.sh(<8 x half> [[X0]], i32 4, i8 [[RES]])633; CHECK-NEXT: store i8 0, ptr @__msan_retval_tls, align 8634; CHECK-NEXT: ret i8 [[RES1]]635;636 %res = call i8 @llvm.x86.avx512fp16.mask.fpclass.sh(<8 x half> %x0, i32 2, i8 -1)637 %res1 = call i8 @llvm.x86.avx512fp16.mask.fpclass.sh(<8 x half> %x0, i32 4, i8 %res)638 ret i8 %res1639}640 641define i8 @test_int_x86_avx512_mask_fpclass_sh_load(ptr %x0ptr) #0 {642; CHECK-LABEL: define i8 @test_int_x86_avx512_mask_fpclass_sh_load(643; CHECK-SAME: ptr [[X0PTR:%.*]]) #[[ATTR1]] {644; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8645; CHECK-NEXT: call void @llvm.donothing()646; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0647; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB2:.*]], label %[[BB3:.*]], !prof [[PROF1]]648; CHECK: [[BB2]]:649; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]650; CHECK-NEXT: unreachable651; CHECK: [[BB3]]:652; CHECK-NEXT: [[X0:%.*]] = load <8 x half>, ptr [[X0PTR]], align 16653; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[X0PTR]] to i64654; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 87960930222080655; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr656; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP6]], align 16657; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i16> [[_MSLD]] to i128658; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP7]], 0659; CHECK-NEXT: br i1 [[_MSCMP1]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]660; CHECK: [[BB8]]:661; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]662; CHECK-NEXT: unreachable663; CHECK: [[BB9]]:664; CHECK-NEXT: [[RES:%.*]] = call i8 @llvm.x86.avx512fp16.mask.fpclass.sh(<8 x half> [[X0]], i32 4, i8 -1)665; CHECK-NEXT: store i8 0, ptr @__msan_retval_tls, align 8666; CHECK-NEXT: ret i8 [[RES]]667;668 %x0 = load <8 x half>, ptr %x0ptr669 %res = call i8 @llvm.x86.avx512fp16.mask.fpclass.sh(<8 x half> %x0, i32 4, i8 -1)670 ret i8 %res671}672 673declare <32 x half> @llvm.x86.avx512fp16.mask.rcp.ph.512(<32 x half>, <32 x half>, i32)674 675define <32 x half> @test_rcp_ph_512(<32 x half> %a0, <32 x half> %a1, i32 %mask) #0 {676; CHECK-LABEL: define <32 x half> @test_rcp_ph_512(677; CHECK-SAME: <32 x half> [[A0:%.*]], <32 x half> [[A1:%.*]], i32 [[MASK:%.*]]) #[[ATTR1]] {678; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 8679; CHECK-NEXT: [[TMP1:%.*]] = load <32 x i16>, ptr @__msan_param_tls, align 8680; CHECK-NEXT: [[TMP2:%.*]] = load <32 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 8681; CHECK-NEXT: call void @llvm.donothing()682; CHECK-NEXT: [[TMP4:%.*]] = bitcast i32 [[MASK]] to <32 x i1>683; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <32 x i16> [[TMP1]], zeroinitializer684; CHECK-NEXT: [[TMP6:%.*]] = sext <32 x i1> [[TMP5]] to <32 x i16>685; CHECK-NEXT: [[TMP7:%.*]] = select <32 x i1> [[TMP4]], <32 x i16> [[TMP6]], <32 x i16> [[TMP2]]686; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i32 [[TMP3]], 0687; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]688; CHECK: [[BB8]]:689; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]690; CHECK-NEXT: unreachable691; CHECK: [[BB9]]:692; CHECK-NEXT: [[RES:%.*]] = call <32 x half> @llvm.x86.avx512fp16.mask.rcp.ph.512(<32 x half> [[A0]], <32 x half> [[A1]], i32 [[MASK]])693; CHECK-NEXT: store <32 x i16> [[TMP7]], ptr @__msan_retval_tls, align 8694; CHECK-NEXT: ret <32 x half> [[RES]]695;696 %res = call <32 x half> @llvm.x86.avx512fp16.mask.rcp.ph.512(<32 x half> %a0, <32 x half> %a1, i32 %mask)697 ret <32 x half> %res698}699 700declare <8 x half> @llvm.x86.avx512fp16.mask.rcp.sh(<8 x half>, <8 x half>, <8 x half>, i8)701 702define <8 x half> @test_rcp_sh(<8 x half> %a0) #0 {703; CHECK-LABEL: define <8 x half> @test_rcp_sh(704; CHECK-SAME: <8 x half> [[A0:%.*]]) #[[ATTR1]] {705; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8706; CHECK-NEXT: call void @llvm.donothing()707; CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i16> [[TMP1]] to i128708; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 0709; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP1]] to i128710; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP3]], 0711; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]712; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]713; CHECK: [[BB4]]:714; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]715; CHECK-NEXT: unreachable716; CHECK: [[BB5]]:717; CHECK-NEXT: [[RES:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.rcp.sh(<8 x half> [[A0]], <8 x half> [[A0]], <8 x half> zeroinitializer, i8 -1)718; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 8719; CHECK-NEXT: ret <8 x half> [[RES]]720;721 %res = call <8 x half> @llvm.x86.avx512fp16.mask.rcp.sh(<8 x half> %a0, <8 x half> %a0, <8 x half> zeroinitializer, i8 -1)722 ret <8 x half> %res723}724 725define <8 x half> @test_rcp_sh_load(<8 x half> %a0, ptr %a1ptr) #0 {726; CHECK-LABEL: define <8 x half> @test_rcp_sh_load(727; CHECK-SAME: <8 x half> [[A0:%.*]], ptr [[A1PTR:%.*]]) #[[ATTR1]] {728; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8729; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8730; CHECK-NEXT: call void @llvm.donothing()731; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0732; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]733; CHECK: [[BB3]]:734; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]735; CHECK-NEXT: unreachable736; CHECK: [[BB4]]:737; CHECK-NEXT: [[A1:%.*]] = load <8 x half>, ptr [[A1PTR]], align 16738; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A1PTR]] to i64739; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 87960930222080740; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr741; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP7]], align 16742; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i16> [[TMP2]] to i128743; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP8]], 0744; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i16> [[_MSLD]] to i128745; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP9]], 0746; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP1]], [[_MSCMP2]]747; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB10:.*]], label %[[BB11:.*]], !prof [[PROF1]]748; CHECK: [[BB10]]:749; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]750; CHECK-NEXT: unreachable751; CHECK: [[BB11]]:752; CHECK-NEXT: [[RES:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.rcp.sh(<8 x half> [[A0]], <8 x half> [[A1]], <8 x half> zeroinitializer, i8 -1)753; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 8754; CHECK-NEXT: ret <8 x half> [[RES]]755;756 %a1 = load <8 x half>, ptr %a1ptr757 %res = call <8 x half> @llvm.x86.avx512fp16.mask.rcp.sh(<8 x half> %a0, <8 x half> %a1, <8 x half> zeroinitializer, i8 -1)758 ret <8 x half> %res759}760 761declare <32 x half> @llvm.x86.avx512fp16.mask.reduce.ph.512(<32 x half>, i32, <32 x half>, i32, i32)762 763define <32 x half>@test_int_x86_avx512_mask_reduce_ph_512(<32 x half> %x0, <32 x half> %x2, i32 %x3) #0 {764; CHECK-LABEL: define <32 x half> @test_int_x86_avx512_mask_reduce_ph_512(765; CHECK-SAME: <32 x half> [[X0:%.*]], <32 x half> [[X2:%.*]], i32 [[X3:%.*]]) #[[ATTR1]] {766; CHECK-NEXT: [[TMP1:%.*]] = load <32 x i16>, ptr @__msan_param_tls, align 8767; CHECK-NEXT: [[TMP2:%.*]] = load <32 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 8768; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 8769; CHECK-NEXT: call void @llvm.donothing()770; CHECK-NEXT: [[TMP4:%.*]] = bitcast <32 x i16> [[TMP1]] to i512771; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP4]], 0772; CHECK-NEXT: [[TMP5:%.*]] = bitcast <32 x i16> [[TMP2]] to i512773; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP5]], 0774; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]775; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i32 [[TMP3]], 0776; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]777; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]778; CHECK: [[BB6]]:779; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]780; CHECK-NEXT: unreachable781; CHECK: [[BB7]]:782; CHECK-NEXT: [[RES:%.*]] = call <32 x half> @llvm.x86.avx512fp16.mask.reduce.ph.512(<32 x half> [[X0]], i32 8, <32 x half> [[X2]], i32 [[X3]], i32 4)783; CHECK-NEXT: [[TMP8:%.*]] = bitcast <32 x i16> [[TMP1]] to i512784; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i512 [[TMP8]], 0785; CHECK-NEXT: [[TMP9:%.*]] = bitcast <32 x i16> [[TMP2]] to i512786; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i512 [[TMP9]], 0787; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSCMP4]], [[_MSCMP5]]788; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB10:.*]], label %[[BB11:.*]], !prof [[PROF1]]789; CHECK: [[BB10]]:790; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]791; CHECK-NEXT: unreachable792; CHECK: [[BB11]]:793; CHECK-NEXT: [[RES1:%.*]] = call <32 x half> @llvm.x86.avx512fp16.mask.reduce.ph.512(<32 x half> [[X0]], i32 4, <32 x half> [[X2]], i32 -1, i32 8)794; CHECK-NEXT: [[RES2:%.*]] = fadd <32 x half> [[RES]], [[RES1]]795; CHECK-NEXT: store <32 x i16> zeroinitializer, ptr @__msan_retval_tls, align 8796; CHECK-NEXT: ret <32 x half> [[RES2]]797;798 %res = call <32 x half> @llvm.x86.avx512fp16.mask.reduce.ph.512(<32 x half> %x0, i32 8, <32 x half> %x2, i32 %x3, i32 4)799 %res1 = call <32 x half> @llvm.x86.avx512fp16.mask.reduce.ph.512(<32 x half> %x0, i32 4, <32 x half> %x2, i32 -1, i32 8)800 %res2 = fadd <32 x half> %res, %res1801 ret <32 x half> %res2802}803 804declare <8 x half> @llvm.x86.avx512fp16.mask.reduce.sh(<8 x half>, <8 x half>,<8 x half>, i8, i32, i32)805 806define <8 x half>@test_int_x86_avx512_mask_reduce_sh(<8 x half> %x0, <8 x half> %x1, <8 x half> %x3, i8 %x4) #0 {807; CHECK-LABEL: define <8 x half> @test_int_x86_avx512_mask_reduce_sh(808; CHECK-SAME: <8 x half> [[X0:%.*]], <8 x half> [[X1:%.*]], <8 x half> [[X3:%.*]], i8 [[X4:%.*]]) #[[ATTR1]] {809; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8810; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8811; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8812; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 8813; CHECK-NEXT: call void @llvm.donothing()814; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP1]] to i128815; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 0816; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i16> [[TMP2]] to i128817; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP6]], 0818; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]819; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i16> [[TMP3]] to i128820; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 0821; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]822; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 0823; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]824; CHECK-NEXT: br i1 [[_MSOR5]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]825; CHECK: [[BB8]]:826; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]827; CHECK-NEXT: unreachable828; CHECK: [[BB9]]:829; CHECK-NEXT: [[RES:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.reduce.sh(<8 x half> [[X0]], <8 x half> [[X1]], <8 x half> [[X3]], i8 [[X4]], i32 4, i32 4)830; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 8831; CHECK-NEXT: ret <8 x half> [[RES]]832;833 %res = call <8 x half> @llvm.x86.avx512fp16.mask.reduce.sh(<8 x half> %x0, <8 x half> %x1, <8 x half> %x3, i8 %x4, i32 4, i32 4)834 ret <8 x half> %res835}836 837define <8 x half>@test_int_x86_avx512_mask_reduce_sh_nomask(<8 x half> %x0, <8 x half> %x1, <8 x half> %x3) #0 {838; CHECK-LABEL: define <8 x half> @test_int_x86_avx512_mask_reduce_sh_nomask(839; CHECK-SAME: <8 x half> [[X0:%.*]], <8 x half> [[X1:%.*]], <8 x half> [[X3:%.*]]) #[[ATTR1]] {840; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8841; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8842; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8843; CHECK-NEXT: call void @llvm.donothing()844; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i16> [[TMP1]] to i128845; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 0846; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP2]] to i128847; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 0848; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]849; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i16> [[TMP3]] to i128850; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP6]], 0851; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]852; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]853; CHECK: [[BB7]]:854; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]855; CHECK-NEXT: unreachable856; CHECK: [[BB8]]:857; CHECK-NEXT: [[RES:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.reduce.sh(<8 x half> [[X0]], <8 x half> [[X1]], <8 x half> [[X3]], i8 -1, i32 4, i32 8)858; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 8859; CHECK-NEXT: ret <8 x half> [[RES]]860;861 %res = call <8 x half> @llvm.x86.avx512fp16.mask.reduce.sh(<8 x half> %x0, <8 x half> %x1, <8 x half> %x3, i8 -1, i32 4, i32 8)862 ret <8 x half> %res863}864 865declare <32 x half> @llvm.x86.avx512fp16.mask.rndscale.ph.512(<32 x half>, i32, <32 x half>, i32, i32)866 867define <32 x half>@test_int_x86_avx512_mask_rndscale_ph_512(<32 x half> %x0, <32 x half> %x2, i32 %x3) #0 {868; CHECK-LABEL: define <32 x half> @test_int_x86_avx512_mask_rndscale_ph_512(869; CHECK-SAME: <32 x half> [[X0:%.*]], <32 x half> [[X2:%.*]], i32 [[X3:%.*]]) #[[ATTR1]] {870; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 8871; CHECK-NEXT: [[TMP1:%.*]] = load <32 x i16>, ptr @__msan_param_tls, align 8872; CHECK-NEXT: [[TMP2:%.*]] = load <32 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 8873; CHECK-NEXT: call void @llvm.donothing()874; CHECK-NEXT: [[TMP4:%.*]] = bitcast i32 [[X3]] to <32 x i1>875; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <32 x i16> [[TMP1]], zeroinitializer876; CHECK-NEXT: [[TMP6:%.*]] = sext <32 x i1> [[TMP5]] to <32 x i16>877; CHECK-NEXT: [[TMP7:%.*]] = select <32 x i1> [[TMP4]], <32 x i16> [[TMP6]], <32 x i16> [[TMP2]]878; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i32 [[TMP3]], 0879; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]880; CHECK: [[BB8]]:881; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]882; CHECK-NEXT: unreachable883; CHECK: [[BB9]]:884; CHECK-NEXT: [[RES:%.*]] = call <32 x half> @llvm.x86.avx512fp16.mask.rndscale.ph.512(<32 x half> [[X0]], i32 8, <32 x half> [[X2]], i32 [[X3]], i32 4)885; CHECK-NEXT: [[TMP10:%.*]] = icmp ne <32 x i16> [[TMP1]], zeroinitializer886; CHECK-NEXT: [[TMP11:%.*]] = sext <32 x i1> [[TMP10]] to <32 x i16>887; CHECK-NEXT: [[TMP12:%.*]] = select <32 x i1> splat (i1 true), <32 x i16> [[TMP11]], <32 x i16> [[TMP2]]888; CHECK-NEXT: [[RES1:%.*]] = call <32 x half> @llvm.x86.avx512fp16.mask.rndscale.ph.512(<32 x half> [[X0]], i32 4, <32 x half> [[X2]], i32 -1, i32 8)889; CHECK-NEXT: [[_MSPROP:%.*]] = or <32 x i16> [[TMP7]], [[TMP12]]890; CHECK-NEXT: [[RES2:%.*]] = fadd <32 x half> [[RES]], [[RES1]]891; CHECK-NEXT: store <32 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8892; CHECK-NEXT: ret <32 x half> [[RES2]]893;894 %res = call <32 x half> @llvm.x86.avx512fp16.mask.rndscale.ph.512(<32 x half> %x0, i32 8, <32 x half> %x2, i32 %x3, i32 4)895 %res1 = call <32 x half> @llvm.x86.avx512fp16.mask.rndscale.ph.512(<32 x half> %x0, i32 4, <32 x half> %x2, i32 -1, i32 8)896 %res2 = fadd <32 x half> %res, %res1897 ret <32 x half> %res2898}899 900declare <8 x half> @llvm.x86.avx512fp16.mask.rndscale.sh(<8 x half>, <8 x half>,<8 x half>, i8, i32, i32)901 902define <8 x half>@test_int_x86_avx512_mask_rndscale_sh(<8 x half> %x0, <8 x half> %x1, <8 x half> %x3, i8 %x4) #0 {903; CHECK-LABEL: define <8 x half> @test_int_x86_avx512_mask_rndscale_sh(904; CHECK-SAME: <8 x half> [[X0:%.*]], <8 x half> [[X1:%.*]], <8 x half> [[X3:%.*]], i8 [[X4:%.*]]) #[[ATTR1]] {905; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8906; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8907; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8908; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 8909; CHECK-NEXT: call void @llvm.donothing()910; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP1]] to i128911; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 0912; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i16> [[TMP2]] to i128913; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP6]], 0914; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]915; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i16> [[TMP3]] to i128916; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 0917; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]918; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 0919; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]920; CHECK-NEXT: br i1 [[_MSOR5]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]921; CHECK: [[BB8]]:922; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]923; CHECK-NEXT: unreachable924; CHECK: [[BB9]]:925; CHECK-NEXT: [[RES:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.rndscale.sh(<8 x half> [[X0]], <8 x half> [[X1]], <8 x half> [[X3]], i8 [[X4]], i32 4, i32 4)926; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 8927; CHECK-NEXT: ret <8 x half> [[RES]]928;929 %res = call <8 x half> @llvm.x86.avx512fp16.mask.rndscale.sh(<8 x half> %x0, <8 x half> %x1, <8 x half> %x3, i8 %x4, i32 4, i32 4)930 ret <8 x half> %res931}932 933define <8 x half>@test_int_x86_avx512_mask_rndscale_sh_nomask(<8 x half> %x0, <8 x half> %x1, <8 x half> %x3) #0 {934; CHECK-LABEL: define <8 x half> @test_int_x86_avx512_mask_rndscale_sh_nomask(935; CHECK-SAME: <8 x half> [[X0:%.*]], <8 x half> [[X1:%.*]], <8 x half> [[X3:%.*]]) #[[ATTR1]] {936; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8937; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8938; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8939; CHECK-NEXT: call void @llvm.donothing()940; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i16> [[TMP1]] to i128941; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 0942; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP2]] to i128943; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 0944; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]945; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i16> [[TMP3]] to i128946; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP6]], 0947; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]948; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]949; CHECK: [[BB7]]:950; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]951; CHECK-NEXT: unreachable952; CHECK: [[BB8]]:953; CHECK-NEXT: [[RES:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.rndscale.sh(<8 x half> [[X0]], <8 x half> [[X1]], <8 x half> [[X3]], i8 -1, i32 4, i32 8)954; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 8955; CHECK-NEXT: ret <8 x half> [[RES]]956;957 %res = call <8 x half> @llvm.x86.avx512fp16.mask.rndscale.sh(<8 x half> %x0, <8 x half> %x1, <8 x half> %x3, i8 -1, i32 4, i32 8)958 ret <8 x half> %res959}960 961declare <32 x half> @llvm.x86.avx512fp16.mask.getexp.ph.512(<32 x half>, <32 x half>, i32, i32)962 963define <32 x half>@test_int_x86_avx512_mask_getexp_ph_512(<32 x half> %x0, <32 x half> %x1, i32 %x2) #0 {964; CHECK-LABEL: define <32 x half> @test_int_x86_avx512_mask_getexp_ph_512(965; CHECK-SAME: <32 x half> [[X0:%.*]], <32 x half> [[X1:%.*]], i32 [[X2:%.*]]) #[[ATTR1]] {966; CHECK-NEXT: [[TMP1:%.*]] = load <32 x i16>, ptr @__msan_param_tls, align 8967; CHECK-NEXT: [[TMP2:%.*]] = load <32 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 8968; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 8969; CHECK-NEXT: call void @llvm.donothing()970; CHECK-NEXT: [[TMP4:%.*]] = bitcast <32 x i16> [[TMP1]] to i512971; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP4]], 0972; CHECK-NEXT: [[TMP5:%.*]] = bitcast <32 x i16> [[TMP2]] to i512973; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP5]], 0974; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]975; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i32 [[TMP3]], 0976; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]977; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]978; CHECK: [[BB6]]:979; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]980; CHECK-NEXT: unreachable981; CHECK: [[BB7]]:982; CHECK-NEXT: [[RES1:%.*]] = call <32 x half> @llvm.x86.avx512fp16.mask.getexp.ph.512(<32 x half> [[X0]], <32 x half> [[X1]], i32 [[X2]], i32 4)983; CHECK-NEXT: [[TMP8:%.*]] = bitcast <32 x i16> [[TMP1]] to i512984; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i512 [[TMP8]], 0985; CHECK-NEXT: br i1 [[_MSCMP4]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]986; CHECK: [[BB9]]:987; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]988; CHECK-NEXT: unreachable989; CHECK: [[BB10]]:990; CHECK-NEXT: [[RES2:%.*]] = call <32 x half> @llvm.x86.avx512fp16.mask.getexp.ph.512(<32 x half> [[X0]], <32 x half> zeroinitializer, i32 -1, i32 8)991; CHECK-NEXT: [[RES3:%.*]] = fadd <32 x half> [[RES1]], [[RES2]]992; CHECK-NEXT: store <32 x i16> zeroinitializer, ptr @__msan_retval_tls, align 8993; CHECK-NEXT: ret <32 x half> [[RES3]]994;995 %res1 = call <32 x half> @llvm.x86.avx512fp16.mask.getexp.ph.512(<32 x half> %x0, <32 x half> %x1, i32 %x2, i32 4)996 %res2 = call <32 x half> @llvm.x86.avx512fp16.mask.getexp.ph.512(<32 x half> %x0, <32 x half> zeroinitializer, i32 -1, i32 8)997 %res3 = fadd <32 x half> %res1, %res2998 ret <32 x half> %res3999}1000 1001declare <8 x half> @llvm.x86.avx512fp16.mask.getexp.sh(<8 x half>, <8 x half>,<8 x half>, i8, i32)1002 1003define <8 x half>@test_int_x86_avx512_mask_getexp_sh(<8 x half> %x0, <8 x half> %x1, <8 x half> %x3, i8 %x4) #0 {1004; CHECK-LABEL: define <8 x half> @test_int_x86_avx512_mask_getexp_sh(1005; CHECK-SAME: <8 x half> [[X0:%.*]], <8 x half> [[X1:%.*]], <8 x half> [[X3:%.*]], i8 [[X4:%.*]]) #[[ATTR1]] {1006; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81007; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81008; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81009; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 81010; CHECK-NEXT: call void @llvm.donothing()1011; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP1]] to i1281012; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 01013; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i16> [[TMP2]] to i1281014; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP6]], 01015; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1016; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i16> [[TMP3]] to i1281017; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 01018; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]1019; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 01020; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]1021; CHECK-NEXT: br i1 [[_MSOR5]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]1022; CHECK: [[BB8]]:1023; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1024; CHECK-NEXT: unreachable1025; CHECK: [[BB9]]:1026; CHECK-NEXT: [[RES:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.getexp.sh(<8 x half> [[X0]], <8 x half> [[X1]], <8 x half> [[X3]], i8 [[X4]], i32 4)1027; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 81028; CHECK-NEXT: ret <8 x half> [[RES]]1029;1030 %res = call <8 x half> @llvm.x86.avx512fp16.mask.getexp.sh(<8 x half> %x0, <8 x half> %x1, <8 x half> %x3, i8 %x4, i32 4)1031 ret <8 x half> %res1032}1033 1034define <8 x half>@test_int_x86_avx512_mask_getexp_sh_nomask(<8 x half> %x0, <8 x half> %x1, <8 x half> %x3) #0 {1035; CHECK-LABEL: define <8 x half> @test_int_x86_avx512_mask_getexp_sh_nomask(1036; CHECK-SAME: <8 x half> [[X0:%.*]], <8 x half> [[X1:%.*]], <8 x half> [[X3:%.*]]) #[[ATTR1]] {1037; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81038; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81039; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81040; CHECK-NEXT: call void @llvm.donothing()1041; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i16> [[TMP1]] to i1281042; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 01043; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP2]] to i1281044; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 01045; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1046; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i16> [[TMP3]] to i1281047; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP6]], 01048; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]1049; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]1050; CHECK: [[BB7]]:1051; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1052; CHECK-NEXT: unreachable1053; CHECK: [[BB8]]:1054; CHECK-NEXT: [[RES:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.getexp.sh(<8 x half> [[X0]], <8 x half> [[X1]], <8 x half> [[X3]], i8 -1, i32 8)1055; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 81056; CHECK-NEXT: ret <8 x half> [[RES]]1057;1058 %res = call <8 x half> @llvm.x86.avx512fp16.mask.getexp.sh(<8 x half> %x0, <8 x half> %x1, <8 x half> %x3, i8 -1, i32 8)1059 ret <8 x half> %res1060}1061 1062define <8 x half>@test_int_x86_avx512_mask_getexp_sh_load(<8 x half> %x0, ptr %x1ptr) #0 {1063; CHECK-LABEL: define <8 x half> @test_int_x86_avx512_mask_getexp_sh_load(1064; CHECK-SAME: <8 x half> [[X0:%.*]], ptr [[X1PTR:%.*]]) #[[ATTR1]] {1065; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81066; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81067; CHECK-NEXT: call void @llvm.donothing()1068; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01069; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]1070; CHECK: [[BB3]]:1071; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1072; CHECK-NEXT: unreachable1073; CHECK: [[BB4]]:1074; CHECK-NEXT: [[X1:%.*]] = load <8 x half>, ptr [[X1PTR]], align 161075; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[X1PTR]] to i641076; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 879609302220801077; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1078; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP7]], align 161079; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i16> [[TMP2]] to i1281080; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP8]], 01081; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i16> [[_MSLD]] to i1281082; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP9]], 01083; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP1]], [[_MSCMP2]]1084; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1085; CHECK-NEXT: [[RES:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.getexp.sh(<8 x half> [[X0]], <8 x half> [[X1]], <8 x half> poison, i8 -1, i32 4)1086; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 81087; CHECK-NEXT: ret <8 x half> [[RES]]1088;1089 %x1 = load <8 x half>, ptr %x1ptr1090 %res = call <8 x half> @llvm.x86.avx512fp16.mask.getexp.sh(<8 x half> %x0, <8 x half> %x1, <8 x half> poison, i8 -1, i32 4)1091 ret <8 x half> %res1092}1093 1094declare <32 x half> @llvm.x86.avx512fp16.mask.getmant.ph.512(<32 x half>, i32, <32 x half>, i32, i32)1095 1096define <32 x half>@test_int_x86_avx512_mask_getmant_ph_512(<32 x half> %x0, <32 x half> %x2, i32 %x3) #0 {1097; CHECK-LABEL: define <32 x half> @test_int_x86_avx512_mask_getmant_ph_512(1098; CHECK-SAME: <32 x half> [[X0:%.*]], <32 x half> [[X2:%.*]], i32 [[X3:%.*]]) #[[ATTR1]] {1099; CHECK-NEXT: [[TMP1:%.*]] = load <32 x i16>, ptr @__msan_param_tls, align 81100; CHECK-NEXT: [[TMP2:%.*]] = load <32 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 81101; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 81102; CHECK-NEXT: call void @llvm.donothing()1103; CHECK-NEXT: [[TMP4:%.*]] = bitcast <32 x i16> [[TMP1]] to i5121104; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP4]], 01105; CHECK-NEXT: [[TMP5:%.*]] = bitcast <32 x i16> [[TMP2]] to i5121106; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP5]], 01107; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1108; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i32 [[TMP3]], 01109; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]1110; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]1111; CHECK: [[BB6]]:1112; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1113; CHECK-NEXT: unreachable1114; CHECK: [[BB7]]:1115; CHECK-NEXT: [[RES:%.*]] = call <32 x half> @llvm.x86.avx512fp16.mask.getmant.ph.512(<32 x half> [[X0]], i32 8, <32 x half> [[X2]], i32 [[X3]], i32 4)1116; CHECK-NEXT: [[TMP8:%.*]] = bitcast <32 x i16> [[TMP1]] to i5121117; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i512 [[TMP8]], 01118; CHECK-NEXT: [[TMP9:%.*]] = bitcast <32 x i16> [[TMP2]] to i5121119; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i512 [[TMP9]], 01120; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSCMP4]], [[_MSCMP5]]1121; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB10:.*]], label %[[BB11:.*]], !prof [[PROF1]]1122; CHECK: [[BB10]]:1123; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1124; CHECK-NEXT: unreachable1125; CHECK: [[BB11]]:1126; CHECK-NEXT: [[RES1:%.*]] = call <32 x half> @llvm.x86.avx512fp16.mask.getmant.ph.512(<32 x half> [[X0]], i32 4, <32 x half> [[X2]], i32 -1, i32 8)1127; CHECK-NEXT: [[RES2:%.*]] = fadd <32 x half> [[RES]], [[RES1]]1128; CHECK-NEXT: store <32 x i16> zeroinitializer, ptr @__msan_retval_tls, align 81129; CHECK-NEXT: ret <32 x half> [[RES2]]1130;1131 %res = call <32 x half> @llvm.x86.avx512fp16.mask.getmant.ph.512(<32 x half> %x0, i32 8, <32 x half> %x2, i32 %x3, i32 4)1132 %res1 = call <32 x half> @llvm.x86.avx512fp16.mask.getmant.ph.512(<32 x half> %x0, i32 4, <32 x half> %x2, i32 -1, i32 8)1133 %res2 = fadd <32 x half> %res, %res11134 ret <32 x half> %res21135}1136 1137declare <8 x half> @llvm.x86.avx512fp16.mask.getmant.sh(<8 x half>, <8 x half>, i32, <8 x half>, i8, i32)1138 1139define <8 x half>@test_int_x86_avx512_mask_getmant_sh(<8 x half> %x0, <8 x half> %x1, <8 x half> %x3, i8 %x4) #0 {1140; CHECK-LABEL: define <8 x half> @test_int_x86_avx512_mask_getmant_sh(1141; CHECK-SAME: <8 x half> [[X0:%.*]], <8 x half> [[X1:%.*]], <8 x half> [[X3:%.*]], i8 [[X4:%.*]]) #[[ATTR1]] {1142; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81143; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81144; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81145; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 81146; CHECK-NEXT: call void @llvm.donothing()1147; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP1]] to i1281148; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 01149; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i16> [[TMP2]] to i1281150; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP6]], 01151; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1152; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i16> [[TMP3]] to i1281153; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 01154; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]1155; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 01156; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]1157; CHECK-NEXT: br i1 [[_MSOR5]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]1158; CHECK: [[BB8]]:1159; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1160; CHECK-NEXT: unreachable1161; CHECK: [[BB9]]:1162; CHECK-NEXT: [[RES:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.getmant.sh(<8 x half> [[X0]], <8 x half> [[X1]], i32 11, <8 x half> [[X3]], i8 [[X4]], i32 4)1163; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 81164; CHECK-NEXT: ret <8 x half> [[RES]]1165;1166 %res = call <8 x half> @llvm.x86.avx512fp16.mask.getmant.sh(<8 x half> %x0, <8 x half> %x1, i32 11, <8 x half> %x3, i8 %x4, i32 4)1167 ret <8 x half> %res1168}1169 1170define <8 x half>@test_int_x86_avx512_mask_getmant_sh_nomask(<8 x half> %x0, <8 x half> %x1, <8 x half> %x3) #0 {1171; CHECK-LABEL: define <8 x half> @test_int_x86_avx512_mask_getmant_sh_nomask(1172; CHECK-SAME: <8 x half> [[X0:%.*]], <8 x half> [[X1:%.*]], <8 x half> [[X3:%.*]]) #[[ATTR1]] {1173; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81174; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81175; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81176; CHECK-NEXT: call void @llvm.donothing()1177; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i16> [[TMP1]] to i1281178; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 01179; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP2]] to i1281180; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 01181; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1182; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i16> [[TMP3]] to i1281183; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP6]], 01184; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]1185; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]1186; CHECK: [[BB7]]:1187; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1188; CHECK-NEXT: unreachable1189; CHECK: [[BB8]]:1190; CHECK-NEXT: [[RES:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.getmant.sh(<8 x half> [[X0]], <8 x half> [[X1]], i32 11, <8 x half> [[X3]], i8 -1, i32 4)1191; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 81192; CHECK-NEXT: ret <8 x half> [[RES]]1193;1194 %res = call <8 x half> @llvm.x86.avx512fp16.mask.getmant.sh(<8 x half> %x0, <8 x half> %x1, i32 11, <8 x half> %x3, i8 -1, i32 4)1195 ret <8 x half> %res1196}1197 1198define <8 x half>@test_int_x86_avx512_mask_getmant_sh_z(<8 x half> %x0, <8 x half> %x1, i8 %x4) #0 {1199; CHECK-LABEL: define <8 x half> @test_int_x86_avx512_mask_getmant_sh_z(1200; CHECK-SAME: <8 x half> [[X0:%.*]], <8 x half> [[X1:%.*]], i8 [[X4:%.*]]) #[[ATTR1]] {1201; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81202; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81203; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81204; CHECK-NEXT: call void @llvm.donothing()1205; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i16> [[TMP1]] to i1281206; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 01207; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP2]] to i1281208; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 01209; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1210; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 01211; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]1212; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]1213; CHECK: [[BB6]]:1214; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1215; CHECK-NEXT: unreachable1216; CHECK: [[BB7]]:1217; CHECK-NEXT: [[RES:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.getmant.sh(<8 x half> [[X0]], <8 x half> [[X1]], i32 11, <8 x half> zeroinitializer, i8 [[X4]], i32 4)1218; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 81219; CHECK-NEXT: ret <8 x half> [[RES]]1220;1221 %res = call <8 x half> @llvm.x86.avx512fp16.mask.getmant.sh(<8 x half> %x0, <8 x half> %x1, i32 11, <8 x half> zeroinitializer, i8 %x4, i32 4)1222 ret <8 x half> %res1223}1224 1225declare <32 x half> @llvm.x86.avx512fp16.mask.scalef.ph.512(<32 x half>, <32 x half>, <32 x half>, i32, i32)1226 1227define <32 x half>@test_int_x86_avx512_mask_scalef_ph_512(<32 x half> %x0, <32 x half> %x1, <32 x half> %x2, i32 %x3) #0 {1228; CHECK-LABEL: define <32 x half> @test_int_x86_avx512_mask_scalef_ph_512(1229; CHECK-SAME: <32 x half> [[X0:%.*]], <32 x half> [[X1:%.*]], <32 x half> [[X2:%.*]], i32 [[X3:%.*]]) #[[ATTR1]] {1230; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_tls, i64 192), align 81231; CHECK-NEXT: [[TMP2:%.*]] = load <32 x i16>, ptr @__msan_param_tls, align 81232; CHECK-NEXT: [[TMP3:%.*]] = load <32 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 81233; CHECK-NEXT: [[TMP4:%.*]] = load <32 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 81234; CHECK-NEXT: call void @llvm.donothing()1235; CHECK-NEXT: [[TMP5:%.*]] = bitcast i32 [[TMP1]] to <32 x i1>1236; CHECK-NEXT: [[MASK:%.*]] = bitcast i32 [[X3]] to <32 x i1>1237; CHECK-NEXT: [[TMP6:%.*]] = bitcast <32 x i16> [[TMP2]] to i5121238; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP6]], 01239; CHECK-NEXT: [[TMP7:%.*]] = bitcast <32 x i16> [[TMP3]] to i5121240; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP7]], 01241; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1242; CHECK-NEXT: [[TMP8:%.*]] = bitcast <32 x i16> [[TMP4]] to i5121243; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i512 [[TMP8]], 01244; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]1245; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i32 [[TMP1]], 01246; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]1247; CHECK-NEXT: br i1 [[_MSOR5]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]1248; CHECK: [[BB9]]:1249; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1250; CHECK-NEXT: unreachable1251; CHECK: [[BB10]]:1252; CHECK-NEXT: [[RES1:%.*]] = call <32 x half> @llvm.x86.avx512fp16.mask.scalef.ph.512(<32 x half> [[X0]], <32 x half> [[X1]], <32 x half> [[X2]], i32 [[X3]], i32 11)1253; CHECK-NEXT: [[TMP11:%.*]] = bitcast <32 x i16> [[TMP2]] to i5121254; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i512 [[TMP11]], 01255; CHECK-NEXT: [[TMP12:%.*]] = bitcast <32 x i16> [[TMP3]] to i5121256; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i512 [[TMP12]], 01257; CHECK-NEXT: [[_MSOR8:%.*]] = or i1 [[_MSCMP6]], [[_MSCMP7]]1258; CHECK-NEXT: br i1 [[_MSOR8]], label %[[BB13:.*]], label %[[BB14:.*]], !prof [[PROF1]]1259; CHECK: [[BB13]]:1260; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1261; CHECK-NEXT: unreachable1262; CHECK: [[BB14]]:1263; CHECK-NEXT: [[RES2:%.*]] = call <32 x half> @llvm.x86.avx512fp16.mask.scalef.ph.512(<32 x half> [[X0]], <32 x half> [[X1]], <32 x half> zeroinitializer, i32 -1, i32 8)1264; CHECK-NEXT: [[RES3:%.*]] = fadd <32 x half> [[RES1]], [[RES2]]1265; CHECK-NEXT: store <32 x i16> zeroinitializer, ptr @__msan_retval_tls, align 81266; CHECK-NEXT: ret <32 x half> [[RES3]]1267;1268 %mask = bitcast i32 %x3 to <32 x i1>1269 %res1 = call <32 x half> @llvm.x86.avx512fp16.mask.scalef.ph.512(<32 x half> %x0, <32 x half> %x1, <32 x half> %x2, i32 %x3, i32 11)1270 %res2 = call <32 x half> @llvm.x86.avx512fp16.mask.scalef.ph.512(<32 x half> %x0, <32 x half> %x1, <32 x half> zeroinitializer, i32 -1, i32 8)1271 %res3 = fadd <32 x half> %res1, %res21272 ret <32 x half> %res31273}1274 1275declare <8 x half> @llvm.x86.avx512fp16.mask.scalef.sh(<8 x half>, <8 x half>,<8 x half>, i8, i32)1276 1277define <8 x half>@test_int_x86_avx512_mask_scalef_sh(<8 x half> %x0, <8 x half> %x1, <8 x half> %x3, i8 %x4) #0 {1278; CHECK-LABEL: define <8 x half> @test_int_x86_avx512_mask_scalef_sh(1279; CHECK-SAME: <8 x half> [[X0:%.*]], <8 x half> [[X1:%.*]], <8 x half> [[X3:%.*]], i8 [[X4:%.*]]) #[[ATTR1]] {1280; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81281; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81282; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81283; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 81284; CHECK-NEXT: call void @llvm.donothing()1285; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP1]] to i1281286; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 01287; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i16> [[TMP2]] to i1281288; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP6]], 01289; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1290; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i16> [[TMP3]] to i1281291; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 01292; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]1293; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 01294; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]1295; CHECK-NEXT: br i1 [[_MSOR5]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]1296; CHECK: [[BB8]]:1297; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1298; CHECK-NEXT: unreachable1299; CHECK: [[BB9]]:1300; CHECK-NEXT: [[RES:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.scalef.sh(<8 x half> [[X0]], <8 x half> [[X1]], <8 x half> [[X3]], i8 [[X4]], i32 4)1301; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 81302; CHECK-NEXT: ret <8 x half> [[RES]]1303;1304 %res = call <8 x half> @llvm.x86.avx512fp16.mask.scalef.sh(<8 x half> %x0, <8 x half> %x1, <8 x half> %x3, i8 %x4, i32 4)1305 ret <8 x half> %res1306}1307 1308define <8 x half>@test_int_x86_avx512_mask_scalef_sh_nomask(<8 x half> %x0, <8 x half> %x1, <8 x half> %x3) #0 {1309; CHECK-LABEL: define <8 x half> @test_int_x86_avx512_mask_scalef_sh_nomask(1310; CHECK-SAME: <8 x half> [[X0:%.*]], <8 x half> [[X1:%.*]], <8 x half> [[X3:%.*]]) #[[ATTR1]] {1311; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81312; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81313; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81314; CHECK-NEXT: call void @llvm.donothing()1315; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i16> [[TMP1]] to i1281316; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 01317; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP2]] to i1281318; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 01319; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1320; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i16> [[TMP3]] to i1281321; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP6]], 01322; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]1323; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]1324; CHECK: [[BB7]]:1325; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1326; CHECK-NEXT: unreachable1327; CHECK: [[BB8]]:1328; CHECK-NEXT: [[RES:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.scalef.sh(<8 x half> [[X0]], <8 x half> [[X1]], <8 x half> [[X3]], i8 -1, i32 8)1329; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 81330; CHECK-NEXT: ret <8 x half> [[RES]]1331;1332 %res = call <8 x half> @llvm.x86.avx512fp16.mask.scalef.sh(<8 x half> %x0, <8 x half> %x1, <8 x half> %x3, i8 -1, i32 8)1333 ret <8 x half> %res1334}1335 1336define <8 x half>@test_int_x86_avx512_mask_scalef_sh_load(<8 x half> %x0, ptr %x1ptr) #0 {1337; CHECK-LABEL: define <8 x half> @test_int_x86_avx512_mask_scalef_sh_load(1338; CHECK-SAME: <8 x half> [[X0:%.*]], ptr [[X1PTR:%.*]]) #[[ATTR1]] {1339; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81340; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81341; CHECK-NEXT: call void @llvm.donothing()1342; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01343; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]1344; CHECK: [[BB3]]:1345; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1346; CHECK-NEXT: unreachable1347; CHECK: [[BB4]]:1348; CHECK-NEXT: [[X1:%.*]] = load <8 x half>, ptr [[X1PTR]], align 161349; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[X1PTR]] to i641350; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 879609302220801351; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1352; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP7]], align 161353; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i16> [[TMP2]] to i1281354; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP8]], 01355; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i16> [[_MSLD]] to i1281356; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP9]], 01357; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP1]], [[_MSCMP2]]1358; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1359; CHECK-NEXT: [[RES:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.scalef.sh(<8 x half> [[X0]], <8 x half> [[X1]], <8 x half> poison, i8 -1, i32 4)1360; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 81361; CHECK-NEXT: ret <8 x half> [[RES]]1362;1363 %x1 = load <8 x half>, ptr %x1ptr1364 %res = call <8 x half> @llvm.x86.avx512fp16.mask.scalef.sh(<8 x half> %x0, <8 x half> %x1, <8 x half> poison, i8 -1, i32 4)1365 ret <8 x half> %res1366}1367 1368declare <8 x half> @llvm.x86.avx512fp16.mask.add.sh.round(<8 x half>, <8 x half>, <8 x half>, i8, i32)1369 1370define <8 x half> @test_int_x86_avx512fp16_mask_add_sh(<8 x half> %x1, <8 x half> %x2, <8 x half> %src, i8 %mask, ptr %ptr) #0 {1371; CHECK-LABEL: define <8 x half> @test_int_x86_avx512fp16_mask_add_sh(1372; CHECK-SAME: <8 x half> [[X1:%.*]], <8 x half> [[X2:%.*]], <8 x half> [[SRC:%.*]], i8 [[MASK:%.*]], ptr [[PTR:%.*]]) #[[ATTR1]] {1373; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 56), align 81374; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81375; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81376; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 81377; CHECK-NEXT: [[TMP6:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81378; CHECK-NEXT: call void @llvm.donothing()1379; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01380; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]1381; CHECK: [[BB6]]:1382; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1383; CHECK-NEXT: unreachable1384; CHECK: [[BB7]]:1385; CHECK-NEXT: [[VAL_HALF:%.*]] = load half, ptr [[PTR]], align 21386; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[PTR]] to i641387; CHECK-NEXT: [[TMP9:%.*]] = xor i64 [[TMP8]], 879609302220801388; CHECK-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP9]] to ptr1389; CHECK-NEXT: [[_MSLD:%.*]] = load i16, ptr [[TMP10]], align 21390; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <8 x i16> splat (i16 -1), i16 [[_MSLD]], i32 01391; CHECK-NEXT: [[VAL:%.*]] = insertelement <8 x half> poison, half [[VAL_HALF]], i32 01392; CHECK-NEXT: [[TMP11:%.*]] = extractelement <8 x i16> [[TMP2]], i32 01393; CHECK-NEXT: [[TMP12:%.*]] = extractelement <8 x i16> [[TMP3]], i32 01394; CHECK-NEXT: [[TMP13:%.*]] = or i16 [[TMP11]], [[TMP12]]1395; CHECK-NEXT: [[TMP14:%.*]] = select i1 true, i16 [[TMP13]], i16 01396; CHECK-NEXT: [[_MSPROP1:%.*]] = insertelement <8 x i16> [[TMP2]], i16 [[TMP14]], i32 01397; CHECK-NEXT: [[RES0:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.add.sh.round(<8 x half> [[X1]], <8 x half> [[X2]], <8 x half> zeroinitializer, i8 -1, i32 4)1398; CHECK-NEXT: [[TMP16:%.*]] = extractelement <8 x i16> [[_MSPROP1]], i32 01399; CHECK-NEXT: [[TMP17:%.*]] = extractelement <8 x i16> [[TMP3]], i32 01400; CHECK-NEXT: [[TMP18:%.*]] = or i16 [[TMP16]], [[TMP17]]1401; CHECK-NEXT: [[TMP19:%.*]] = extractelement <8 x i16> [[TMP6]], i32 01402; CHECK-NEXT: [[TMP22:%.*]] = bitcast i8 [[MASK]] to <8 x i1>1403; CHECK-NEXT: [[TMP20:%.*]] = extractelement <8 x i1> [[TMP22]], i32 01404; CHECK-NEXT: [[TMP21:%.*]] = select i1 [[TMP20]], i16 [[TMP18]], i16 [[TMP19]]1405; CHECK-NEXT: [[_MSPROP2:%.*]] = insertelement <8 x i16> [[_MSPROP1]], i16 [[TMP21]], i32 01406; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i8 [[TMP5]], 01407; CHECK-NEXT: br i1 [[_MSCMP6]], label %[[BB22:.*]], label %[[BB23:.*]], !prof [[PROF1]]1408; CHECK: [[BB22]]:1409; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1410; CHECK-NEXT: unreachable1411; CHECK: [[BB23]]:1412; CHECK-NEXT: [[RES1:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.add.sh.round(<8 x half> [[RES0]], <8 x half> [[X2]], <8 x half> [[SRC]], i8 [[MASK]], i32 4)1413; CHECK-NEXT: [[TMP25:%.*]] = extractelement <8 x i16> [[_MSPROP2]], i32 01414; CHECK-NEXT: [[TMP26:%.*]] = extractelement <8 x i16> [[TMP3]], i32 01415; CHECK-NEXT: [[TMP27:%.*]] = or i16 [[TMP25]], [[TMP26]]1416; CHECK-NEXT: [[TMP30:%.*]] = bitcast i8 [[MASK]] to <8 x i1>1417; CHECK-NEXT: [[TMP28:%.*]] = extractelement <8 x i1> [[TMP30]], i32 01418; CHECK-NEXT: [[TMP29:%.*]] = select i1 [[TMP28]], i16 [[TMP27]], i16 01419; CHECK-NEXT: [[_MSPROP3:%.*]] = insertelement <8 x i16> [[_MSPROP2]], i16 [[TMP29]], i32 01420; CHECK-NEXT: [[_MSCMP9:%.*]] = icmp ne i8 [[TMP5]], 01421; CHECK-NEXT: br i1 [[_MSCMP9]], label %[[BB30:.*]], label %[[BB31:.*]], !prof [[PROF1]]1422; CHECK: [[BB30]]:1423; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1424; CHECK-NEXT: unreachable1425; CHECK: [[BB31]]:1426; CHECK-NEXT: [[RES2:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.add.sh.round(<8 x half> [[RES1]], <8 x half> [[X2]], <8 x half> zeroinitializer, i8 [[MASK]], i32 4)1427; CHECK-NEXT: [[TMP33:%.*]] = extractelement <8 x i16> [[_MSPROP3]], i32 01428; CHECK-NEXT: [[TMP34:%.*]] = extractelement <8 x i16> [[_MSPROP]], i32 01429; CHECK-NEXT: [[TMP35:%.*]] = or i16 [[TMP33]], [[TMP34]]1430; CHECK-NEXT: [[TMP36:%.*]] = extractelement <8 x i16> [[TMP6]], i32 01431; CHECK-NEXT: [[TMP39:%.*]] = bitcast i8 [[MASK]] to <8 x i1>1432; CHECK-NEXT: [[TMP37:%.*]] = extractelement <8 x i1> [[TMP39]], i32 01433; CHECK-NEXT: [[TMP38:%.*]] = select i1 [[TMP37]], i16 [[TMP35]], i16 [[TMP36]]1434; CHECK-NEXT: [[_MSPROP4:%.*]] = insertelement <8 x i16> [[_MSPROP3]], i16 [[TMP38]], i32 01435; CHECK-NEXT: [[_MSCMP14:%.*]] = icmp ne i8 [[TMP5]], 01436; CHECK-NEXT: br i1 [[_MSCMP14]], label %[[BB39:.*]], label %[[BB40:.*]], !prof [[PROF1]]1437; CHECK: [[BB39]]:1438; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1439; CHECK-NEXT: unreachable1440; CHECK: [[BB40]]:1441; CHECK-NEXT: [[RES3:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.add.sh.round(<8 x half> [[RES2]], <8 x half> [[VAL]], <8 x half> [[SRC]], i8 [[MASK]], i32 4)1442; CHECK-NEXT: store <8 x i16> [[_MSPROP4]], ptr @__msan_retval_tls, align 81443; CHECK-NEXT: ret <8 x half> [[RES3]]1444;1445 %val.half = load half,ptr %ptr1446 %val = insertelement <8 x half> poison, half %val.half, i32 01447 %res0 = call <8 x half> @llvm.x86.avx512fp16.mask.add.sh.round(<8 x half> %x1, <8 x half> %x2, <8 x half> zeroinitializer, i8 -1, i32 4)1448 %res1 = call <8 x half> @llvm.x86.avx512fp16.mask.add.sh.round(<8 x half> %res0, <8 x half> %x2, <8 x half> %src , i8 %mask, i32 4)1449 %res2 = call <8 x half> @llvm.x86.avx512fp16.mask.add.sh.round(<8 x half> %res1, <8 x half> %x2, <8 x half> zeroinitializer , i8 %mask, i32 4)1450 %res3 = call <8 x half> @llvm.x86.avx512fp16.mask.add.sh.round(<8 x half> %res2, <8 x half> %val, <8 x half> %src , i8 %mask, i32 4)1451 ret <8 x half> %res31452}1453 1454declare <8 x half> @llvm.x86.avx512fp16.mask.sub.sh.round(<8 x half>, <8 x half>, <8 x half>, i8, i32)1455 1456define <8 x half> @test_int_x86_avx512fp16_mask_sub_sh(<8 x half> %x1, <8 x half> %x2, <8 x half> %src, i8 %mask, ptr %ptr) #0 {1457; CHECK-LABEL: define <8 x half> @test_int_x86_avx512fp16_mask_sub_sh(1458; CHECK-SAME: <8 x half> [[X1:%.*]], <8 x half> [[X2:%.*]], <8 x half> [[SRC:%.*]], i8 [[MASK:%.*]], ptr [[PTR:%.*]]) #[[ATTR1]] {1459; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 56), align 81460; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81461; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81462; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 81463; CHECK-NEXT: [[TMP6:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81464; CHECK-NEXT: call void @llvm.donothing()1465; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01466; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]1467; CHECK: [[BB6]]:1468; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1469; CHECK-NEXT: unreachable1470; CHECK: [[BB7]]:1471; CHECK-NEXT: [[VAL_HALF:%.*]] = load half, ptr [[PTR]], align 21472; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[PTR]] to i641473; CHECK-NEXT: [[TMP9:%.*]] = xor i64 [[TMP8]], 879609302220801474; CHECK-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP9]] to ptr1475; CHECK-NEXT: [[_MSLD:%.*]] = load i16, ptr [[TMP10]], align 21476; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <8 x i16> splat (i16 -1), i16 [[_MSLD]], i32 01477; CHECK-NEXT: [[VAL:%.*]] = insertelement <8 x half> poison, half [[VAL_HALF]], i32 01478; CHECK-NEXT: [[TMP11:%.*]] = extractelement <8 x i16> [[TMP2]], i32 01479; CHECK-NEXT: [[TMP12:%.*]] = extractelement <8 x i16> [[TMP3]], i32 01480; CHECK-NEXT: [[TMP13:%.*]] = or i16 [[TMP11]], [[TMP12]]1481; CHECK-NEXT: [[TMP14:%.*]] = select i1 true, i16 [[TMP13]], i16 01482; CHECK-NEXT: [[_MSPROP1:%.*]] = insertelement <8 x i16> [[TMP2]], i16 [[TMP14]], i32 01483; CHECK-NEXT: [[RES0:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.sub.sh.round(<8 x half> [[X1]], <8 x half> [[X2]], <8 x half> zeroinitializer, i8 -1, i32 4)1484; CHECK-NEXT: [[TMP16:%.*]] = extractelement <8 x i16> [[_MSPROP1]], i32 01485; CHECK-NEXT: [[TMP17:%.*]] = extractelement <8 x i16> [[TMP3]], i32 01486; CHECK-NEXT: [[TMP18:%.*]] = or i16 [[TMP16]], [[TMP17]]1487; CHECK-NEXT: [[TMP19:%.*]] = extractelement <8 x i16> [[TMP6]], i32 01488; CHECK-NEXT: [[TMP22:%.*]] = bitcast i8 [[MASK]] to <8 x i1>1489; CHECK-NEXT: [[TMP20:%.*]] = extractelement <8 x i1> [[TMP22]], i32 01490; CHECK-NEXT: [[TMP21:%.*]] = select i1 [[TMP20]], i16 [[TMP18]], i16 [[TMP19]]1491; CHECK-NEXT: [[_MSPROP2:%.*]] = insertelement <8 x i16> [[_MSPROP1]], i16 [[TMP21]], i32 01492; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i8 [[TMP5]], 01493; CHECK-NEXT: br i1 [[_MSCMP6]], label %[[BB22:.*]], label %[[BB23:.*]], !prof [[PROF1]]1494; CHECK: [[BB22]]:1495; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1496; CHECK-NEXT: unreachable1497; CHECK: [[BB23]]:1498; CHECK-NEXT: [[RES1:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.sub.sh.round(<8 x half> [[RES0]], <8 x half> [[X2]], <8 x half> [[SRC]], i8 [[MASK]], i32 4)1499; CHECK-NEXT: [[TMP25:%.*]] = extractelement <8 x i16> [[_MSPROP2]], i32 01500; CHECK-NEXT: [[TMP26:%.*]] = extractelement <8 x i16> [[TMP3]], i32 01501; CHECK-NEXT: [[TMP27:%.*]] = or i16 [[TMP25]], [[TMP26]]1502; CHECK-NEXT: [[TMP30:%.*]] = bitcast i8 [[MASK]] to <8 x i1>1503; CHECK-NEXT: [[TMP28:%.*]] = extractelement <8 x i1> [[TMP30]], i32 01504; CHECK-NEXT: [[TMP29:%.*]] = select i1 [[TMP28]], i16 [[TMP27]], i16 01505; CHECK-NEXT: [[_MSPROP3:%.*]] = insertelement <8 x i16> [[_MSPROP2]], i16 [[TMP29]], i32 01506; CHECK-NEXT: [[_MSCMP9:%.*]] = icmp ne i8 [[TMP5]], 01507; CHECK-NEXT: br i1 [[_MSCMP9]], label %[[BB30:.*]], label %[[BB31:.*]], !prof [[PROF1]]1508; CHECK: [[BB30]]:1509; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1510; CHECK-NEXT: unreachable1511; CHECK: [[BB31]]:1512; CHECK-NEXT: [[RES2:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.sub.sh.round(<8 x half> [[RES1]], <8 x half> [[X2]], <8 x half> zeroinitializer, i8 [[MASK]], i32 4)1513; CHECK-NEXT: [[TMP33:%.*]] = extractelement <8 x i16> [[_MSPROP3]], i32 01514; CHECK-NEXT: [[TMP34:%.*]] = extractelement <8 x i16> [[_MSPROP]], i32 01515; CHECK-NEXT: [[TMP35:%.*]] = or i16 [[TMP33]], [[TMP34]]1516; CHECK-NEXT: [[TMP36:%.*]] = extractelement <8 x i16> [[TMP6]], i32 01517; CHECK-NEXT: [[TMP39:%.*]] = bitcast i8 [[MASK]] to <8 x i1>1518; CHECK-NEXT: [[TMP37:%.*]] = extractelement <8 x i1> [[TMP39]], i32 01519; CHECK-NEXT: [[TMP38:%.*]] = select i1 [[TMP37]], i16 [[TMP35]], i16 [[TMP36]]1520; CHECK-NEXT: [[_MSPROP4:%.*]] = insertelement <8 x i16> [[_MSPROP3]], i16 [[TMP38]], i32 01521; CHECK-NEXT: [[_MSCMP14:%.*]] = icmp ne i8 [[TMP5]], 01522; CHECK-NEXT: br i1 [[_MSCMP14]], label %[[BB39:.*]], label %[[BB40:.*]], !prof [[PROF1]]1523; CHECK: [[BB39]]:1524; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1525; CHECK-NEXT: unreachable1526; CHECK: [[BB40]]:1527; CHECK-NEXT: [[RES3:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.sub.sh.round(<8 x half> [[RES2]], <8 x half> [[VAL]], <8 x half> [[SRC]], i8 [[MASK]], i32 4)1528; CHECK-NEXT: store <8 x i16> [[_MSPROP4]], ptr @__msan_retval_tls, align 81529; CHECK-NEXT: ret <8 x half> [[RES3]]1530;1531 %val.half = load half,ptr %ptr1532 %val = insertelement <8 x half> poison, half %val.half, i32 01533 %res0 = call <8 x half> @llvm.x86.avx512fp16.mask.sub.sh.round(<8 x half> %x1, <8 x half> %x2, <8 x half> zeroinitializer, i8 -1, i32 4)1534 %res1 = call <8 x half> @llvm.x86.avx512fp16.mask.sub.sh.round(<8 x half> %res0, <8 x half> %x2, <8 x half> %src , i8 %mask, i32 4)1535 %res2 = call <8 x half> @llvm.x86.avx512fp16.mask.sub.sh.round(<8 x half> %res1, <8 x half> %x2, <8 x half> zeroinitializer , i8 %mask, i32 4)1536 %res3 = call <8 x half> @llvm.x86.avx512fp16.mask.sub.sh.round(<8 x half> %res2, <8 x half> %val, <8 x half> %src , i8 %mask, i32 4)1537 ret <8 x half> %res31538}1539 1540declare <8 x half> @llvm.x86.avx512fp16.mask.mul.sh.round(<8 x half>, <8 x half>, <8 x half>, i8, i32)1541 1542define <8 x half> @test_int_x86_avx512fp16_mask_mul_sh(<8 x half> %x1, <8 x half> %x2, <8 x half> %src, i8 %mask, ptr %ptr) #0 {1543; CHECK-LABEL: define <8 x half> @test_int_x86_avx512fp16_mask_mul_sh(1544; CHECK-SAME: <8 x half> [[X1:%.*]], <8 x half> [[X2:%.*]], <8 x half> [[SRC:%.*]], i8 [[MASK:%.*]], ptr [[PTR:%.*]]) #[[ATTR1]] {1545; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 56), align 81546; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81547; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81548; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 81549; CHECK-NEXT: [[TMP6:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81550; CHECK-NEXT: call void @llvm.donothing()1551; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01552; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]1553; CHECK: [[BB6]]:1554; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1555; CHECK-NEXT: unreachable1556; CHECK: [[BB7]]:1557; CHECK-NEXT: [[VAL_HALF:%.*]] = load half, ptr [[PTR]], align 21558; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[PTR]] to i641559; CHECK-NEXT: [[TMP9:%.*]] = xor i64 [[TMP8]], 879609302220801560; CHECK-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP9]] to ptr1561; CHECK-NEXT: [[_MSLD:%.*]] = load i16, ptr [[TMP10]], align 21562; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <8 x i16> splat (i16 -1), i16 [[_MSLD]], i32 01563; CHECK-NEXT: [[VAL:%.*]] = insertelement <8 x half> poison, half [[VAL_HALF]], i32 01564; CHECK-NEXT: [[TMP11:%.*]] = extractelement <8 x i16> [[TMP2]], i32 01565; CHECK-NEXT: [[TMP12:%.*]] = extractelement <8 x i16> [[TMP3]], i32 01566; CHECK-NEXT: [[TMP13:%.*]] = or i16 [[TMP11]], [[TMP12]]1567; CHECK-NEXT: [[TMP14:%.*]] = select i1 true, i16 [[TMP13]], i16 01568; CHECK-NEXT: [[_MSPROP1:%.*]] = insertelement <8 x i16> [[TMP2]], i16 [[TMP14]], i32 01569; CHECK-NEXT: [[RES0:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.mul.sh.round(<8 x half> [[X1]], <8 x half> [[X2]], <8 x half> zeroinitializer, i8 -1, i32 4)1570; CHECK-NEXT: [[TMP16:%.*]] = extractelement <8 x i16> [[_MSPROP1]], i32 01571; CHECK-NEXT: [[TMP17:%.*]] = extractelement <8 x i16> [[TMP3]], i32 01572; CHECK-NEXT: [[TMP18:%.*]] = or i16 [[TMP16]], [[TMP17]]1573; CHECK-NEXT: [[TMP19:%.*]] = extractelement <8 x i16> [[TMP6]], i32 01574; CHECK-NEXT: [[TMP22:%.*]] = bitcast i8 [[MASK]] to <8 x i1>1575; CHECK-NEXT: [[TMP20:%.*]] = extractelement <8 x i1> [[TMP22]], i32 01576; CHECK-NEXT: [[TMP21:%.*]] = select i1 [[TMP20]], i16 [[TMP18]], i16 [[TMP19]]1577; CHECK-NEXT: [[_MSPROP2:%.*]] = insertelement <8 x i16> [[_MSPROP1]], i16 [[TMP21]], i32 01578; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i8 [[TMP5]], 01579; CHECK-NEXT: br i1 [[_MSCMP6]], label %[[BB22:.*]], label %[[BB23:.*]], !prof [[PROF1]]1580; CHECK: [[BB22]]:1581; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1582; CHECK-NEXT: unreachable1583; CHECK: [[BB23]]:1584; CHECK-NEXT: [[RES1:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.mul.sh.round(<8 x half> [[RES0]], <8 x half> [[X2]], <8 x half> [[SRC]], i8 [[MASK]], i32 4)1585; CHECK-NEXT: [[TMP25:%.*]] = extractelement <8 x i16> [[_MSPROP2]], i32 01586; CHECK-NEXT: [[TMP26:%.*]] = extractelement <8 x i16> [[TMP3]], i32 01587; CHECK-NEXT: [[TMP27:%.*]] = or i16 [[TMP25]], [[TMP26]]1588; CHECK-NEXT: [[TMP30:%.*]] = bitcast i8 [[MASK]] to <8 x i1>1589; CHECK-NEXT: [[TMP28:%.*]] = extractelement <8 x i1> [[TMP30]], i32 01590; CHECK-NEXT: [[TMP29:%.*]] = select i1 [[TMP28]], i16 [[TMP27]], i16 01591; CHECK-NEXT: [[_MSPROP3:%.*]] = insertelement <8 x i16> [[_MSPROP2]], i16 [[TMP29]], i32 01592; CHECK-NEXT: [[_MSCMP9:%.*]] = icmp ne i8 [[TMP5]], 01593; CHECK-NEXT: br i1 [[_MSCMP9]], label %[[BB30:.*]], label %[[BB31:.*]], !prof [[PROF1]]1594; CHECK: [[BB30]]:1595; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1596; CHECK-NEXT: unreachable1597; CHECK: [[BB31]]:1598; CHECK-NEXT: [[RES2:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.mul.sh.round(<8 x half> [[RES1]], <8 x half> [[X2]], <8 x half> zeroinitializer, i8 [[MASK]], i32 4)1599; CHECK-NEXT: [[TMP33:%.*]] = extractelement <8 x i16> [[_MSPROP3]], i32 01600; CHECK-NEXT: [[TMP34:%.*]] = extractelement <8 x i16> [[_MSPROP]], i32 01601; CHECK-NEXT: [[TMP35:%.*]] = or i16 [[TMP33]], [[TMP34]]1602; CHECK-NEXT: [[TMP36:%.*]] = extractelement <8 x i16> [[TMP6]], i32 01603; CHECK-NEXT: [[TMP39:%.*]] = bitcast i8 [[MASK]] to <8 x i1>1604; CHECK-NEXT: [[TMP37:%.*]] = extractelement <8 x i1> [[TMP39]], i32 01605; CHECK-NEXT: [[TMP38:%.*]] = select i1 [[TMP37]], i16 [[TMP35]], i16 [[TMP36]]1606; CHECK-NEXT: [[_MSPROP4:%.*]] = insertelement <8 x i16> [[_MSPROP3]], i16 [[TMP38]], i32 01607; CHECK-NEXT: [[_MSCMP14:%.*]] = icmp ne i8 [[TMP5]], 01608; CHECK-NEXT: br i1 [[_MSCMP14]], label %[[BB39:.*]], label %[[BB40:.*]], !prof [[PROF1]]1609; CHECK: [[BB39]]:1610; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1611; CHECK-NEXT: unreachable1612; CHECK: [[BB40]]:1613; CHECK-NEXT: [[RES3:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.mul.sh.round(<8 x half> [[RES2]], <8 x half> [[VAL]], <8 x half> [[SRC]], i8 [[MASK]], i32 4)1614; CHECK-NEXT: store <8 x i16> [[_MSPROP4]], ptr @__msan_retval_tls, align 81615; CHECK-NEXT: ret <8 x half> [[RES3]]1616;1617 %val.half = load half,ptr %ptr1618 %val = insertelement <8 x half> poison, half %val.half, i32 01619 %res0 = call <8 x half> @llvm.x86.avx512fp16.mask.mul.sh.round(<8 x half> %x1, <8 x half> %x2, <8 x half> zeroinitializer, i8 -1, i32 4)1620 %res1 = call <8 x half> @llvm.x86.avx512fp16.mask.mul.sh.round(<8 x half> %res0, <8 x half> %x2, <8 x half> %src , i8 %mask, i32 4)1621 %res2 = call <8 x half> @llvm.x86.avx512fp16.mask.mul.sh.round(<8 x half> %res1, <8 x half> %x2, <8 x half> zeroinitializer , i8 %mask, i32 4)1622 %res3 = call <8 x half> @llvm.x86.avx512fp16.mask.mul.sh.round(<8 x half> %res2, <8 x half> %val, <8 x half> %src , i8 %mask, i32 4)1623 ret <8 x half> %res31624}1625 1626declare <8 x half> @llvm.x86.avx512fp16.mask.div.sh.round(<8 x half>, <8 x half>, <8 x half>, i8, i32)1627 1628define <8 x half> @test_int_x86_avx512fp16_mask_div_sh(<8 x half> %x1, <8 x half> %x2, <8 x half> %src, i8 %mask, ptr %ptr) #0 {1629; CHECK-LABEL: define <8 x half> @test_int_x86_avx512fp16_mask_div_sh(1630; CHECK-SAME: <8 x half> [[X1:%.*]], <8 x half> [[X2:%.*]], <8 x half> [[SRC:%.*]], i8 [[MASK:%.*]], ptr [[PTR:%.*]]) #[[ATTR1]] {1631; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 56), align 81632; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81633; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81634; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 81635; CHECK-NEXT: [[TMP6:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81636; CHECK-NEXT: call void @llvm.donothing()1637; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01638; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]1639; CHECK: [[BB6]]:1640; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1641; CHECK-NEXT: unreachable1642; CHECK: [[BB7]]:1643; CHECK-NEXT: [[VAL_HALF:%.*]] = load half, ptr [[PTR]], align 21644; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[PTR]] to i641645; CHECK-NEXT: [[TMP9:%.*]] = xor i64 [[TMP8]], 879609302220801646; CHECK-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP9]] to ptr1647; CHECK-NEXT: [[_MSLD:%.*]] = load i16, ptr [[TMP10]], align 21648; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <8 x i16> splat (i16 -1), i16 [[_MSLD]], i32 01649; CHECK-NEXT: [[VAL:%.*]] = insertelement <8 x half> poison, half [[VAL_HALF]], i32 01650; CHECK-NEXT: [[TMP11:%.*]] = extractelement <8 x i16> [[TMP2]], i32 01651; CHECK-NEXT: [[TMP12:%.*]] = extractelement <8 x i16> [[TMP3]], i32 01652; CHECK-NEXT: [[TMP13:%.*]] = or i16 [[TMP11]], [[TMP12]]1653; CHECK-NEXT: [[TMP14:%.*]] = select i1 true, i16 [[TMP13]], i16 01654; CHECK-NEXT: [[_MSPROP1:%.*]] = insertelement <8 x i16> [[TMP2]], i16 [[TMP14]], i32 01655; CHECK-NEXT: [[RES0:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.div.sh.round(<8 x half> [[X1]], <8 x half> [[X2]], <8 x half> zeroinitializer, i8 -1, i32 4)1656; CHECK-NEXT: [[TMP16:%.*]] = extractelement <8 x i16> [[_MSPROP1]], i32 01657; CHECK-NEXT: [[TMP17:%.*]] = extractelement <8 x i16> [[TMP3]], i32 01658; CHECK-NEXT: [[TMP18:%.*]] = or i16 [[TMP16]], [[TMP17]]1659; CHECK-NEXT: [[TMP19:%.*]] = extractelement <8 x i16> [[TMP6]], i32 01660; CHECK-NEXT: [[TMP22:%.*]] = bitcast i8 [[MASK]] to <8 x i1>1661; CHECK-NEXT: [[TMP20:%.*]] = extractelement <8 x i1> [[TMP22]], i32 01662; CHECK-NEXT: [[TMP21:%.*]] = select i1 [[TMP20]], i16 [[TMP18]], i16 [[TMP19]]1663; CHECK-NEXT: [[_MSPROP2:%.*]] = insertelement <8 x i16> [[_MSPROP1]], i16 [[TMP21]], i32 01664; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i8 [[TMP5]], 01665; CHECK-NEXT: br i1 [[_MSCMP6]], label %[[BB22:.*]], label %[[BB23:.*]], !prof [[PROF1]]1666; CHECK: [[BB22]]:1667; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1668; CHECK-NEXT: unreachable1669; CHECK: [[BB23]]:1670; CHECK-NEXT: [[RES1:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.div.sh.round(<8 x half> [[RES0]], <8 x half> [[X2]], <8 x half> [[SRC]], i8 [[MASK]], i32 4)1671; CHECK-NEXT: [[TMP25:%.*]] = extractelement <8 x i16> [[_MSPROP2]], i32 01672; CHECK-NEXT: [[TMP26:%.*]] = extractelement <8 x i16> [[TMP3]], i32 01673; CHECK-NEXT: [[TMP27:%.*]] = or i16 [[TMP25]], [[TMP26]]1674; CHECK-NEXT: [[TMP30:%.*]] = bitcast i8 [[MASK]] to <8 x i1>1675; CHECK-NEXT: [[TMP28:%.*]] = extractelement <8 x i1> [[TMP30]], i32 01676; CHECK-NEXT: [[TMP29:%.*]] = select i1 [[TMP28]], i16 [[TMP27]], i16 01677; CHECK-NEXT: [[_MSPROP3:%.*]] = insertelement <8 x i16> [[_MSPROP2]], i16 [[TMP29]], i32 01678; CHECK-NEXT: [[_MSCMP9:%.*]] = icmp ne i8 [[TMP5]], 01679; CHECK-NEXT: br i1 [[_MSCMP9]], label %[[BB30:.*]], label %[[BB31:.*]], !prof [[PROF1]]1680; CHECK: [[BB30]]:1681; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1682; CHECK-NEXT: unreachable1683; CHECK: [[BB31]]:1684; CHECK-NEXT: [[RES2:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.div.sh.round(<8 x half> [[RES1]], <8 x half> [[X2]], <8 x half> zeroinitializer, i8 [[MASK]], i32 4)1685; CHECK-NEXT: [[TMP33:%.*]] = extractelement <8 x i16> [[_MSPROP3]], i32 01686; CHECK-NEXT: [[TMP34:%.*]] = extractelement <8 x i16> [[_MSPROP]], i32 01687; CHECK-NEXT: [[TMP35:%.*]] = or i16 [[TMP33]], [[TMP34]]1688; CHECK-NEXT: [[TMP36:%.*]] = extractelement <8 x i16> [[TMP6]], i32 01689; CHECK-NEXT: [[TMP39:%.*]] = bitcast i8 [[MASK]] to <8 x i1>1690; CHECK-NEXT: [[TMP37:%.*]] = extractelement <8 x i1> [[TMP39]], i32 01691; CHECK-NEXT: [[TMP38:%.*]] = select i1 [[TMP37]], i16 [[TMP35]], i16 [[TMP36]]1692; CHECK-NEXT: [[_MSPROP4:%.*]] = insertelement <8 x i16> [[_MSPROP3]], i16 [[TMP38]], i32 01693; CHECK-NEXT: [[_MSCMP14:%.*]] = icmp ne i8 [[TMP5]], 01694; CHECK-NEXT: br i1 [[_MSCMP14]], label %[[BB39:.*]], label %[[BB40:.*]], !prof [[PROF1]]1695; CHECK: [[BB39]]:1696; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1697; CHECK-NEXT: unreachable1698; CHECK: [[BB40]]:1699; CHECK-NEXT: [[RES3:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.div.sh.round(<8 x half> [[RES2]], <8 x half> [[VAL]], <8 x half> [[SRC]], i8 [[MASK]], i32 4)1700; CHECK-NEXT: store <8 x i16> [[_MSPROP4]], ptr @__msan_retval_tls, align 81701; CHECK-NEXT: ret <8 x half> [[RES3]]1702;1703 %val.half = load half,ptr %ptr1704 %val = insertelement <8 x half> poison, half %val.half, i32 01705 %res0 = call <8 x half> @llvm.x86.avx512fp16.mask.div.sh.round(<8 x half> %x1, <8 x half> %x2, <8 x half> zeroinitializer, i8 -1, i32 4)1706 %res1 = call <8 x half> @llvm.x86.avx512fp16.mask.div.sh.round(<8 x half> %res0, <8 x half> %x2, <8 x half> %src , i8 %mask, i32 4)1707 %res2 = call <8 x half> @llvm.x86.avx512fp16.mask.div.sh.round(<8 x half> %res1, <8 x half> %x2, <8 x half> zeroinitializer , i8 %mask, i32 4)1708 %res3 = call <8 x half> @llvm.x86.avx512fp16.mask.div.sh.round(<8 x half> %res2, <8 x half> %val, <8 x half> %src , i8 %mask, i32 4)1709 ret <8 x half> %res31710}1711 1712declare <8 x half> @llvm.x86.avx512fp16.mask.min.sh.round(<8 x half>, <8 x half>, <8 x half>, i8, i32)1713 1714define <8 x half> @test_int_x86_avx512fp16_mask_min_sh(<8 x half> %x1, <8 x half> %x2, <8 x half> %src, i8 %mask, ptr %ptr) #0 {1715; CHECK-LABEL: define <8 x half> @test_int_x86_avx512fp16_mask_min_sh(1716; CHECK-SAME: <8 x half> [[X1:%.*]], <8 x half> [[X2:%.*]], <8 x half> [[SRC:%.*]], i8 [[MASK:%.*]], ptr [[PTR:%.*]]) #[[ATTR1]] {1717; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 56), align 81718; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81719; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81720; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 81721; CHECK-NEXT: [[TMP6:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81722; CHECK-NEXT: call void @llvm.donothing()1723; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01724; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]1725; CHECK: [[BB6]]:1726; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1727; CHECK-NEXT: unreachable1728; CHECK: [[BB7]]:1729; CHECK-NEXT: [[VAL_HALF:%.*]] = load half, ptr [[PTR]], align 21730; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[PTR]] to i641731; CHECK-NEXT: [[TMP9:%.*]] = xor i64 [[TMP8]], 879609302220801732; CHECK-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP9]] to ptr1733; CHECK-NEXT: [[_MSLD:%.*]] = load i16, ptr [[TMP10]], align 21734; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <8 x i16> splat (i16 -1), i16 [[_MSLD]], i32 01735; CHECK-NEXT: [[VAL:%.*]] = insertelement <8 x half> poison, half [[VAL_HALF]], i32 01736; CHECK-NEXT: [[TMP11:%.*]] = extractelement <8 x i16> [[TMP2]], i32 01737; CHECK-NEXT: [[TMP12:%.*]] = extractelement <8 x i16> [[TMP3]], i32 01738; CHECK-NEXT: [[TMP13:%.*]] = or i16 [[TMP11]], [[TMP12]]1739; CHECK-NEXT: [[TMP14:%.*]] = select i1 true, i16 [[TMP13]], i16 01740; CHECK-NEXT: [[_MSPROP1:%.*]] = insertelement <8 x i16> [[TMP2]], i16 [[TMP14]], i32 01741; CHECK-NEXT: [[RES0:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.min.sh.round(<8 x half> [[X1]], <8 x half> [[X2]], <8 x half> zeroinitializer, i8 -1, i32 4)1742; CHECK-NEXT: [[TMP16:%.*]] = extractelement <8 x i16> [[_MSPROP1]], i32 01743; CHECK-NEXT: [[TMP17:%.*]] = extractelement <8 x i16> [[TMP3]], i32 01744; CHECK-NEXT: [[TMP18:%.*]] = or i16 [[TMP16]], [[TMP17]]1745; CHECK-NEXT: [[TMP19:%.*]] = extractelement <8 x i16> [[TMP6]], i32 01746; CHECK-NEXT: [[TMP22:%.*]] = bitcast i8 [[MASK]] to <8 x i1>1747; CHECK-NEXT: [[TMP20:%.*]] = extractelement <8 x i1> [[TMP22]], i32 01748; CHECK-NEXT: [[TMP21:%.*]] = select i1 [[TMP20]], i16 [[TMP18]], i16 [[TMP19]]1749; CHECK-NEXT: [[_MSPROP2:%.*]] = insertelement <8 x i16> [[_MSPROP1]], i16 [[TMP21]], i32 01750; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i8 [[TMP5]], 01751; CHECK-NEXT: br i1 [[_MSCMP6]], label %[[BB22:.*]], label %[[BB23:.*]], !prof [[PROF1]]1752; CHECK: [[BB22]]:1753; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1754; CHECK-NEXT: unreachable1755; CHECK: [[BB23]]:1756; CHECK-NEXT: [[RES1:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.min.sh.round(<8 x half> [[RES0]], <8 x half> [[X2]], <8 x half> [[SRC]], i8 [[MASK]], i32 4)1757; CHECK-NEXT: [[TMP25:%.*]] = extractelement <8 x i16> [[_MSPROP2]], i32 01758; CHECK-NEXT: [[TMP26:%.*]] = extractelement <8 x i16> [[TMP3]], i32 01759; CHECK-NEXT: [[TMP27:%.*]] = or i16 [[TMP25]], [[TMP26]]1760; CHECK-NEXT: [[TMP30:%.*]] = bitcast i8 [[MASK]] to <8 x i1>1761; CHECK-NEXT: [[TMP28:%.*]] = extractelement <8 x i1> [[TMP30]], i32 01762; CHECK-NEXT: [[TMP29:%.*]] = select i1 [[TMP28]], i16 [[TMP27]], i16 01763; CHECK-NEXT: [[_MSPROP3:%.*]] = insertelement <8 x i16> [[_MSPROP2]], i16 [[TMP29]], i32 01764; CHECK-NEXT: [[_MSCMP9:%.*]] = icmp ne i8 [[TMP5]], 01765; CHECK-NEXT: br i1 [[_MSCMP9]], label %[[BB30:.*]], label %[[BB31:.*]], !prof [[PROF1]]1766; CHECK: [[BB30]]:1767; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1768; CHECK-NEXT: unreachable1769; CHECK: [[BB31]]:1770; CHECK-NEXT: [[RES2:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.min.sh.round(<8 x half> [[RES1]], <8 x half> [[X2]], <8 x half> zeroinitializer, i8 [[MASK]], i32 4)1771; CHECK-NEXT: [[TMP33:%.*]] = extractelement <8 x i16> [[_MSPROP3]], i32 01772; CHECK-NEXT: [[TMP34:%.*]] = extractelement <8 x i16> [[_MSPROP]], i32 01773; CHECK-NEXT: [[TMP35:%.*]] = or i16 [[TMP33]], [[TMP34]]1774; CHECK-NEXT: [[TMP36:%.*]] = extractelement <8 x i16> [[TMP6]], i32 01775; CHECK-NEXT: [[TMP39:%.*]] = bitcast i8 [[MASK]] to <8 x i1>1776; CHECK-NEXT: [[TMP37:%.*]] = extractelement <8 x i1> [[TMP39]], i32 01777; CHECK-NEXT: [[TMP38:%.*]] = select i1 [[TMP37]], i16 [[TMP35]], i16 [[TMP36]]1778; CHECK-NEXT: [[_MSPROP4:%.*]] = insertelement <8 x i16> [[_MSPROP3]], i16 [[TMP38]], i32 01779; CHECK-NEXT: [[_MSCMP14:%.*]] = icmp ne i8 [[TMP5]], 01780; CHECK-NEXT: br i1 [[_MSCMP14]], label %[[BB39:.*]], label %[[BB40:.*]], !prof [[PROF1]]1781; CHECK: [[BB39]]:1782; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1783; CHECK-NEXT: unreachable1784; CHECK: [[BB40]]:1785; CHECK-NEXT: [[RES3:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.min.sh.round(<8 x half> [[RES2]], <8 x half> [[VAL]], <8 x half> [[SRC]], i8 [[MASK]], i32 4)1786; CHECK-NEXT: store <8 x i16> [[_MSPROP4]], ptr @__msan_retval_tls, align 81787; CHECK-NEXT: ret <8 x half> [[RES3]]1788;1789 %val.half = load half,ptr %ptr1790 %val = insertelement <8 x half> poison, half %val.half, i32 01791 %res0 = call <8 x half> @llvm.x86.avx512fp16.mask.min.sh.round(<8 x half> %x1, <8 x half> %x2, <8 x half> zeroinitializer, i8 -1, i32 4)1792 %res1 = call <8 x half> @llvm.x86.avx512fp16.mask.min.sh.round(<8 x half> %res0, <8 x half> %x2, <8 x half> %src , i8 %mask, i32 4)1793 %res2 = call <8 x half> @llvm.x86.avx512fp16.mask.min.sh.round(<8 x half> %res1, <8 x half> %x2, <8 x half> zeroinitializer , i8 %mask, i32 4)1794 %res3 = call <8 x half> @llvm.x86.avx512fp16.mask.min.sh.round(<8 x half> %res2, <8 x half> %val, <8 x half> %src , i8 %mask, i32 4)1795 ret <8 x half> %res31796}1797 1798declare <8 x half> @llvm.x86.avx512fp16.mask.max.sh.round(<8 x half>, <8 x half>, <8 x half>, i8, i32)1799 1800define <8 x half> @test_int_x86_avx512fp16_mask_max_sh(<8 x half> %x1, <8 x half> %x2, <8 x half> %src, i8 %mask, ptr %ptr) #0 {1801; CHECK-LABEL: define <8 x half> @test_int_x86_avx512fp16_mask_max_sh(1802; CHECK-SAME: <8 x half> [[X1:%.*]], <8 x half> [[X2:%.*]], <8 x half> [[SRC:%.*]], i8 [[MASK:%.*]], ptr [[PTR:%.*]]) #[[ATTR1]] {1803; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 56), align 81804; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81805; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81806; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 81807; CHECK-NEXT: [[TMP6:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81808; CHECK-NEXT: call void @llvm.donothing()1809; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01810; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]1811; CHECK: [[BB6]]:1812; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1813; CHECK-NEXT: unreachable1814; CHECK: [[BB7]]:1815; CHECK-NEXT: [[VAL_HALF:%.*]] = load half, ptr [[PTR]], align 21816; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[PTR]] to i641817; CHECK-NEXT: [[TMP9:%.*]] = xor i64 [[TMP8]], 879609302220801818; CHECK-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP9]] to ptr1819; CHECK-NEXT: [[_MSLD:%.*]] = load i16, ptr [[TMP10]], align 21820; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <8 x i16> splat (i16 -1), i16 [[_MSLD]], i32 01821; CHECK-NEXT: [[VAL:%.*]] = insertelement <8 x half> poison, half [[VAL_HALF]], i32 01822; CHECK-NEXT: [[TMP11:%.*]] = extractelement <8 x i16> [[TMP2]], i32 01823; CHECK-NEXT: [[TMP12:%.*]] = extractelement <8 x i16> [[TMP3]], i32 01824; CHECK-NEXT: [[TMP13:%.*]] = or i16 [[TMP11]], [[TMP12]]1825; CHECK-NEXT: [[TMP14:%.*]] = select i1 true, i16 [[TMP13]], i16 01826; CHECK-NEXT: [[_MSPROP1:%.*]] = insertelement <8 x i16> [[TMP2]], i16 [[TMP14]], i32 01827; CHECK-NEXT: [[RES0:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.max.sh.round(<8 x half> [[X1]], <8 x half> [[X2]], <8 x half> zeroinitializer, i8 -1, i32 4)1828; CHECK-NEXT: [[TMP16:%.*]] = extractelement <8 x i16> [[_MSPROP1]], i32 01829; CHECK-NEXT: [[TMP17:%.*]] = extractelement <8 x i16> [[TMP3]], i32 01830; CHECK-NEXT: [[TMP18:%.*]] = or i16 [[TMP16]], [[TMP17]]1831; CHECK-NEXT: [[TMP19:%.*]] = extractelement <8 x i16> [[TMP6]], i32 01832; CHECK-NEXT: [[TMP22:%.*]] = bitcast i8 [[MASK]] to <8 x i1>1833; CHECK-NEXT: [[TMP20:%.*]] = extractelement <8 x i1> [[TMP22]], i32 01834; CHECK-NEXT: [[TMP21:%.*]] = select i1 [[TMP20]], i16 [[TMP18]], i16 [[TMP19]]1835; CHECK-NEXT: [[_MSPROP2:%.*]] = insertelement <8 x i16> [[_MSPROP1]], i16 [[TMP21]], i32 01836; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i8 [[TMP5]], 01837; CHECK-NEXT: br i1 [[_MSCMP6]], label %[[BB22:.*]], label %[[BB23:.*]], !prof [[PROF1]]1838; CHECK: [[BB22]]:1839; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1840; CHECK-NEXT: unreachable1841; CHECK: [[BB23]]:1842; CHECK-NEXT: [[RES1:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.max.sh.round(<8 x half> [[RES0]], <8 x half> [[X2]], <8 x half> [[SRC]], i8 [[MASK]], i32 4)1843; CHECK-NEXT: [[TMP25:%.*]] = extractelement <8 x i16> [[_MSPROP2]], i32 01844; CHECK-NEXT: [[TMP26:%.*]] = extractelement <8 x i16> [[TMP3]], i32 01845; CHECK-NEXT: [[TMP27:%.*]] = or i16 [[TMP25]], [[TMP26]]1846; CHECK-NEXT: [[TMP30:%.*]] = bitcast i8 [[MASK]] to <8 x i1>1847; CHECK-NEXT: [[TMP28:%.*]] = extractelement <8 x i1> [[TMP30]], i32 01848; CHECK-NEXT: [[TMP29:%.*]] = select i1 [[TMP28]], i16 [[TMP27]], i16 01849; CHECK-NEXT: [[_MSPROP3:%.*]] = insertelement <8 x i16> [[_MSPROP2]], i16 [[TMP29]], i32 01850; CHECK-NEXT: [[_MSCMP9:%.*]] = icmp ne i8 [[TMP5]], 01851; CHECK-NEXT: br i1 [[_MSCMP9]], label %[[BB30:.*]], label %[[BB31:.*]], !prof [[PROF1]]1852; CHECK: [[BB30]]:1853; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1854; CHECK-NEXT: unreachable1855; CHECK: [[BB31]]:1856; CHECK-NEXT: [[RES2:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.max.sh.round(<8 x half> [[RES1]], <8 x half> [[X2]], <8 x half> zeroinitializer, i8 [[MASK]], i32 4)1857; CHECK-NEXT: [[TMP33:%.*]] = extractelement <8 x i16> [[_MSPROP3]], i32 01858; CHECK-NEXT: [[TMP34:%.*]] = extractelement <8 x i16> [[_MSPROP]], i32 01859; CHECK-NEXT: [[TMP35:%.*]] = or i16 [[TMP33]], [[TMP34]]1860; CHECK-NEXT: [[TMP36:%.*]] = extractelement <8 x i16> [[TMP6]], i32 01861; CHECK-NEXT: [[TMP39:%.*]] = bitcast i8 [[MASK]] to <8 x i1>1862; CHECK-NEXT: [[TMP37:%.*]] = extractelement <8 x i1> [[TMP39]], i32 01863; CHECK-NEXT: [[TMP38:%.*]] = select i1 [[TMP37]], i16 [[TMP35]], i16 [[TMP36]]1864; CHECK-NEXT: [[_MSPROP4:%.*]] = insertelement <8 x i16> [[_MSPROP3]], i16 [[TMP38]], i32 01865; CHECK-NEXT: [[_MSCMP14:%.*]] = icmp ne i8 [[TMP5]], 01866; CHECK-NEXT: br i1 [[_MSCMP14]], label %[[BB39:.*]], label %[[BB40:.*]], !prof [[PROF1]]1867; CHECK: [[BB39]]:1868; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1869; CHECK-NEXT: unreachable1870; CHECK: [[BB40]]:1871; CHECK-NEXT: [[RES3:%.*]] = call <8 x half> @llvm.x86.avx512fp16.mask.max.sh.round(<8 x half> [[RES2]], <8 x half> [[VAL]], <8 x half> [[SRC]], i8 [[MASK]], i32 4)1872; CHECK-NEXT: store <8 x i16> [[_MSPROP4]], ptr @__msan_retval_tls, align 81873; CHECK-NEXT: ret <8 x half> [[RES3]]1874;1875 %val.half = load half,ptr %ptr1876 %val = insertelement <8 x half> poison, half %val.half, i32 01877 %res0 = call <8 x half> @llvm.x86.avx512fp16.mask.max.sh.round(<8 x half> %x1, <8 x half> %x2, <8 x half> zeroinitializer, i8 -1, i32 4)1878 %res1 = call <8 x half> @llvm.x86.avx512fp16.mask.max.sh.round(<8 x half> %res0, <8 x half> %x2, <8 x half> %src , i8 %mask, i32 4)1879 %res2 = call <8 x half> @llvm.x86.avx512fp16.mask.max.sh.round(<8 x half> %res1, <8 x half> %x2, <8 x half> zeroinitializer , i8 %mask, i32 4)1880 %res3 = call <8 x half> @llvm.x86.avx512fp16.mask.max.sh.round(<8 x half> %res2, <8 x half> %val, <8 x half> %src , i8 %mask, i32 4)1881 ret <8 x half> %res31882}1883 1884declare i8 @llvm.x86.avx512fp16.mask.cmp.sh(<8 x half>, <8 x half>, i32, i8, i32)1885 1886define i8 @test_int_x86_avx512_mask_cmp_sh(<8 x half> %x0, <8 x half> %x1, i8 %x3, i32 %x4) #0 {1887; CHECK-LABEL: define i8 @test_int_x86_avx512_mask_cmp_sh(1888; CHECK-SAME: <8 x half> [[X0:%.*]], <8 x half> [[X1:%.*]], i8 [[X3:%.*]], i32 [[X4:%.*]]) #[[ATTR1]] {1889; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81890; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81891; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81892; CHECK-NEXT: call void @llvm.donothing()1893; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i16> [[TMP1]] to i1281894; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 01895; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP2]] to i1281896; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 01897; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1898; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 01899; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]1900; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]1901; CHECK: [[BB6]]:1902; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1903; CHECK-NEXT: unreachable1904; CHECK: [[BB7]]:1905; CHECK-NEXT: [[RES2:%.*]] = call i8 @llvm.x86.avx512fp16.mask.cmp.sh(<8 x half> [[X0]], <8 x half> [[X1]], i32 3, i8 [[X3]], i32 4)1906; CHECK-NEXT: store i8 0, ptr @__msan_retval_tls, align 81907; CHECK-NEXT: ret i8 [[RES2]]1908;1909 %res2 = call i8 @llvm.x86.avx512fp16.mask.cmp.sh(<8 x half> %x0, <8 x half> %x1, i32 3, i8 %x3, i32 4)1910 ret i8 %res21911}1912 1913 1914define i8 @test_int_x86_avx512_mask_cmp_sh_all(<8 x half> %x0, <8 x half> %x1, i8 %x3, i32 %x4) #0 {1915; CHECK-LABEL: define i8 @test_int_x86_avx512_mask_cmp_sh_all(1916; CHECK-SAME: <8 x half> [[X0:%.*]], <8 x half> [[X1:%.*]], i8 [[X3:%.*]], i32 [[X4:%.*]]) #[[ATTR1]] {1917; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81918; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81919; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81920; CHECK-NEXT: call void @llvm.donothing()1921; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i16> [[TMP1]] to i1281922; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 01923; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP2]] to i1281924; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 01925; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1926; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]1927; CHECK: [[BB6]]:1928; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1929; CHECK-NEXT: unreachable1930; CHECK: [[BB7]]:1931; CHECK-NEXT: [[RES1:%.*]] = call i8 @llvm.x86.avx512fp16.mask.cmp.sh(<8 x half> [[X0]], <8 x half> [[X1]], i32 2, i8 -1, i32 4)1932; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i16> [[TMP1]] to i1281933; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP8]], 01934; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i16> [[TMP2]] to i1281935; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP9]], 01936; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]1937; CHECK-NEXT: br i1 [[_MSOR4]], label %[[BB10:.*]], label %[[BB11:.*]], !prof [[PROF1]]1938; CHECK: [[BB10]]:1939; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1940; CHECK-NEXT: unreachable1941; CHECK: [[BB11]]:1942; CHECK-NEXT: [[RES2:%.*]] = call i8 @llvm.x86.avx512fp16.mask.cmp.sh(<8 x half> [[X0]], <8 x half> [[X1]], i32 3, i8 -1, i32 8)1943; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x i16> [[TMP1]] to i1281944; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i128 [[TMP12]], 01945; CHECK-NEXT: [[TMP13:%.*]] = bitcast <8 x i16> [[TMP2]] to i1281946; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i128 [[TMP13]], 01947; CHECK-NEXT: [[_MSOR7:%.*]] = or i1 [[_MSCMP5]], [[_MSCMP6]]1948; CHECK-NEXT: [[_MSCMP8:%.*]] = icmp ne i8 [[TMP3]], 01949; CHECK-NEXT: [[_MSOR9:%.*]] = or i1 [[_MSOR7]], [[_MSCMP8]]1950; CHECK-NEXT: br i1 [[_MSOR9]], label %[[BB14:.*]], label %[[BB15:.*]], !prof [[PROF1]]1951; CHECK: [[BB14]]:1952; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1953; CHECK-NEXT: unreachable1954; CHECK: [[BB15]]:1955; CHECK-NEXT: [[RES3:%.*]] = call i8 @llvm.x86.avx512fp16.mask.cmp.sh(<8 x half> [[X0]], <8 x half> [[X1]], i32 4, i8 [[X3]], i32 4)1956; CHECK-NEXT: [[TMP16:%.*]] = bitcast <8 x i16> [[TMP1]] to i1281957; CHECK-NEXT: [[_MSCMP10:%.*]] = icmp ne i128 [[TMP16]], 01958; CHECK-NEXT: [[TMP17:%.*]] = bitcast <8 x i16> [[TMP2]] to i1281959; CHECK-NEXT: [[_MSCMP11:%.*]] = icmp ne i128 [[TMP17]], 01960; CHECK-NEXT: [[_MSOR12:%.*]] = or i1 [[_MSCMP10]], [[_MSCMP11]]1961; CHECK-NEXT: [[_MSCMP13:%.*]] = icmp ne i8 [[TMP3]], 01962; CHECK-NEXT: [[_MSOR14:%.*]] = or i1 [[_MSOR12]], [[_MSCMP13]]1963; CHECK-NEXT: br i1 [[_MSOR14]], label %[[BB18:.*]], label %[[BB19:.*]], !prof [[PROF1]]1964; CHECK: [[BB18]]:1965; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1966; CHECK-NEXT: unreachable1967; CHECK: [[BB19]]:1968; CHECK-NEXT: [[RES4:%.*]] = call i8 @llvm.x86.avx512fp16.mask.cmp.sh(<8 x half> [[X0]], <8 x half> [[X1]], i32 5, i8 [[X3]], i32 8)1969; CHECK-NEXT: [[TMP20:%.*]] = and i8 [[RES1]], 01970; CHECK-NEXT: [[TMP21:%.*]] = and i8 0, [[RES2]]1971; CHECK-NEXT: [[TMP22:%.*]] = or i8 0, [[TMP20]]1972; CHECK-NEXT: [[TMP23:%.*]] = or i8 [[TMP22]], [[TMP21]]1973; CHECK-NEXT: [[RES11:%.*]] = and i8 [[RES1]], [[RES2]]1974; CHECK-NEXT: [[TMP24:%.*]] = and i8 [[RES3]], 01975; CHECK-NEXT: [[TMP25:%.*]] = and i8 0, [[RES4]]1976; CHECK-NEXT: [[TMP26:%.*]] = or i8 0, [[TMP24]]1977; CHECK-NEXT: [[TMP27:%.*]] = or i8 [[TMP26]], [[TMP25]]1978; CHECK-NEXT: [[RES12:%.*]] = and i8 [[RES3]], [[RES4]]1979; CHECK-NEXT: [[TMP28:%.*]] = and i8 [[TMP23]], [[TMP27]]1980; CHECK-NEXT: [[TMP29:%.*]] = and i8 [[RES11]], [[TMP27]]1981; CHECK-NEXT: [[TMP30:%.*]] = and i8 [[TMP23]], [[RES12]]1982; CHECK-NEXT: [[TMP31:%.*]] = or i8 [[TMP28]], [[TMP29]]1983; CHECK-NEXT: [[TMP32:%.*]] = or i8 [[TMP31]], [[TMP30]]1984; CHECK-NEXT: [[RES13:%.*]] = and i8 [[RES11]], [[RES12]]1985; CHECK-NEXT: store i8 [[TMP32]], ptr @__msan_retval_tls, align 81986; CHECK-NEXT: ret i8 [[RES13]]1987;1988 %res1 = call i8 @llvm.x86.avx512fp16.mask.cmp.sh(<8 x half> %x0, <8 x half> %x1, i32 2, i8 -1, i32 4)1989 %res2 = call i8 @llvm.x86.avx512fp16.mask.cmp.sh(<8 x half> %x0, <8 x half> %x1, i32 3, i8 -1, i32 8)1990 %res3 = call i8 @llvm.x86.avx512fp16.mask.cmp.sh(<8 x half> %x0, <8 x half> %x1, i32 4, i8 %x3, i32 4)1991 %res4 = call i8 @llvm.x86.avx512fp16.mask.cmp.sh(<8 x half> %x0, <8 x half> %x1, i32 5, i8 %x3, i32 8)1992 1993 %res11 = and i8 %res1, %res21994 %res12 = and i8 %res3, %res41995 %res13 = and i8 %res11, %res121996 ret i8 %res131997}1998 1999declare <16 x half> @llvm.x86.avx512.sitofp.round.v16f16.v16i32(<16 x i32>, i32)2000 2001define <16 x half> @test_int_x86_avx512_mask_cvt_dq2ph_512(<16 x i32> %x0, <16 x half> %x1, i16 %x2) #0 {2002; CHECK-LABEL: define <16 x half> @test_int_x86_avx512_mask_cvt_dq2ph_512(2003; CHECK-SAME: <16 x i32> [[X0:%.*]], <16 x half> [[X1:%.*]], i16 [[X2:%.*]]) #[[ATTR1]] {2004; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 82005; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 82006; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82007; CHECK-NEXT: call void @llvm.donothing()2008; CHECK-NEXT: [[TMP4:%.*]] = bitcast i16 [[TMP1]] to <16 x i1>2009; CHECK-NEXT: [[MASK:%.*]] = bitcast i16 [[X2]] to <16 x i1>2010; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP2]] to i5122011; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP5]], 02012; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]2013; CHECK: [[BB6]]:2014; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2015; CHECK-NEXT: unreachable2016; CHECK: [[BB7]]:2017; CHECK-NEXT: [[RES0:%.*]] = call <16 x half> @llvm.x86.avx512.sitofp.round.v16f16.v16i32(<16 x i32> [[X0]], i32 4)2018; CHECK-NEXT: [[TMP8:%.*]] = select <16 x i1> [[MASK]], <16 x i16> zeroinitializer, <16 x i16> [[TMP3]]2019; CHECK-NEXT: [[TMP9:%.*]] = bitcast <16 x half> [[RES0]] to <16 x i16>2020; CHECK-NEXT: [[TMP10:%.*]] = bitcast <16 x half> [[X1]] to <16 x i16>2021; CHECK-NEXT: [[TMP11:%.*]] = xor <16 x i16> [[TMP9]], [[TMP10]]2022; CHECK-NEXT: [[TMP12:%.*]] = or <16 x i16> [[TMP11]], zeroinitializer2023; CHECK-NEXT: [[TMP13:%.*]] = or <16 x i16> [[TMP12]], [[TMP3]]2024; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP4]], <16 x i16> [[TMP13]], <16 x i16> [[TMP8]]2025; CHECK-NEXT: [[RES:%.*]] = select <16 x i1> [[MASK]], <16 x half> [[RES0]], <16 x half> [[X1]]2026; CHECK-NEXT: store <16 x i16> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82027; CHECK-NEXT: ret <16 x half> [[RES]]2028;2029 %mask = bitcast i16 %x2 to <16 x i1>2030 %res0 = call <16 x half> @llvm.x86.avx512.sitofp.round.v16f16.v16i32(<16 x i32> %x0, i32 4)2031 %res = select <16 x i1> %mask, <16 x half> %res0, <16 x half> %x12032 ret <16 x half> %res2033}2034 2035define <16 x half> @test_int_x86_avx512_mask_cvt_dq2ph_512_r(<16 x i32> %x0, <16 x half> %x1, i16 %x2) #0 {2036; CHECK-LABEL: define <16 x half> @test_int_x86_avx512_mask_cvt_dq2ph_512_r(2037; CHECK-SAME: <16 x i32> [[X0:%.*]], <16 x half> [[X1:%.*]], i16 [[X2:%.*]]) #[[ATTR1]] {2038; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 82039; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 82040; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82041; CHECK-NEXT: call void @llvm.donothing()2042; CHECK-NEXT: [[TMP4:%.*]] = bitcast i16 [[TMP1]] to <16 x i1>2043; CHECK-NEXT: [[MASK:%.*]] = bitcast i16 [[X2]] to <16 x i1>2044; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP2]] to i5122045; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP5]], 02046; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]2047; CHECK: [[BB6]]:2048; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2049; CHECK-NEXT: unreachable2050; CHECK: [[BB7]]:2051; CHECK-NEXT: [[RES0:%.*]] = call <16 x half> @llvm.x86.avx512.sitofp.round.v16f16.v16i32(<16 x i32> [[X0]], i32 10)2052; CHECK-NEXT: [[TMP8:%.*]] = select <16 x i1> [[MASK]], <16 x i16> zeroinitializer, <16 x i16> [[TMP3]]2053; CHECK-NEXT: [[TMP9:%.*]] = bitcast <16 x half> [[RES0]] to <16 x i16>2054; CHECK-NEXT: [[TMP10:%.*]] = bitcast <16 x half> [[X1]] to <16 x i16>2055; CHECK-NEXT: [[TMP11:%.*]] = xor <16 x i16> [[TMP9]], [[TMP10]]2056; CHECK-NEXT: [[TMP12:%.*]] = or <16 x i16> [[TMP11]], zeroinitializer2057; CHECK-NEXT: [[TMP13:%.*]] = or <16 x i16> [[TMP12]], [[TMP3]]2058; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP4]], <16 x i16> [[TMP13]], <16 x i16> [[TMP8]]2059; CHECK-NEXT: [[RES:%.*]] = select <16 x i1> [[MASK]], <16 x half> [[RES0]], <16 x half> [[X1]]2060; CHECK-NEXT: store <16 x i16> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82061; CHECK-NEXT: ret <16 x half> [[RES]]2062;2063 %mask = bitcast i16 %x2 to <16 x i1>2064 %res0 = call <16 x half> @llvm.x86.avx512.sitofp.round.v16f16.v16i32(<16 x i32> %x0, i32 10)2065 %res = select <16 x i1> %mask, <16 x half> %res0, <16 x half> %x12066 ret <16 x half> %res2067}2068 2069define <16 x half> @test_int_x86_avx512_mask_cvt_dq2ph_512_nomask(<16 x i32> %x0, <16 x half> %x1) #0 {2070; CHECK-LABEL: define <16 x half> @test_int_x86_avx512_mask_cvt_dq2ph_512_nomask(2071; CHECK-SAME: <16 x i32> [[X0:%.*]], <16 x half> [[X1:%.*]]) #[[ATTR1]] {2072; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 82073; CHECK-NEXT: call void @llvm.donothing()2074; CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i32> [[TMP1]] to i5122075; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP2]], 02076; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]2077; CHECK: [[BB3]]:2078; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2079; CHECK-NEXT: unreachable2080; CHECK: [[BB4]]:2081; CHECK-NEXT: [[RES:%.*]] = call <16 x half> @llvm.x86.avx512.sitofp.round.v16f16.v16i32(<16 x i32> [[X0]], i32 4)2082; CHECK-NEXT: store <16 x i16> zeroinitializer, ptr @__msan_retval_tls, align 82083; CHECK-NEXT: ret <16 x half> [[RES]]2084;2085 %res = call <16 x half> @llvm.x86.avx512.sitofp.round.v16f16.v16i32(<16 x i32> %x0, i32 4)2086 ret <16 x half> %res2087}2088 2089define <16 x half> @test_int_x86_avx512_mask_cvt_dq2ph_512_z(<16 x i32> %x0, i16 %x2) #0 {2090; CHECK-LABEL: define <16 x half> @test_int_x86_avx512_mask_cvt_dq2ph_512_z(2091; CHECK-SAME: <16 x i32> [[X0:%.*]], i16 [[X2:%.*]]) #[[ATTR1]] {2092; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82093; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 82094; CHECK-NEXT: call void @llvm.donothing()2095; CHECK-NEXT: [[TMP3:%.*]] = bitcast i16 [[TMP1]] to <16 x i1>2096; CHECK-NEXT: [[MASK:%.*]] = bitcast i16 [[X2]] to <16 x i1>2097; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP2]] to i5122098; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP4]], 02099; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]2100; CHECK: [[BB5]]:2101; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2102; CHECK-NEXT: unreachable2103; CHECK: [[BB6]]:2104; CHECK-NEXT: [[RES0:%.*]] = call <16 x half> @llvm.x86.avx512.sitofp.round.v16f16.v16i32(<16 x i32> [[X0]], i32 4)2105; CHECK-NEXT: [[TMP7:%.*]] = select <16 x i1> [[MASK]], <16 x i16> zeroinitializer, <16 x i16> zeroinitializer2106; CHECK-NEXT: [[TMP8:%.*]] = bitcast <16 x half> [[RES0]] to <16 x i16>2107; CHECK-NEXT: [[TMP9:%.*]] = xor <16 x i16> [[TMP8]], zeroinitializer2108; CHECK-NEXT: [[TMP10:%.*]] = or <16 x i16> [[TMP9]], zeroinitializer2109; CHECK-NEXT: [[TMP11:%.*]] = or <16 x i16> [[TMP10]], zeroinitializer2110; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP3]], <16 x i16> [[TMP11]], <16 x i16> [[TMP7]]2111; CHECK-NEXT: [[RES:%.*]] = select <16 x i1> [[MASK]], <16 x half> [[RES0]], <16 x half> zeroinitializer2112; CHECK-NEXT: store <16 x i16> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82113; CHECK-NEXT: ret <16 x half> [[RES]]2114;2115 %mask = bitcast i16 %x2 to <16 x i1>2116 %res0 = call <16 x half> @llvm.x86.avx512.sitofp.round.v16f16.v16i32(<16 x i32> %x0, i32 4)2117 %res = select <16 x i1> %mask, <16 x half> %res0, <16 x half> zeroinitializer2118 ret <16 x half> %res2119}2120 2121define <16 x half> @sint_to_fp_16i32_to_16f16(<16 x i32> %x) #0 {2122; CHECK-LABEL: define <16 x half> @sint_to_fp_16i32_to_16f16(2123; CHECK-SAME: <16 x i32> [[X:%.*]]) #[[ATTR1]] {2124; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 82125; CHECK-NEXT: call void @llvm.donothing()2126; CHECK-NEXT: [[TMP2:%.*]] = trunc <16 x i32> [[TMP1]] to <16 x i16>2127; CHECK-NEXT: [[RES:%.*]] = sitofp <16 x i32> [[X]] to <16 x half>2128; CHECK-NEXT: store <16 x i16> [[TMP2]], ptr @__msan_retval_tls, align 82129; CHECK-NEXT: ret <16 x half> [[RES]]2130;2131 %res = sitofp <16 x i32> %x to <16 x half>2132 ret <16 x half> %res2133}2134 2135declare <16 x half> @llvm.x86.avx512.uitofp.round.v16f16.v16i32(<16 x i32>, i32)2136 2137define <16 x half> @test_int_x86_avx512_mask_cvt_udq2ph_512_r(<16 x i32> %x0, <16 x half> %x1, i16 %x2) #0 {2138; CHECK-LABEL: define <16 x half> @test_int_x86_avx512_mask_cvt_udq2ph_512_r(2139; CHECK-SAME: <16 x i32> [[X0:%.*]], <16 x half> [[X1:%.*]], i16 [[X2:%.*]]) #[[ATTR1]] {2140; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 82141; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 82142; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82143; CHECK-NEXT: call void @llvm.donothing()2144; CHECK-NEXT: [[TMP4:%.*]] = bitcast i16 [[TMP1]] to <16 x i1>2145; CHECK-NEXT: [[MASK:%.*]] = bitcast i16 [[X2]] to <16 x i1>2146; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP2]] to i5122147; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP5]], 02148; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]2149; CHECK: [[BB6]]:2150; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2151; CHECK-NEXT: unreachable2152; CHECK: [[BB7]]:2153; CHECK-NEXT: [[RES0:%.*]] = call <16 x half> @llvm.x86.avx512.uitofp.round.v16f16.v16i32(<16 x i32> [[X0]], i32 10)2154; CHECK-NEXT: [[TMP8:%.*]] = select <16 x i1> [[MASK]], <16 x i16> zeroinitializer, <16 x i16> [[TMP3]]2155; CHECK-NEXT: [[TMP9:%.*]] = bitcast <16 x half> [[RES0]] to <16 x i16>2156; CHECK-NEXT: [[TMP10:%.*]] = bitcast <16 x half> [[X1]] to <16 x i16>2157; CHECK-NEXT: [[TMP11:%.*]] = xor <16 x i16> [[TMP9]], [[TMP10]]2158; CHECK-NEXT: [[TMP12:%.*]] = or <16 x i16> [[TMP11]], zeroinitializer2159; CHECK-NEXT: [[TMP13:%.*]] = or <16 x i16> [[TMP12]], [[TMP3]]2160; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP4]], <16 x i16> [[TMP13]], <16 x i16> [[TMP8]]2161; CHECK-NEXT: [[RES:%.*]] = select <16 x i1> [[MASK]], <16 x half> [[RES0]], <16 x half> [[X1]]2162; CHECK-NEXT: store <16 x i16> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82163; CHECK-NEXT: ret <16 x half> [[RES]]2164;2165 %mask = bitcast i16 %x2 to <16 x i1>2166 %res0 = call <16 x half> @llvm.x86.avx512.uitofp.round.v16f16.v16i32(<16 x i32> %x0, i32 10)2167 %res = select <16 x i1> %mask, <16 x half> %res0, <16 x half> %x12168 ret <16 x half> %res2169}2170 2171define <16 x half> @test_int_x86_avx512_mask_cvt_udq2ph_512_nomask(<16 x i32> %x0, <16 x half> %x1) #0 {2172; CHECK-LABEL: define <16 x half> @test_int_x86_avx512_mask_cvt_udq2ph_512_nomask(2173; CHECK-SAME: <16 x i32> [[X0:%.*]], <16 x half> [[X1:%.*]]) #[[ATTR1]] {2174; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 82175; CHECK-NEXT: call void @llvm.donothing()2176; CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i32> [[TMP1]] to i5122177; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP2]], 02178; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]2179; CHECK: [[BB3]]:2180; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2181; CHECK-NEXT: unreachable2182; CHECK: [[BB4]]:2183; CHECK-NEXT: [[RES:%.*]] = call <16 x half> @llvm.x86.avx512.uitofp.round.v16f16.v16i32(<16 x i32> [[X0]], i32 4)2184; CHECK-NEXT: store <16 x i16> zeroinitializer, ptr @__msan_retval_tls, align 82185; CHECK-NEXT: ret <16 x half> [[RES]]2186;2187 %res = call <16 x half> @llvm.x86.avx512.uitofp.round.v16f16.v16i32(<16 x i32> %x0, i32 4)2188 ret <16 x half> %res2189}2190 2191define <16 x half> @test_int_x86_avx512_mask_cvt_udq2ph_512_z(<16 x i32> %x0, i16 %x2) #0 {2192; CHECK-LABEL: define <16 x half> @test_int_x86_avx512_mask_cvt_udq2ph_512_z(2193; CHECK-SAME: <16 x i32> [[X0:%.*]], i16 [[X2:%.*]]) #[[ATTR1]] {2194; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82195; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 82196; CHECK-NEXT: call void @llvm.donothing()2197; CHECK-NEXT: [[TMP3:%.*]] = bitcast i16 [[TMP1]] to <16 x i1>2198; CHECK-NEXT: [[MASK:%.*]] = bitcast i16 [[X2]] to <16 x i1>2199; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP2]] to i5122200; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP4]], 02201; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]2202; CHECK: [[BB5]]:2203; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2204; CHECK-NEXT: unreachable2205; CHECK: [[BB6]]:2206; CHECK-NEXT: [[RES0:%.*]] = call <16 x half> @llvm.x86.avx512.uitofp.round.v16f16.v16i32(<16 x i32> [[X0]], i32 4)2207; CHECK-NEXT: [[TMP7:%.*]] = select <16 x i1> [[MASK]], <16 x i16> zeroinitializer, <16 x i16> zeroinitializer2208; CHECK-NEXT: [[TMP8:%.*]] = bitcast <16 x half> [[RES0]] to <16 x i16>2209; CHECK-NEXT: [[TMP9:%.*]] = xor <16 x i16> [[TMP8]], zeroinitializer2210; CHECK-NEXT: [[TMP10:%.*]] = or <16 x i16> [[TMP9]], zeroinitializer2211; CHECK-NEXT: [[TMP11:%.*]] = or <16 x i16> [[TMP10]], zeroinitializer2212; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP3]], <16 x i16> [[TMP11]], <16 x i16> [[TMP7]]2213; CHECK-NEXT: [[RES:%.*]] = select <16 x i1> [[MASK]], <16 x half> [[RES0]], <16 x half> zeroinitializer2214; CHECK-NEXT: store <16 x i16> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82215; CHECK-NEXT: ret <16 x half> [[RES]]2216;2217 %mask = bitcast i16 %x2 to <16 x i1>2218 %res0 = call <16 x half> @llvm.x86.avx512.uitofp.round.v16f16.v16i32(<16 x i32> %x0, i32 4)2219 %res = select <16 x i1> %mask, <16 x half> %res0, <16 x half> zeroinitializer2220 ret <16 x half> %res2221}2222 2223define <16 x half> @uint_to_fp_16i32_to_16f16(<16 x i32> %x) #0 {2224; CHECK-LABEL: define <16 x half> @uint_to_fp_16i32_to_16f16(2225; CHECK-SAME: <16 x i32> [[X:%.*]]) #[[ATTR1]] {2226; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 82227; CHECK-NEXT: call void @llvm.donothing()2228; CHECK-NEXT: [[TMP2:%.*]] = trunc <16 x i32> [[TMP1]] to <16 x i16>2229; CHECK-NEXT: [[RES:%.*]] = uitofp <16 x i32> [[X]] to <16 x half>2230; CHECK-NEXT: store <16 x i16> [[TMP2]], ptr @__msan_retval_tls, align 82231; CHECK-NEXT: ret <16 x half> [[RES]]2232;2233 %res = uitofp <16 x i32> %x to <16 x half>2234 ret <16 x half> %res2235}2236 2237declare <16 x i32> @llvm.x86.avx512fp16.mask.vcvtph2dq.512(<16 x half>, <16 x i32>, i16, i32)2238 2239define <16 x i32> @test_int_x86_avx512_mask_cvt_ph2dq_512(<16 x half> %x0, <16 x i32> %x1, i16 %x2) #0 {2240; CHECK-LABEL: define <16 x i32> @test_int_x86_avx512_mask_cvt_ph2dq_512(2241; CHECK-SAME: <16 x half> [[X0:%.*]], <16 x i32> [[X1:%.*]], i16 [[X2:%.*]]) #[[ATTR1]] {2242; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 82243; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 82244; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 82245; CHECK-NEXT: call void @llvm.donothing()2246; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i16> [[TMP1]] to i2562247; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP4]], 02248; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP2]] to i5122249; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP5]], 02250; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]2251; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i16 [[TMP3]], 02252; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]2253; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]2254; CHECK: [[BB6]]:2255; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2256; CHECK-NEXT: unreachable2257; CHECK: [[BB7]]:2258; CHECK-NEXT: [[RES:%.*]] = call <16 x i32> @llvm.x86.avx512fp16.mask.vcvtph2dq.512(<16 x half> [[X0]], <16 x i32> [[X1]], i16 [[X2]], i32 10)2259; CHECK-NEXT: [[TMP8:%.*]] = bitcast <16 x i16> [[TMP1]] to i2562260; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i256 [[TMP8]], 02261; CHECK-NEXT: [[TMP9:%.*]] = bitcast <16 x i32> [[TMP2]] to i5122262; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i512 [[TMP9]], 02263; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSCMP4]], [[_MSCMP5]]2264; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB10:.*]], label %[[BB11:.*]], !prof [[PROF1]]2265; CHECK: [[BB10]]:2266; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2267; CHECK-NEXT: unreachable2268; CHECK: [[BB11]]:2269; CHECK-NEXT: [[RES1:%.*]] = call <16 x i32> @llvm.x86.avx512fp16.mask.vcvtph2dq.512(<16 x half> [[X0]], <16 x i32> [[X1]], i16 -1, i32 8)2270; CHECK-NEXT: [[RES2:%.*]] = add <16 x i32> [[RES]], [[RES1]]2271; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 82272; CHECK-NEXT: ret <16 x i32> [[RES2]]2273;2274 %res = call <16 x i32> @llvm.x86.avx512fp16.mask.vcvtph2dq.512(<16 x half> %x0, <16 x i32> %x1, i16 %x2, i32 10)2275 %res1 = call <16 x i32> @llvm.x86.avx512fp16.mask.vcvtph2dq.512(<16 x half> %x0, <16 x i32> %x1, i16 -1, i32 8)2276 %res2 = add <16 x i32> %res, %res12277 ret <16 x i32> %res22278}2279 2280declare <16 x i32> @llvm.x86.avx512fp16.mask.vcvtph2udq.512(<16 x half>, <16 x i32>, i16, i32)2281 2282define <16 x i32> @test_int_x86_avx512_mask_cvt_ph2udq_512(<16 x half> %x0, <16 x i32> %x1, i16 %x2) #0 {2283; CHECK-LABEL: define <16 x i32> @test_int_x86_avx512_mask_cvt_ph2udq_512(2284; CHECK-SAME: <16 x half> [[X0:%.*]], <16 x i32> [[X1:%.*]], i16 [[X2:%.*]]) #[[ATTR1]] {2285; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 82286; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 82287; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 82288; CHECK-NEXT: call void @llvm.donothing()2289; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i16> [[TMP1]] to i2562290; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP4]], 02291; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP2]] to i5122292; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP5]], 02293; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]2294; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i16 [[TMP3]], 02295; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]2296; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]2297; CHECK: [[BB6]]:2298; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2299; CHECK-NEXT: unreachable2300; CHECK: [[BB7]]:2301; CHECK-NEXT: [[RES:%.*]] = call <16 x i32> @llvm.x86.avx512fp16.mask.vcvtph2udq.512(<16 x half> [[X0]], <16 x i32> [[X1]], i16 [[X2]], i32 10)2302; CHECK-NEXT: [[TMP8:%.*]] = bitcast <16 x i16> [[TMP1]] to i2562303; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i256 [[TMP8]], 02304; CHECK-NEXT: [[TMP9:%.*]] = bitcast <16 x i32> [[TMP2]] to i5122305; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i512 [[TMP9]], 02306; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSCMP4]], [[_MSCMP5]]2307; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB10:.*]], label %[[BB11:.*]], !prof [[PROF1]]2308; CHECK: [[BB10]]:2309; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2310; CHECK-NEXT: unreachable2311; CHECK: [[BB11]]:2312; CHECK-NEXT: [[RES1:%.*]] = call <16 x i32> @llvm.x86.avx512fp16.mask.vcvtph2udq.512(<16 x half> [[X0]], <16 x i32> [[X1]], i16 -1, i32 8)2313; CHECK-NEXT: [[RES2:%.*]] = add <16 x i32> [[RES]], [[RES1]]2314; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 82315; CHECK-NEXT: ret <16 x i32> [[RES2]]2316;2317 %res = call <16 x i32> @llvm.x86.avx512fp16.mask.vcvtph2udq.512(<16 x half> %x0, <16 x i32> %x1, i16 %x2, i32 10)2318 %res1 = call <16 x i32> @llvm.x86.avx512fp16.mask.vcvtph2udq.512(<16 x half> %x0, <16 x i32> %x1, i16 -1, i32 8)2319 %res2 = add <16 x i32> %res, %res12320 ret <16 x i32> %res22321}2322 2323declare <16 x i32> @llvm.x86.avx512fp16.mask.vcvttph2dq.512(<16 x half>, <16 x i32>, i16, i32)2324 2325define <16 x i32> @test_int_x86_avx512_mask_cvtt_ph2dq_512(<16 x half> %x0, <16 x i32> %x1, i16 %x2) #0 {2326; CHECK-LABEL: define <16 x i32> @test_int_x86_avx512_mask_cvtt_ph2dq_512(2327; CHECK-SAME: <16 x half> [[X0:%.*]], <16 x i32> [[X1:%.*]], i16 [[X2:%.*]]) #[[ATTR1]] {2328; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 82329; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 82330; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 82331; CHECK-NEXT: call void @llvm.donothing()2332; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i16> [[TMP1]] to i2562333; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP4]], 02334; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP2]] to i5122335; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP5]], 02336; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]2337; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i16 [[TMP3]], 02338; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]2339; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]2340; CHECK: [[BB6]]:2341; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2342; CHECK-NEXT: unreachable2343; CHECK: [[BB7]]:2344; CHECK-NEXT: [[RES:%.*]] = call <16 x i32> @llvm.x86.avx512fp16.mask.vcvttph2dq.512(<16 x half> [[X0]], <16 x i32> [[X1]], i16 [[X2]], i32 4)2345; CHECK-NEXT: [[TMP8:%.*]] = bitcast <16 x i16> [[TMP1]] to i2562346; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i256 [[TMP8]], 02347; CHECK-NEXT: [[TMP9:%.*]] = bitcast <16 x i32> [[TMP2]] to i5122348; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i512 [[TMP9]], 02349; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSCMP4]], [[_MSCMP5]]2350; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB10:.*]], label %[[BB11:.*]], !prof [[PROF1]]2351; CHECK: [[BB10]]:2352; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2353; CHECK-NEXT: unreachable2354; CHECK: [[BB11]]:2355; CHECK-NEXT: [[RES1:%.*]] = call <16 x i32> @llvm.x86.avx512fp16.mask.vcvttph2dq.512(<16 x half> [[X0]], <16 x i32> [[X1]], i16 -1, i32 8)2356; CHECK-NEXT: [[RES2:%.*]] = add <16 x i32> [[RES]], [[RES1]]2357; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 82358; CHECK-NEXT: ret <16 x i32> [[RES2]]2359;2360 %res = call <16 x i32> @llvm.x86.avx512fp16.mask.vcvttph2dq.512(<16 x half> %x0, <16 x i32> %x1, i16 %x2, i32 4)2361 %res1 = call <16 x i32> @llvm.x86.avx512fp16.mask.vcvttph2dq.512(<16 x half> %x0, <16 x i32> %x1, i16 -1, i32 8)2362 %res2 = add <16 x i32> %res, %res12363 ret <16 x i32> %res22364}2365 2366declare <16 x i32> @llvm.x86.avx512fp16.mask.vcvttph2udq.512(<16 x half>, <16 x i32>, i16, i32)2367 2368define <16 x i32> @test_int_x86_avx512_mask_cvtt_ph2udq_512(<16 x half> %x0, <16 x i32> %x1, i16 %x2) #0 {2369; CHECK-LABEL: define <16 x i32> @test_int_x86_avx512_mask_cvtt_ph2udq_512(2370; CHECK-SAME: <16 x half> [[X0:%.*]], <16 x i32> [[X1:%.*]], i16 [[X2:%.*]]) #[[ATTR1]] {2371; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 82372; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 82373; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 82374; CHECK-NEXT: call void @llvm.donothing()2375; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i16> [[TMP1]] to i2562376; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP4]], 02377; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i32> [[TMP2]] to i5122378; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP5]], 02379; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]2380; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i16 [[TMP3]], 02381; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]2382; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]2383; CHECK: [[BB6]]:2384; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2385; CHECK-NEXT: unreachable2386; CHECK: [[BB7]]:2387; CHECK-NEXT: [[RES:%.*]] = call <16 x i32> @llvm.x86.avx512fp16.mask.vcvttph2udq.512(<16 x half> [[X0]], <16 x i32> [[X1]], i16 [[X2]], i32 4)2388; CHECK-NEXT: [[TMP8:%.*]] = bitcast <16 x i16> [[TMP1]] to i2562389; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i256 [[TMP8]], 02390; CHECK-NEXT: [[TMP9:%.*]] = bitcast <16 x i32> [[TMP2]] to i5122391; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i512 [[TMP9]], 02392; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSCMP4]], [[_MSCMP5]]2393; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB10:.*]], label %[[BB11:.*]], !prof [[PROF1]]2394; CHECK: [[BB10]]:2395; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2396; CHECK-NEXT: unreachable2397; CHECK: [[BB11]]:2398; CHECK-NEXT: [[RES1:%.*]] = call <16 x i32> @llvm.x86.avx512fp16.mask.vcvttph2udq.512(<16 x half> [[X0]], <16 x i32> [[X1]], i16 -1, i32 8)2399; CHECK-NEXT: [[RES2:%.*]] = add <16 x i32> [[RES]], [[RES1]]2400; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 82401; CHECK-NEXT: ret <16 x i32> [[RES2]]2402;2403 %res = call <16 x i32> @llvm.x86.avx512fp16.mask.vcvttph2udq.512(<16 x half> %x0, <16 x i32> %x1, i16 %x2, i32 4)2404 %res1 = call <16 x i32> @llvm.x86.avx512fp16.mask.vcvttph2udq.512(<16 x half> %x0, <16 x i32> %x1, i16 -1, i32 8)2405 %res2 = add <16 x i32> %res, %res12406 ret <16 x i32> %res22407}2408 2409declare <8 x half> @llvm.x86.avx512.sitofp.round.v8f16.v8i64(<8 x i64>, i32)2410 2411define <8 x half> @test_int_x86_avx512_mask_cvt_qq2ph_512(<8 x i64> %x0, <8 x half> %x1, i8 %x2) #0 {2412; CHECK-LABEL: define <8 x half> @test_int_x86_avx512_mask_cvt_qq2ph_512(2413; CHECK-SAME: <8 x i64> [[X0:%.*]], <8 x half> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR1]] {2414; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 80), align 82415; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 82416; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82417; CHECK-NEXT: call void @llvm.donothing()2418; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8 [[TMP1]] to <8 x i1>2419; CHECK-NEXT: [[MASK:%.*]] = bitcast i8 [[X2]] to <8 x i1>2420; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i64> [[TMP2]] to i5122421; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP5]], 02422; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]2423; CHECK: [[BB6]]:2424; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2425; CHECK-NEXT: unreachable2426; CHECK: [[BB7]]:2427; CHECK-NEXT: [[RES0:%.*]] = call <8 x half> @llvm.x86.avx512.sitofp.round.v8f16.v8i64(<8 x i64> [[X0]], i32 4)2428; CHECK-NEXT: [[TMP8:%.*]] = select <8 x i1> [[MASK]], <8 x i16> zeroinitializer, <8 x i16> [[TMP3]]2429; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x half> [[RES0]] to <8 x i16>2430; CHECK-NEXT: [[TMP10:%.*]] = bitcast <8 x half> [[X1]] to <8 x i16>2431; CHECK-NEXT: [[TMP11:%.*]] = xor <8 x i16> [[TMP9]], [[TMP10]]2432; CHECK-NEXT: [[TMP12:%.*]] = or <8 x i16> [[TMP11]], zeroinitializer2433; CHECK-NEXT: [[TMP13:%.*]] = or <8 x i16> [[TMP12]], [[TMP3]]2434; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP4]], <8 x i16> [[TMP13]], <8 x i16> [[TMP8]]2435; CHECK-NEXT: [[RES:%.*]] = select <8 x i1> [[MASK]], <8 x half> [[RES0]], <8 x half> [[X1]]2436; CHECK-NEXT: store <8 x i16> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82437; CHECK-NEXT: ret <8 x half> [[RES]]2438;2439 %mask = bitcast i8 %x2 to <8 x i1>2440 %res0 = call <8 x half> @llvm.x86.avx512.sitofp.round.v8f16.v8i64(<8 x i64> %x0, i32 4)2441 %res = select <8 x i1> %mask, <8 x half> %res0, <8 x half> %x12442 ret <8 x half> %res2443}2444 2445define <8 x half> @test_int_x86_avx512_mask_cvt_qq2ph_512_r(<8 x i64> %x0, <8 x half> %x1, i8 %x2) #0 {2446; CHECK-LABEL: define <8 x half> @test_int_x86_avx512_mask_cvt_qq2ph_512_r(2447; CHECK-SAME: <8 x i64> [[X0:%.*]], <8 x half> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR1]] {2448; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 80), align 82449; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 82450; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82451; CHECK-NEXT: call void @llvm.donothing()2452; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8 [[TMP1]] to <8 x i1>2453; CHECK-NEXT: [[MASK:%.*]] = bitcast i8 [[X2]] to <8 x i1>2454; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i64> [[TMP2]] to i5122455; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP5]], 02456; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]2457; CHECK: [[BB6]]:2458; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2459; CHECK-NEXT: unreachable2460; CHECK: [[BB7]]:2461; CHECK-NEXT: [[RES0:%.*]] = call <8 x half> @llvm.x86.avx512.sitofp.round.v8f16.v8i64(<8 x i64> [[X0]], i32 10)2462; CHECK-NEXT: [[TMP8:%.*]] = select <8 x i1> [[MASK]], <8 x i16> zeroinitializer, <8 x i16> [[TMP3]]2463; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x half> [[RES0]] to <8 x i16>2464; CHECK-NEXT: [[TMP10:%.*]] = bitcast <8 x half> [[X1]] to <8 x i16>2465; CHECK-NEXT: [[TMP11:%.*]] = xor <8 x i16> [[TMP9]], [[TMP10]]2466; CHECK-NEXT: [[TMP12:%.*]] = or <8 x i16> [[TMP11]], zeroinitializer2467; CHECK-NEXT: [[TMP13:%.*]] = or <8 x i16> [[TMP12]], [[TMP3]]2468; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP4]], <8 x i16> [[TMP13]], <8 x i16> [[TMP8]]2469; CHECK-NEXT: [[RES:%.*]] = select <8 x i1> [[MASK]], <8 x half> [[RES0]], <8 x half> [[X1]]2470; CHECK-NEXT: store <8 x i16> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82471; CHECK-NEXT: ret <8 x half> [[RES]]2472;2473 %mask = bitcast i8 %x2 to <8 x i1>2474 %res0 = call <8 x half> @llvm.x86.avx512.sitofp.round.v8f16.v8i64(<8 x i64> %x0, i32 10)2475 %res = select <8 x i1> %mask, <8 x half> %res0, <8 x half> %x12476 ret <8 x half> %res2477}2478 2479define <8 x half> @test_int_x86_avx512_mask_cvt_qq2ph_512_nomask(<8 x i64> %x0, <8 x half> %x1) #0 {2480; CHECK-LABEL: define <8 x half> @test_int_x86_avx512_mask_cvt_qq2ph_512_nomask(2481; CHECK-SAME: <8 x i64> [[X0:%.*]], <8 x half> [[X1:%.*]]) #[[ATTR1]] {2482; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 82483; CHECK-NEXT: call void @llvm.donothing()2484; CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i64> [[TMP1]] to i5122485; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP2]], 02486; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]2487; CHECK: [[BB3]]:2488; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2489; CHECK-NEXT: unreachable2490; CHECK: [[BB4]]:2491; CHECK-NEXT: [[RES:%.*]] = call <8 x half> @llvm.x86.avx512.sitofp.round.v8f16.v8i64(<8 x i64> [[X0]], i32 4)2492; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 82493; CHECK-NEXT: ret <8 x half> [[RES]]2494;2495 %res = call <8 x half> @llvm.x86.avx512.sitofp.round.v8f16.v8i64(<8 x i64> %x0, i32 4)2496 ret <8 x half> %res2497}2498 2499define <8 x half> @test_int_x86_avx512_mask_cvt_qq2ph_512_z(<8 x i64> %x0, i8 %x2) #0 {2500; CHECK-LABEL: define <8 x half> @test_int_x86_avx512_mask_cvt_qq2ph_512_z(2501; CHECK-SAME: <8 x i64> [[X0:%.*]], i8 [[X2:%.*]]) #[[ATTR1]] {2502; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82503; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 82504; CHECK-NEXT: call void @llvm.donothing()2505; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8 [[TMP1]] to <8 x i1>2506; CHECK-NEXT: [[MASK:%.*]] = bitcast i8 [[X2]] to <8 x i1>2507; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i64> [[TMP2]] to i5122508; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP4]], 02509; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]2510; CHECK: [[BB5]]:2511; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2512; CHECK-NEXT: unreachable2513; CHECK: [[BB6]]:2514; CHECK-NEXT: [[RES0:%.*]] = call <8 x half> @llvm.x86.avx512.sitofp.round.v8f16.v8i64(<8 x i64> [[X0]], i32 4)2515; CHECK-NEXT: [[TMP7:%.*]] = select <8 x i1> [[MASK]], <8 x i16> zeroinitializer, <8 x i16> zeroinitializer2516; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x half> [[RES0]] to <8 x i16>2517; CHECK-NEXT: [[TMP9:%.*]] = xor <8 x i16> [[TMP8]], zeroinitializer2518; CHECK-NEXT: [[TMP10:%.*]] = or <8 x i16> [[TMP9]], zeroinitializer2519; CHECK-NEXT: [[TMP11:%.*]] = or <8 x i16> [[TMP10]], zeroinitializer2520; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP3]], <8 x i16> [[TMP11]], <8 x i16> [[TMP7]]2521; CHECK-NEXT: [[RES:%.*]] = select <8 x i1> [[MASK]], <8 x half> [[RES0]], <8 x half> zeroinitializer2522; CHECK-NEXT: store <8 x i16> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82523; CHECK-NEXT: ret <8 x half> [[RES]]2524;2525 %mask = bitcast i8 %x2 to <8 x i1>2526 %res0 = call <8 x half> @llvm.x86.avx512.sitofp.round.v8f16.v8i64(<8 x i64> %x0, i32 4)2527 %res = select <8 x i1> %mask, <8 x half> %res0, <8 x half> zeroinitializer2528 ret <8 x half> %res2529}2530 2531declare <8 x half> @llvm.x86.avx512.uitofp.round.v8f16.v8i64(<8 x i64>, i32)2532 2533define <8 x half> @test_int_x86_avx512_mask_cvt_uqq2ph_512(<8 x i64> %x0, <8 x half> %x1, i8 %x2) #0 {2534; CHECK-LABEL: define <8 x half> @test_int_x86_avx512_mask_cvt_uqq2ph_512(2535; CHECK-SAME: <8 x i64> [[X0:%.*]], <8 x half> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR1]] {2536; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 80), align 82537; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 82538; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82539; CHECK-NEXT: call void @llvm.donothing()2540; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8 [[TMP1]] to <8 x i1>2541; CHECK-NEXT: [[MASK:%.*]] = bitcast i8 [[X2]] to <8 x i1>2542; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i64> [[TMP2]] to i5122543; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP5]], 02544; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]2545; CHECK: [[BB6]]:2546; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2547; CHECK-NEXT: unreachable2548; CHECK: [[BB7]]:2549; CHECK-NEXT: [[RES0:%.*]] = call <8 x half> @llvm.x86.avx512.uitofp.round.v8f16.v8i64(<8 x i64> [[X0]], i32 4)2550; CHECK-NEXT: [[TMP8:%.*]] = select <8 x i1> [[MASK]], <8 x i16> zeroinitializer, <8 x i16> [[TMP3]]2551; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x half> [[RES0]] to <8 x i16>2552; CHECK-NEXT: [[TMP10:%.*]] = bitcast <8 x half> [[X1]] to <8 x i16>2553; CHECK-NEXT: [[TMP11:%.*]] = xor <8 x i16> [[TMP9]], [[TMP10]]2554; CHECK-NEXT: [[TMP12:%.*]] = or <8 x i16> [[TMP11]], zeroinitializer2555; CHECK-NEXT: [[TMP13:%.*]] = or <8 x i16> [[TMP12]], [[TMP3]]2556; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP4]], <8 x i16> [[TMP13]], <8 x i16> [[TMP8]]2557; CHECK-NEXT: [[RES:%.*]] = select <8 x i1> [[MASK]], <8 x half> [[RES0]], <8 x half> [[X1]]2558; CHECK-NEXT: store <8 x i16> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82559; CHECK-NEXT: ret <8 x half> [[RES]]2560;2561 %mask = bitcast i8 %x2 to <8 x i1>2562 %res0 = call <8 x half> @llvm.x86.avx512.uitofp.round.v8f16.v8i64(<8 x i64> %x0, i32 4)2563 %res = select <8 x i1> %mask, <8 x half> %res0, <8 x half> %x12564 ret <8 x half> %res2565}2566 2567define <8 x half> @test_int_x86_avx512_mask_cvt_uqq2ph_512_r(<8 x i64> %x0, <8 x half> %x1, i8 %x2) #0 {2568; CHECK-LABEL: define <8 x half> @test_int_x86_avx512_mask_cvt_uqq2ph_512_r(2569; CHECK-SAME: <8 x i64> [[X0:%.*]], <8 x half> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR1]] {2570; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 80), align 82571; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 82572; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82573; CHECK-NEXT: call void @llvm.donothing()2574; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8 [[TMP1]] to <8 x i1>2575; CHECK-NEXT: [[MASK:%.*]] = bitcast i8 [[X2]] to <8 x i1>2576; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i64> [[TMP2]] to i5122577; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP5]], 02578; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]2579; CHECK: [[BB6]]:2580; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2581; CHECK-NEXT: unreachable2582; CHECK: [[BB7]]:2583; CHECK-NEXT: [[RES0:%.*]] = call <8 x half> @llvm.x86.avx512.uitofp.round.v8f16.v8i64(<8 x i64> [[X0]], i32 10)2584; CHECK-NEXT: [[TMP8:%.*]] = select <8 x i1> [[MASK]], <8 x i16> zeroinitializer, <8 x i16> [[TMP3]]2585; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x half> [[RES0]] to <8 x i16>2586; CHECK-NEXT: [[TMP10:%.*]] = bitcast <8 x half> [[X1]] to <8 x i16>2587; CHECK-NEXT: [[TMP11:%.*]] = xor <8 x i16> [[TMP9]], [[TMP10]]2588; CHECK-NEXT: [[TMP12:%.*]] = or <8 x i16> [[TMP11]], zeroinitializer2589; CHECK-NEXT: [[TMP13:%.*]] = or <8 x i16> [[TMP12]], [[TMP3]]2590; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP4]], <8 x i16> [[TMP13]], <8 x i16> [[TMP8]]2591; CHECK-NEXT: [[RES:%.*]] = select <8 x i1> [[MASK]], <8 x half> [[RES0]], <8 x half> [[X1]]2592; CHECK-NEXT: store <8 x i16> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82593; CHECK-NEXT: ret <8 x half> [[RES]]2594;2595 %mask = bitcast i8 %x2 to <8 x i1>2596 %res0 = call <8 x half> @llvm.x86.avx512.uitofp.round.v8f16.v8i64(<8 x i64> %x0, i32 10)2597 %res = select <8 x i1> %mask, <8 x half> %res0, <8 x half> %x12598 ret <8 x half> %res2599}2600 2601define <8 x half> @test_int_x86_avx512_mask_cvt_uqq2ph_512_nomask(<8 x i64> %x0, <8 x half> %x1) #0 {2602; CHECK-LABEL: define <8 x half> @test_int_x86_avx512_mask_cvt_uqq2ph_512_nomask(2603; CHECK-SAME: <8 x i64> [[X0:%.*]], <8 x half> [[X1:%.*]]) #[[ATTR1]] {2604; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 82605; CHECK-NEXT: call void @llvm.donothing()2606; CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i64> [[TMP1]] to i5122607; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP2]], 02608; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]2609; CHECK: [[BB3]]:2610; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2611; CHECK-NEXT: unreachable2612; CHECK: [[BB4]]:2613; CHECK-NEXT: [[RES:%.*]] = call <8 x half> @llvm.x86.avx512.uitofp.round.v8f16.v8i64(<8 x i64> [[X0]], i32 4)2614; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 82615; CHECK-NEXT: ret <8 x half> [[RES]]2616;2617 %res = call <8 x half> @llvm.x86.avx512.uitofp.round.v8f16.v8i64(<8 x i64> %x0, i32 4)2618 ret <8 x half> %res2619}2620 2621define <8 x half> @test_int_x86_avx512_mask_cvt_uqq2ph_512_z(<8 x i64> %x0, i8 %x2) #0 {2622; CHECK-LABEL: define <8 x half> @test_int_x86_avx512_mask_cvt_uqq2ph_512_z(2623; CHECK-SAME: <8 x i64> [[X0:%.*]], i8 [[X2:%.*]]) #[[ATTR1]] {2624; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82625; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 82626; CHECK-NEXT: call void @llvm.donothing()2627; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8 [[TMP1]] to <8 x i1>2628; CHECK-NEXT: [[MASK:%.*]] = bitcast i8 [[X2]] to <8 x i1>2629; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i64> [[TMP2]] to i5122630; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i512 [[TMP4]], 02631; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]2632; CHECK: [[BB5]]:2633; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2634; CHECK-NEXT: unreachable2635; CHECK: [[BB6]]:2636; CHECK-NEXT: [[RES0:%.*]] = call <8 x half> @llvm.x86.avx512.uitofp.round.v8f16.v8i64(<8 x i64> [[X0]], i32 4)2637; CHECK-NEXT: [[TMP7:%.*]] = select <8 x i1> [[MASK]], <8 x i16> zeroinitializer, <8 x i16> zeroinitializer2638; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x half> [[RES0]] to <8 x i16>2639; CHECK-NEXT: [[TMP9:%.*]] = xor <8 x i16> [[TMP8]], zeroinitializer2640; CHECK-NEXT: [[TMP10:%.*]] = or <8 x i16> [[TMP9]], zeroinitializer2641; CHECK-NEXT: [[TMP11:%.*]] = or <8 x i16> [[TMP10]], zeroinitializer2642; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP3]], <8 x i16> [[TMP11]], <8 x i16> [[TMP7]]2643; CHECK-NEXT: [[RES:%.*]] = select <8 x i1> [[MASK]], <8 x half> [[RES0]], <8 x half> zeroinitializer2644; CHECK-NEXT: store <8 x i16> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82645; CHECK-NEXT: ret <8 x half> [[RES]]2646;2647 %mask = bitcast i8 %x2 to <8 x i1>2648 %res0 = call <8 x half> @llvm.x86.avx512.uitofp.round.v8f16.v8i64(<8 x i64> %x0, i32 4)2649 %res = select <8 x i1> %mask, <8 x half> %res0, <8 x half> zeroinitializer2650 ret <8 x half> %res2651}2652 2653declare <8 x i64> @llvm.x86.avx512fp16.mask.vcvtph2qq.512(<8 x half>, <8 x i64>, i8, i32)2654 2655define <8 x i64> @test_int_x86_avx512_mask_cvt_ph2qq_512(<8 x half> %x0, <8 x i64> %x1, i8 %x2) #0 {2656; CHECK-LABEL: define <8 x i64> @test_int_x86_avx512_mask_cvt_ph2qq_512(2657; CHECK-SAME: <8 x half> [[X0:%.*]], <8 x i64> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR1]] {2658; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 82659; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 82660; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 80), align 82661; CHECK-NEXT: call void @llvm.donothing()2662; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i16> [[TMP1]] to i1282663; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 02664; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i64> [[TMP2]] to i5122665; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP5]], 02666; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]2667; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 02668; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]2669; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]2670; CHECK: [[BB6]]:2671; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2672; CHECK-NEXT: unreachable2673; CHECK: [[BB7]]:2674; CHECK-NEXT: [[RES:%.*]] = call <8 x i64> @llvm.x86.avx512fp16.mask.vcvtph2qq.512(<8 x half> [[X0]], <8 x i64> [[X1]], i8 [[X2]], i32 10)2675; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i16> [[TMP1]] to i1282676; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i128 [[TMP8]], 02677; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i64> [[TMP2]] to i5122678; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i512 [[TMP9]], 02679; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSCMP4]], [[_MSCMP5]]2680; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB10:.*]], label %[[BB11:.*]], !prof [[PROF1]]2681; CHECK: [[BB10]]:2682; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2683; CHECK-NEXT: unreachable2684; CHECK: [[BB11]]:2685; CHECK-NEXT: [[RES1:%.*]] = call <8 x i64> @llvm.x86.avx512fp16.mask.vcvtph2qq.512(<8 x half> [[X0]], <8 x i64> [[X1]], i8 -1, i32 8)2686; CHECK-NEXT: [[RES2:%.*]] = add <8 x i64> [[RES]], [[RES1]]2687; CHECK-NEXT: store <8 x i64> zeroinitializer, ptr @__msan_retval_tls, align 82688; CHECK-NEXT: ret <8 x i64> [[RES2]]2689;2690 %res = call <8 x i64> @llvm.x86.avx512fp16.mask.vcvtph2qq.512(<8 x half> %x0, <8 x i64> %x1, i8 %x2, i32 10)2691 %res1 = call <8 x i64> @llvm.x86.avx512fp16.mask.vcvtph2qq.512(<8 x half> %x0, <8 x i64> %x1, i8 -1, i32 8)2692 %res2 = add <8 x i64> %res, %res12693 ret <8 x i64> %res22694}2695 2696declare <8 x i64> @llvm.x86.avx512fp16.mask.vcvtph2uqq.512(<8 x half>, <8 x i64>, i8, i32)2697 2698define <8 x i64> @test_int_x86_avx512_mask_cvt_ph2uqq_512(<8 x half> %x0, <8 x i64> %x1, i8 %x2) #0 {2699; CHECK-LABEL: define <8 x i64> @test_int_x86_avx512_mask_cvt_ph2uqq_512(2700; CHECK-SAME: <8 x half> [[X0:%.*]], <8 x i64> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR1]] {2701; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 82702; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 82703; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 80), align 82704; CHECK-NEXT: call void @llvm.donothing()2705; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i16> [[TMP1]] to i1282706; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 02707; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i64> [[TMP2]] to i5122708; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP5]], 02709; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]2710; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 02711; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]2712; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]2713; CHECK: [[BB6]]:2714; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2715; CHECK-NEXT: unreachable2716; CHECK: [[BB7]]:2717; CHECK-NEXT: [[RES:%.*]] = call <8 x i64> @llvm.x86.avx512fp16.mask.vcvtph2uqq.512(<8 x half> [[X0]], <8 x i64> [[X1]], i8 [[X2]], i32 10)2718; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i16> [[TMP1]] to i1282719; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i128 [[TMP8]], 02720; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i64> [[TMP2]] to i5122721; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i512 [[TMP9]], 02722; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSCMP4]], [[_MSCMP5]]2723; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB10:.*]], label %[[BB11:.*]], !prof [[PROF1]]2724; CHECK: [[BB10]]:2725; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2726; CHECK-NEXT: unreachable2727; CHECK: [[BB11]]:2728; CHECK-NEXT: [[RES1:%.*]] = call <8 x i64> @llvm.x86.avx512fp16.mask.vcvtph2uqq.512(<8 x half> [[X0]], <8 x i64> [[X1]], i8 -1, i32 8)2729; CHECK-NEXT: [[RES2:%.*]] = add <8 x i64> [[RES]], [[RES1]]2730; CHECK-NEXT: store <8 x i64> zeroinitializer, ptr @__msan_retval_tls, align 82731; CHECK-NEXT: ret <8 x i64> [[RES2]]2732;2733 %res = call <8 x i64> @llvm.x86.avx512fp16.mask.vcvtph2uqq.512(<8 x half> %x0, <8 x i64> %x1, i8 %x2, i32 10)2734 %res1 = call <8 x i64> @llvm.x86.avx512fp16.mask.vcvtph2uqq.512(<8 x half> %x0, <8 x i64> %x1, i8 -1, i32 8)2735 %res2 = add <8 x i64> %res, %res12736 ret <8 x i64> %res22737}2738 2739declare <8 x i64> @llvm.x86.avx512fp16.mask.vcvttph2uqq.512(<8 x half>, <8 x i64>, i8, i32)2740 2741define <8 x i64> @test_int_x86_avx512_mask_cvtt_ph2uqq_512(<8 x half> %x0, <8 x i64> %x1, i8 %x2) #0 {2742; CHECK-LABEL: define <8 x i64> @test_int_x86_avx512_mask_cvtt_ph2uqq_512(2743; CHECK-SAME: <8 x half> [[X0:%.*]], <8 x i64> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR1]] {2744; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 82745; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 82746; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 80), align 82747; CHECK-NEXT: call void @llvm.donothing()2748; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i16> [[TMP1]] to i1282749; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 02750; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i64> [[TMP2]] to i5122751; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP5]], 02752; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]2753; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 02754; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]2755; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]2756; CHECK: [[BB6]]:2757; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2758; CHECK-NEXT: unreachable2759; CHECK: [[BB7]]:2760; CHECK-NEXT: [[RES:%.*]] = call <8 x i64> @llvm.x86.avx512fp16.mask.vcvttph2uqq.512(<8 x half> [[X0]], <8 x i64> [[X1]], i8 [[X2]], i32 8)2761; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i16> [[TMP1]] to i1282762; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i128 [[TMP8]], 02763; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i64> [[TMP2]] to i5122764; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i512 [[TMP9]], 02765; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSCMP4]], [[_MSCMP5]]2766; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB10:.*]], label %[[BB11:.*]], !prof [[PROF1]]2767; CHECK: [[BB10]]:2768; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2769; CHECK-NEXT: unreachable2770; CHECK: [[BB11]]:2771; CHECK-NEXT: [[RES1:%.*]] = call <8 x i64> @llvm.x86.avx512fp16.mask.vcvttph2uqq.512(<8 x half> [[X0]], <8 x i64> [[X1]], i8 -1, i32 4)2772; CHECK-NEXT: [[RES2:%.*]] = add <8 x i64> [[RES]], [[RES1]]2773; CHECK-NEXT: store <8 x i64> zeroinitializer, ptr @__msan_retval_tls, align 82774; CHECK-NEXT: ret <8 x i64> [[RES2]]2775;2776 %res = call <8 x i64> @llvm.x86.avx512fp16.mask.vcvttph2uqq.512(<8 x half> %x0, <8 x i64> %x1, i8 %x2, i32 8)2777 %res1 = call <8 x i64> @llvm.x86.avx512fp16.mask.vcvttph2uqq.512(<8 x half> %x0, <8 x i64> %x1, i8 -1, i32 4)2778 %res2 = add <8 x i64> %res, %res12779 ret <8 x i64> %res22780}2781 2782declare i32 @llvm.x86.avx512fp16.vcvtsh2si32(<8 x half>, i32)2783 2784define i32 @test_x86_avx512fp16_vcvtsh2si32(<8 x half> %arg0) #0 {2785; CHECK-LABEL: define i32 @test_x86_avx512fp16_vcvtsh2si32(2786; CHECK-SAME: <8 x half> [[ARG0:%.*]]) #[[ATTR1]] {2787; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 82788; CHECK-NEXT: call void @llvm.donothing()2789; CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i16> [[TMP1]] to i1282790; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 02791; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]2792; CHECK: [[BB3]]:2793; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2794; CHECK-NEXT: unreachable2795; CHECK: [[BB4]]:2796; CHECK-NEXT: [[RES1:%.*]] = call i32 @llvm.x86.avx512fp16.vcvtsh2si32(<8 x half> [[ARG0]], i32 4)2797; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP1]] to i1282798; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 02799; CHECK-NEXT: br i1 [[_MSCMP1]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]2800; CHECK: [[BB6]]:2801; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2802; CHECK-NEXT: unreachable2803; CHECK: [[BB7]]:2804; CHECK-NEXT: [[RES2:%.*]] = call i32 @llvm.x86.avx512fp16.vcvtsh2si32(<8 x half> [[ARG0]], i32 11)2805; CHECK-NEXT: [[RES:%.*]] = add i32 [[RES1]], [[RES2]]2806; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 82807; CHECK-NEXT: ret i32 [[RES]]2808;2809 %res1 = call i32 @llvm.x86.avx512fp16.vcvtsh2si32(<8 x half> %arg0, i32 4)2810 %res2 = call i32 @llvm.x86.avx512fp16.vcvtsh2si32(<8 x half> %arg0, i32 11)2811 %res = add i32 %res1, %res22812 ret i32 %res2813}2814 2815declare i64 @llvm.x86.avx512fp16.vcvtsh2si64(<8 x half>, i32)2816 2817define i64 @test_x86_avx512fp16_vcvtsh2si64(<8 x half> %arg0) #0 {2818; CHECK-LABEL: define i64 @test_x86_avx512fp16_vcvtsh2si64(2819; CHECK-SAME: <8 x half> [[ARG0:%.*]]) #[[ATTR1]] {2820; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 82821; CHECK-NEXT: call void @llvm.donothing()2822; CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i16> [[TMP1]] to i1282823; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 02824; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]2825; CHECK: [[BB3]]:2826; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2827; CHECK-NEXT: unreachable2828; CHECK: [[BB4]]:2829; CHECK-NEXT: [[RES1:%.*]] = call i64 @llvm.x86.avx512fp16.vcvtsh2si64(<8 x half> [[ARG0]], i32 4)2830; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP1]] to i1282831; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 02832; CHECK-NEXT: br i1 [[_MSCMP1]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]2833; CHECK: [[BB6]]:2834; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2835; CHECK-NEXT: unreachable2836; CHECK: [[BB7]]:2837; CHECK-NEXT: [[RES2:%.*]] = call i64 @llvm.x86.avx512fp16.vcvtsh2si64(<8 x half> [[ARG0]], i32 10)2838; CHECK-NEXT: [[RES:%.*]] = add i64 [[RES1]], [[RES2]]2839; CHECK-NEXT: store i64 0, ptr @__msan_retval_tls, align 82840; CHECK-NEXT: ret i64 [[RES]]2841;2842 %res1 = call i64 @llvm.x86.avx512fp16.vcvtsh2si64(<8 x half> %arg0, i32 4)2843 %res2 = call i64 @llvm.x86.avx512fp16.vcvtsh2si64(<8 x half> %arg0, i32 10)2844 %res = add i64 %res1, %res22845 ret i64 %res2846}2847 2848declare i32 @llvm.x86.avx512fp16.vcvttsh2si32(<8 x half>, i32)2849 2850define i32 @test_x86_avx512fp16_vcvttsh2si32(<8 x half> %arg0) #0 {2851; CHECK-LABEL: define i32 @test_x86_avx512fp16_vcvttsh2si32(2852; CHECK-SAME: <8 x half> [[ARG0:%.*]]) #[[ATTR1]] {2853; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 82854; CHECK-NEXT: call void @llvm.donothing()2855; CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i16> [[TMP1]] to i1282856; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 02857; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]2858; CHECK: [[BB3]]:2859; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2860; CHECK-NEXT: unreachable2861; CHECK: [[BB4]]:2862; CHECK-NEXT: [[RES1:%.*]] = call i32 @llvm.x86.avx512fp16.vcvttsh2si32(<8 x half> [[ARG0]], i32 4)2863; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP1]] to i1282864; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 02865; CHECK-NEXT: br i1 [[_MSCMP1]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]2866; CHECK: [[BB6]]:2867; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2868; CHECK-NEXT: unreachable2869; CHECK: [[BB7]]:2870; CHECK-NEXT: [[RES2:%.*]] = call i32 @llvm.x86.avx512fp16.vcvttsh2si32(<8 x half> [[ARG0]], i32 8)2871; CHECK-NEXT: [[RES:%.*]] = add i32 [[RES1]], [[RES2]]2872; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 82873; CHECK-NEXT: ret i32 [[RES]]2874;2875 %res1 = call i32 @llvm.x86.avx512fp16.vcvttsh2si32(<8 x half> %arg0, i32 4)2876 %res2 = call i32 @llvm.x86.avx512fp16.vcvttsh2si32(<8 x half> %arg0, i32 8)2877 %res = add i32 %res1, %res22878 ret i32 %res2879}2880 2881declare i64 @llvm.x86.avx512fp16.vcvttsh2si64(<8 x half>, i32)2882 2883define i64 @test_x86_avx512fp16_vcvttsh2si64(<8 x half> %arg0) #0 {2884; CHECK-LABEL: define i64 @test_x86_avx512fp16_vcvttsh2si64(2885; CHECK-SAME: <8 x half> [[ARG0:%.*]]) #[[ATTR1]] {2886; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 82887; CHECK-NEXT: call void @llvm.donothing()2888; CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i16> [[TMP1]] to i1282889; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 02890; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]2891; CHECK: [[BB3]]:2892; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2893; CHECK-NEXT: unreachable2894; CHECK: [[BB4]]:2895; CHECK-NEXT: [[RES1:%.*]] = call i64 @llvm.x86.avx512fp16.vcvttsh2si64(<8 x half> [[ARG0]], i32 4)2896; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP1]] to i1282897; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 02898; CHECK-NEXT: br i1 [[_MSCMP1]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]2899; CHECK: [[BB6]]:2900; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2901; CHECK-NEXT: unreachable2902; CHECK: [[BB7]]:2903; CHECK-NEXT: [[RES2:%.*]] = call i64 @llvm.x86.avx512fp16.vcvttsh2si64(<8 x half> [[ARG0]], i32 8)2904; CHECK-NEXT: [[RES:%.*]] = add i64 [[RES1]], [[RES2]]2905; CHECK-NEXT: store i64 0, ptr @__msan_retval_tls, align 82906; CHECK-NEXT: ret i64 [[RES]]2907;2908 %res1 = call i64 @llvm.x86.avx512fp16.vcvttsh2si64(<8 x half> %arg0, i32 4)2909 %res2 = call i64 @llvm.x86.avx512fp16.vcvttsh2si64(<8 x half> %arg0, i32 8)2910 %res = add i64 %res1, %res22911 ret i64 %res2912}2913 2914 2915declare i32 @llvm.x86.avx512fp16.vcvtsh2usi32(<8 x half>, i32)2916 2917define i32 @test_x86_avx512fp16_vcvtsh2usi32(<8 x half> %arg0) #0 {2918; CHECK-LABEL: define i32 @test_x86_avx512fp16_vcvtsh2usi32(2919; CHECK-SAME: <8 x half> [[ARG0:%.*]]) #[[ATTR1]] {2920; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 82921; CHECK-NEXT: call void @llvm.donothing()2922; CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i16> [[TMP1]] to i1282923; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 02924; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]2925; CHECK: [[BB3]]:2926; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2927; CHECK-NEXT: unreachable2928; CHECK: [[BB4]]:2929; CHECK-NEXT: [[RES1:%.*]] = call i32 @llvm.x86.avx512fp16.vcvtsh2usi32(<8 x half> [[ARG0]], i32 4)2930; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP1]] to i1282931; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 02932; CHECK-NEXT: br i1 [[_MSCMP1]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]2933; CHECK: [[BB6]]:2934; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2935; CHECK-NEXT: unreachable2936; CHECK: [[BB7]]:2937; CHECK-NEXT: [[RES2:%.*]] = call i32 @llvm.x86.avx512fp16.vcvtsh2usi32(<8 x half> [[ARG0]], i32 9)2938; CHECK-NEXT: [[RES:%.*]] = add i32 [[RES1]], [[RES2]]2939; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 82940; CHECK-NEXT: ret i32 [[RES]]2941;2942 %res1 = call i32 @llvm.x86.avx512fp16.vcvtsh2usi32(<8 x half> %arg0, i32 4)2943 %res2 = call i32 @llvm.x86.avx512fp16.vcvtsh2usi32(<8 x half> %arg0, i32 9)2944 %res = add i32 %res1, %res22945 ret i32 %res2946}2947 2948 2949declare i64 @llvm.x86.avx512fp16.vcvtsh2usi64(<8 x half>, i32)2950 2951define i64 @test_x86_avx512fp16_vcvtsh2usi64(<8 x half> %arg0) #0 {2952; CHECK-LABEL: define i64 @test_x86_avx512fp16_vcvtsh2usi64(2953; CHECK-SAME: <8 x half> [[ARG0:%.*]]) #[[ATTR1]] {2954; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 82955; CHECK-NEXT: call void @llvm.donothing()2956; CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i16> [[TMP1]] to i1282957; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 02958; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]2959; CHECK: [[BB3]]:2960; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2961; CHECK-NEXT: unreachable2962; CHECK: [[BB4]]:2963; CHECK-NEXT: [[RES1:%.*]] = call i64 @llvm.x86.avx512fp16.vcvtsh2usi64(<8 x half> [[ARG0]], i32 4)2964; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP1]] to i1282965; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 02966; CHECK-NEXT: br i1 [[_MSCMP1]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]2967; CHECK: [[BB6]]:2968; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2969; CHECK-NEXT: unreachable2970; CHECK: [[BB7]]:2971; CHECK-NEXT: [[RES2:%.*]] = call i64 @llvm.x86.avx512fp16.vcvtsh2usi64(<8 x half> [[ARG0]], i32 10)2972; CHECK-NEXT: [[RES:%.*]] = add i64 [[RES1]], [[RES2]]2973; CHECK-NEXT: store i64 0, ptr @__msan_retval_tls, align 82974; CHECK-NEXT: ret i64 [[RES]]2975;2976 %res1 = call i64 @llvm.x86.avx512fp16.vcvtsh2usi64(<8 x half> %arg0, i32 4)2977 %res2 = call i64 @llvm.x86.avx512fp16.vcvtsh2usi64(<8 x half> %arg0, i32 10)2978 %res = add i64 %res1, %res22979 ret i64 %res2980}2981 2982declare i32 @llvm.x86.avx512fp16.vcvttsh2usi32(<8 x half>, i32)2983 2984define i32 @test_x86_avx512fp16_vcvttsh2usi32(<8 x half> %arg0) #0 {2985; CHECK-LABEL: define i32 @test_x86_avx512fp16_vcvttsh2usi32(2986; CHECK-SAME: <8 x half> [[ARG0:%.*]]) #[[ATTR1]] {2987; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 82988; CHECK-NEXT: call void @llvm.donothing()2989; CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i16> [[TMP1]] to i1282990; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 02991; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]2992; CHECK: [[BB3]]:2993; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2994; CHECK-NEXT: unreachable2995; CHECK: [[BB4]]:2996; CHECK-NEXT: [[RES1:%.*]] = call i32 @llvm.x86.avx512fp16.vcvttsh2usi32(<8 x half> [[ARG0]], i32 4)2997; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP1]] to i1282998; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 02999; CHECK-NEXT: br i1 [[_MSCMP1]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]3000; CHECK: [[BB6]]:3001; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]3002; CHECK-NEXT: unreachable3003; CHECK: [[BB7]]:3004; CHECK-NEXT: [[RES2:%.*]] = call i32 @llvm.x86.avx512fp16.vcvttsh2usi32(<8 x half> [[ARG0]], i32 8)3005; CHECK-NEXT: [[RES:%.*]] = add i32 [[RES1]], [[RES2]]3006; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 83007; CHECK-NEXT: ret i32 [[RES]]3008;3009 %res1 = call i32 @llvm.x86.avx512fp16.vcvttsh2usi32(<8 x half> %arg0, i32 4)3010 %res2 = call i32 @llvm.x86.avx512fp16.vcvttsh2usi32(<8 x half> %arg0, i32 8)3011 %res = add i32 %res1, %res23012 ret i32 %res3013}3014 3015declare i64 @llvm.x86.avx512fp16.vcvttsh2usi64(<8 x half>, i32)3016 3017define i64 @test_x86_avx512fp16_vcvttsh2usi64(<8 x half> %arg0) #0 {3018; CHECK-LABEL: define i64 @test_x86_avx512fp16_vcvttsh2usi64(3019; CHECK-SAME: <8 x half> [[ARG0:%.*]]) #[[ATTR1]] {3020; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 83021; CHECK-NEXT: call void @llvm.donothing()3022; CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i16> [[TMP1]] to i1283023; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 03024; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]3025; CHECK: [[BB3]]:3026; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]3027; CHECK-NEXT: unreachable3028; CHECK: [[BB4]]:3029; CHECK-NEXT: [[RES1:%.*]] = call i64 @llvm.x86.avx512fp16.vcvttsh2usi64(<8 x half> [[ARG0]], i32 4)3030; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP1]] to i1283031; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 03032; CHECK-NEXT: br i1 [[_MSCMP1]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]3033; CHECK: [[BB6]]:3034; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]3035; CHECK-NEXT: unreachable3036; CHECK: [[BB7]]:3037; CHECK-NEXT: [[RES2:%.*]] = call i64 @llvm.x86.avx512fp16.vcvttsh2usi64(<8 x half> [[ARG0]], i32 8)3038; CHECK-NEXT: [[RES:%.*]] = add i64 [[RES1]], [[RES2]]3039; CHECK-NEXT: store i64 0, ptr @__msan_retval_tls, align 83040; CHECK-NEXT: ret i64 [[RES]]3041;3042 %res1 = call i64 @llvm.x86.avx512fp16.vcvttsh2usi64(<8 x half> %arg0, i32 4)3043 %res2 = call i64 @llvm.x86.avx512fp16.vcvttsh2usi64(<8 x half> %arg0, i32 8)3044 %res = add i64 %res1, %res23045 ret i64 %res3046}3047 3048declare <8 x half> @llvm.x86.avx512fp16.vcvtsi2sh(<8 x half>, i32, i32)3049 3050define <8 x half> @test_x86_avx512fp16_vcvtsi2sh(<8 x half> %arg0, i32 %arg1) #0 {3051; CHECK-LABEL: define <8 x half> @test_x86_avx512fp16_vcvtsi2sh(3052; CHECK-SAME: <8 x half> [[ARG0:%.*]], i32 [[ARG1:%.*]]) #[[ATTR1]] {3053; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 83054; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83055; CHECK-NEXT: call void @llvm.donothing()3056; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP1]] to i1283057; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 03058; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i32 [[TMP2]], 03059; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3060; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]3061; CHECK: [[BB4]]:3062; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]3063; CHECK-NEXT: unreachable3064; CHECK: [[BB5]]:3065; CHECK-NEXT: [[RES1:%.*]] = call <8 x half> @llvm.x86.avx512fp16.vcvtsi2sh(<8 x half> [[ARG0]], i32 [[ARG1]], i32 4)3066; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i16> [[TMP1]] to i1283067; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP6]], 03068; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i32 [[TMP2]], 03069; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]3070; CHECK-NEXT: br i1 [[_MSOR4]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]3071; CHECK: [[BB7]]:3072; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]3073; CHECK-NEXT: unreachable3074; CHECK: [[BB8]]:3075; CHECK-NEXT: [[RES2:%.*]] = call <8 x half> @llvm.x86.avx512fp16.vcvtsi2sh(<8 x half> [[ARG0]], i32 [[ARG1]], i32 9)3076; CHECK-NEXT: [[RES:%.*]] = fadd <8 x half> [[RES1]], [[RES2]]3077; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 83078; CHECK-NEXT: ret <8 x half> [[RES]]3079;3080 %res1 = call <8 x half> @llvm.x86.avx512fp16.vcvtsi2sh(<8 x half> %arg0, i32 %arg1, i32 4)3081 %res2 = call <8 x half> @llvm.x86.avx512fp16.vcvtsi2sh(<8 x half> %arg0, i32 %arg1, i32 9)3082 %res = fadd <8 x half> %res1, %res23083 ret <8 x half> %res3084}3085 3086declare <8 x half> @llvm.x86.avx512fp16.vcvtsi642sh(<8 x half>, i64, i32)3087 3088define <8 x half> @test_x86_avx512fp16_vcvtsi642sh(<8 x half> %arg0, i64 %arg1) #0 {3089; CHECK-LABEL: define <8 x half> @test_x86_avx512fp16_vcvtsi642sh(3090; CHECK-SAME: <8 x half> [[ARG0:%.*]], i64 [[ARG1:%.*]]) #[[ATTR1]] {3091; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 83092; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83093; CHECK-NEXT: call void @llvm.donothing()3094; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP1]] to i1283095; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 03096; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 03097; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3098; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]3099; CHECK: [[BB4]]:3100; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]3101; CHECK-NEXT: unreachable3102; CHECK: [[BB5]]:3103; CHECK-NEXT: [[RES1:%.*]] = call <8 x half> @llvm.x86.avx512fp16.vcvtsi642sh(<8 x half> [[ARG0]], i64 [[ARG1]], i32 4)3104; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i16> [[TMP1]] to i1283105; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP6]], 03106; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 03107; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]3108; CHECK-NEXT: br i1 [[_MSOR4]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]3109; CHECK: [[BB7]]:3110; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]3111; CHECK-NEXT: unreachable3112; CHECK: [[BB8]]:3113; CHECK-NEXT: [[RES2:%.*]] = call <8 x half> @llvm.x86.avx512fp16.vcvtsi642sh(<8 x half> [[ARG0]], i64 [[ARG1]], i32 8)3114; CHECK-NEXT: [[RES:%.*]] = fadd <8 x half> [[RES1]], [[RES2]]3115; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 83116; CHECK-NEXT: ret <8 x half> [[RES]]3117;3118 %res1 = call <8 x half> @llvm.x86.avx512fp16.vcvtsi642sh(<8 x half> %arg0, i64 %arg1, i32 4)3119 %res2 = call <8 x half> @llvm.x86.avx512fp16.vcvtsi642sh(<8 x half> %arg0, i64 %arg1, i32 8)3120 %res = fadd <8 x half> %res1, %res23121 ret <8 x half> %res3122}3123 3124declare <8 x half> @llvm.x86.avx512fp16.vcvtusi2sh(<8 x half>, i32, i32)3125 3126define <8 x half> @test_x86_avx512fp16_vcvtusi2sh(<8 x half> %arg0, i32 %arg1) #0 {3127; CHECK-LABEL: define <8 x half> @test_x86_avx512fp16_vcvtusi2sh(3128; CHECK-SAME: <8 x half> [[ARG0:%.*]], i32 [[ARG1:%.*]]) #[[ATTR1]] {3129; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 83130; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83131; CHECK-NEXT: call void @llvm.donothing()3132; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP1]] to i1283133; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 03134; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i32 [[TMP2]], 03135; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3136; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]3137; CHECK: [[BB4]]:3138; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]3139; CHECK-NEXT: unreachable3140; CHECK: [[BB5]]:3141; CHECK-NEXT: [[RES1:%.*]] = call <8 x half> @llvm.x86.avx512fp16.vcvtusi2sh(<8 x half> [[ARG0]], i32 [[ARG1]], i32 4)3142; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i16> [[TMP1]] to i1283143; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP6]], 03144; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i32 [[TMP2]], 03145; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]3146; CHECK-NEXT: br i1 [[_MSOR4]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]3147; CHECK: [[BB7]]:3148; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]3149; CHECK-NEXT: unreachable3150; CHECK: [[BB8]]:3151; CHECK-NEXT: [[RES2:%.*]] = call <8 x half> @llvm.x86.avx512fp16.vcvtusi2sh(<8 x half> [[ARG0]], i32 [[ARG1]], i32 9)3152; CHECK-NEXT: [[RES:%.*]] = fadd <8 x half> [[RES1]], [[RES2]]3153; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 83154; CHECK-NEXT: ret <8 x half> [[RES]]3155;3156 %res1 = call <8 x half> @llvm.x86.avx512fp16.vcvtusi2sh(<8 x half> %arg0, i32 %arg1, i32 4)3157 %res2 = call <8 x half> @llvm.x86.avx512fp16.vcvtusi2sh(<8 x half> %arg0, i32 %arg1, i32 9)3158 %res = fadd <8 x half> %res1, %res23159 ret <8 x half> %res3160}3161 3162declare <8 x half> @llvm.x86.avx512fp16.vcvtusi642sh(<8 x half>, i64, i32)3163 3164define <8 x half> @test_x86_avx512fp16_vcvtusi642sh(<8 x half> %arg0, i64 %arg1) #0 {3165; CHECK-LABEL: define <8 x half> @test_x86_avx512fp16_vcvtusi642sh(3166; CHECK-SAME: <8 x half> [[ARG0:%.*]], i64 [[ARG1:%.*]]) #[[ATTR1]] {3167; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 83168; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83169; CHECK-NEXT: call void @llvm.donothing()3170; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP1]] to i1283171; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 03172; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 03173; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3174; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]3175; CHECK: [[BB4]]:3176; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]3177; CHECK-NEXT: unreachable3178; CHECK: [[BB5]]:3179; CHECK-NEXT: [[RES1:%.*]] = call <8 x half> @llvm.x86.avx512fp16.vcvtusi642sh(<8 x half> [[ARG0]], i64 [[ARG1]], i32 4)3180; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i16> [[TMP1]] to i1283181; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP6]], 03182; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 03183; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]3184; CHECK-NEXT: br i1 [[_MSOR4]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]3185; CHECK: [[BB7]]:3186; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]3187; CHECK-NEXT: unreachable3188; CHECK: [[BB8]]:3189; CHECK-NEXT: [[RES2:%.*]] = call <8 x half> @llvm.x86.avx512fp16.vcvtusi642sh(<8 x half> [[ARG0]], i64 [[ARG1]], i32 9)3190; CHECK-NEXT: [[RES:%.*]] = fadd <8 x half> [[RES1]], [[RES2]]3191; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 83192; CHECK-NEXT: ret <8 x half> [[RES]]3193;3194 %res1 = call <8 x half> @llvm.x86.avx512fp16.vcvtusi642sh(<8 x half> %arg0, i64 %arg1, i32 4)3195 %res2 = call <8 x half> @llvm.x86.avx512fp16.vcvtusi642sh(<8 x half> %arg0, i64 %arg1, i32 9)3196 %res = fadd <8 x half> %res1, %res23197 ret <8 x half> %res3198}3199 3200 3201define <16 x half> @test_mm256_castph128_ph256_freeze(<8 x half> %a0) nounwind {3202; CHECK-LABEL: define <16 x half> @test_mm256_castph128_ph256_freeze(3203; CHECK-SAME: <8 x half> [[A0:%.*]]) #[[ATTR5:[0-9]+]] {3204; CHECK-NEXT: call void @llvm.donothing()3205; CHECK-NEXT: [[A1:%.*]] = freeze <8 x half> poison3206; CHECK-NEXT: [[RES:%.*]] = shufflevector <8 x half> [[A0]], <8 x half> [[A1]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>3207; CHECK-NEXT: store <16 x i16> zeroinitializer, ptr @__msan_retval_tls, align 83208; CHECK-NEXT: ret <16 x half> [[RES]]3209;3210 %a1 = freeze <8 x half> poison3211; The cold never bothered me anyway3212 %res = shufflevector <8 x half> %a0, <8 x half> %a1, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>3213 ret <16 x half> %res3214}3215 3216 3217define <32 x half> @test_mm512_castph128_ph512_freeze(<8 x half> %a0) nounwind {3218; CHECK-LABEL: define <32 x half> @test_mm512_castph128_ph512_freeze(3219; CHECK-SAME: <8 x half> [[A0:%.*]]) #[[ATTR5]] {3220; CHECK-NEXT: call void @llvm.donothing()3221; CHECK-NEXT: [[A1:%.*]] = freeze <8 x half> poison3222; CHECK-NEXT: [[RES:%.*]] = shufflevector <8 x half> [[A0]], <8 x half> [[A1]], <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>3223; CHECK-NEXT: store <32 x i16> zeroinitializer, ptr @__msan_retval_tls, align 83224; CHECK-NEXT: ret <32 x half> [[RES]]3225;3226 %a1 = freeze <8 x half> poison3227 %res = shufflevector <8 x half> %a0, <8 x half> %a1, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>3228 ret <32 x half> %res3229}3230 3231 3232define <32 x half> @test_mm512_castph256_ph512_freeze(<16 x half> %a0) nounwind {3233; CHECK-LABEL: define <32 x half> @test_mm512_castph256_ph512_freeze(3234; CHECK-SAME: <16 x half> [[A0:%.*]]) #[[ATTR5]] {3235; CHECK-NEXT: call void @llvm.donothing()3236; CHECK-NEXT: [[A1:%.*]] = freeze <16 x half> poison3237; CHECK-NEXT: [[RES:%.*]] = shufflevector <16 x half> [[A0]], <16 x half> [[A1]], <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>3238; CHECK-NEXT: store <32 x i16> zeroinitializer, ptr @__msan_retval_tls, align 83239; CHECK-NEXT: ret <32 x half> [[RES]]3240;3241 %a1 = freeze <16 x half> poison3242 %res = shufflevector <16 x half> %a0, <16 x half> %a1, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>3243 ret <32 x half> %res3244}3245 3246attributes #0 = { sanitize_memory }3247;.3248; CHECK: [[PROF1]] = !{!"branch_weights", i32 1, i32 1048575}3249;.3250