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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt < %s -mattr=+avx512f -passes=msan -S | FileCheck %s3;4; Forked from llvm/test/CodeGen/X86/avx512vl-intrinsics.ll5;6; Handled strictly:7; - llvm.x86.avx512.mask.cmp.pd.128, llvm.x86.avx512.mask.cmp.pd.2568; - llvm.x86.avx512.mask.cmp.ps.128, llvm.x86.avx512.mask.cmp.ps.2569; - llvm.x86.avx512.mask.compress.v2f64, llvm.x86.avx512.mask.compress.v4f32, llvm.x86.avx512.mask.compress.v4f64, llvm.x86.avx512.mask.compress.v8f3210; - llvm.x86.avx512.mask.compress.v2i64, llvm.x86.avx512.mask.compress.v4i32, llvm.x86.avx512.mask.compress.v4i64, llvm.x86.avx512.mask.compress.v8i3211; - llvm.x86.avx512.mask.cvtpd2dq.12812; - llvm.x86.avx512.mask.cvtpd2ps13; - llvm.x86.avx512.mask.cvtpd2udq.128, llvm.x86.avx512.mask.cvtpd2udq.25614; - llvm.x86.avx512.mask.cvtps2dq.128, llvm.x86.avx512.mask.cvtps2dq.25615; - llvm.x86.avx512.mask.cvtps2udq.128, llvm.x86.avx512.mask.cvtps2udq.25616; - llvm.x86.avx512.mask.cvttpd2dq.12817; - llvm.x86.avx512.mask.cvttpd2udq.128, llvm.x86.avx512.mask.cvttpd2udq.25618; - llvm.x86.avx512.mask.cvttps2udq.128, llvm.x86.avx512.mask.cvttps2udq.25619; - llvm.x86.avx512.mask.expand.v2f64, llvm.x86.avx512.mask.expand.v4f32, llvm.x86.avx512.mask.expand.v4f64, llvm.x86.avx512.mask.expand.v8f3220; - llvm.x86.avx512.mask.expand.v2i64, llvm.x86.avx512.mask.expand.v4i32, llvm.x86.avx512.mask.expand.v4i64, llvm.x86.avx512.mask.expand.v8i3221; - llvm.x86.avx512.mask.fixupimm.pd.128, llvm.x86.avx512.mask.fixupimm.pd.25622; - llvm.x86.avx512.mask.fixupimm.ps.128 llvm.x86.avx512.mask.fixupimm.ps.25623; - llvm.x86.avx512.mask.getexp.pd.25624; - llvm.x86.avx512.mask.getexp.ps.25625; - llvm.x86.avx512.mask.getmant.pd.128, llvm.x86.avx512.mask.getmant.pd.25626; - llvm.x86.avx512.mask.getmant.ps.128, llvm.x86.avx512.mask.getmant.ps.25627; - llvm.x86.avx512.mask.pmov.db.128, llvm.x86.avx512.mask.pmov.db.25628; - llvm.x86.avx512.mask.pmov.db.mem.128, llvm.x86.avx512.mask.pmov.db.mem.25629; - llvm.x86.avx512.mask.pmov.dw.128, llvm.x86.avx512.mask.pmov.dw.25630; - llvm.x86.avx512.mask.pmov.dw.mem.128, llvm.x86.avx512.mask.pmov.dw.mem.25631; - llvm.x86.avx512.mask.pmov.qb.128, llvm.x86.avx512.mask.pmov.qb.25632; - llvm.x86.avx512.mask.pmov.qb.mem.128, llvm.x86.avx512.mask.pmov.qb.mem.25633; - llvm.x86.avx512.mask.pmov.qd.12834; - llvm.x86.avx512.mask.pmov.qd.mem.128, llvm.x86.avx512.mask.pmov.qd.mem.25635; - llvm.x86.avx512.mask.pmov.qw.128, llvm.x86.avx512.mask.pmov.qw.25636; - llvm.x86.avx512.mask.pmov.qw.mem.128, llvm.x86.avx512.mask.pmov.qw.mem.25637; - llvm.x86.avx512.mask.pmovs.db.128, llvm.x86.avx512.mask.pmovs.db.25638; - llvm.x86.avx512.mask.pmovs.db.mem.128, llvm.x86.avx512.mask.pmovs.db.mem.25639; - llvm.x86.avx512.mask.pmovs.dw.128, llvm.x86.avx512.mask.pmovs.dw.25640; - llvm.x86.avx512.mask.pmovs.dw.mem.128, llvm.x86.avx512.mask.pmovs.dw.mem.25641; - llvm.x86.avx512.mask.pmovs.qb.128, llvm.x86.avx512.mask.pmovs.qb.25642; - llvm.x86.avx512.mask.pmovs.qb.mem.128, llvm.x86.avx512.mask.pmovs.qb.mem.25643; - llvm.x86.avx512.mask.pmovs.qd.128, llvm.x86.avx512.mask.pmovs.qd.25644; - llvm.x86.avx512.mask.pmovs.qd.mem.128, llvm.x86.avx512.mask.pmovs.qd.mem.25645; - llvm.x86.avx512.mask.pmovs.qw.128, llvm.x86.avx512.mask.pmovs.qw.25646; - llvm.x86.avx512.mask.pmovs.qw.mem.128, llvm.x86.avx512.mask.pmovs.qw.mem.25647; - llvm.x86.avx512.mask.pmovus.db.128, llvm.x86.avx512.mask.pmovus.db.25648; - llvm.x86.avx512.mask.pmovus.db.mem.128, llvm.x86.avx512.mask.pmovus.db.mem.25649; - llvm.x86.avx512.mask.pmovus.dw.128, llvm.x86.avx512.mask.pmovus.dw.25650; - llvm.x86.avx512.mask.pmovus.dw.mem.128, llvm.x86.avx512.mask.pmovus.dw.mem.25651; - llvm.x86.avx512.mask.pmovus.qb.128, llvm.x86.avx512.mask.pmovus.qb.25652; - llvm.x86.avx512.mask.pmovus.qb.mem.128, llvm.x86.avx512.mask.pmovus.qb.mem.25653; - llvm.x86.avx512.mask.pmovus.qd.128, llvm.x86.avx512.mask.pmovus.qd.25654; - llvm.x86.avx512.mask.pmovus.qd.mem.128, llvm.x86.avx512.mask.pmovus.qd.mem.25655; - llvm.x86.avx512.mask.pmovus.qw.128, llvm.x86.avx512.mask.pmovus.qw.25656; - llvm.x86.avx512.mask.pmovus.qw.mem.128, llvm.x86.avx512.mask.pmovus.qw.mem.25657; - llvm.x86.avx512.mask.scalef.pd.128, llvm.x86.avx512.mask.scalef.pd.25658; - llvm.x86.avx512.mask.scalef.ps.128, llvm.x86.avx512.mask.scalef.ps.25659; - llvm.x86.avx512.maskz.fixupimm.pd.128, llvm.x86.avx512.maskz.fixupimm.pd.25660; - llvm.x86.avx512.maskz.fixupimm.ps.128, llvm.x86.avx512.maskz.fixupimm.ps.25661; - llvm.x86.avx512.permvar.df.25662; - llvm.x86.avx512.pternlog.d.128, llvm.x86.avx512.pternlog.d.25663; - llvm.x86.avx512.pternlog.q.128, llvm.x86.avx512.pternlog.q.25664;65; Handled heuristically: (none)66 67target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"68target triple = "x86_64-unknown-linux-gnu"69 70define <2 x double> @test_mask_compress_pd_128(<2 x double> %data, <2 x double> %passthru, i8 %mask) #0 {71;72; CHECK-LABEL: define <2 x double> @test_mask_compress_pd_128(73; CHECK-SAME: <2 x double> [[DATA:%.*]], <2 x double> [[PASSTHRU:%.*]], i8 [[MASK:%.*]]) #[[ATTR0:[0-9]+]] {74; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 875; CHECK-NEXT: [[TMP9:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 876; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 877; CHECK-NEXT: call void @llvm.donothing()78; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8 [[TMP5]] to <8 x i1>79; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8 [[MASK]] to <8 x i1>80; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP4]], <8 x i1> [[TMP4]], <2 x i32> <i32 0, i32 1>81; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> [[TMP1]], <2 x i32> <i32 0, i32 1>82; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i64> [[TMP9]] to i12883; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP6]], 084; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i64> [[TMP3]] to i12885; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP7]], 086; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]87; CHECK-NEXT: [[TMP8:%.*]] = bitcast <2 x i1> [[_MSPROP]] to i288; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i2 [[TMP8]], 089; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]90; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1:![0-9]+]]91; CHECK: [[BB9]]:92; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6:[0-9]+]]93; CHECK-NEXT: unreachable94; CHECK: [[BB10]]:95; CHECK-NEXT: [[TMP2:%.*]] = call <2 x double> @llvm.x86.avx512.mask.compress.v2f64(<2 x double> [[DATA]], <2 x double> [[PASSTHRU]], <2 x i1> [[EXTRACT]])96; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 897; CHECK-NEXT: ret <2 x double> [[TMP2]]98;99 %1 = bitcast i8 %mask to <8 x i1>100 %extract = shufflevector <8 x i1> %1, <8 x i1> %1, <2 x i32> <i32 0, i32 1>101 %2 = call <2 x double> @llvm.x86.avx512.mask.compress.v2f64(<2 x double> %data, <2 x double> %passthru, <2 x i1> %extract)102 ret <2 x double> %2103}104 105define <2 x double> @test_maskz_compress_pd_128(<2 x double> %data, i8 %mask) #0 {106;107; CHECK-LABEL: define <2 x double> @test_maskz_compress_pd_128(108; CHECK-SAME: <2 x double> [[DATA:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {109; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8110; CHECK-NEXT: [[TMP7:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8111; CHECK-NEXT: call void @llvm.donothing()112; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>113; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8 [[MASK]] to <8 x i1>114; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP3]], <8 x i1> [[TMP3]], <2 x i32> <i32 0, i32 1>115; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> [[TMP1]], <2 x i32> <i32 0, i32 1>116; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP7]] to i128117; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 0118; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i1> [[_MSPROP]] to i2119; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i2 [[TMP6]], 0120; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]121; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]122; CHECK: [[BB7]]:123; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]124; CHECK-NEXT: unreachable125; CHECK: [[BB8]]:126; CHECK-NEXT: [[TMP2:%.*]] = call <2 x double> @llvm.x86.avx512.mask.compress.v2f64(<2 x double> [[DATA]], <2 x double> zeroinitializer, <2 x i1> [[EXTRACT]])127; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8128; CHECK-NEXT: ret <2 x double> [[TMP2]]129;130 %1 = bitcast i8 %mask to <8 x i1>131 %extract = shufflevector <8 x i1> %1, <8 x i1> %1, <2 x i32> <i32 0, i32 1>132 %2 = call <2 x double> @llvm.x86.avx512.mask.compress.v2f64(<2 x double> %data, <2 x double> zeroinitializer, <2 x i1> %extract)133 ret <2 x double> %2134}135 136define <2 x double> @test_compress_pd_128(<2 x double> %data, <2 x double> %data2) #0 {137; CHECK-LABEL: define <2 x double> @test_compress_pd_128(138; CHECK-SAME: <2 x double> [[DATA:%.*]], <2 x double> [[DATA2:%.*]]) #[[ATTR0]] {139; CHECK-NEXT: [[TMP5:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8140; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8141; CHECK-NEXT: call void @llvm.donothing()142; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP5]] to i128143; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 0144; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP2]] to i128145; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 0146; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]147; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]148; CHECK: [[BB5]]:149; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]150; CHECK-NEXT: unreachable151; CHECK: [[BB6]]:152; CHECK-NEXT: [[TMP1:%.*]] = call <2 x double> @llvm.x86.avx512.mask.compress.v2f64(<2 x double> [[DATA]], <2 x double> [[DATA2]], <2 x i1> splat (i1 true))153; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8154; CHECK-NEXT: ret <2 x double> [[TMP1]]155;156 %1 = call <2 x double> @llvm.x86.avx512.mask.compress.v2f64(<2 x double> %data, <2 x double> %data2, <2 x i1> <i1 true, i1 true>)157 ret <2 x double> %1158}159 160define <4 x float> @test_mask_compress_ps_128(<4 x float> %data, <4 x float> %passthru, i8 %mask) #0 {161;162; CHECK-LABEL: define <4 x float> @test_mask_compress_ps_128(163; CHECK-SAME: <4 x float> [[DATA:%.*]], <4 x float> [[PASSTHRU:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {164; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8165; CHECK-NEXT: [[TMP9:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8166; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8167; CHECK-NEXT: call void @llvm.donothing()168; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8 [[TMP5]] to <8 x i1>169; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8 [[MASK]] to <8 x i1>170; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP4]], <8 x i1> [[TMP4]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>171; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> [[TMP1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>172; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i32> [[TMP9]] to i128173; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP6]], 0174; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i32> [[TMP3]] to i128175; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP7]], 0176; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]177; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x i1> [[_MSPROP]] to i4178; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i4 [[TMP8]], 0179; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]180; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]181; CHECK: [[BB9]]:182; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]183; CHECK-NEXT: unreachable184; CHECK: [[BB10]]:185; CHECK-NEXT: [[TMP2:%.*]] = call <4 x float> @llvm.x86.avx512.mask.compress.v4f32(<4 x float> [[DATA]], <4 x float> [[PASSTHRU]], <4 x i1> [[EXTRACT]])186; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8187; CHECK-NEXT: ret <4 x float> [[TMP2]]188;189 %1 = bitcast i8 %mask to <8 x i1>190 %extract = shufflevector <8 x i1> %1, <8 x i1> %1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>191 %2 = call <4 x float> @llvm.x86.avx512.mask.compress.v4f32(<4 x float> %data, <4 x float> %passthru, <4 x i1> %extract)192 ret <4 x float> %2193}194 195define <4 x float> @test_maskz_compress_ps_128(<4 x float> %data, i8 %mask) #0 {196;197; CHECK-LABEL: define <4 x float> @test_maskz_compress_ps_128(198; CHECK-SAME: <4 x float> [[DATA:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {199; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8200; CHECK-NEXT: [[TMP7:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8201; CHECK-NEXT: call void @llvm.donothing()202; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>203; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8 [[MASK]] to <8 x i1>204; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP3]], <8 x i1> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>205; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> [[TMP1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>206; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP7]] to i128207; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 0208; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i1> [[_MSPROP]] to i4209; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i4 [[TMP6]], 0210; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]211; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]212; CHECK: [[BB7]]:213; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]214; CHECK-NEXT: unreachable215; CHECK: [[BB8]]:216; CHECK-NEXT: [[TMP2:%.*]] = call <4 x float> @llvm.x86.avx512.mask.compress.v4f32(<4 x float> [[DATA]], <4 x float> zeroinitializer, <4 x i1> [[EXTRACT]])217; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8218; CHECK-NEXT: ret <4 x float> [[TMP2]]219;220 %1 = bitcast i8 %mask to <8 x i1>221 %extract = shufflevector <8 x i1> %1, <8 x i1> %1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>222 %2 = call <4 x float> @llvm.x86.avx512.mask.compress.v4f32(<4 x float> %data, <4 x float> zeroinitializer, <4 x i1> %extract)223 ret <4 x float> %2224}225 226define <4 x float> @test_compress_ps_128(<4 x float> %data, <4 x float> %data2) #0 {227; CHECK-LABEL: define <4 x float> @test_compress_ps_128(228; CHECK-SAME: <4 x float> [[DATA:%.*]], <4 x float> [[DATA2:%.*]]) #[[ATTR0]] {229; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8230; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8231; CHECK-NEXT: call void @llvm.donothing()232; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP5]] to i128233; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 0234; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i128235; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 0236; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]237; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]238; CHECK: [[BB5]]:239; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]240; CHECK-NEXT: unreachable241; CHECK: [[BB6]]:242; CHECK-NEXT: [[TMP1:%.*]] = call <4 x float> @llvm.x86.avx512.mask.compress.v4f32(<4 x float> [[DATA]], <4 x float> [[DATA2]], <4 x i1> splat (i1 true))243; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8244; CHECK-NEXT: ret <4 x float> [[TMP1]]245;246 %1 = call <4 x float> @llvm.x86.avx512.mask.compress.v4f32(<4 x float> %data, <4 x float> %data2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)247 ret <4 x float> %1248}249 250define <2 x i64> @test_mask_compress_q_128(<2 x i64> %data, <2 x i64> %passthru, i8 %mask) #0 {251;252; CHECK-LABEL: define <2 x i64> @test_mask_compress_q_128(253; CHECK-SAME: <2 x i64> [[DATA:%.*]], <2 x i64> [[PASSTHRU:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {254; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8255; CHECK-NEXT: [[TMP9:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8256; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8257; CHECK-NEXT: call void @llvm.donothing()258; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8 [[TMP5]] to <8 x i1>259; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8 [[MASK]] to <8 x i1>260; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP4]], <8 x i1> [[TMP4]], <2 x i32> <i32 0, i32 1>261; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> [[TMP1]], <2 x i32> <i32 0, i32 1>262; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i64> [[TMP9]] to i128263; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP6]], 0264; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i64> [[TMP3]] to i128265; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP7]], 0266; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]267; CHECK-NEXT: [[TMP8:%.*]] = bitcast <2 x i1> [[_MSPROP]] to i2268; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i2 [[TMP8]], 0269; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]270; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]271; CHECK: [[BB9]]:272; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]273; CHECK-NEXT: unreachable274; CHECK: [[BB10]]:275; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i64> @llvm.x86.avx512.mask.compress.v2i64(<2 x i64> [[DATA]], <2 x i64> [[PASSTHRU]], <2 x i1> [[EXTRACT]])276; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8277; CHECK-NEXT: ret <2 x i64> [[TMP2]]278;279 %1 = bitcast i8 %mask to <8 x i1>280 %extract = shufflevector <8 x i1> %1, <8 x i1> %1, <2 x i32> <i32 0, i32 1>281 %2 = call <2 x i64> @llvm.x86.avx512.mask.compress.v2i64(<2 x i64> %data, <2 x i64> %passthru, <2 x i1> %extract)282 ret <2 x i64> %2283}284 285define <2 x i64> @test_maskz_compress_q_128(<2 x i64> %data, i8 %mask) #0 {286;287; CHECK-LABEL: define <2 x i64> @test_maskz_compress_q_128(288; CHECK-SAME: <2 x i64> [[DATA:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {289; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8290; CHECK-NEXT: [[TMP7:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8291; CHECK-NEXT: call void @llvm.donothing()292; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>293; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8 [[MASK]] to <8 x i1>294; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP3]], <8 x i1> [[TMP3]], <2 x i32> <i32 0, i32 1>295; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> [[TMP1]], <2 x i32> <i32 0, i32 1>296; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP7]] to i128297; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 0298; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i1> [[_MSPROP]] to i2299; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i2 [[TMP6]], 0300; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]301; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]302; CHECK: [[BB7]]:303; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]304; CHECK-NEXT: unreachable305; CHECK: [[BB8]]:306; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i64> @llvm.x86.avx512.mask.compress.v2i64(<2 x i64> [[DATA]], <2 x i64> zeroinitializer, <2 x i1> [[EXTRACT]])307; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8308; CHECK-NEXT: ret <2 x i64> [[TMP2]]309;310 %1 = bitcast i8 %mask to <8 x i1>311 %extract = shufflevector <8 x i1> %1, <8 x i1> %1, <2 x i32> <i32 0, i32 1>312 %2 = call <2 x i64> @llvm.x86.avx512.mask.compress.v2i64(<2 x i64> %data, <2 x i64> zeroinitializer, <2 x i1> %extract)313 ret <2 x i64> %2314}315 316define <2 x i64> @test_compress_q_128(<2 x i64> %data, <2 x i64> %data2) #0 {317; CHECK-LABEL: define <2 x i64> @test_compress_q_128(318; CHECK-SAME: <2 x i64> [[DATA:%.*]], <2 x i64> [[DATA2:%.*]]) #[[ATTR0]] {319; CHECK-NEXT: [[TMP5:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8320; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8321; CHECK-NEXT: call void @llvm.donothing()322; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP5]] to i128323; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 0324; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP2]] to i128325; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 0326; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]327; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]328; CHECK: [[BB5]]:329; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]330; CHECK-NEXT: unreachable331; CHECK: [[BB6]]:332; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i64> @llvm.x86.avx512.mask.compress.v2i64(<2 x i64> [[DATA]], <2 x i64> [[DATA2]], <2 x i1> splat (i1 true))333; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8334; CHECK-NEXT: ret <2 x i64> [[TMP1]]335;336 %1 = call <2 x i64> @llvm.x86.avx512.mask.compress.v2i64(<2 x i64> %data, <2 x i64> %data2, <2 x i1> <i1 true, i1 true>)337 ret <2 x i64> %1338}339 340define <4 x i32> @test_mask_compress_d_128(<4 x i32> %data, <4 x i32> %passthru, i8 %mask) #0 {341;342; CHECK-LABEL: define <4 x i32> @test_mask_compress_d_128(343; CHECK-SAME: <4 x i32> [[DATA:%.*]], <4 x i32> [[PASSTHRU:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {344; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8345; CHECK-NEXT: [[TMP9:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8346; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8347; CHECK-NEXT: call void @llvm.donothing()348; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8 [[TMP5]] to <8 x i1>349; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8 [[MASK]] to <8 x i1>350; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP4]], <8 x i1> [[TMP4]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>351; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> [[TMP1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>352; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i32> [[TMP9]] to i128353; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP6]], 0354; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i32> [[TMP3]] to i128355; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP7]], 0356; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]357; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x i1> [[_MSPROP]] to i4358; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i4 [[TMP8]], 0359; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]360; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]361; CHECK: [[BB9]]:362; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]363; CHECK-NEXT: unreachable364; CHECK: [[BB10]]:365; CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.x86.avx512.mask.compress.v4i32(<4 x i32> [[DATA]], <4 x i32> [[PASSTHRU]], <4 x i1> [[EXTRACT]])366; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8367; CHECK-NEXT: ret <4 x i32> [[TMP2]]368;369 %1 = bitcast i8 %mask to <8 x i1>370 %extract = shufflevector <8 x i1> %1, <8 x i1> %1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>371 %2 = call <4 x i32> @llvm.x86.avx512.mask.compress.v4i32(<4 x i32> %data, <4 x i32> %passthru, <4 x i1> %extract)372 ret <4 x i32> %2373}374 375define <4 x i32> @test_maskz_compress_d_128(<4 x i32> %data, i8 %mask) #0 {376;377; CHECK-LABEL: define <4 x i32> @test_maskz_compress_d_128(378; CHECK-SAME: <4 x i32> [[DATA:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {379; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8380; CHECK-NEXT: [[TMP7:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8381; CHECK-NEXT: call void @llvm.donothing()382; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>383; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8 [[MASK]] to <8 x i1>384; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP3]], <8 x i1> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>385; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> [[TMP1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>386; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP7]] to i128387; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 0388; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i1> [[_MSPROP]] to i4389; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i4 [[TMP6]], 0390; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]391; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]392; CHECK: [[BB7]]:393; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]394; CHECK-NEXT: unreachable395; CHECK: [[BB8]]:396; CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.x86.avx512.mask.compress.v4i32(<4 x i32> [[DATA]], <4 x i32> zeroinitializer, <4 x i1> [[EXTRACT]])397; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8398; CHECK-NEXT: ret <4 x i32> [[TMP2]]399;400 %1 = bitcast i8 %mask to <8 x i1>401 %extract = shufflevector <8 x i1> %1, <8 x i1> %1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>402 %2 = call <4 x i32> @llvm.x86.avx512.mask.compress.v4i32(<4 x i32> %data, <4 x i32> zeroinitializer, <4 x i1> %extract)403 ret <4 x i32> %2404}405 406define <4 x i32> @test_compress_d_128(<4 x i32> %data, <4 x i32> %data2) #0 {407; CHECK-LABEL: define <4 x i32> @test_compress_d_128(408; CHECK-SAME: <4 x i32> [[DATA:%.*]], <4 x i32> [[DATA2:%.*]]) #[[ATTR0]] {409; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8410; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8411; CHECK-NEXT: call void @llvm.donothing()412; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP5]] to i128413; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 0414; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i128415; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 0416; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]417; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]418; CHECK: [[BB5]]:419; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]420; CHECK-NEXT: unreachable421; CHECK: [[BB6]]:422; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.x86.avx512.mask.compress.v4i32(<4 x i32> [[DATA]], <4 x i32> [[DATA2]], <4 x i1> splat (i1 true))423; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8424; CHECK-NEXT: ret <4 x i32> [[TMP1]]425;426 %1 = call <4 x i32> @llvm.x86.avx512.mask.compress.v4i32(<4 x i32> %data, <4 x i32> %data2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)427 ret <4 x i32> %1428}429 430define <2 x double> @test_expand_pd_128(<2 x double> %data, <2 x double> %data2) #0 {431; CHECK-LABEL: define <2 x double> @test_expand_pd_128(432; CHECK-SAME: <2 x double> [[DATA:%.*]], <2 x double> [[DATA2:%.*]]) #[[ATTR0]] {433; CHECK-NEXT: [[TMP5:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8434; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8435; CHECK-NEXT: call void @llvm.donothing()436; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP5]] to i128437; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 0438; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP2]] to i128439; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 0440; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]441; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]442; CHECK: [[BB5]]:443; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]444; CHECK-NEXT: unreachable445; CHECK: [[BB6]]:446; CHECK-NEXT: [[TMP1:%.*]] = call <2 x double> @llvm.x86.avx512.mask.expand.v2f64(<2 x double> [[DATA]], <2 x double> [[DATA2]], <2 x i1> splat (i1 true))447; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8448; CHECK-NEXT: ret <2 x double> [[TMP1]]449;450 %1 = call <2 x double> @llvm.x86.avx512.mask.expand.v2f64(<2 x double> %data, <2 x double> %data2, <2 x i1> <i1 true, i1 true>)451 ret <2 x double> %1452}453 454define <2 x double> @test_mask_expand_pd_128(<2 x double> %data, <2 x double> %passthru, i8 %mask) #0 {455;456; CHECK-LABEL: define <2 x double> @test_mask_expand_pd_128(457; CHECK-SAME: <2 x double> [[DATA:%.*]], <2 x double> [[PASSTHRU:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {458; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8459; CHECK-NEXT: [[TMP9:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8460; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8461; CHECK-NEXT: call void @llvm.donothing()462; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8 [[TMP5]] to <8 x i1>463; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8 [[MASK]] to <8 x i1>464; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP4]], <8 x i1> [[TMP4]], <2 x i32> <i32 0, i32 1>465; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> [[TMP1]], <2 x i32> <i32 0, i32 1>466; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i64> [[TMP9]] to i128467; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP6]], 0468; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i64> [[TMP3]] to i128469; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP7]], 0470; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]471; CHECK-NEXT: [[TMP8:%.*]] = bitcast <2 x i1> [[_MSPROP]] to i2472; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i2 [[TMP8]], 0473; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]474; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]475; CHECK: [[BB9]]:476; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]477; CHECK-NEXT: unreachable478; CHECK: [[BB10]]:479; CHECK-NEXT: [[TMP2:%.*]] = call <2 x double> @llvm.x86.avx512.mask.expand.v2f64(<2 x double> [[DATA]], <2 x double> [[PASSTHRU]], <2 x i1> [[EXTRACT]])480; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8481; CHECK-NEXT: ret <2 x double> [[TMP2]]482;483 %1 = bitcast i8 %mask to <8 x i1>484 %extract = shufflevector <8 x i1> %1, <8 x i1> %1, <2 x i32> <i32 0, i32 1>485 %2 = call <2 x double> @llvm.x86.avx512.mask.expand.v2f64(<2 x double> %data, <2 x double> %passthru, <2 x i1> %extract)486 ret <2 x double> %2487}488 489define <2 x double> @test_maskz_expand_pd_128(<2 x double> %data, i8 %mask) #0 {490;491; CHECK-LABEL: define <2 x double> @test_maskz_expand_pd_128(492; CHECK-SAME: <2 x double> [[DATA:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {493; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8494; CHECK-NEXT: [[TMP7:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8495; CHECK-NEXT: call void @llvm.donothing()496; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>497; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8 [[MASK]] to <8 x i1>498; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP3]], <8 x i1> [[TMP3]], <2 x i32> <i32 0, i32 1>499; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> [[TMP1]], <2 x i32> <i32 0, i32 1>500; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP7]] to i128501; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 0502; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i1> [[_MSPROP]] to i2503; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i2 [[TMP6]], 0504; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]505; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]506; CHECK: [[BB7]]:507; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]508; CHECK-NEXT: unreachable509; CHECK: [[BB8]]:510; CHECK-NEXT: [[TMP2:%.*]] = call <2 x double> @llvm.x86.avx512.mask.expand.v2f64(<2 x double> [[DATA]], <2 x double> zeroinitializer, <2 x i1> [[EXTRACT]])511; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8512; CHECK-NEXT: ret <2 x double> [[TMP2]]513;514 %1 = bitcast i8 %mask to <8 x i1>515 %extract = shufflevector <8 x i1> %1, <8 x i1> %1, <2 x i32> <i32 0, i32 1>516 %2 = call <2 x double> @llvm.x86.avx512.mask.expand.v2f64(<2 x double> %data, <2 x double> zeroinitializer, <2 x i1> %extract)517 ret <2 x double> %2518}519 520define <4 x float> @test_expand_ps_128(<4 x float> %data, <4 x float> %data2) #0 {521; CHECK-LABEL: define <4 x float> @test_expand_ps_128(522; CHECK-SAME: <4 x float> [[DATA:%.*]], <4 x float> [[DATA2:%.*]]) #[[ATTR0]] {523; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8524; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8525; CHECK-NEXT: call void @llvm.donothing()526; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP5]] to i128527; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 0528; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i128529; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 0530; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]531; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]532; CHECK: [[BB5]]:533; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]534; CHECK-NEXT: unreachable535; CHECK: [[BB6]]:536; CHECK-NEXT: [[TMP1:%.*]] = call <4 x float> @llvm.x86.avx512.mask.expand.v4f32(<4 x float> [[DATA]], <4 x float> [[DATA2]], <4 x i1> splat (i1 true))537; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8538; CHECK-NEXT: ret <4 x float> [[TMP1]]539;540 %1 = call <4 x float> @llvm.x86.avx512.mask.expand.v4f32(<4 x float> %data, <4 x float> %data2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)541 ret <4 x float> %1542}543 544define <4 x float> @test_mask_expand_ps_128(<4 x float> %data, <4 x float> %passthru, i8 %mask) #0 {545;546; CHECK-LABEL: define <4 x float> @test_mask_expand_ps_128(547; CHECK-SAME: <4 x float> [[DATA:%.*]], <4 x float> [[PASSTHRU:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {548; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8549; CHECK-NEXT: [[TMP9:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8550; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8551; CHECK-NEXT: call void @llvm.donothing()552; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8 [[TMP5]] to <8 x i1>553; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8 [[MASK]] to <8 x i1>554; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP4]], <8 x i1> [[TMP4]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>555; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> [[TMP1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>556; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i32> [[TMP9]] to i128557; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP6]], 0558; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i32> [[TMP3]] to i128559; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP7]], 0560; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]561; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x i1> [[_MSPROP]] to i4562; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i4 [[TMP8]], 0563; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]564; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]565; CHECK: [[BB9]]:566; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]567; CHECK-NEXT: unreachable568; CHECK: [[BB10]]:569; CHECK-NEXT: [[TMP2:%.*]] = call <4 x float> @llvm.x86.avx512.mask.expand.v4f32(<4 x float> [[DATA]], <4 x float> [[PASSTHRU]], <4 x i1> [[EXTRACT]])570; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8571; CHECK-NEXT: ret <4 x float> [[TMP2]]572;573 %1 = bitcast i8 %mask to <8 x i1>574 %extract = shufflevector <8 x i1> %1, <8 x i1> %1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>575 %2 = call <4 x float> @llvm.x86.avx512.mask.expand.v4f32(<4 x float> %data, <4 x float> %passthru, <4 x i1> %extract)576 ret <4 x float> %2577}578 579define <4 x float> @test_maskz_expand_ps_128(<4 x float> %data, i8 %mask) #0 {580;581; CHECK-LABEL: define <4 x float> @test_maskz_expand_ps_128(582; CHECK-SAME: <4 x float> [[DATA:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {583; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8584; CHECK-NEXT: [[TMP7:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8585; CHECK-NEXT: call void @llvm.donothing()586; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>587; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8 [[MASK]] to <8 x i1>588; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP3]], <8 x i1> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>589; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> [[TMP1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>590; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP7]] to i128591; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 0592; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i1> [[_MSPROP]] to i4593; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i4 [[TMP6]], 0594; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]595; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]596; CHECK: [[BB7]]:597; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]598; CHECK-NEXT: unreachable599; CHECK: [[BB8]]:600; CHECK-NEXT: [[TMP2:%.*]] = call <4 x float> @llvm.x86.avx512.mask.expand.v4f32(<4 x float> [[DATA]], <4 x float> zeroinitializer, <4 x i1> [[EXTRACT]])601; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8602; CHECK-NEXT: ret <4 x float> [[TMP2]]603;604 %1 = bitcast i8 %mask to <8 x i1>605 %extract = shufflevector <8 x i1> %1, <8 x i1> %1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>606 %2 = call <4 x float> @llvm.x86.avx512.mask.expand.v4f32(<4 x float> %data, <4 x float> zeroinitializer, <4 x i1> %extract)607 ret <4 x float> %2608}609 610define <2 x i64> @test_expand_q_128(<2 x i64> %data, <2 x i64> %data2) #0 {611; CHECK-LABEL: define <2 x i64> @test_expand_q_128(612; CHECK-SAME: <2 x i64> [[DATA:%.*]], <2 x i64> [[DATA2:%.*]]) #[[ATTR0]] {613; CHECK-NEXT: [[TMP5:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8614; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8615; CHECK-NEXT: call void @llvm.donothing()616; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP5]] to i128617; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 0618; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP2]] to i128619; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 0620; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]621; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]622; CHECK: [[BB5]]:623; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]624; CHECK-NEXT: unreachable625; CHECK: [[BB6]]:626; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i64> @llvm.x86.avx512.mask.expand.v2i64(<2 x i64> [[DATA]], <2 x i64> [[DATA2]], <2 x i1> splat (i1 true))627; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8628; CHECK-NEXT: ret <2 x i64> [[TMP1]]629;630 %1 = call <2 x i64> @llvm.x86.avx512.mask.expand.v2i64(<2 x i64> %data, <2 x i64> %data2, <2 x i1> <i1 true, i1 true>)631 ret <2 x i64> %1632}633 634define <2 x i64> @test_mask_expand_q_128(<2 x i64> %data, <2 x i64> %passthru, i8 %mask) #0 {635;636; CHECK-LABEL: define <2 x i64> @test_mask_expand_q_128(637; CHECK-SAME: <2 x i64> [[DATA:%.*]], <2 x i64> [[PASSTHRU:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {638; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8639; CHECK-NEXT: [[TMP9:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8640; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8641; CHECK-NEXT: call void @llvm.donothing()642; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8 [[TMP5]] to <8 x i1>643; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8 [[MASK]] to <8 x i1>644; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP4]], <8 x i1> [[TMP4]], <2 x i32> <i32 0, i32 1>645; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> [[TMP1]], <2 x i32> <i32 0, i32 1>646; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i64> [[TMP9]] to i128647; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP6]], 0648; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i64> [[TMP3]] to i128649; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP7]], 0650; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]651; CHECK-NEXT: [[TMP8:%.*]] = bitcast <2 x i1> [[_MSPROP]] to i2652; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i2 [[TMP8]], 0653; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]654; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]655; CHECK: [[BB9]]:656; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]657; CHECK-NEXT: unreachable658; CHECK: [[BB10]]:659; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i64> @llvm.x86.avx512.mask.expand.v2i64(<2 x i64> [[DATA]], <2 x i64> [[PASSTHRU]], <2 x i1> [[EXTRACT]])660; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8661; CHECK-NEXT: ret <2 x i64> [[TMP2]]662;663 %1 = bitcast i8 %mask to <8 x i1>664 %extract = shufflevector <8 x i1> %1, <8 x i1> %1, <2 x i32> <i32 0, i32 1>665 %2 = call <2 x i64> @llvm.x86.avx512.mask.expand.v2i64(<2 x i64> %data, <2 x i64> %passthru, <2 x i1> %extract)666 ret <2 x i64> %2667}668 669define <2 x i64> @test_maskz_expand_q_128(<2 x i64> %data, i8 %mask) #0 {670;671; CHECK-LABEL: define <2 x i64> @test_maskz_expand_q_128(672; CHECK-SAME: <2 x i64> [[DATA:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {673; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8674; CHECK-NEXT: [[TMP7:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8675; CHECK-NEXT: call void @llvm.donothing()676; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>677; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8 [[MASK]] to <8 x i1>678; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP3]], <8 x i1> [[TMP3]], <2 x i32> <i32 0, i32 1>679; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> [[TMP1]], <2 x i32> <i32 0, i32 1>680; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP7]] to i128681; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 0682; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i1> [[_MSPROP]] to i2683; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i2 [[TMP6]], 0684; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]685; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]686; CHECK: [[BB7]]:687; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]688; CHECK-NEXT: unreachable689; CHECK: [[BB8]]:690; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i64> @llvm.x86.avx512.mask.expand.v2i64(<2 x i64> [[DATA]], <2 x i64> zeroinitializer, <2 x i1> [[EXTRACT]])691; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8692; CHECK-NEXT: ret <2 x i64> [[TMP2]]693;694 %1 = bitcast i8 %mask to <8 x i1>695 %extract = shufflevector <8 x i1> %1, <8 x i1> %1, <2 x i32> <i32 0, i32 1>696 %2 = call <2 x i64> @llvm.x86.avx512.mask.expand.v2i64(<2 x i64> %data, <2 x i64> zeroinitializer, <2 x i1> %extract)697 ret <2 x i64> %2698}699 700define <4 x i32> @test_expand_d_128(<4 x i32> %data, <4 x i32> %data2) #0 {701; CHECK-LABEL: define <4 x i32> @test_expand_d_128(702; CHECK-SAME: <4 x i32> [[DATA:%.*]], <4 x i32> [[DATA2:%.*]]) #[[ATTR0]] {703; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8704; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8705; CHECK-NEXT: call void @llvm.donothing()706; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP5]] to i128707; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 0708; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i128709; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 0710; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]711; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]712; CHECK: [[BB5]]:713; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]714; CHECK-NEXT: unreachable715; CHECK: [[BB6]]:716; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.x86.avx512.mask.expand.v4i32(<4 x i32> [[DATA]], <4 x i32> [[DATA2]], <4 x i1> splat (i1 true))717; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8718; CHECK-NEXT: ret <4 x i32> [[TMP1]]719;720 %1 = call <4 x i32> @llvm.x86.avx512.mask.expand.v4i32(<4 x i32> %data, <4 x i32> %data2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)721 ret <4 x i32> %1722}723 724define <4 x i32> @test_mask_expand_d_128(<4 x i32> %data, <4 x i32> %passthru, i8 %mask) #0 {725;726; CHECK-LABEL: define <4 x i32> @test_mask_expand_d_128(727; CHECK-SAME: <4 x i32> [[DATA:%.*]], <4 x i32> [[PASSTHRU:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {728; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8729; CHECK-NEXT: [[TMP9:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8730; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8731; CHECK-NEXT: call void @llvm.donothing()732; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8 [[TMP5]] to <8 x i1>733; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8 [[MASK]] to <8 x i1>734; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP4]], <8 x i1> [[TMP4]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>735; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> [[TMP1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>736; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i32> [[TMP9]] to i128737; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP6]], 0738; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i32> [[TMP3]] to i128739; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP7]], 0740; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]741; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x i1> [[_MSPROP]] to i4742; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i4 [[TMP8]], 0743; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]744; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]745; CHECK: [[BB9]]:746; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]747; CHECK-NEXT: unreachable748; CHECK: [[BB10]]:749; CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.x86.avx512.mask.expand.v4i32(<4 x i32> [[DATA]], <4 x i32> [[PASSTHRU]], <4 x i1> [[EXTRACT]])750; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8751; CHECK-NEXT: ret <4 x i32> [[TMP2]]752;753 %1 = bitcast i8 %mask to <8 x i1>754 %extract = shufflevector <8 x i1> %1, <8 x i1> %1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>755 %2 = call <4 x i32> @llvm.x86.avx512.mask.expand.v4i32(<4 x i32> %data, <4 x i32> %passthru, <4 x i1> %extract)756 ret <4 x i32> %2757}758 759define <4 x i32> @test_maskz_expand_d_128(<4 x i32> %data, i8 %mask) #0 {760;761; CHECK-LABEL: define <4 x i32> @test_maskz_expand_d_128(762; CHECK-SAME: <4 x i32> [[DATA:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {763; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8764; CHECK-NEXT: [[TMP7:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8765; CHECK-NEXT: call void @llvm.donothing()766; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>767; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8 [[MASK]] to <8 x i1>768; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP3]], <8 x i1> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>769; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> [[TMP1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>770; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP7]] to i128771; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 0772; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i1> [[_MSPROP]] to i4773; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i4 [[TMP6]], 0774; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]775; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]776; CHECK: [[BB7]]:777; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]778; CHECK-NEXT: unreachable779; CHECK: [[BB8]]:780; CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.x86.avx512.mask.expand.v4i32(<4 x i32> [[DATA]], <4 x i32> zeroinitializer, <4 x i1> [[EXTRACT]])781; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8782; CHECK-NEXT: ret <4 x i32> [[TMP2]]783;784 %1 = bitcast i8 %mask to <8 x i1>785 %extract = shufflevector <8 x i1> %1, <8 x i1> %1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>786 %2 = call <4 x i32> @llvm.x86.avx512.mask.expand.v4i32(<4 x i32> %data, <4 x i32> zeroinitializer, <4 x i1> %extract)787 ret <4 x i32> %2788}789 790define <4 x double> @test_mask_compress_pd_256(<4 x double> %data, <4 x double> %passthru, i8 %mask) #0 {791;792; CHECK-LABEL: define <4 x double> @test_mask_compress_pd_256(793; CHECK-SAME: <4 x double> [[DATA:%.*]], <4 x double> [[PASSTHRU:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {794; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 8795; CHECK-NEXT: [[TMP9:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8796; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8797; CHECK-NEXT: call void @llvm.donothing()798; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8 [[TMP5]] to <8 x i1>799; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8 [[MASK]] to <8 x i1>800; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP4]], <8 x i1> [[TMP4]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>801; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> [[TMP1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>802; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i64> [[TMP9]] to i256803; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP6]], 0804; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i64> [[TMP3]] to i256805; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP7]], 0806; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]807; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x i1> [[_MSPROP]] to i4808; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i4 [[TMP8]], 0809; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]810; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]811; CHECK: [[BB9]]:812; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]813; CHECK-NEXT: unreachable814; CHECK: [[BB10]]:815; CHECK-NEXT: [[TMP2:%.*]] = call <4 x double> @llvm.x86.avx512.mask.compress.v4f64(<4 x double> [[DATA]], <4 x double> [[PASSTHRU]], <4 x i1> [[EXTRACT]])816; CHECK-NEXT: store <4 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8817; CHECK-NEXT: ret <4 x double> [[TMP2]]818;819 %1 = bitcast i8 %mask to <8 x i1>820 %extract = shufflevector <8 x i1> %1, <8 x i1> %1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>821 %2 = call <4 x double> @llvm.x86.avx512.mask.compress.v4f64(<4 x double> %data, <4 x double> %passthru, <4 x i1> %extract)822 ret <4 x double> %2823}824 825define <4 x double> @test_maskz_compress_pd_256(<4 x double> %data, i8 %mask) #0 {826;827; CHECK-LABEL: define <4 x double> @test_maskz_compress_pd_256(828; CHECK-SAME: <4 x double> [[DATA:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {829; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8830; CHECK-NEXT: [[TMP7:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8831; CHECK-NEXT: call void @llvm.donothing()832; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>833; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8 [[MASK]] to <8 x i1>834; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP3]], <8 x i1> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>835; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> [[TMP1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>836; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i64> [[TMP7]] to i256837; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP5]], 0838; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i1> [[_MSPROP]] to i4839; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i4 [[TMP6]], 0840; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]841; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]842; CHECK: [[BB7]]:843; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]844; CHECK-NEXT: unreachable845; CHECK: [[BB8]]:846; CHECK-NEXT: [[TMP2:%.*]] = call <4 x double> @llvm.x86.avx512.mask.compress.v4f64(<4 x double> [[DATA]], <4 x double> zeroinitializer, <4 x i1> [[EXTRACT]])847; CHECK-NEXT: store <4 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8848; CHECK-NEXT: ret <4 x double> [[TMP2]]849;850 %1 = bitcast i8 %mask to <8 x i1>851 %extract = shufflevector <8 x i1> %1, <8 x i1> %1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>852 %2 = call <4 x double> @llvm.x86.avx512.mask.compress.v4f64(<4 x double> %data, <4 x double> zeroinitializer, <4 x i1> %extract)853 ret <4 x double> %2854}855 856define <4 x double> @test_compress_pd_256(<4 x double> %data, <4 x double> %data2) #0 {857; CHECK-LABEL: define <4 x double> @test_compress_pd_256(858; CHECK-SAME: <4 x double> [[DATA:%.*]], <4 x double> [[DATA2:%.*]]) #[[ATTR0]] {859; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8860; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8861; CHECK-NEXT: call void @llvm.donothing()862; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i64> [[TMP5]] to i256863; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP3]], 0864; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i64> [[TMP2]] to i256865; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP4]], 0866; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]867; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]868; CHECK: [[BB5]]:869; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]870; CHECK-NEXT: unreachable871; CHECK: [[BB6]]:872; CHECK-NEXT: [[TMP1:%.*]] = call <4 x double> @llvm.x86.avx512.mask.compress.v4f64(<4 x double> [[DATA]], <4 x double> [[DATA2]], <4 x i1> splat (i1 true))873; CHECK-NEXT: store <4 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8874; CHECK-NEXT: ret <4 x double> [[TMP1]]875;876 %1 = call <4 x double> @llvm.x86.avx512.mask.compress.v4f64(<4 x double> %data, <4 x double> %data2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)877 ret <4 x double> %1878}879 880define <8 x float> @test_mask_compress_ps_256(<8 x float> %data, <8 x float> %passthru, i8 %mask) #0 {881;882; CHECK-LABEL: define <8 x float> @test_mask_compress_ps_256(883; CHECK-SAME: <8 x float> [[DATA:%.*]], <8 x float> [[PASSTHRU:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {884; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 8885; CHECK-NEXT: [[TMP9:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8886; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8887; CHECK-NEXT: call void @llvm.donothing()888; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8 [[TMP5]] to <8 x i1>889; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8 [[MASK]] to <8 x i1>890; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i32> [[TMP9]] to i256891; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP6]], 0892; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i32> [[TMP3]] to i256893; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP7]], 0894; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]895; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i1> [[TMP4]] to i8896; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP8]], 0897; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]898; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]899; CHECK: [[BB9]]:900; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]901; CHECK-NEXT: unreachable902; CHECK: [[BB10]]:903; CHECK-NEXT: [[TMP2:%.*]] = call <8 x float> @llvm.x86.avx512.mask.compress.v8f32(<8 x float> [[DATA]], <8 x float> [[PASSTHRU]], <8 x i1> [[TMP1]])904; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8905; CHECK-NEXT: ret <8 x float> [[TMP2]]906;907 %1 = bitcast i8 %mask to <8 x i1>908 %2 = call <8 x float> @llvm.x86.avx512.mask.compress.v8f32(<8 x float> %data, <8 x float> %passthru, <8 x i1> %1)909 ret <8 x float> %2910}911 912define <8 x float> @test_maskz_compress_ps_256(<8 x float> %data, i8 %mask) #0 {913;914; CHECK-LABEL: define <8 x float> @test_maskz_compress_ps_256(915; CHECK-SAME: <8 x float> [[DATA:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {916; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8917; CHECK-NEXT: [[TMP7:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8918; CHECK-NEXT: call void @llvm.donothing()919; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>920; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8 [[MASK]] to <8 x i1>921; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i32> [[TMP7]] to i256922; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP5]], 0923; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i1> [[TMP3]] to i8924; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i8 [[TMP6]], 0925; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]926; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]927; CHECK: [[BB7]]:928; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]929; CHECK-NEXT: unreachable930; CHECK: [[BB8]]:931; CHECK-NEXT: [[TMP2:%.*]] = call <8 x float> @llvm.x86.avx512.mask.compress.v8f32(<8 x float> [[DATA]], <8 x float> zeroinitializer, <8 x i1> [[TMP1]])932; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8933; CHECK-NEXT: ret <8 x float> [[TMP2]]934;935 %1 = bitcast i8 %mask to <8 x i1>936 %2 = call <8 x float> @llvm.x86.avx512.mask.compress.v8f32(<8 x float> %data, <8 x float> zeroinitializer, <8 x i1> %1)937 ret <8 x float> %2938}939 940define <8 x float> @test_compress_ps_256(<8 x float> %data, <8 x float> %data2) #0 {941; CHECK-LABEL: define <8 x float> @test_compress_ps_256(942; CHECK-SAME: <8 x float> [[DATA:%.*]], <8 x float> [[DATA2:%.*]]) #[[ATTR0]] {943; CHECK-NEXT: [[TMP5:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8944; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8945; CHECK-NEXT: call void @llvm.donothing()946; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i32> [[TMP5]] to i256947; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP3]], 0948; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i32> [[TMP2]] to i256949; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP4]], 0950; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]951; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]952; CHECK: [[BB5]]:953; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]954; CHECK-NEXT: unreachable955; CHECK: [[BB6]]:956; CHECK-NEXT: [[TMP1:%.*]] = call <8 x float> @llvm.x86.avx512.mask.compress.v8f32(<8 x float> [[DATA]], <8 x float> [[DATA2]], <8 x i1> splat (i1 true))957; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8958; CHECK-NEXT: ret <8 x float> [[TMP1]]959;960 %1 = call <8 x float> @llvm.x86.avx512.mask.compress.v8f32(<8 x float> %data, <8 x float> %data2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)961 ret <8 x float> %1962}963 964define <4 x i64> @test_mask_compress_q_256(<4 x i64> %data, <4 x i64> %passthru, i8 %mask) #0 {965;966; CHECK-LABEL: define <4 x i64> @test_mask_compress_q_256(967; CHECK-SAME: <4 x i64> [[DATA:%.*]], <4 x i64> [[PASSTHRU:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {968; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 8969; CHECK-NEXT: [[TMP9:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8970; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8971; CHECK-NEXT: call void @llvm.donothing()972; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8 [[TMP5]] to <8 x i1>973; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8 [[MASK]] to <8 x i1>974; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP4]], <8 x i1> [[TMP4]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>975; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> [[TMP1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>976; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i64> [[TMP9]] to i256977; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP6]], 0978; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i64> [[TMP3]] to i256979; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP7]], 0980; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]981; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x i1> [[_MSPROP]] to i4982; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i4 [[TMP8]], 0983; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]984; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]985; CHECK: [[BB9]]:986; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]987; CHECK-NEXT: unreachable988; CHECK: [[BB10]]:989; CHECK-NEXT: [[TMP2:%.*]] = call <4 x i64> @llvm.x86.avx512.mask.compress.v4i64(<4 x i64> [[DATA]], <4 x i64> [[PASSTHRU]], <4 x i1> [[EXTRACT]])990; CHECK-NEXT: store <4 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8991; CHECK-NEXT: ret <4 x i64> [[TMP2]]992;993 %1 = bitcast i8 %mask to <8 x i1>994 %extract = shufflevector <8 x i1> %1, <8 x i1> %1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>995 %2 = call <4 x i64> @llvm.x86.avx512.mask.compress.v4i64(<4 x i64> %data, <4 x i64> %passthru, <4 x i1> %extract)996 ret <4 x i64> %2997}998 999define <4 x i64> @test_maskz_compress_q_256(<4 x i64> %data, i8 %mask) #0 {1000;1001; CHECK-LABEL: define <4 x i64> @test_maskz_compress_q_256(1002; CHECK-SAME: <4 x i64> [[DATA:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {1003; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81004; CHECK-NEXT: [[TMP7:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 81005; CHECK-NEXT: call void @llvm.donothing()1006; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>1007; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8 [[MASK]] to <8 x i1>1008; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP3]], <8 x i1> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>1009; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> [[TMP1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>1010; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i64> [[TMP7]] to i2561011; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP5]], 01012; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i1> [[_MSPROP]] to i41013; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i4 [[TMP6]], 01014; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1015; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]1016; CHECK: [[BB7]]:1017; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]1018; CHECK-NEXT: unreachable1019; CHECK: [[BB8]]:1020; CHECK-NEXT: [[TMP2:%.*]] = call <4 x i64> @llvm.x86.avx512.mask.compress.v4i64(<4 x i64> [[DATA]], <4 x i64> zeroinitializer, <4 x i1> [[EXTRACT]])1021; CHECK-NEXT: store <4 x i64> zeroinitializer, ptr @__msan_retval_tls, align 81022; CHECK-NEXT: ret <4 x i64> [[TMP2]]1023;1024 %1 = bitcast i8 %mask to <8 x i1>1025 %extract = shufflevector <8 x i1> %1, <8 x i1> %1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>1026 %2 = call <4 x i64> @llvm.x86.avx512.mask.compress.v4i64(<4 x i64> %data, <4 x i64> zeroinitializer, <4 x i1> %extract)1027 ret <4 x i64> %21028}1029 1030define <4 x i64> @test_compress_q_256(<4 x i64> %data, <4 x i64> %data2) #0 {1031; CHECK-LABEL: define <4 x i64> @test_compress_q_256(1032; CHECK-SAME: <4 x i64> [[DATA:%.*]], <4 x i64> [[DATA2:%.*]]) #[[ATTR0]] {1033; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 81034; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81035; CHECK-NEXT: call void @llvm.donothing()1036; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i64> [[TMP5]] to i2561037; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP3]], 01038; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i64> [[TMP2]] to i2561039; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP4]], 01040; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1041; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]1042; CHECK: [[BB5]]:1043; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]1044; CHECK-NEXT: unreachable1045; CHECK: [[BB6]]:1046; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i64> @llvm.x86.avx512.mask.compress.v4i64(<4 x i64> [[DATA]], <4 x i64> [[DATA2]], <4 x i1> splat (i1 true))1047; CHECK-NEXT: store <4 x i64> zeroinitializer, ptr @__msan_retval_tls, align 81048; CHECK-NEXT: ret <4 x i64> [[TMP1]]1049;1050 %1 = call <4 x i64> @llvm.x86.avx512.mask.compress.v4i64(<4 x i64> %data, <4 x i64> %data2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)1051 ret <4 x i64> %11052}1053 1054define <8 x i32> @test_mask_compress_d_256(<8 x i32> %data, <8 x i32> %passthru, i8 %mask) #0 {1055;1056; CHECK-LABEL: define <8 x i32> @test_mask_compress_d_256(1057; CHECK-SAME: <8 x i32> [[DATA:%.*]], <8 x i32> [[PASSTHRU:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {1058; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 81059; CHECK-NEXT: [[TMP9:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 81060; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81061; CHECK-NEXT: call void @llvm.donothing()1062; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8 [[TMP5]] to <8 x i1>1063; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8 [[MASK]] to <8 x i1>1064; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i32> [[TMP9]] to i2561065; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP6]], 01066; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i32> [[TMP3]] to i2561067; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP7]], 01068; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1069; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i1> [[TMP4]] to i81070; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP8]], 01071; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]1072; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]1073; CHECK: [[BB9]]:1074; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]1075; CHECK-NEXT: unreachable1076; CHECK: [[BB10]]:1077; CHECK-NEXT: [[TMP2:%.*]] = call <8 x i32> @llvm.x86.avx512.mask.compress.v8i32(<8 x i32> [[DATA]], <8 x i32> [[PASSTHRU]], <8 x i1> [[TMP1]])1078; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81079; CHECK-NEXT: ret <8 x i32> [[TMP2]]1080;1081 %1 = bitcast i8 %mask to <8 x i1>1082 %2 = call <8 x i32> @llvm.x86.avx512.mask.compress.v8i32(<8 x i32> %data, <8 x i32> %passthru, <8 x i1> %1)1083 ret <8 x i32> %21084}1085 1086define <8 x i32> @test_maskz_compress_d_256(<8 x i32> %data, i8 %mask) #0 {1087;1088; CHECK-LABEL: define <8 x i32> @test_maskz_compress_d_256(1089; CHECK-SAME: <8 x i32> [[DATA:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {1090; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81091; CHECK-NEXT: [[TMP7:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 81092; CHECK-NEXT: call void @llvm.donothing()1093; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>1094; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8 [[MASK]] to <8 x i1>1095; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i32> [[TMP7]] to i2561096; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP5]], 01097; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i1> [[TMP3]] to i81098; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i8 [[TMP6]], 01099; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1100; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]1101; CHECK: [[BB7]]:1102; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]1103; CHECK-NEXT: unreachable1104; CHECK: [[BB8]]:1105; CHECK-NEXT: [[TMP2:%.*]] = call <8 x i32> @llvm.x86.avx512.mask.compress.v8i32(<8 x i32> [[DATA]], <8 x i32> zeroinitializer, <8 x i1> [[TMP1]])1106; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81107; CHECK-NEXT: ret <8 x i32> [[TMP2]]1108;1109 %1 = bitcast i8 %mask to <8 x i1>1110 %2 = call <8 x i32> @llvm.x86.avx512.mask.compress.v8i32(<8 x i32> %data, <8 x i32> zeroinitializer, <8 x i1> %1)1111 ret <8 x i32> %21112}1113 1114define <8 x i32> @test_compress_d_256(<8 x i32> %data, <8 x i32> %data2) #0 {1115; CHECK-LABEL: define <8 x i32> @test_compress_d_256(1116; CHECK-SAME: <8 x i32> [[DATA:%.*]], <8 x i32> [[DATA2:%.*]]) #[[ATTR0]] {1117; CHECK-NEXT: [[TMP5:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 81118; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81119; CHECK-NEXT: call void @llvm.donothing()1120; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i32> [[TMP5]] to i2561121; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP3]], 01122; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i32> [[TMP2]] to i2561123; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP4]], 01124; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1125; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]1126; CHECK: [[BB5]]:1127; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]1128; CHECK-NEXT: unreachable1129; CHECK: [[BB6]]:1130; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i32> @llvm.x86.avx512.mask.compress.v8i32(<8 x i32> [[DATA]], <8 x i32> [[DATA2]], <8 x i1> splat (i1 true))1131; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81132; CHECK-NEXT: ret <8 x i32> [[TMP1]]1133;1134 %1 = call <8 x i32> @llvm.x86.avx512.mask.compress.v8i32(<8 x i32> %data, <8 x i32> %data2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)1135 ret <8 x i32> %11136}1137 1138define <4 x double> @test_expand_pd_256(<4 x double> %data, <4 x double> %data2) #0 {1139; CHECK-LABEL: define <4 x double> @test_expand_pd_256(1140; CHECK-SAME: <4 x double> [[DATA:%.*]], <4 x double> [[DATA2:%.*]]) #[[ATTR0]] {1141; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 81142; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81143; CHECK-NEXT: call void @llvm.donothing()1144; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i64> [[TMP5]] to i2561145; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP3]], 01146; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i64> [[TMP2]] to i2561147; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP4]], 01148; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1149; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]1150; CHECK: [[BB5]]:1151; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]1152; CHECK-NEXT: unreachable1153; CHECK: [[BB6]]:1154; CHECK-NEXT: [[TMP1:%.*]] = call <4 x double> @llvm.x86.avx512.mask.expand.v4f64(<4 x double> [[DATA]], <4 x double> [[DATA2]], <4 x i1> splat (i1 true))1155; CHECK-NEXT: store <4 x i64> zeroinitializer, ptr @__msan_retval_tls, align 81156; CHECK-NEXT: ret <4 x double> [[TMP1]]1157;1158 %1 = call <4 x double> @llvm.x86.avx512.mask.expand.v4f64(<4 x double> %data, <4 x double> %data2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)1159 ret <4 x double> %11160}1161 1162define <4 x double> @test_mask_expand_pd_256(<4 x double> %data, <4 x double> %passthru, i8 %mask) #0 {1163;1164; CHECK-LABEL: define <4 x double> @test_mask_expand_pd_256(1165; CHECK-SAME: <4 x double> [[DATA:%.*]], <4 x double> [[PASSTHRU:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {1166; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 81167; CHECK-NEXT: [[TMP9:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 81168; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81169; CHECK-NEXT: call void @llvm.donothing()1170; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8 [[TMP5]] to <8 x i1>1171; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8 [[MASK]] to <8 x i1>1172; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP4]], <8 x i1> [[TMP4]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>1173; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> [[TMP1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>1174; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i64> [[TMP9]] to i2561175; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP6]], 01176; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i64> [[TMP3]] to i2561177; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP7]], 01178; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1179; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x i1> [[_MSPROP]] to i41180; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i4 [[TMP8]], 01181; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]1182; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]1183; CHECK: [[BB9]]:1184; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]1185; CHECK-NEXT: unreachable1186; CHECK: [[BB10]]:1187; CHECK-NEXT: [[TMP2:%.*]] = call <4 x double> @llvm.x86.avx512.mask.expand.v4f64(<4 x double> [[DATA]], <4 x double> [[PASSTHRU]], <4 x i1> [[EXTRACT]])1188; CHECK-NEXT: store <4 x i64> zeroinitializer, ptr @__msan_retval_tls, align 81189; CHECK-NEXT: ret <4 x double> [[TMP2]]1190;1191 %1 = bitcast i8 %mask to <8 x i1>1192 %extract = shufflevector <8 x i1> %1, <8 x i1> %1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>1193 %2 = call <4 x double> @llvm.x86.avx512.mask.expand.v4f64(<4 x double> %data, <4 x double> %passthru, <4 x i1> %extract)1194 ret <4 x double> %21195}1196 1197define <4 x double> @test_maskz_expand_pd_256(<4 x double> %data, i8 %mask) #0 {1198;1199; CHECK-LABEL: define <4 x double> @test_maskz_expand_pd_256(1200; CHECK-SAME: <4 x double> [[DATA:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {1201; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81202; CHECK-NEXT: [[TMP7:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 81203; CHECK-NEXT: call void @llvm.donothing()1204; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>1205; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8 [[MASK]] to <8 x i1>1206; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP3]], <8 x i1> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>1207; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> [[TMP1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>1208; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i64> [[TMP7]] to i2561209; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP5]], 01210; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i1> [[_MSPROP]] to i41211; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i4 [[TMP6]], 01212; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1213; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]1214; CHECK: [[BB7]]:1215; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]1216; CHECK-NEXT: unreachable1217; CHECK: [[BB8]]:1218; CHECK-NEXT: [[TMP2:%.*]] = call <4 x double> @llvm.x86.avx512.mask.expand.v4f64(<4 x double> [[DATA]], <4 x double> zeroinitializer, <4 x i1> [[EXTRACT]])1219; CHECK-NEXT: store <4 x i64> zeroinitializer, ptr @__msan_retval_tls, align 81220; CHECK-NEXT: ret <4 x double> [[TMP2]]1221;1222 %1 = bitcast i8 %mask to <8 x i1>1223 %extract = shufflevector <8 x i1> %1, <8 x i1> %1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>1224 %2 = call <4 x double> @llvm.x86.avx512.mask.expand.v4f64(<4 x double> %data, <4 x double> zeroinitializer, <4 x i1> %extract)1225 ret <4 x double> %21226}1227 1228define <8 x float> @test_expand_ps_256(<8 x float> %data, <8 x float> %data2) #0 {1229; CHECK-LABEL: define <8 x float> @test_expand_ps_256(1230; CHECK-SAME: <8 x float> [[DATA:%.*]], <8 x float> [[DATA2:%.*]]) #[[ATTR0]] {1231; CHECK-NEXT: [[TMP5:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 81232; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81233; CHECK-NEXT: call void @llvm.donothing()1234; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i32> [[TMP5]] to i2561235; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP3]], 01236; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i32> [[TMP2]] to i2561237; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP4]], 01238; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1239; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]1240; CHECK: [[BB5]]:1241; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]1242; CHECK-NEXT: unreachable1243; CHECK: [[BB6]]:1244; CHECK-NEXT: [[TMP1:%.*]] = call <8 x float> @llvm.x86.avx512.mask.expand.v8f32(<8 x float> [[DATA]], <8 x float> [[DATA2]], <8 x i1> splat (i1 true))1245; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81246; CHECK-NEXT: ret <8 x float> [[TMP1]]1247;1248 %1 = call <8 x float> @llvm.x86.avx512.mask.expand.v8f32(<8 x float> %data, <8 x float> %data2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)1249 ret <8 x float> %11250}1251 1252define <8 x float> @test_mask_expand_ps_256(<8 x float> %data, <8 x float> %passthru, i8 %mask) #0 {1253;1254; CHECK-LABEL: define <8 x float> @test_mask_expand_ps_256(1255; CHECK-SAME: <8 x float> [[DATA:%.*]], <8 x float> [[PASSTHRU:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {1256; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 81257; CHECK-NEXT: [[TMP9:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 81258; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81259; CHECK-NEXT: call void @llvm.donothing()1260; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8 [[TMP5]] to <8 x i1>1261; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8 [[MASK]] to <8 x i1>1262; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i32> [[TMP9]] to i2561263; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP6]], 01264; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i32> [[TMP3]] to i2561265; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP7]], 01266; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1267; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i1> [[TMP4]] to i81268; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP8]], 01269; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]1270; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]1271; CHECK: [[BB9]]:1272; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]1273; CHECK-NEXT: unreachable1274; CHECK: [[BB10]]:1275; CHECK-NEXT: [[TMP2:%.*]] = call <8 x float> @llvm.x86.avx512.mask.expand.v8f32(<8 x float> [[DATA]], <8 x float> [[PASSTHRU]], <8 x i1> [[TMP1]])1276; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81277; CHECK-NEXT: ret <8 x float> [[TMP2]]1278;1279 %1 = bitcast i8 %mask to <8 x i1>1280 %2 = call <8 x float> @llvm.x86.avx512.mask.expand.v8f32(<8 x float> %data, <8 x float> %passthru, <8 x i1> %1)1281 ret <8 x float> %21282}1283 1284define <8 x float> @test_maskz_expand_ps_256(<8 x float> %data, i8 %mask) #0 {1285;1286; CHECK-LABEL: define <8 x float> @test_maskz_expand_ps_256(1287; CHECK-SAME: <8 x float> [[DATA:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {1288; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81289; CHECK-NEXT: [[TMP7:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 81290; CHECK-NEXT: call void @llvm.donothing()1291; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>1292; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8 [[MASK]] to <8 x i1>1293; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i32> [[TMP7]] to i2561294; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP5]], 01295; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i1> [[TMP3]] to i81296; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i8 [[TMP6]], 01297; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1298; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]1299; CHECK: [[BB7]]:1300; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]1301; CHECK-NEXT: unreachable1302; CHECK: [[BB8]]:1303; CHECK-NEXT: [[TMP2:%.*]] = call <8 x float> @llvm.x86.avx512.mask.expand.v8f32(<8 x float> [[DATA]], <8 x float> zeroinitializer, <8 x i1> [[TMP1]])1304; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81305; CHECK-NEXT: ret <8 x float> [[TMP2]]1306;1307 %1 = bitcast i8 %mask to <8 x i1>1308 %2 = call <8 x float> @llvm.x86.avx512.mask.expand.v8f32(<8 x float> %data, <8 x float> zeroinitializer, <8 x i1> %1)1309 ret <8 x float> %21310}1311 1312define <4 x i64> @test_expand_q_256(<4 x i64> %data, <4 x i64> %data2) #0 {1313; CHECK-LABEL: define <4 x i64> @test_expand_q_256(1314; CHECK-SAME: <4 x i64> [[DATA:%.*]], <4 x i64> [[DATA2:%.*]]) #[[ATTR0]] {1315; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 81316; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81317; CHECK-NEXT: call void @llvm.donothing()1318; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i64> [[TMP5]] to i2561319; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP3]], 01320; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i64> [[TMP2]] to i2561321; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP4]], 01322; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1323; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]1324; CHECK: [[BB5]]:1325; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]1326; CHECK-NEXT: unreachable1327; CHECK: [[BB6]]:1328; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i64> @llvm.x86.avx512.mask.expand.v4i64(<4 x i64> [[DATA]], <4 x i64> [[DATA2]], <4 x i1> splat (i1 true))1329; CHECK-NEXT: store <4 x i64> zeroinitializer, ptr @__msan_retval_tls, align 81330; CHECK-NEXT: ret <4 x i64> [[TMP1]]1331;1332 %1 = call <4 x i64> @llvm.x86.avx512.mask.expand.v4i64(<4 x i64> %data, <4 x i64> %data2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)1333 ret <4 x i64> %11334}1335 1336define <4 x i64> @test_mask_expand_q_256(<4 x i64> %data, <4 x i64> %passthru, i8 %mask) #0 {1337;1338; CHECK-LABEL: define <4 x i64> @test_mask_expand_q_256(1339; CHECK-SAME: <4 x i64> [[DATA:%.*]], <4 x i64> [[PASSTHRU:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {1340; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 81341; CHECK-NEXT: [[TMP9:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 81342; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81343; CHECK-NEXT: call void @llvm.donothing()1344; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8 [[TMP5]] to <8 x i1>1345; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8 [[MASK]] to <8 x i1>1346; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP4]], <8 x i1> [[TMP4]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>1347; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> [[TMP1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>1348; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i64> [[TMP9]] to i2561349; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP6]], 01350; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i64> [[TMP3]] to i2561351; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP7]], 01352; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1353; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x i1> [[_MSPROP]] to i41354; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i4 [[TMP8]], 01355; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]1356; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]1357; CHECK: [[BB9]]:1358; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]1359; CHECK-NEXT: unreachable1360; CHECK: [[BB10]]:1361; CHECK-NEXT: [[TMP2:%.*]] = call <4 x i64> @llvm.x86.avx512.mask.expand.v4i64(<4 x i64> [[DATA]], <4 x i64> [[PASSTHRU]], <4 x i1> [[EXTRACT]])1362; CHECK-NEXT: store <4 x i64> zeroinitializer, ptr @__msan_retval_tls, align 81363; CHECK-NEXT: ret <4 x i64> [[TMP2]]1364;1365 %1 = bitcast i8 %mask to <8 x i1>1366 %extract = shufflevector <8 x i1> %1, <8 x i1> %1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>1367 %2 = call <4 x i64> @llvm.x86.avx512.mask.expand.v4i64(<4 x i64> %data, <4 x i64> %passthru, <4 x i1> %extract)1368 ret <4 x i64> %21369}1370 1371define <4 x i64> @test_maskz_expand_q_256(<4 x i64> %data, i8 %mask) #0 {1372;1373; CHECK-LABEL: define <4 x i64> @test_maskz_expand_q_256(1374; CHECK-SAME: <4 x i64> [[DATA:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {1375; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81376; CHECK-NEXT: [[TMP7:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 81377; CHECK-NEXT: call void @llvm.donothing()1378; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>1379; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8 [[MASK]] to <8 x i1>1380; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP3]], <8 x i1> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>1381; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> [[TMP1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>1382; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i64> [[TMP7]] to i2561383; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP5]], 01384; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i1> [[_MSPROP]] to i41385; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i4 [[TMP6]], 01386; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1387; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]1388; CHECK: [[BB7]]:1389; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]1390; CHECK-NEXT: unreachable1391; CHECK: [[BB8]]:1392; CHECK-NEXT: [[TMP2:%.*]] = call <4 x i64> @llvm.x86.avx512.mask.expand.v4i64(<4 x i64> [[DATA]], <4 x i64> zeroinitializer, <4 x i1> [[EXTRACT]])1393; CHECK-NEXT: store <4 x i64> zeroinitializer, ptr @__msan_retval_tls, align 81394; CHECK-NEXT: ret <4 x i64> [[TMP2]]1395;1396 %1 = bitcast i8 %mask to <8 x i1>1397 %extract = shufflevector <8 x i1> %1, <8 x i1> %1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>1398 %2 = call <4 x i64> @llvm.x86.avx512.mask.expand.v4i64(<4 x i64> %data, <4 x i64> zeroinitializer, <4 x i1> %extract)1399 ret <4 x i64> %21400}1401 1402define <8 x i32> @test_expand_d_256(<8 x i32> %data, <8 x i32> %data2) #0 {1403; CHECK-LABEL: define <8 x i32> @test_expand_d_256(1404; CHECK-SAME: <8 x i32> [[DATA:%.*]], <8 x i32> [[DATA2:%.*]]) #[[ATTR0]] {1405; CHECK-NEXT: [[TMP5:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 81406; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81407; CHECK-NEXT: call void @llvm.donothing()1408; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i32> [[TMP5]] to i2561409; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP3]], 01410; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i32> [[TMP2]] to i2561411; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP4]], 01412; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1413; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]1414; CHECK: [[BB5]]:1415; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]1416; CHECK-NEXT: unreachable1417; CHECK: [[BB6]]:1418; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i32> @llvm.x86.avx512.mask.expand.v8i32(<8 x i32> [[DATA]], <8 x i32> [[DATA2]], <8 x i1> splat (i1 true))1419; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81420; CHECK-NEXT: ret <8 x i32> [[TMP1]]1421;1422 %1 = call <8 x i32> @llvm.x86.avx512.mask.expand.v8i32(<8 x i32> %data, <8 x i32> %data2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)1423 ret <8 x i32> %11424}1425 1426define <8 x i32> @test_mask_expand_d_256(<8 x i32> %data, <8 x i32> %passthru, i8 %mask) #0 {1427;1428; CHECK-LABEL: define <8 x i32> @test_mask_expand_d_256(1429; CHECK-SAME: <8 x i32> [[DATA:%.*]], <8 x i32> [[PASSTHRU:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {1430; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 81431; CHECK-NEXT: [[TMP9:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 81432; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81433; CHECK-NEXT: call void @llvm.donothing()1434; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8 [[TMP5]] to <8 x i1>1435; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8 [[MASK]] to <8 x i1>1436; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i32> [[TMP9]] to i2561437; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP6]], 01438; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i32> [[TMP3]] to i2561439; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP7]], 01440; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1441; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i1> [[TMP4]] to i81442; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP8]], 01443; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]1444; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]1445; CHECK: [[BB9]]:1446; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]1447; CHECK-NEXT: unreachable1448; CHECK: [[BB10]]:1449; CHECK-NEXT: [[TMP2:%.*]] = call <8 x i32> @llvm.x86.avx512.mask.expand.v8i32(<8 x i32> [[DATA]], <8 x i32> [[PASSTHRU]], <8 x i1> [[TMP1]])1450; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81451; CHECK-NEXT: ret <8 x i32> [[TMP2]]1452;1453 %1 = bitcast i8 %mask to <8 x i1>1454 %2 = call <8 x i32> @llvm.x86.avx512.mask.expand.v8i32(<8 x i32> %data, <8 x i32> %passthru, <8 x i1> %1)1455 ret <8 x i32> %21456}1457 1458define <8 x i32> @test_maskz_expand_d_256(<8 x i32> %data, i8 %mask) #0 {1459;1460; CHECK-LABEL: define <8 x i32> @test_maskz_expand_d_256(1461; CHECK-SAME: <8 x i32> [[DATA:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {1462; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81463; CHECK-NEXT: [[TMP7:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 81464; CHECK-NEXT: call void @llvm.donothing()1465; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>1466; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8 [[MASK]] to <8 x i1>1467; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i32> [[TMP7]] to i2561468; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP5]], 01469; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i1> [[TMP3]] to i81470; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i8 [[TMP6]], 01471; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1472; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]1473; CHECK: [[BB7]]:1474; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]1475; CHECK-NEXT: unreachable1476; CHECK: [[BB8]]:1477; CHECK-NEXT: [[TMP2:%.*]] = call <8 x i32> @llvm.x86.avx512.mask.expand.v8i32(<8 x i32> [[DATA]], <8 x i32> zeroinitializer, <8 x i1> [[TMP1]])1478; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81479; CHECK-NEXT: ret <8 x i32> [[TMP2]]1480;1481 %1 = bitcast i8 %mask to <8 x i1>1482 %2 = call <8 x i32> @llvm.x86.avx512.mask.expand.v8i32(<8 x i32> %data, <8 x i32> zeroinitializer, <8 x i1> %1)1483 ret <8 x i32> %21484}1485 1486define i8 @test_cmpps_256(<8 x float> %a, <8 x float> %b) #0 {1487; CHECK-LABEL: define i8 @test_cmpps_256(1488; CHECK-SAME: <8 x float> [[A:%.*]], <8 x float> [[B:%.*]]) #[[ATTR0]] {1489; CHECK-NEXT: [[TMP5:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 81490; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81491; CHECK-NEXT: call void @llvm.donothing()1492; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i32> [[TMP5]] to i2561493; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP3]], 01494; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i32> [[TMP2]] to i2561495; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP4]], 01496; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1497; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]1498; CHECK: [[BB5]]:1499; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]1500; CHECK-NEXT: unreachable1501; CHECK: [[BB6]]:1502; CHECK-NEXT: [[RES:%.*]] = call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> [[A]], <8 x float> [[B]], i32 2, <8 x i1> splat (i1 true))1503; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[RES]] to i81504; CHECK-NEXT: store i8 0, ptr @__msan_retval_tls, align 81505; CHECK-NEXT: ret i8 [[TMP1]]1506;1507 %res = call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %a, <8 x float> %b, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)1508 %1 = bitcast <8 x i1> %res to i81509 ret i8 %11510}1511declare <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float>, <8 x float>, i32, <8 x i1>)1512 1513define i8 @test_cmpps_128(<4 x float> %a, <4 x float> %b) #0 {1514; CHECK-LABEL: define i8 @test_cmpps_128(1515; CHECK-SAME: <4 x float> [[A:%.*]], <4 x float> [[B:%.*]]) #[[ATTR0]] {1516; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 81517; CHECK-NEXT: [[TMP6:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81518; CHECK-NEXT: call void @llvm.donothing()1519; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP5]] to i1281520; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 01521; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP6]] to i1281522; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 01523; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1524; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]1525; CHECK: [[BB5]]:1526; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]1527; CHECK-NEXT: unreachable1528; CHECK: [[BB6]]:1529; CHECK-NEXT: [[RES:%.*]] = call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> [[A]], <4 x float> [[B]], i32 2, <4 x i1> splat (i1 true))1530; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i1> [[RES]], <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>1531; CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i1> [[TMP1]] to i81532; CHECK-NEXT: store i8 0, ptr @__msan_retval_tls, align 81533; CHECK-NEXT: ret i8 [[TMP2]]1534;1535 %res = call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %a, <4 x float> %b, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)1536 %1 = shufflevector <4 x i1> %res, <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>1537 %2 = bitcast <8 x i1> %1 to i81538 ret i8 %21539}1540declare <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float>, <4 x float>, i32, <4 x i1>)1541 1542define i8 @test_cmppd_256(<4 x double> %a, <4 x double> %b) #0 {1543; CHECK-LABEL: define i8 @test_cmppd_256(1544; CHECK-SAME: <4 x double> [[A:%.*]], <4 x double> [[B:%.*]]) #[[ATTR0]] {1545; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 81546; CHECK-NEXT: [[TMP6:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81547; CHECK-NEXT: call void @llvm.donothing()1548; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i64> [[TMP5]] to i2561549; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP3]], 01550; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i64> [[TMP6]] to i2561551; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP4]], 01552; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1553; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]1554; CHECK: [[BB5]]:1555; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]1556; CHECK-NEXT: unreachable1557; CHECK: [[BB6]]:1558; CHECK-NEXT: [[RES:%.*]] = call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> [[A]], <4 x double> [[B]], i32 2, <4 x i1> splat (i1 true))1559; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i1> [[RES]], <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>1560; CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i1> [[TMP1]] to i81561; CHECK-NEXT: store i8 0, ptr @__msan_retval_tls, align 81562; CHECK-NEXT: ret i8 [[TMP2]]1563;1564 %res = call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %a, <4 x double> %b, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)1565 %1 = shufflevector <4 x i1> %res, <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>1566 %2 = bitcast <8 x i1> %1 to i81567 ret i8 %21568}1569declare <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double>, <4 x double>, i32, <4 x i1>)1570 1571define i8 @test_cmppd_128(<2 x double> %a, <2 x double> %b) #0 {1572; CHECK-LABEL: define i8 @test_cmppd_128(1573; CHECK-SAME: <2 x double> [[A:%.*]], <2 x double> [[B:%.*]]) #[[ATTR0]] {1574; CHECK-NEXT: [[TMP5:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 81575; CHECK-NEXT: [[TMP6:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81576; CHECK-NEXT: call void @llvm.donothing()1577; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP5]] to i1281578; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 01579; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP6]] to i1281580; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 01581; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]1582; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]1583; CHECK: [[BB5]]:1584; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]1585; CHECK-NEXT: unreachable1586; CHECK: [[BB6]]:1587; CHECK-NEXT: [[RES:%.*]] = call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> [[A]], <2 x double> [[B]], i32 2, <2 x i1> splat (i1 true))1588; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x i1> [[RES]], <2 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>1589; CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i1> [[TMP1]] to i81590; CHECK-NEXT: store i8 0, ptr @__msan_retval_tls, align 81591; CHECK-NEXT: ret i8 [[TMP2]]1592;1593 %res = call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %a, <2 x double> %b, i32 2, <2 x i1> <i1 true, i1 true>)1594 %1 = shufflevector <2 x i1> %res, <2 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>1595 %2 = bitcast <8 x i1> %1 to i81596 ret i8 %21597}1598declare <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double>, <2 x double>, i32, <2 x i1>)1599 1600define <8 x float> @test_mm512_maskz_max_ps_256(<8 x float> %a0, <8 x float> %a1, i8 %mask) #0 {1601;1602; CHECK-LABEL: define <8 x float> @test_mm512_maskz_max_ps_256(1603; CHECK-SAME: <8 x float> [[A0:%.*]], <8 x float> [[A1:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {1604; CHECK-NEXT: [[TMP9:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 81605; CHECK-NEXT: [[TMP10:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81606; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 81607; CHECK-NEXT: call void @llvm.donothing()1608; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> [[TMP9]], [[TMP10]]1609; CHECK-NEXT: [[TMP1:%.*]] = call <8 x float> @llvm.x86.avx.max.ps.256(<8 x float> [[A0]], <8 x float> [[A1]])1610; CHECK-NEXT: [[TMP11:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>1611; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[MASK]] to <8 x i1>1612; CHECK-NEXT: [[TMP12:%.*]] = select <8 x i1> [[TMP2]], <8 x i32> [[_MSPROP]], <8 x i32> zeroinitializer1613; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x float> [[TMP1]] to <8 x i32>1614; CHECK-NEXT: [[TMP5:%.*]] = xor <8 x i32> [[TMP4]], zeroinitializer1615; CHECK-NEXT: [[TMP6:%.*]] = or <8 x i32> [[TMP5]], [[_MSPROP]]1616; CHECK-NEXT: [[TMP7:%.*]] = or <8 x i32> [[TMP6]], zeroinitializer1617; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP11]], <8 x i32> [[TMP7]], <8 x i32> [[TMP12]]1618; CHECK-NEXT: [[TMP8:%.*]] = select <8 x i1> [[TMP2]], <8 x float> [[TMP1]], <8 x float> zeroinitializer1619; CHECK-NEXT: store <8 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 81620; CHECK-NEXT: ret <8 x float> [[TMP8]]1621;1622 %1 = call <8 x float> @llvm.x86.avx.max.ps.256(<8 x float> %a0, <8 x float> %a1)1623 %2 = bitcast i8 %mask to <8 x i1>1624 %3 = select <8 x i1> %2, <8 x float> %1, <8 x float> zeroinitializer1625 ret <8 x float> %31626}1627 1628define <8 x float> @test_mm512_mask_max_ps_256(<8 x float> %a0, <8 x float> %a1, <8 x float> %src, i8 %mask) #0 {1629;1630; CHECK-LABEL: define <8 x float> @test_mm512_mask_max_ps_256(1631; CHECK-SAME: <8 x float> [[A0:%.*]], <8 x float> [[A1:%.*]], <8 x float> [[SRC:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {1632; CHECK-NEXT: [[TMP7:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 81633; CHECK-NEXT: [[TMP10:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81634; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 81635; CHECK-NEXT: [[TMP11:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 81636; CHECK-NEXT: call void @llvm.donothing()1637; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> [[TMP7]], [[TMP10]]1638; CHECK-NEXT: [[TMP1:%.*]] = call <8 x float> @llvm.x86.avx.max.ps.256(<8 x float> [[A0]], <8 x float> [[A1]])1639; CHECK-NEXT: [[TMP14:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>1640; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[MASK]] to <8 x i1>1641; CHECK-NEXT: [[TMP8:%.*]] = select <8 x i1> [[TMP2]], <8 x i32> [[_MSPROP]], <8 x i32> [[TMP11]]1642; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x float> [[TMP1]] to <8 x i32>1643; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x float> [[SRC]] to <8 x i32>1644; CHECK-NEXT: [[TMP6:%.*]] = xor <8 x i32> [[TMP4]], [[TMP5]]1645; CHECK-NEXT: [[TMP12:%.*]] = or <8 x i32> [[TMP6]], [[_MSPROP]]1646; CHECK-NEXT: [[TMP13:%.*]] = or <8 x i32> [[TMP12]], [[TMP11]]1647; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP14]], <8 x i32> [[TMP13]], <8 x i32> [[TMP8]]1648; CHECK-NEXT: [[TMP9:%.*]] = select <8 x i1> [[TMP2]], <8 x float> [[TMP1]], <8 x float> [[SRC]]1649; CHECK-NEXT: store <8 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 81650; CHECK-NEXT: ret <8 x float> [[TMP9]]1651;1652 %1 = call <8 x float> @llvm.x86.avx.max.ps.256(<8 x float> %a0, <8 x float> %a1)1653 %2 = bitcast i8 %mask to <8 x i1>1654 %3 = select <8 x i1> %2, <8 x float> %1, <8 x float> %src1655 ret <8 x float> %31656}1657 1658define <8 x float> @test_mm512_max_ps_256(<8 x float> %a0, <8 x float> %a1, i8 %mask) #0 {1659; CHECK-LABEL: define <8 x float> @test_mm512_max_ps_256(1660; CHECK-SAME: <8 x float> [[A0:%.*]], <8 x float> [[A1:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {1661; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 81662; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81663; CHECK-NEXT: call void @llvm.donothing()1664; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> [[TMP3]], [[TMP2]]1665; CHECK-NEXT: [[TMP1:%.*]] = call <8 x float> @llvm.x86.avx.max.ps.256(<8 x float> [[A0]], <8 x float> [[A1]])1666; CHECK-NEXT: store <8 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 81667; CHECK-NEXT: ret <8 x float> [[TMP1]]1668;1669 %1 = call <8 x float> @llvm.x86.avx.max.ps.256(<8 x float> %a0, <8 x float> %a1)1670 ret <8 x float> %11671}1672declare <8 x float> @llvm.x86.avx.max.ps.256(<8 x float>, <8 x float>)1673 1674define <4 x float> @test_mm512_maskz_max_ps_128(<4 x float> %a0, <4 x float> %a1, i8 %mask) #0 {1675;1676; CHECK-LABEL: define <4 x float> @test_mm512_maskz_max_ps_128(1677; CHECK-SAME: <4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {1678; CHECK-NEXT: [[TMP9:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 81679; CHECK-NEXT: [[TMP10:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81680; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81681; CHECK-NEXT: call void @llvm.donothing()1682; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP9]], [[TMP10]]1683; CHECK-NEXT: [[TMP1:%.*]] = call <4 x float> @llvm.x86.sse.max.ps(<4 x float> [[A0]], <4 x float> [[A1]])1684; CHECK-NEXT: [[TMP11:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>1685; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[MASK]] to <8 x i1>1686; CHECK-NEXT: [[_MSPROP1:%.*]] = shufflevector <8 x i1> [[TMP11]], <8 x i1> splat (i1 true), <4 x i32> <i32 0, i32 1, i32 2, i32 3>1687; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>1688; CHECK-NEXT: [[TMP12:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i32> [[_MSPROP]], <4 x i32> zeroinitializer1689; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x float> [[TMP1]] to <4 x i32>1690; CHECK-NEXT: [[TMP5:%.*]] = xor <4 x i32> [[TMP4]], zeroinitializer1691; CHECK-NEXT: [[TMP6:%.*]] = or <4 x i32> [[TMP5]], [[_MSPROP]]1692; CHECK-NEXT: [[TMP7:%.*]] = or <4 x i32> [[TMP6]], zeroinitializer1693; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP1]], <4 x i32> [[TMP7]], <4 x i32> [[TMP12]]1694; CHECK-NEXT: [[TMP8:%.*]] = select <4 x i1> [[EXTRACT]], <4 x float> [[TMP1]], <4 x float> zeroinitializer1695; CHECK-NEXT: store <4 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 81696; CHECK-NEXT: ret <4 x float> [[TMP8]]1697;1698 %1 = call <4 x float> @llvm.x86.sse.max.ps(<4 x float> %a0, <4 x float> %a1)1699 %2 = bitcast i8 %mask to <8 x i1>1700 %extract = shufflevector <8 x i1> %2, <8 x i1> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>1701 %4 = select <4 x i1> %extract, <4 x float> %1, <4 x float> zeroinitializer1702 ret <4 x float> %41703}1704 1705define <4 x float> @test_mm512_mask_max_ps_128(<4 x float> %a0, <4 x float> %a1, <4 x float> %src, i8 %mask) #0 {1706;1707; CHECK-LABEL: define <4 x float> @test_mm512_mask_max_ps_128(1708; CHECK-SAME: <4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], <4 x float> [[SRC:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {1709; CHECK-NEXT: [[TMP7:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 81710; CHECK-NEXT: [[TMP10:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81711; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 81712; CHECK-NEXT: [[TMP11:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81713; CHECK-NEXT: call void @llvm.donothing()1714; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP7]], [[TMP10]]1715; CHECK-NEXT: [[TMP1:%.*]] = call <4 x float> @llvm.x86.sse.max.ps(<4 x float> [[A0]], <4 x float> [[A1]])1716; CHECK-NEXT: [[TMP14:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>1717; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[MASK]] to <8 x i1>1718; CHECK-NEXT: [[_MSPROP1:%.*]] = shufflevector <8 x i1> [[TMP14]], <8 x i1> splat (i1 true), <4 x i32> <i32 0, i32 1, i32 2, i32 3>1719; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>1720; CHECK-NEXT: [[TMP8:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i32> [[_MSPROP]], <4 x i32> [[TMP11]]1721; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x float> [[TMP1]] to <4 x i32>1722; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x float> [[SRC]] to <4 x i32>1723; CHECK-NEXT: [[TMP6:%.*]] = xor <4 x i32> [[TMP4]], [[TMP5]]1724; CHECK-NEXT: [[TMP12:%.*]] = or <4 x i32> [[TMP6]], [[_MSPROP]]1725; CHECK-NEXT: [[TMP13:%.*]] = or <4 x i32> [[TMP12]], [[TMP11]]1726; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP1]], <4 x i32> [[TMP13]], <4 x i32> [[TMP8]]1727; CHECK-NEXT: [[TMP9:%.*]] = select <4 x i1> [[EXTRACT]], <4 x float> [[TMP1]], <4 x float> [[SRC]]1728; CHECK-NEXT: store <4 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 81729; CHECK-NEXT: ret <4 x float> [[TMP9]]1730;1731 %1 = call <4 x float> @llvm.x86.sse.max.ps(<4 x float> %a0, <4 x float> %a1)1732 %2 = bitcast i8 %mask to <8 x i1>1733 %extract = shufflevector <8 x i1> %2, <8 x i1> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>1734 %4 = select <4 x i1> %extract, <4 x float> %1, <4 x float> %src1735 ret <4 x float> %41736}1737 1738define <4 x float> @test_mm512_max_ps_128(<4 x float> %a0, <4 x float> %a1, i8 %mask) #0 {1739; CHECK-LABEL: define <4 x float> @test_mm512_max_ps_128(1740; CHECK-SAME: <4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {1741; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 81742; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81743; CHECK-NEXT: call void @llvm.donothing()1744; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP3]], [[TMP2]]1745; CHECK-NEXT: [[TMP1:%.*]] = call <4 x float> @llvm.x86.sse.max.ps(<4 x float> [[A0]], <4 x float> [[A1]])1746; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 81747; CHECK-NEXT: ret <4 x float> [[TMP1]]1748;1749 %1 = call <4 x float> @llvm.x86.sse.max.ps(<4 x float> %a0, <4 x float> %a1)1750 ret <4 x float> %11751}1752declare <4 x float> @llvm.x86.sse.max.ps(<4 x float>, <4 x float>)1753 1754define <8 x float> @test_mm512_maskz_min_ps_256(<8 x float> %a0, <8 x float> %a1, i8 %mask) #0 {1755;1756; CHECK-LABEL: define <8 x float> @test_mm512_maskz_min_ps_256(1757; CHECK-SAME: <8 x float> [[A0:%.*]], <8 x float> [[A1:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {1758; CHECK-NEXT: [[TMP9:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 81759; CHECK-NEXT: [[TMP10:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81760; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 81761; CHECK-NEXT: call void @llvm.donothing()1762; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> [[TMP9]], [[TMP10]]1763; CHECK-NEXT: [[TMP1:%.*]] = call <8 x float> @llvm.x86.avx.min.ps.256(<8 x float> [[A0]], <8 x float> [[A1]])1764; CHECK-NEXT: [[TMP11:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>1765; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[MASK]] to <8 x i1>1766; CHECK-NEXT: [[TMP12:%.*]] = select <8 x i1> [[TMP2]], <8 x i32> [[_MSPROP]], <8 x i32> zeroinitializer1767; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x float> [[TMP1]] to <8 x i32>1768; CHECK-NEXT: [[TMP5:%.*]] = xor <8 x i32> [[TMP4]], zeroinitializer1769; CHECK-NEXT: [[TMP6:%.*]] = or <8 x i32> [[TMP5]], [[_MSPROP]]1770; CHECK-NEXT: [[TMP7:%.*]] = or <8 x i32> [[TMP6]], zeroinitializer1771; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP11]], <8 x i32> [[TMP7]], <8 x i32> [[TMP12]]1772; CHECK-NEXT: [[TMP8:%.*]] = select <8 x i1> [[TMP2]], <8 x float> [[TMP1]], <8 x float> zeroinitializer1773; CHECK-NEXT: store <8 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 81774; CHECK-NEXT: ret <8 x float> [[TMP8]]1775;1776 %1 = call <8 x float> @llvm.x86.avx.min.ps.256(<8 x float> %a0, <8 x float> %a1)1777 %2 = bitcast i8 %mask to <8 x i1>1778 %3 = select <8 x i1> %2, <8 x float> %1, <8 x float> zeroinitializer1779 ret <8 x float> %31780}1781 1782define <8 x float> @test_mm512_mask_min_ps_256(<8 x float> %a0, <8 x float> %a1, <8 x float> %src, i8 %mask) #0 {1783;1784; CHECK-LABEL: define <8 x float> @test_mm512_mask_min_ps_256(1785; CHECK-SAME: <8 x float> [[A0:%.*]], <8 x float> [[A1:%.*]], <8 x float> [[SRC:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {1786; CHECK-NEXT: [[TMP7:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 81787; CHECK-NEXT: [[TMP10:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81788; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 81789; CHECK-NEXT: [[TMP11:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 81790; CHECK-NEXT: call void @llvm.donothing()1791; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> [[TMP7]], [[TMP10]]1792; CHECK-NEXT: [[TMP1:%.*]] = call <8 x float> @llvm.x86.avx.min.ps.256(<8 x float> [[A0]], <8 x float> [[A1]])1793; CHECK-NEXT: [[TMP14:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>1794; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[MASK]] to <8 x i1>1795; CHECK-NEXT: [[TMP8:%.*]] = select <8 x i1> [[TMP2]], <8 x i32> [[_MSPROP]], <8 x i32> [[TMP11]]1796; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x float> [[TMP1]] to <8 x i32>1797; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x float> [[SRC]] to <8 x i32>1798; CHECK-NEXT: [[TMP6:%.*]] = xor <8 x i32> [[TMP4]], [[TMP5]]1799; CHECK-NEXT: [[TMP12:%.*]] = or <8 x i32> [[TMP6]], [[_MSPROP]]1800; CHECK-NEXT: [[TMP13:%.*]] = or <8 x i32> [[TMP12]], [[TMP11]]1801; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP14]], <8 x i32> [[TMP13]], <8 x i32> [[TMP8]]1802; CHECK-NEXT: [[TMP9:%.*]] = select <8 x i1> [[TMP2]], <8 x float> [[TMP1]], <8 x float> [[SRC]]1803; CHECK-NEXT: store <8 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 81804; CHECK-NEXT: ret <8 x float> [[TMP9]]1805;1806 %1 = call <8 x float> @llvm.x86.avx.min.ps.256(<8 x float> %a0, <8 x float> %a1)1807 %2 = bitcast i8 %mask to <8 x i1>1808 %3 = select <8 x i1> %2, <8 x float> %1, <8 x float> %src1809 ret <8 x float> %31810}1811 1812define <8 x float> @test_mm512_min_ps_256(<8 x float> %a0, <8 x float> %a1, i8 %mask) #0 {1813; CHECK-LABEL: define <8 x float> @test_mm512_min_ps_256(1814; CHECK-SAME: <8 x float> [[A0:%.*]], <8 x float> [[A1:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {1815; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 81816; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81817; CHECK-NEXT: call void @llvm.donothing()1818; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> [[TMP3]], [[TMP2]]1819; CHECK-NEXT: [[TMP1:%.*]] = call <8 x float> @llvm.x86.avx.min.ps.256(<8 x float> [[A0]], <8 x float> [[A1]])1820; CHECK-NEXT: store <8 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 81821; CHECK-NEXT: ret <8 x float> [[TMP1]]1822;1823 %1 = call <8 x float> @llvm.x86.avx.min.ps.256(<8 x float> %a0, <8 x float> %a1)1824 ret <8 x float> %11825}1826declare <8 x float> @llvm.x86.avx.min.ps.256(<8 x float>, <8 x float>)1827 1828define <4 x float> @test_mm512_maskz_min_ps_128(<4 x float> %a0, <4 x float> %a1, i8 %mask, i8 %mask2) #0 {1829;1830; CHECK-LABEL: define <4 x float> @test_mm512_maskz_min_ps_128(1831; CHECK-SAME: <4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], i8 [[MASK:%.*]], i8 [[MASK2:%.*]]) #[[ATTR0]] {1832; CHECK-NEXT: [[TMP11:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 81833; CHECK-NEXT: [[TMP12:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81834; CHECK-NEXT: [[TMP13:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81835; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 81836; CHECK-NEXT: call void @llvm.donothing()1837; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP11]], [[TMP12]]1838; CHECK-NEXT: [[TMP1:%.*]] = call <4 x float> @llvm.x86.sse.min.ps(<4 x float> [[A0]], <4 x float> [[A1]])1839; CHECK-NEXT: [[TMP14:%.*]] = bitcast i8 [[TMP13]] to <8 x i1>1840; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[MASK]] to <8 x i1>1841; CHECK-NEXT: [[TMP15:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>1842; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8 [[MASK2]] to <8 x i1>1843; CHECK-NEXT: [[_MSPROP1:%.*]] = shufflevector <8 x i1> [[TMP14]], <8 x i1> [[TMP15]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>1844; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>1845; CHECK-NEXT: [[TMP10:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i32> [[_MSPROP]], <4 x i32> zeroinitializer1846; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x float> [[TMP1]] to <4 x i32>1847; CHECK-NEXT: [[TMP6:%.*]] = xor <4 x i32> [[TMP5]], zeroinitializer1848; CHECK-NEXT: [[TMP7:%.*]] = or <4 x i32> [[TMP6]], [[_MSPROP]]1849; CHECK-NEXT: [[TMP8:%.*]] = or <4 x i32> [[TMP7]], zeroinitializer1850; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP1]], <4 x i32> [[TMP8]], <4 x i32> [[TMP10]]1851; CHECK-NEXT: [[TMP9:%.*]] = select <4 x i1> [[EXTRACT]], <4 x float> [[TMP1]], <4 x float> zeroinitializer1852; CHECK-NEXT: store <4 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 81853; CHECK-NEXT: ret <4 x float> [[TMP9]]1854;1855 %1 = call <4 x float> @llvm.x86.sse.min.ps(<4 x float> %a0, <4 x float> %a1)1856 %2 = bitcast i8 %mask to <8 x i1>1857 %3 = bitcast i8 %mask2 to <8 x i1>1858 %extract = shufflevector <8 x i1> %2, <8 x i1> %3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>1859 %4 = select <4 x i1> %extract, <4 x float> %1, <4 x float> zeroinitializer1860 ret <4 x float> %41861}1862 1863define <4 x float> @test_mm512_mask_min_ps_128(<4 x float> %a0, <4 x float> %a1, <4 x float> %src, i8 %mask, i8 %mask2) #0 {1864;1865; CHECK-LABEL: define <4 x float> @test_mm512_mask_min_ps_128(1866; CHECK-SAME: <4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], <4 x float> [[SRC:%.*]], i8 [[MASK:%.*]], i8 [[MASK2:%.*]]) #[[ATTR0]] {1867; CHECK-NEXT: [[TMP8:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 81868; CHECK-NEXT: [[TMP12:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81869; CHECK-NEXT: [[TMP13:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 81870; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 56), align 81871; CHECK-NEXT: [[TMP14:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81872; CHECK-NEXT: call void @llvm.donothing()1873; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP8]], [[TMP12]]1874; CHECK-NEXT: [[TMP1:%.*]] = call <4 x float> @llvm.x86.sse.min.ps(<4 x float> [[A0]], <4 x float> [[A1]])1875; CHECK-NEXT: [[TMP17:%.*]] = bitcast i8 [[TMP13]] to <8 x i1>1876; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[MASK]] to <8 x i1>1877; CHECK-NEXT: [[TMP9:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>1878; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8 [[MASK2]] to <8 x i1>1879; CHECK-NEXT: [[_MSPROP1:%.*]] = shufflevector <8 x i1> [[TMP17]], <8 x i1> [[TMP9]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>1880; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>1881; CHECK-NEXT: [[TMP11:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i32> [[_MSPROP]], <4 x i32> [[TMP14]]1882; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x float> [[TMP1]] to <4 x i32>1883; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x float> [[SRC]] to <4 x i32>1884; CHECK-NEXT: [[TMP7:%.*]] = xor <4 x i32> [[TMP5]], [[TMP6]]1885; CHECK-NEXT: [[TMP15:%.*]] = or <4 x i32> [[TMP7]], [[_MSPROP]]1886; CHECK-NEXT: [[TMP16:%.*]] = or <4 x i32> [[TMP15]], [[TMP14]]1887; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP1]], <4 x i32> [[TMP16]], <4 x i32> [[TMP11]]1888; CHECK-NEXT: [[TMP10:%.*]] = select <4 x i1> [[EXTRACT]], <4 x float> [[TMP1]], <4 x float> [[SRC]]1889; CHECK-NEXT: store <4 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 81890; CHECK-NEXT: ret <4 x float> [[TMP10]]1891;1892 %1 = call <4 x float> @llvm.x86.sse.min.ps(<4 x float> %a0, <4 x float> %a1)1893 %2 = bitcast i8 %mask to <8 x i1>1894 %3 = bitcast i8 %mask2 to <8 x i1>1895 %extract = shufflevector <8 x i1> %2, <8 x i1> %3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>1896 %4 = select <4 x i1> %extract, <4 x float> %1, <4 x float> %src1897 ret <4 x float> %41898}1899 1900define <4 x float> @test_mm512_min_ps_128(<4 x float> %a0, <4 x float> %a1, i8 %mask) #0 {1901; CHECK-LABEL: define <4 x float> @test_mm512_min_ps_128(1902; CHECK-SAME: <4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {1903; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 81904; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81905; CHECK-NEXT: call void @llvm.donothing()1906; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP3]], [[TMP2]]1907; CHECK-NEXT: [[TMP1:%.*]] = call <4 x float> @llvm.x86.sse.min.ps(<4 x float> [[A0]], <4 x float> [[A1]])1908; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 81909; CHECK-NEXT: ret <4 x float> [[TMP1]]1910;1911 %1 = call <4 x float> @llvm.x86.sse.min.ps(<4 x float> %a0, <4 x float> %a1)1912 ret <4 x float> %11913}1914declare <4 x float> @llvm.x86.sse.min.ps(<4 x float>, <4 x float>)1915 1916define <4 x double> @test_getexp_pd_256(<4 x double> %a0) #0 {1917; CHECK-LABEL: define <4 x double> @test_getexp_pd_256(1918; CHECK-SAME: <4 x double> [[A0:%.*]]) #[[ATTR0]] {1919; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 81920; CHECK-NEXT: call void @llvm.donothing()1921; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i64> [[TMP1]] to i2561922; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP2]], 01923; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]1924; CHECK: [[BB3]]:1925; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]1926; CHECK-NEXT: unreachable1927; CHECK: [[BB4]]:1928; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.x86.avx512.mask.getexp.pd.256(<4 x double> [[A0]], <4 x double> zeroinitializer, i8 -1)1929; CHECK-NEXT: store <4 x i64> zeroinitializer, ptr @__msan_retval_tls, align 81930; CHECK-NEXT: ret <4 x double> [[RES]]1931;1932 %res = call <4 x double> @llvm.x86.avx512.mask.getexp.pd.256(<4 x double> %a0, <4 x double> zeroinitializer, i8 -1)1933 ret <4 x double> %res1934}1935 1936declare <4 x double> @llvm.x86.avx512.mask.getexp.pd.256(<4 x double>, <4 x double>, i8) nounwind readnone1937 1938define <8 x float> @test_getexp_ps_256(<8 x float> %a0) #0 {1939; CHECK-LABEL: define <8 x float> @test_getexp_ps_256(1940; CHECK-SAME: <8 x float> [[A0:%.*]]) #[[ATTR0]] {1941; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 81942; CHECK-NEXT: call void @llvm.donothing()1943; CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i32> [[TMP1]] to i2561944; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP2]], 01945; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]1946; CHECK: [[BB3]]:1947; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]1948; CHECK-NEXT: unreachable1949; CHECK: [[BB4]]:1950; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx512.mask.getexp.ps.256(<8 x float> [[A0]], <8 x float> zeroinitializer, i8 -1)1951; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81952; CHECK-NEXT: ret <8 x float> [[RES]]1953;1954 %res = call <8 x float> @llvm.x86.avx512.mask.getexp.ps.256(<8 x float> %a0, <8 x float> zeroinitializer, i8 -1)1955 ret <8 x float> %res1956}1957declare <8 x float> @llvm.x86.avx512.mask.getexp.ps.256(<8 x float>, <8 x float>, i8) nounwind readnone1958 1959declare <4 x i32> @llvm.x86.avx512.vpermi2var.d.128(<4 x i32>, <4 x i32>, <4 x i32>)1960 1961define <4 x i32>@test_int_x86_avx512_vpermi2var_d_128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2) #0 {1962; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_vpermi2var_d_128(1963; CHECK-SAME: <4 x i32> [[X0:%.*]], <4 x i32> [[X1:%.*]], <4 x i32> [[X2:%.*]]) #[[ATTR0]] {1964; CHECK-NEXT: [[TMP6:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 81965; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81966; CHECK-NEXT: [[TMP8:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81967; CHECK-NEXT: call void @llvm.donothing()1968; CHECK-NEXT: [[TMP3:%.*]] = trunc <4 x i32> [[TMP8]] to <4 x i2>1969; CHECK-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.x86.avx512.vpermi2var.d.128(<4 x i32> [[TMP6]], <4 x i32> [[X1]], <4 x i32> [[TMP5]])1970; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i2> [[TMP3]] to i81971; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i8 [[TMP7]], 01972; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]1973; CHECK: [[BB7]]:1974; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]1975; CHECK-NEXT: unreachable1976; CHECK: [[BB8]]:1977; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.x86.avx512.vpermi2var.d.128(<4 x i32> [[X0]], <4 x i32> [[X1]], <4 x i32> [[X2]])1978; CHECK-NEXT: store <4 x i32> [[TMP4]], ptr @__msan_retval_tls, align 81979; CHECK-NEXT: ret <4 x i32> [[TMP1]]1980;1981 %1 = call <4 x i32> @llvm.x86.avx512.vpermi2var.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2)1982 ret <4 x i32> %11983}1984 1985define <4 x i32>@test_int_x86_avx512_mask_vpermi2var_d_128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %x3) #0 {1986;1987; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_mask_vpermi2var_d_128(1988; CHECK-SAME: <4 x i32> [[X0:%.*]], <4 x i32> [[X1:%.*]], <4 x i32> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {1989; CHECK-NEXT: [[TMP8:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 81990; CHECK-NEXT: [[TMP6:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81991; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81992; CHECK-NEXT: [[TMP11:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 81993; CHECK-NEXT: call void @llvm.donothing()1994; CHECK-NEXT: [[TMP9:%.*]] = trunc <4 x i32> [[TMP3]] to <4 x i2>1995; CHECK-NEXT: [[TMP5:%.*]] = call <4 x i32> @llvm.x86.avx512.vpermi2var.d.128(<4 x i32> [[TMP8]], <4 x i32> [[X1]], <4 x i32> [[TMP6]])1996; CHECK-NEXT: [[TMP13:%.*]] = bitcast <4 x i2> [[TMP9]] to i81997; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i8 [[TMP13]], 01998; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]1999; CHECK: [[BB8]]:2000; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]2001; CHECK-NEXT: unreachable2002; CHECK: [[BB9]]:2003; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.x86.avx512.vpermi2var.d.128(<4 x i32> [[X0]], <4 x i32> [[X1]], <4 x i32> [[X2]])2004; CHECK-NEXT: [[TMP10:%.*]] = bitcast i8 [[TMP11]] to <8 x i1>2005; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[X3]] to <8 x i1>2006; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP10]], <8 x i1> [[TMP10]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>2007; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> [[TMP2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>2008; CHECK-NEXT: [[TMP12:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i32> [[TMP5]], <4 x i32> [[TMP3]]2009; CHECK-NEXT: [[TMP4:%.*]] = xor <4 x i32> [[TMP1]], [[X1]]2010; CHECK-NEXT: [[TMP14:%.*]] = or <4 x i32> [[TMP4]], [[TMP5]]2011; CHECK-NEXT: [[TMP15:%.*]] = or <4 x i32> [[TMP14]], [[TMP3]]2012; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP]], <4 x i32> [[TMP15]], <4 x i32> [[TMP12]]2013; CHECK-NEXT: [[TMP7:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i32> [[TMP1]], <4 x i32> [[X1]]2014; CHECK-NEXT: store <4 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82015; CHECK-NEXT: ret <4 x i32> [[TMP7]]2016;2017 %1 = call <4 x i32> @llvm.x86.avx512.vpermi2var.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2)2018 %2 = bitcast i8 %x3 to <8 x i1>2019 %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>2020 %3 = select <4 x i1> %extract, <4 x i32> %1, <4 x i32> %x12021 ret <4 x i32> %32022}2023 2024define <4 x i32>@test_int_x86_avx512_vpermt2var_d_128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2) #0 {2025; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_vpermt2var_d_128(2026; CHECK-SAME: <4 x i32> [[X0:%.*]], <4 x i32> [[X1:%.*]], <4 x i32> [[X2:%.*]]) #[[ATTR0]] {2027; CHECK-NEXT: [[TMP6:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 82028; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 82029; CHECK-NEXT: [[TMP8:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 82030; CHECK-NEXT: call void @llvm.donothing()2031; CHECK-NEXT: [[TMP3:%.*]] = trunc <4 x i32> [[TMP8]] to <4 x i2>2032; CHECK-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.x86.avx512.vpermi2var.d.128(<4 x i32> [[TMP6]], <4 x i32> [[X0]], <4 x i32> [[TMP5]])2033; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i2> [[TMP3]] to i82034; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i8 [[TMP7]], 02035; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]2036; CHECK: [[BB7]]:2037; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]2038; CHECK-NEXT: unreachable2039; CHECK: [[BB8]]:2040; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.x86.avx512.vpermi2var.d.128(<4 x i32> [[X1]], <4 x i32> [[X0]], <4 x i32> [[X2]])2041; CHECK-NEXT: store <4 x i32> [[TMP4]], ptr @__msan_retval_tls, align 82042; CHECK-NEXT: ret <4 x i32> [[TMP1]]2043;2044 %1 = call <4 x i32> @llvm.x86.avx512.vpermi2var.d.128(<4 x i32> %x1, <4 x i32> %x0, <4 x i32> %x2)2045 ret <4 x i32> %12046}2047 2048define <4 x i32>@test_int_x86_avx512_mask_vpermt2var_d_128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %x3) #0 {2049;2050; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_mask_vpermt2var_d_128(2051; CHECK-SAME: <4 x i32> [[X0:%.*]], <4 x i32> [[X1:%.*]], <4 x i32> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {2052; CHECK-NEXT: [[TMP8:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 82053; CHECK-NEXT: [[TMP6:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 82054; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 82055; CHECK-NEXT: [[TMP11:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 82056; CHECK-NEXT: call void @llvm.donothing()2057; CHECK-NEXT: [[TMP9:%.*]] = trunc <4 x i32> [[TMP3]] to <4 x i2>2058; CHECK-NEXT: [[TMP5:%.*]] = call <4 x i32> @llvm.x86.avx512.vpermi2var.d.128(<4 x i32> [[TMP8]], <4 x i32> [[X0]], <4 x i32> [[TMP6]])2059; CHECK-NEXT: [[TMP13:%.*]] = bitcast <4 x i2> [[TMP9]] to i82060; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i8 [[TMP13]], 02061; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]2062; CHECK: [[BB8]]:2063; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]2064; CHECK-NEXT: unreachable2065; CHECK: [[BB9]]:2066; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.x86.avx512.vpermi2var.d.128(<4 x i32> [[X1]], <4 x i32> [[X0]], <4 x i32> [[X2]])2067; CHECK-NEXT: [[TMP10:%.*]] = bitcast i8 [[TMP11]] to <8 x i1>2068; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[X3]] to <8 x i1>2069; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP10]], <8 x i1> [[TMP10]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>2070; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> [[TMP2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>2071; CHECK-NEXT: [[TMP12:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i32> [[TMP5]], <4 x i32> [[TMP8]]2072; CHECK-NEXT: [[TMP4:%.*]] = xor <4 x i32> [[TMP1]], [[X1]]2073; CHECK-NEXT: [[TMP14:%.*]] = or <4 x i32> [[TMP4]], [[TMP5]]2074; CHECK-NEXT: [[TMP15:%.*]] = or <4 x i32> [[TMP14]], [[TMP8]]2075; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP]], <4 x i32> [[TMP15]], <4 x i32> [[TMP12]]2076; CHECK-NEXT: [[TMP7:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i32> [[TMP1]], <4 x i32> [[X1]]2077; CHECK-NEXT: store <4 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82078; CHECK-NEXT: ret <4 x i32> [[TMP7]]2079;2080 %1 = call <4 x i32> @llvm.x86.avx512.vpermi2var.d.128(<4 x i32> %x1, <4 x i32> %x0, <4 x i32> %x2)2081 %2 = bitcast i8 %x3 to <8 x i1>2082 %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>2083 %3 = select <4 x i1> %extract, <4 x i32> %1, <4 x i32> %x12084 ret <4 x i32> %32085}2086 2087define <4 x i32>@test_int_x86_avx512_maskz_vpermt2var_d_128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %x3) #0 {2088;2089; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_maskz_vpermt2var_d_128(2090; CHECK-SAME: <4 x i32> [[X0:%.*]], <4 x i32> [[X1:%.*]], <4 x i32> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {2091; CHECK-NEXT: [[TMP8:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 82092; CHECK-NEXT: [[TMP9:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 82093; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 82094; CHECK-NEXT: [[TMP11:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 82095; CHECK-NEXT: call void @llvm.donothing()2096; CHECK-NEXT: [[TMP14:%.*]] = trunc <4 x i32> [[TMP3]] to <4 x i2>2097; CHECK-NEXT: [[TMP13:%.*]] = call <4 x i32> @llvm.x86.avx512.vpermi2var.d.128(<4 x i32> [[TMP8]], <4 x i32> [[X0]], <4 x i32> [[TMP9]])2098; CHECK-NEXT: [[TMP15:%.*]] = bitcast <4 x i2> [[TMP14]] to i82099; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i8 [[TMP15]], 02100; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]2101; CHECK: [[BB8]]:2102; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]2103; CHECK-NEXT: unreachable2104; CHECK: [[BB9]]:2105; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.x86.avx512.vpermi2var.d.128(<4 x i32> [[X1]], <4 x i32> [[X0]], <4 x i32> [[X2]])2106; CHECK-NEXT: [[TMP10:%.*]] = bitcast i8 [[TMP11]] to <8 x i1>2107; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[X3]] to <8 x i1>2108; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP10]], <8 x i1> [[TMP10]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>2109; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> [[TMP2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>2110; CHECK-NEXT: [[TMP12:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i32> [[TMP13]], <4 x i32> zeroinitializer2111; CHECK-NEXT: [[TMP4:%.*]] = xor <4 x i32> [[TMP1]], zeroinitializer2112; CHECK-NEXT: [[TMP5:%.*]] = or <4 x i32> [[TMP4]], [[TMP13]]2113; CHECK-NEXT: [[TMP6:%.*]] = or <4 x i32> [[TMP5]], zeroinitializer2114; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP]], <4 x i32> [[TMP6]], <4 x i32> [[TMP12]]2115; CHECK-NEXT: [[TMP7:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i32> [[TMP1]], <4 x i32> zeroinitializer2116; CHECK-NEXT: store <4 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82117; CHECK-NEXT: ret <4 x i32> [[TMP7]]2118;2119 %1 = call <4 x i32> @llvm.x86.avx512.vpermi2var.d.128(<4 x i32> %x1, <4 x i32> %x0, <4 x i32> %x2)2120 %2 = bitcast i8 %x3 to <8 x i1>2121 %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>2122 %3 = select <4 x i1> %extract, <4 x i32> %1, <4 x i32> zeroinitializer2123 ret <4 x i32> %32124}2125 2126declare <8 x i32> @llvm.x86.avx512.vpermi2var.d.256(<8 x i32>, <8 x i32>, <8 x i32>)2127 2128define <8 x i32>@test_int_x86_avx512_vpermi2var_d_256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2) #0 {2129; CHECK-LABEL: define <8 x i32> @test_int_x86_avx512_vpermi2var_d_256(2130; CHECK-SAME: <8 x i32> [[X0:%.*]], <8 x i32> [[X1:%.*]], <8 x i32> [[X2:%.*]]) #[[ATTR0]] {2131; CHECK-NEXT: [[TMP6:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 82132; CHECK-NEXT: [[TMP5:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82133; CHECK-NEXT: [[TMP8:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 82134; CHECK-NEXT: call void @llvm.donothing()2135; CHECK-NEXT: [[TMP3:%.*]] = trunc <8 x i32> [[TMP8]] to <8 x i3>2136; CHECK-NEXT: [[TMP4:%.*]] = call <8 x i32> @llvm.x86.avx512.vpermi2var.d.256(<8 x i32> [[TMP6]], <8 x i32> [[X1]], <8 x i32> [[TMP5]])2137; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i3> [[TMP3]] to i242138; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i24 [[TMP7]], 02139; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]2140; CHECK: [[BB7]]:2141; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]2142; CHECK-NEXT: unreachable2143; CHECK: [[BB8]]:2144; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i32> @llvm.x86.avx512.vpermi2var.d.256(<8 x i32> [[X0]], <8 x i32> [[X1]], <8 x i32> [[X2]])2145; CHECK-NEXT: store <8 x i32> [[TMP4]], ptr @__msan_retval_tls, align 82146; CHECK-NEXT: ret <8 x i32> [[TMP1]]2147;2148 %1 = call <8 x i32> @llvm.x86.avx512.vpermi2var.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2)2149 ret <8 x i32> %12150}2151 2152define <8 x i32>@test_int_x86_avx512_mask_vpermi2var_d_256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3) #0 {2153;2154; CHECK-LABEL: define <8 x i32> @test_int_x86_avx512_mask_vpermi2var_d_256(2155; CHECK-SAME: <8 x i32> [[X0:%.*]], <8 x i32> [[X1:%.*]], <8 x i32> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {2156; CHECK-NEXT: [[TMP8:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 82157; CHECK-NEXT: [[TMP6:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82158; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 82159; CHECK-NEXT: [[TMP11:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 82160; CHECK-NEXT: call void @llvm.donothing()2161; CHECK-NEXT: [[TMP9:%.*]] = trunc <8 x i32> [[TMP3]] to <8 x i3>2162; CHECK-NEXT: [[TMP5:%.*]] = call <8 x i32> @llvm.x86.avx512.vpermi2var.d.256(<8 x i32> [[TMP8]], <8 x i32> [[X1]], <8 x i32> [[TMP6]])2163; CHECK-NEXT: [[TMP13:%.*]] = bitcast <8 x i3> [[TMP9]] to i242164; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i24 [[TMP13]], 02165; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]2166; CHECK: [[BB8]]:2167; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]2168; CHECK-NEXT: unreachable2169; CHECK: [[BB9]]:2170; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i32> @llvm.x86.avx512.vpermi2var.d.256(<8 x i32> [[X0]], <8 x i32> [[X1]], <8 x i32> [[X2]])2171; CHECK-NEXT: [[TMP10:%.*]] = bitcast i8 [[TMP11]] to <8 x i1>2172; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[X3]] to <8 x i1>2173; CHECK-NEXT: [[TMP12:%.*]] = select <8 x i1> [[TMP2]], <8 x i32> [[TMP5]], <8 x i32> [[TMP3]]2174; CHECK-NEXT: [[TMP4:%.*]] = xor <8 x i32> [[TMP1]], [[X1]]2175; CHECK-NEXT: [[TMP14:%.*]] = or <8 x i32> [[TMP4]], [[TMP5]]2176; CHECK-NEXT: [[TMP15:%.*]] = or <8 x i32> [[TMP14]], [[TMP3]]2177; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP10]], <8 x i32> [[TMP15]], <8 x i32> [[TMP12]]2178; CHECK-NEXT: [[TMP7:%.*]] = select <8 x i1> [[TMP2]], <8 x i32> [[TMP1]], <8 x i32> [[X1]]2179; CHECK-NEXT: store <8 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82180; CHECK-NEXT: ret <8 x i32> [[TMP7]]2181;2182 %1 = call <8 x i32> @llvm.x86.avx512.vpermi2var.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2)2183 %2 = bitcast i8 %x3 to <8 x i1>2184 %3 = select <8 x i1> %2, <8 x i32> %1, <8 x i32> %x12185 ret <8 x i32> %32186}2187 2188define <8 x i32>@test_int_x86_avx512_ask_vpermt2var_d_256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2) #0 {2189; CHECK-LABEL: define <8 x i32> @test_int_x86_avx512_ask_vpermt2var_d_256(2190; CHECK-SAME: <8 x i32> [[X0:%.*]], <8 x i32> [[X1:%.*]], <8 x i32> [[X2:%.*]]) #[[ATTR0]] {2191; CHECK-NEXT: [[TMP6:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 82192; CHECK-NEXT: [[TMP5:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82193; CHECK-NEXT: [[TMP8:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 82194; CHECK-NEXT: call void @llvm.donothing()2195; CHECK-NEXT: [[TMP3:%.*]] = trunc <8 x i32> [[TMP8]] to <8 x i3>2196; CHECK-NEXT: [[TMP4:%.*]] = call <8 x i32> @llvm.x86.avx512.vpermi2var.d.256(<8 x i32> [[TMP6]], <8 x i32> [[X0]], <8 x i32> [[TMP5]])2197; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i3> [[TMP3]] to i242198; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i24 [[TMP7]], 02199; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]2200; CHECK: [[BB7]]:2201; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]2202; CHECK-NEXT: unreachable2203; CHECK: [[BB8]]:2204; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i32> @llvm.x86.avx512.vpermi2var.d.256(<8 x i32> [[X1]], <8 x i32> [[X0]], <8 x i32> [[X2]])2205; CHECK-NEXT: store <8 x i32> [[TMP4]], ptr @__msan_retval_tls, align 82206; CHECK-NEXT: ret <8 x i32> [[TMP1]]2207;2208 %1 = call <8 x i32> @llvm.x86.avx512.vpermi2var.d.256(<8 x i32> %x1, <8 x i32> %x0, <8 x i32> %x2)2209 ret <8 x i32> %12210}2211 2212define <8 x i32>@test_int_x86_avx512_mask_vpermt2var_d_256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3) #0 {2213;2214; CHECK-LABEL: define <8 x i32> @test_int_x86_avx512_mask_vpermt2var_d_256(2215; CHECK-SAME: <8 x i32> [[X0:%.*]], <8 x i32> [[X1:%.*]], <8 x i32> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {2216; CHECK-NEXT: [[TMP8:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 82217; CHECK-NEXT: [[TMP6:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82218; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 82219; CHECK-NEXT: [[TMP11:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 82220; CHECK-NEXT: call void @llvm.donothing()2221; CHECK-NEXT: [[TMP9:%.*]] = trunc <8 x i32> [[TMP3]] to <8 x i3>2222; CHECK-NEXT: [[TMP5:%.*]] = call <8 x i32> @llvm.x86.avx512.vpermi2var.d.256(<8 x i32> [[TMP8]], <8 x i32> [[X0]], <8 x i32> [[TMP6]])2223; CHECK-NEXT: [[TMP13:%.*]] = bitcast <8 x i3> [[TMP9]] to i242224; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i24 [[TMP13]], 02225; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]2226; CHECK: [[BB8]]:2227; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]2228; CHECK-NEXT: unreachable2229; CHECK: [[BB9]]:2230; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i32> @llvm.x86.avx512.vpermi2var.d.256(<8 x i32> [[X1]], <8 x i32> [[X0]], <8 x i32> [[X2]])2231; CHECK-NEXT: [[TMP10:%.*]] = bitcast i8 [[TMP11]] to <8 x i1>2232; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[X3]] to <8 x i1>2233; CHECK-NEXT: [[TMP12:%.*]] = select <8 x i1> [[TMP2]], <8 x i32> [[TMP5]], <8 x i32> [[TMP8]]2234; CHECK-NEXT: [[TMP4:%.*]] = xor <8 x i32> [[TMP1]], [[X1]]2235; CHECK-NEXT: [[TMP14:%.*]] = or <8 x i32> [[TMP4]], [[TMP5]]2236; CHECK-NEXT: [[TMP15:%.*]] = or <8 x i32> [[TMP14]], [[TMP8]]2237; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP10]], <8 x i32> [[TMP15]], <8 x i32> [[TMP12]]2238; CHECK-NEXT: [[TMP7:%.*]] = select <8 x i1> [[TMP2]], <8 x i32> [[TMP1]], <8 x i32> [[X1]]2239; CHECK-NEXT: store <8 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82240; CHECK-NEXT: ret <8 x i32> [[TMP7]]2241;2242 %1 = call <8 x i32> @llvm.x86.avx512.vpermi2var.d.256(<8 x i32> %x1, <8 x i32> %x0, <8 x i32> %x2)2243 %2 = bitcast i8 %x3 to <8 x i1>2244 %3 = select <8 x i1> %2, <8 x i32> %1, <8 x i32> %x12245 ret <8 x i32> %32246}2247 2248define <8 x i32>@test_int_x86_avx512_maskz_vpermt2var_d_256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3) #0 {2249;2250; CHECK-LABEL: define <8 x i32> @test_int_x86_avx512_maskz_vpermt2var_d_256(2251; CHECK-SAME: <8 x i32> [[X0:%.*]], <8 x i32> [[X1:%.*]], <8 x i32> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {2252; CHECK-NEXT: [[TMP8:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 82253; CHECK-NEXT: [[TMP9:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82254; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 82255; CHECK-NEXT: [[TMP11:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 82256; CHECK-NEXT: call void @llvm.donothing()2257; CHECK-NEXT: [[TMP14:%.*]] = trunc <8 x i32> [[TMP3]] to <8 x i3>2258; CHECK-NEXT: [[TMP13:%.*]] = call <8 x i32> @llvm.x86.avx512.vpermi2var.d.256(<8 x i32> [[TMP8]], <8 x i32> [[X0]], <8 x i32> [[TMP9]])2259; CHECK-NEXT: [[TMP15:%.*]] = bitcast <8 x i3> [[TMP14]] to i242260; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i24 [[TMP15]], 02261; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]2262; CHECK: [[BB8]]:2263; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]2264; CHECK-NEXT: unreachable2265; CHECK: [[BB9]]:2266; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i32> @llvm.x86.avx512.vpermi2var.d.256(<8 x i32> [[X1]], <8 x i32> [[X0]], <8 x i32> [[X2]])2267; CHECK-NEXT: [[TMP10:%.*]] = bitcast i8 [[TMP11]] to <8 x i1>2268; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[X3]] to <8 x i1>2269; CHECK-NEXT: [[TMP12:%.*]] = select <8 x i1> [[TMP2]], <8 x i32> [[TMP13]], <8 x i32> zeroinitializer2270; CHECK-NEXT: [[TMP4:%.*]] = xor <8 x i32> [[TMP1]], zeroinitializer2271; CHECK-NEXT: [[TMP5:%.*]] = or <8 x i32> [[TMP4]], [[TMP13]]2272; CHECK-NEXT: [[TMP6:%.*]] = or <8 x i32> [[TMP5]], zeroinitializer2273; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP10]], <8 x i32> [[TMP6]], <8 x i32> [[TMP12]]2274; CHECK-NEXT: [[TMP7:%.*]] = select <8 x i1> [[TMP2]], <8 x i32> [[TMP1]], <8 x i32> zeroinitializer2275; CHECK-NEXT: store <8 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82276; CHECK-NEXT: ret <8 x i32> [[TMP7]]2277;2278 %1 = call <8 x i32> @llvm.x86.avx512.vpermi2var.d.256(<8 x i32> %x1, <8 x i32> %x0, <8 x i32> %x2)2279 %2 = bitcast i8 %x3 to <8 x i1>2280 %3 = select <8 x i1> %2, <8 x i32> %1, <8 x i32> zeroinitializer2281 ret <8 x i32> %32282}2283 2284declare <2 x double> @llvm.x86.avx512.vpermi2var.pd.128(<2 x double>, <2 x i64>, <2 x double>)2285 2286define <2 x double>@test_int_x86_avx512_vpermi2var_pd_128(<2 x double> %x0, <2 x i64> %x1, <2 x double> %x2) #0 {2287; CHECK-LABEL: define <2 x double> @test_int_x86_avx512_vpermi2var_pd_128(2288; CHECK-SAME: <2 x double> [[X0:%.*]], <2 x i64> [[X1:%.*]], <2 x double> [[X2:%.*]]) #[[ATTR0]] {2289; CHECK-NEXT: [[TMP9:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 82290; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 82291; CHECK-NEXT: [[TMP6:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 82292; CHECK-NEXT: call void @llvm.donothing()2293; CHECK-NEXT: [[TMP3:%.*]] = trunc <2 x i64> [[TMP6]] to <2 x i1>2294; CHECK-NEXT: [[TMP8:%.*]] = bitcast <2 x i64> [[TMP9]] to <2 x double>2295; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <2 x double>2296; CHECK-NEXT: [[TMP10:%.*]] = call <2 x double> @llvm.x86.avx512.vpermi2var.pd.128(<2 x double> [[TMP8]], <2 x i64> [[X1]], <2 x double> [[TMP5]])2297; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x double> [[TMP10]] to <2 x i64>2298; CHECK-NEXT: [[TMP11:%.*]] = bitcast <2 x i1> [[TMP3]] to i22299; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i2 [[TMP11]], 02300; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB10:.*]], label %[[BB11:.*]], !prof [[PROF1]]2301; CHECK: [[BB10]]:2302; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]2303; CHECK-NEXT: unreachable2304; CHECK: [[BB11]]:2305; CHECK-NEXT: [[TMP1:%.*]] = call <2 x double> @llvm.x86.avx512.vpermi2var.pd.128(<2 x double> [[X0]], <2 x i64> [[X1]], <2 x double> [[X2]])2306; CHECK-NEXT: store <2 x i64> [[TMP7]], ptr @__msan_retval_tls, align 82307; CHECK-NEXT: ret <2 x double> [[TMP1]]2308;2309 %1 = call <2 x double> @llvm.x86.avx512.vpermi2var.pd.128(<2 x double> %x0, <2 x i64> %x1, <2 x double> %x2)2310 ret <2 x double> %12311}2312 2313define <2 x double>@test_int_x86_avx512_mask_vpermi2var_pd_128(<2 x double> %x0, <2 x i64> %x1, <2 x double> %x2, i8 %x3) #0 {2314;2315; CHECK-LABEL: define <2 x double> @test_int_x86_avx512_mask_vpermi2var_pd_128(2316; CHECK-SAME: <2 x double> [[X0:%.*]], <2 x i64> [[X1:%.*]], <2 x double> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {2317; CHECK-NEXT: [[TMP11:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 82318; CHECK-NEXT: [[TMP8:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 82319; CHECK-NEXT: [[TMP13:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 82320; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 82321; CHECK-NEXT: call void @llvm.donothing()2322; CHECK-NEXT: [[TMP15:%.*]] = trunc <2 x i64> [[TMP13]] to <2 x i1>2323; CHECK-NEXT: [[TMP9:%.*]] = bitcast <2 x i64> [[TMP11]] to <2 x double>2324; CHECK-NEXT: [[TMP12:%.*]] = bitcast <2 x i64> [[TMP8]] to <2 x double>2325; CHECK-NEXT: [[TMP17:%.*]] = call <2 x double> @llvm.x86.avx512.vpermi2var.pd.128(<2 x double> [[TMP9]], <2 x i64> [[X1]], <2 x double> [[TMP12]])2326; CHECK-NEXT: [[TMP18:%.*]] = bitcast <2 x double> [[TMP17]] to <2 x i64>2327; CHECK-NEXT: [[TMP19:%.*]] = bitcast <2 x i1> [[TMP15]] to i22328; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i2 [[TMP19]], 02329; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB11:.*]], label %[[BB12:.*]], !prof [[PROF1]]2330; CHECK: [[BB11]]:2331; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]2332; CHECK-NEXT: unreachable2333; CHECK: [[BB12]]:2334; CHECK-NEXT: [[TMP1:%.*]] = call <2 x double> @llvm.x86.avx512.vpermi2var.pd.128(<2 x double> [[X0]], <2 x i64> [[X1]], <2 x double> [[X2]])2335; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[X1]] to <2 x double>2336; CHECK-NEXT: [[TMP14:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>2337; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8 [[X3]] to <8 x i1>2338; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP14]], <8 x i1> [[TMP14]], <2 x i32> <i32 0, i32 1>2339; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP3]], <8 x i1> [[TMP3]], <2 x i32> <i32 0, i32 1>2340; CHECK-NEXT: [[TMP16:%.*]] = select <2 x i1> [[EXTRACT]], <2 x i64> [[TMP18]], <2 x i64> [[TMP13]]2341; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x double> [[TMP1]] to <2 x i64>2342; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x double> [[TMP2]] to <2 x i64>2343; CHECK-NEXT: [[TMP7:%.*]] = xor <2 x i64> [[TMP5]], [[TMP6]]2344; CHECK-NEXT: [[TMP20:%.*]] = or <2 x i64> [[TMP7]], [[TMP18]]2345; CHECK-NEXT: [[TMP21:%.*]] = or <2 x i64> [[TMP20]], [[TMP13]]2346; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <2 x i1> [[_MSPROP]], <2 x i64> [[TMP21]], <2 x i64> [[TMP16]]2347; CHECK-NEXT: [[TMP10:%.*]] = select <2 x i1> [[EXTRACT]], <2 x double> [[TMP1]], <2 x double> [[TMP2]]2348; CHECK-NEXT: store <2 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82349; CHECK-NEXT: ret <2 x double> [[TMP10]]2350;2351 %1 = call <2 x double> @llvm.x86.avx512.vpermi2var.pd.128(<2 x double> %x0, <2 x i64> %x1, <2 x double> %x2)2352 %2 = bitcast <2 x i64> %x1 to <2 x double>2353 %3 = bitcast i8 %x3 to <8 x i1>2354 %extract = shufflevector <8 x i1> %3, <8 x i1> %3, <2 x i32> <i32 0, i32 1>2355 %4 = select <2 x i1> %extract, <2 x double> %1, <2 x double> %22356 ret <2 x double> %42357}2358 2359declare <4 x double> @llvm.x86.avx512.vpermi2var.pd.256(<4 x double>, <4 x i64>, <4 x double>)2360 2361define <4 x double>@test_int_x86_avx512_vpermi2var_pd_256(<4 x double> %x0, <4 x i64> %x1, <4 x double> %x2) #0 {2362; CHECK-LABEL: define <4 x double> @test_int_x86_avx512_vpermi2var_pd_256(2363; CHECK-SAME: <4 x double> [[X0:%.*]], <4 x i64> [[X1:%.*]], <4 x double> [[X2:%.*]]) #[[ATTR0]] {2364; CHECK-NEXT: [[TMP9:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 82365; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82366; CHECK-NEXT: [[TMP6:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 82367; CHECK-NEXT: call void @llvm.donothing()2368; CHECK-NEXT: [[TMP3:%.*]] = trunc <4 x i64> [[TMP6]] to <4 x i2>2369; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x i64> [[TMP9]] to <4 x double>2370; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i64> [[TMP4]] to <4 x double>2371; CHECK-NEXT: [[TMP10:%.*]] = call <4 x double> @llvm.x86.avx512.vpermi2var.pd.256(<4 x double> [[TMP8]], <4 x i64> [[X1]], <4 x double> [[TMP5]])2372; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x double> [[TMP10]] to <4 x i64>2373; CHECK-NEXT: [[TMP11:%.*]] = bitcast <4 x i2> [[TMP3]] to i82374; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i8 [[TMP11]], 02375; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB10:.*]], label %[[BB11:.*]], !prof [[PROF1]]2376; CHECK: [[BB10]]:2377; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]2378; CHECK-NEXT: unreachable2379; CHECK: [[BB11]]:2380; CHECK-NEXT: [[TMP1:%.*]] = call <4 x double> @llvm.x86.avx512.vpermi2var.pd.256(<4 x double> [[X0]], <4 x i64> [[X1]], <4 x double> [[X2]])2381; CHECK-NEXT: store <4 x i64> [[TMP7]], ptr @__msan_retval_tls, align 82382; CHECK-NEXT: ret <4 x double> [[TMP1]]2383;2384 %1 = call <4 x double> @llvm.x86.avx512.vpermi2var.pd.256(<4 x double> %x0, <4 x i64> %x1, <4 x double> %x2)2385 ret <4 x double> %12386}2387 2388define <4 x double>@test_int_x86_avx512_mask_vpermi2var_pd_256(<4 x double> %x0, <4 x i64> %x1, <4 x double> %x2, i8 %x3) #0 {2389;2390; CHECK-LABEL: define <4 x double> @test_int_x86_avx512_mask_vpermi2var_pd_256(2391; CHECK-SAME: <4 x double> [[X0:%.*]], <4 x i64> [[X1:%.*]], <4 x double> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {2392; CHECK-NEXT: [[TMP11:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 82393; CHECK-NEXT: [[TMP8:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82394; CHECK-NEXT: [[TMP13:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 82395; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 82396; CHECK-NEXT: call void @llvm.donothing()2397; CHECK-NEXT: [[TMP15:%.*]] = trunc <4 x i64> [[TMP13]] to <4 x i2>2398; CHECK-NEXT: [[TMP9:%.*]] = bitcast <4 x i64> [[TMP11]] to <4 x double>2399; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i64> [[TMP8]] to <4 x double>2400; CHECK-NEXT: [[TMP17:%.*]] = call <4 x double> @llvm.x86.avx512.vpermi2var.pd.256(<4 x double> [[TMP9]], <4 x i64> [[X1]], <4 x double> [[TMP12]])2401; CHECK-NEXT: [[TMP18:%.*]] = bitcast <4 x double> [[TMP17]] to <4 x i64>2402; CHECK-NEXT: [[TMP19:%.*]] = bitcast <4 x i2> [[TMP15]] to i82403; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i8 [[TMP19]], 02404; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB11:.*]], label %[[BB12:.*]], !prof [[PROF1]]2405; CHECK: [[BB11]]:2406; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]2407; CHECK-NEXT: unreachable2408; CHECK: [[BB12]]:2409; CHECK-NEXT: [[TMP1:%.*]] = call <4 x double> @llvm.x86.avx512.vpermi2var.pd.256(<4 x double> [[X0]], <4 x i64> [[X1]], <4 x double> [[X2]])2410; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i64> [[X1]] to <4 x double>2411; CHECK-NEXT: [[TMP14:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>2412; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8 [[X3]] to <8 x i1>2413; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP14]], <8 x i1> [[TMP14]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>2414; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP3]], <8 x i1> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>2415; CHECK-NEXT: [[TMP16:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i64> [[TMP18]], <4 x i64> [[TMP13]]2416; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x double> [[TMP1]] to <4 x i64>2417; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x double> [[TMP2]] to <4 x i64>2418; CHECK-NEXT: [[TMP7:%.*]] = xor <4 x i64> [[TMP5]], [[TMP6]]2419; CHECK-NEXT: [[TMP20:%.*]] = or <4 x i64> [[TMP7]], [[TMP18]]2420; CHECK-NEXT: [[TMP21:%.*]] = or <4 x i64> [[TMP20]], [[TMP13]]2421; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP]], <4 x i64> [[TMP21]], <4 x i64> [[TMP16]]2422; CHECK-NEXT: [[TMP10:%.*]] = select <4 x i1> [[EXTRACT]], <4 x double> [[TMP1]], <4 x double> [[TMP2]]2423; CHECK-NEXT: store <4 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82424; CHECK-NEXT: ret <4 x double> [[TMP10]]2425;2426 %1 = call <4 x double> @llvm.x86.avx512.vpermi2var.pd.256(<4 x double> %x0, <4 x i64> %x1, <4 x double> %x2)2427 %2 = bitcast <4 x i64> %x1 to <4 x double>2428 %3 = bitcast i8 %x3 to <8 x i1>2429 %extract = shufflevector <8 x i1> %3, <8 x i1> %3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>2430 %4 = select <4 x i1> %extract, <4 x double> %1, <4 x double> %22431 ret <4 x double> %42432}2433 2434declare <4 x float> @llvm.x86.avx512.vpermi2var.ps.128(<4 x float>, <4 x i32>, <4 x float>)2435 2436define <4 x float>@test_int_x86_avx512_vpermi2var_ps_128(<4 x float> %x0, <4 x i32> %x1, <4 x float> %x2) #0 {2437; CHECK-LABEL: define <4 x float> @test_int_x86_avx512_vpermi2var_ps_128(2438; CHECK-SAME: <4 x float> [[X0:%.*]], <4 x i32> [[X1:%.*]], <4 x float> [[X2:%.*]]) #[[ATTR0]] {2439; CHECK-NEXT: [[TMP9:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 82440; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 82441; CHECK-NEXT: [[TMP6:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 82442; CHECK-NEXT: call void @llvm.donothing()2443; CHECK-NEXT: [[TMP3:%.*]] = trunc <4 x i32> [[TMP6]] to <4 x i2>2444; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x i32> [[TMP9]] to <4 x float>2445; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <4 x float>2446; CHECK-NEXT: [[TMP10:%.*]] = call <4 x float> @llvm.x86.avx512.vpermi2var.ps.128(<4 x float> [[TMP8]], <4 x i32> [[X1]], <4 x float> [[TMP5]])2447; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x float> [[TMP10]] to <4 x i32>2448; CHECK-NEXT: [[TMP11:%.*]] = bitcast <4 x i2> [[TMP3]] to i82449; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i8 [[TMP11]], 02450; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB10:.*]], label %[[BB11:.*]], !prof [[PROF1]]2451; CHECK: [[BB10]]:2452; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]2453; CHECK-NEXT: unreachable2454; CHECK: [[BB11]]:2455; CHECK-NEXT: [[TMP1:%.*]] = call <4 x float> @llvm.x86.avx512.vpermi2var.ps.128(<4 x float> [[X0]], <4 x i32> [[X1]], <4 x float> [[X2]])2456; CHECK-NEXT: store <4 x i32> [[TMP7]], ptr @__msan_retval_tls, align 82457; CHECK-NEXT: ret <4 x float> [[TMP1]]2458;2459 %1 = call <4 x float> @llvm.x86.avx512.vpermi2var.ps.128(<4 x float> %x0, <4 x i32> %x1, <4 x float> %x2)2460 ret <4 x float> %12461}2462 2463define <4 x float>@test_int_x86_avx512_mask_vpermi2var_ps_128(<4 x float> %x0, <4 x i32> %x1, <4 x float> %x2, i8 %x3) #0 {2464;2465; CHECK-LABEL: define <4 x float> @test_int_x86_avx512_mask_vpermi2var_ps_128(2466; CHECK-SAME: <4 x float> [[X0:%.*]], <4 x i32> [[X1:%.*]], <4 x float> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {2467; CHECK-NEXT: [[TMP11:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 82468; CHECK-NEXT: [[TMP8:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 82469; CHECK-NEXT: [[TMP13:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 82470; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 82471; CHECK-NEXT: call void @llvm.donothing()2472; CHECK-NEXT: [[TMP15:%.*]] = trunc <4 x i32> [[TMP13]] to <4 x i2>2473; CHECK-NEXT: [[TMP9:%.*]] = bitcast <4 x i32> [[TMP11]] to <4 x float>2474; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i32> [[TMP8]] to <4 x float>2475; CHECK-NEXT: [[TMP17:%.*]] = call <4 x float> @llvm.x86.avx512.vpermi2var.ps.128(<4 x float> [[TMP9]], <4 x i32> [[X1]], <4 x float> [[TMP12]])2476; CHECK-NEXT: [[TMP18:%.*]] = bitcast <4 x float> [[TMP17]] to <4 x i32>2477; CHECK-NEXT: [[TMP19:%.*]] = bitcast <4 x i2> [[TMP15]] to i82478; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i8 [[TMP19]], 02479; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB11:.*]], label %[[BB12:.*]], !prof [[PROF1]]2480; CHECK: [[BB11]]:2481; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]2482; CHECK-NEXT: unreachable2483; CHECK: [[BB12]]:2484; CHECK-NEXT: [[TMP1:%.*]] = call <4 x float> @llvm.x86.avx512.vpermi2var.ps.128(<4 x float> [[X0]], <4 x i32> [[X1]], <4 x float> [[X2]])2485; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[X1]] to <4 x float>2486; CHECK-NEXT: [[TMP14:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>2487; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8 [[X3]] to <8 x i1>2488; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP14]], <8 x i1> [[TMP14]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>2489; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP3]], <8 x i1> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>2490; CHECK-NEXT: [[TMP16:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i32> [[TMP18]], <4 x i32> [[TMP13]]2491; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x float> [[TMP1]] to <4 x i32>2492; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x float> [[TMP2]] to <4 x i32>2493; CHECK-NEXT: [[TMP7:%.*]] = xor <4 x i32> [[TMP5]], [[TMP6]]2494; CHECK-NEXT: [[TMP20:%.*]] = or <4 x i32> [[TMP7]], [[TMP18]]2495; CHECK-NEXT: [[TMP21:%.*]] = or <4 x i32> [[TMP20]], [[TMP13]]2496; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP]], <4 x i32> [[TMP21]], <4 x i32> [[TMP16]]2497; CHECK-NEXT: [[TMP10:%.*]] = select <4 x i1> [[EXTRACT]], <4 x float> [[TMP1]], <4 x float> [[TMP2]]2498; CHECK-NEXT: store <4 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82499; CHECK-NEXT: ret <4 x float> [[TMP10]]2500;2501 %1 = call <4 x float> @llvm.x86.avx512.vpermi2var.ps.128(<4 x float> %x0, <4 x i32> %x1, <4 x float> %x2)2502 %2 = bitcast <4 x i32> %x1 to <4 x float>2503 %3 = bitcast i8 %x3 to <8 x i1>2504 %extract = shufflevector <8 x i1> %3, <8 x i1> %3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>2505 %4 = select <4 x i1> %extract, <4 x float> %1, <4 x float> %22506 ret <4 x float> %42507}2508 2509define <4 x float>@test_int_x86_avx512_mask_vpermi2var_ps_128_cast(<4 x float> %x0, <2 x i64> %x1, <4 x float> %x2, i8 %x3) #0 {2510;2511; CHECK-LABEL: define <4 x float> @test_int_x86_avx512_mask_vpermi2var_ps_128_cast(2512; CHECK-SAME: <4 x float> [[X0:%.*]], <2 x i64> [[X1:%.*]], <4 x float> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {2513; CHECK-NEXT: [[TMP11:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 82514; CHECK-NEXT: [[TMP12:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 82515; CHECK-NEXT: [[TMP13:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 82516; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 82517; CHECK-NEXT: call void @llvm.donothing()2518; CHECK-NEXT: [[TMP14:%.*]] = bitcast <2 x i64> [[TMP11]] to <4 x i32>2519; CHECK-NEXT: [[X1CAST:%.*]] = bitcast <2 x i64> [[X1]] to <4 x i32>2520; CHECK-NEXT: [[TMP8:%.*]] = trunc <4 x i32> [[TMP14]] to <4 x i2>2521; CHECK-NEXT: [[TMP16:%.*]] = bitcast <4 x i32> [[TMP12]] to <4 x float>2522; CHECK-NEXT: [[TMP18:%.*]] = bitcast <4 x i32> [[TMP13]] to <4 x float>2523; CHECK-NEXT: [[TMP19:%.*]] = call <4 x float> @llvm.x86.avx512.vpermi2var.ps.128(<4 x float> [[TMP16]], <4 x i32> [[X1CAST]], <4 x float> [[TMP18]])2524; CHECK-NEXT: [[TMP9:%.*]] = bitcast <4 x float> [[TMP19]] to <4 x i32>2525; CHECK-NEXT: [[TMP20:%.*]] = bitcast <4 x i2> [[TMP8]] to i82526; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i8 [[TMP20]], 02527; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB12:.*]], label %[[BB13:.*]], !prof [[PROF1]]2528; CHECK: [[BB12]]:2529; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]2530; CHECK-NEXT: unreachable2531; CHECK: [[BB13]]:2532; CHECK-NEXT: [[TMP1:%.*]] = call <4 x float> @llvm.x86.avx512.vpermi2var.ps.128(<4 x float> [[X0]], <4 x i32> [[X1CAST]], <4 x float> [[X2]])2533; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[X1CAST]] to <4 x float>2534; CHECK-NEXT: [[TMP15:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>2535; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8 [[X3]] to <8 x i1>2536; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP15]], <8 x i1> [[TMP15]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>2537; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP3]], <8 x i1> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>2538; CHECK-NEXT: [[TMP17:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i32> [[TMP9]], <4 x i32> [[TMP14]]2539; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x float> [[TMP1]] to <4 x i32>2540; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x float> [[TMP2]] to <4 x i32>2541; CHECK-NEXT: [[TMP7:%.*]] = xor <4 x i32> [[TMP5]], [[TMP6]]2542; CHECK-NEXT: [[TMP21:%.*]] = or <4 x i32> [[TMP7]], [[TMP9]]2543; CHECK-NEXT: [[TMP22:%.*]] = or <4 x i32> [[TMP21]], [[TMP14]]2544; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP]], <4 x i32> [[TMP22]], <4 x i32> [[TMP17]]2545; CHECK-NEXT: [[TMP10:%.*]] = select <4 x i1> [[EXTRACT]], <4 x float> [[TMP1]], <4 x float> [[TMP2]]2546; CHECK-NEXT: store <4 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82547; CHECK-NEXT: ret <4 x float> [[TMP10]]2548;2549 %x1cast = bitcast <2 x i64> %x1 to <4 x i32>2550 %1 = call <4 x float> @llvm.x86.avx512.vpermi2var.ps.128(<4 x float> %x0, <4 x i32> %x1cast, <4 x float> %x2)2551 %2 = bitcast <4 x i32> %x1cast to <4 x float>2552 %3 = bitcast i8 %x3 to <8 x i1>2553 %extract = shufflevector <8 x i1> %3, <8 x i1> %3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>2554 %4 = select <4 x i1> %extract, <4 x float> %1, <4 x float> %22555 ret <4 x float> %42556}2557 2558declare <8 x float> @llvm.x86.avx512.vpermi2var.ps.256(<8 x float>, <8 x i32>, <8 x float>)2559 2560define <8 x float>@test_int_x86_avx512_vpermi2var_ps_256(<8 x float> %x0, <8 x i32> %x1, <8 x float> %x2) #0 {2561; CHECK-LABEL: define <8 x float> @test_int_x86_avx512_vpermi2var_ps_256(2562; CHECK-SAME: <8 x float> [[X0:%.*]], <8 x i32> [[X1:%.*]], <8 x float> [[X2:%.*]]) #[[ATTR0]] {2563; CHECK-NEXT: [[TMP9:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 82564; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82565; CHECK-NEXT: [[TMP6:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 82566; CHECK-NEXT: call void @llvm.donothing()2567; CHECK-NEXT: [[TMP3:%.*]] = trunc <8 x i32> [[TMP6]] to <8 x i3>2568; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i32> [[TMP9]] to <8 x float>2569; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i32> [[TMP4]] to <8 x float>2570; CHECK-NEXT: [[TMP10:%.*]] = call <8 x float> @llvm.x86.avx512.vpermi2var.ps.256(<8 x float> [[TMP8]], <8 x i32> [[X1]], <8 x float> [[TMP5]])2571; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x float> [[TMP10]] to <8 x i32>2572; CHECK-NEXT: [[TMP11:%.*]] = bitcast <8 x i3> [[TMP3]] to i242573; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i24 [[TMP11]], 02574; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB10:.*]], label %[[BB11:.*]], !prof [[PROF1]]2575; CHECK: [[BB10]]:2576; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]2577; CHECK-NEXT: unreachable2578; CHECK: [[BB11]]:2579; CHECK-NEXT: [[TMP1:%.*]] = call <8 x float> @llvm.x86.avx512.vpermi2var.ps.256(<8 x float> [[X0]], <8 x i32> [[X1]], <8 x float> [[X2]])2580; CHECK-NEXT: store <8 x i32> [[TMP7]], ptr @__msan_retval_tls, align 82581; CHECK-NEXT: ret <8 x float> [[TMP1]]2582;2583 %1 = call <8 x float> @llvm.x86.avx512.vpermi2var.ps.256(<8 x float> %x0, <8 x i32> %x1, <8 x float> %x2)2584 ret <8 x float> %12585}2586 2587define <8 x float>@test_int_x86_avx512_mask_vpermi2var_ps_256(<8 x float> %x0, <8 x i32> %x1, <8 x float> %x2, i8 %x3) #0 {2588;2589; CHECK-LABEL: define <8 x float> @test_int_x86_avx512_mask_vpermi2var_ps_256(2590; CHECK-SAME: <8 x float> [[X0:%.*]], <8 x i32> [[X1:%.*]], <8 x float> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {2591; CHECK-NEXT: [[TMP11:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 82592; CHECK-NEXT: [[TMP8:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82593; CHECK-NEXT: [[TMP13:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 82594; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 82595; CHECK-NEXT: call void @llvm.donothing()2596; CHECK-NEXT: [[TMP15:%.*]] = trunc <8 x i32> [[TMP13]] to <8 x i3>2597; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i32> [[TMP11]] to <8 x float>2598; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x i32> [[TMP8]] to <8 x float>2599; CHECK-NEXT: [[TMP17:%.*]] = call <8 x float> @llvm.x86.avx512.vpermi2var.ps.256(<8 x float> [[TMP9]], <8 x i32> [[X1]], <8 x float> [[TMP12]])2600; CHECK-NEXT: [[TMP18:%.*]] = bitcast <8 x float> [[TMP17]] to <8 x i32>2601; CHECK-NEXT: [[TMP19:%.*]] = bitcast <8 x i3> [[TMP15]] to i242602; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i24 [[TMP19]], 02603; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB11:.*]], label %[[BB12:.*]], !prof [[PROF1]]2604; CHECK: [[BB11]]:2605; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]2606; CHECK-NEXT: unreachable2607; CHECK: [[BB12]]:2608; CHECK-NEXT: [[TMP1:%.*]] = call <8 x float> @llvm.x86.avx512.vpermi2var.ps.256(<8 x float> [[X0]], <8 x i32> [[X1]], <8 x float> [[X2]])2609; CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i32> [[X1]] to <8 x float>2610; CHECK-NEXT: [[TMP14:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>2611; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8 [[X3]] to <8 x i1>2612; CHECK-NEXT: [[TMP16:%.*]] = select <8 x i1> [[TMP3]], <8 x i32> [[TMP18]], <8 x i32> [[TMP13]]2613; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x float> [[TMP1]] to <8 x i32>2614; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x float> [[TMP2]] to <8 x i32>2615; CHECK-NEXT: [[TMP7:%.*]] = xor <8 x i32> [[TMP5]], [[TMP6]]2616; CHECK-NEXT: [[TMP20:%.*]] = or <8 x i32> [[TMP7]], [[TMP18]]2617; CHECK-NEXT: [[TMP21:%.*]] = or <8 x i32> [[TMP20]], [[TMP13]]2618; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP14]], <8 x i32> [[TMP21]], <8 x i32> [[TMP16]]2619; CHECK-NEXT: [[TMP10:%.*]] = select <8 x i1> [[TMP3]], <8 x float> [[TMP1]], <8 x float> [[TMP2]]2620; CHECK-NEXT: store <8 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82621; CHECK-NEXT: ret <8 x float> [[TMP10]]2622;2623 %1 = call <8 x float> @llvm.x86.avx512.vpermi2var.ps.256(<8 x float> %x0, <8 x i32> %x1, <8 x float> %x2)2624 %2 = bitcast <8 x i32> %x1 to <8 x float>2625 %3 = bitcast i8 %x3 to <8 x i1>2626 %4 = select <8 x i1> %3, <8 x float> %1, <8 x float> %22627 ret <8 x float> %42628}2629 2630declare <2 x i64> @llvm.x86.avx512.vpermi2var.q.128(<2 x i64>, <2 x i64>, <2 x i64>)2631 2632define <2 x i64>@test_int_x86_avx512_vpermi2var_q_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2) #0 {2633; CHECK-LABEL: define <2 x i64> @test_int_x86_avx512_vpermi2var_q_128(2634; CHECK-SAME: <2 x i64> [[X0:%.*]], <2 x i64> [[X1:%.*]], <2 x i64> [[X2:%.*]]) #[[ATTR0]] {2635; CHECK-NEXT: [[TMP6:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 82636; CHECK-NEXT: [[TMP5:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 82637; CHECK-NEXT: [[TMP8:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 82638; CHECK-NEXT: call void @llvm.donothing()2639; CHECK-NEXT: [[TMP3:%.*]] = trunc <2 x i64> [[TMP8]] to <2 x i1>2640; CHECK-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.x86.avx512.vpermi2var.q.128(<2 x i64> [[TMP6]], <2 x i64> [[X1]], <2 x i64> [[TMP5]])2641; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i1> [[TMP3]] to i22642; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i2 [[TMP7]], 02643; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]2644; CHECK: [[BB7]]:2645; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]2646; CHECK-NEXT: unreachable2647; CHECK: [[BB8]]:2648; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i64> @llvm.x86.avx512.vpermi2var.q.128(<2 x i64> [[X0]], <2 x i64> [[X1]], <2 x i64> [[X2]])2649; CHECK-NEXT: store <2 x i64> [[TMP4]], ptr @__msan_retval_tls, align 82650; CHECK-NEXT: ret <2 x i64> [[TMP1]]2651;2652 %1 = call <2 x i64> @llvm.x86.avx512.vpermi2var.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2)2653 ret <2 x i64> %12654}2655 2656define <2 x i64>@test_int_x86_avx512_mask_vpermi2var_q_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) #0 {2657;2658; CHECK-LABEL: define <2 x i64> @test_int_x86_avx512_mask_vpermi2var_q_128(2659; CHECK-SAME: <2 x i64> [[X0:%.*]], <2 x i64> [[X1:%.*]], <2 x i64> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {2660; CHECK-NEXT: [[TMP8:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 82661; CHECK-NEXT: [[TMP6:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 82662; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 82663; CHECK-NEXT: [[TMP11:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 82664; CHECK-NEXT: call void @llvm.donothing()2665; CHECK-NEXT: [[TMP9:%.*]] = trunc <2 x i64> [[TMP3]] to <2 x i1>2666; CHECK-NEXT: [[TMP5:%.*]] = call <2 x i64> @llvm.x86.avx512.vpermi2var.q.128(<2 x i64> [[TMP8]], <2 x i64> [[X1]], <2 x i64> [[TMP6]])2667; CHECK-NEXT: [[TMP13:%.*]] = bitcast <2 x i1> [[TMP9]] to i22668; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i2 [[TMP13]], 02669; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]2670; CHECK: [[BB8]]:2671; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]2672; CHECK-NEXT: unreachable2673; CHECK: [[BB9]]:2674; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i64> @llvm.x86.avx512.vpermi2var.q.128(<2 x i64> [[X0]], <2 x i64> [[X1]], <2 x i64> [[X2]])2675; CHECK-NEXT: [[TMP10:%.*]] = bitcast i8 [[TMP11]] to <8 x i1>2676; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[X3]] to <8 x i1>2677; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP10]], <8 x i1> [[TMP10]], <2 x i32> <i32 0, i32 1>2678; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> [[TMP2]], <2 x i32> <i32 0, i32 1>2679; CHECK-NEXT: [[TMP12:%.*]] = select <2 x i1> [[EXTRACT]], <2 x i64> [[TMP5]], <2 x i64> [[TMP3]]2680; CHECK-NEXT: [[TMP4:%.*]] = xor <2 x i64> [[TMP1]], [[X1]]2681; CHECK-NEXT: [[TMP14:%.*]] = or <2 x i64> [[TMP4]], [[TMP5]]2682; CHECK-NEXT: [[TMP15:%.*]] = or <2 x i64> [[TMP14]], [[TMP3]]2683; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <2 x i1> [[_MSPROP]], <2 x i64> [[TMP15]], <2 x i64> [[TMP12]]2684; CHECK-NEXT: [[TMP7:%.*]] = select <2 x i1> [[EXTRACT]], <2 x i64> [[TMP1]], <2 x i64> [[X1]]2685; CHECK-NEXT: store <2 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82686; CHECK-NEXT: ret <2 x i64> [[TMP7]]2687;2688 %1 = call <2 x i64> @llvm.x86.avx512.vpermi2var.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2)2689 %2 = bitcast i8 %x3 to <8 x i1>2690 %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <2 x i32> <i32 0, i32 1>2691 %3 = select <2 x i1> %extract, <2 x i64> %1, <2 x i64> %x12692 ret <2 x i64> %32693}2694 2695define <2 x i64>@test_int_x86_avx512_vpermt2var_q_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2) #0 {2696; CHECK-LABEL: define <2 x i64> @test_int_x86_avx512_vpermt2var_q_128(2697; CHECK-SAME: <2 x i64> [[X0:%.*]], <2 x i64> [[X1:%.*]], <2 x i64> [[X2:%.*]]) #[[ATTR0]] {2698; CHECK-NEXT: [[TMP6:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 82699; CHECK-NEXT: [[TMP5:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 82700; CHECK-NEXT: [[TMP8:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 82701; CHECK-NEXT: call void @llvm.donothing()2702; CHECK-NEXT: [[TMP3:%.*]] = trunc <2 x i64> [[TMP8]] to <2 x i1>2703; CHECK-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.x86.avx512.vpermi2var.q.128(<2 x i64> [[TMP6]], <2 x i64> [[X0]], <2 x i64> [[TMP5]])2704; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i1> [[TMP3]] to i22705; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i2 [[TMP7]], 02706; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]2707; CHECK: [[BB7]]:2708; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]2709; CHECK-NEXT: unreachable2710; CHECK: [[BB8]]:2711; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i64> @llvm.x86.avx512.vpermi2var.q.128(<2 x i64> [[X1]], <2 x i64> [[X0]], <2 x i64> [[X2]])2712; CHECK-NEXT: store <2 x i64> [[TMP4]], ptr @__msan_retval_tls, align 82713; CHECK-NEXT: ret <2 x i64> [[TMP1]]2714;2715 %1 = call <2 x i64> @llvm.x86.avx512.vpermi2var.q.128(<2 x i64> %x1, <2 x i64> %x0, <2 x i64> %x2)2716 ret <2 x i64> %12717}2718 2719define <2 x i64>@test_int_x86_avx512_mask_vpermt2var_q_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) #0 {2720;2721; CHECK-LABEL: define <2 x i64> @test_int_x86_avx512_mask_vpermt2var_q_128(2722; CHECK-SAME: <2 x i64> [[X0:%.*]], <2 x i64> [[X1:%.*]], <2 x i64> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {2723; CHECK-NEXT: [[TMP8:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 82724; CHECK-NEXT: [[TMP6:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 82725; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 82726; CHECK-NEXT: [[TMP11:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 82727; CHECK-NEXT: call void @llvm.donothing()2728; CHECK-NEXT: [[TMP9:%.*]] = trunc <2 x i64> [[TMP3]] to <2 x i1>2729; CHECK-NEXT: [[TMP5:%.*]] = call <2 x i64> @llvm.x86.avx512.vpermi2var.q.128(<2 x i64> [[TMP8]], <2 x i64> [[X0]], <2 x i64> [[TMP6]])2730; CHECK-NEXT: [[TMP13:%.*]] = bitcast <2 x i1> [[TMP9]] to i22731; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i2 [[TMP13]], 02732; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]2733; CHECK: [[BB8]]:2734; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]2735; CHECK-NEXT: unreachable2736; CHECK: [[BB9]]:2737; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i64> @llvm.x86.avx512.vpermi2var.q.128(<2 x i64> [[X1]], <2 x i64> [[X0]], <2 x i64> [[X2]])2738; CHECK-NEXT: [[TMP10:%.*]] = bitcast i8 [[TMP11]] to <8 x i1>2739; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[X3]] to <8 x i1>2740; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP10]], <8 x i1> [[TMP10]], <2 x i32> <i32 0, i32 1>2741; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> [[TMP2]], <2 x i32> <i32 0, i32 1>2742; CHECK-NEXT: [[TMP12:%.*]] = select <2 x i1> [[EXTRACT]], <2 x i64> [[TMP5]], <2 x i64> [[TMP8]]2743; CHECK-NEXT: [[TMP4:%.*]] = xor <2 x i64> [[TMP1]], [[X1]]2744; CHECK-NEXT: [[TMP14:%.*]] = or <2 x i64> [[TMP4]], [[TMP5]]2745; CHECK-NEXT: [[TMP15:%.*]] = or <2 x i64> [[TMP14]], [[TMP8]]2746; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <2 x i1> [[_MSPROP]], <2 x i64> [[TMP15]], <2 x i64> [[TMP12]]2747; CHECK-NEXT: [[TMP7:%.*]] = select <2 x i1> [[EXTRACT]], <2 x i64> [[TMP1]], <2 x i64> [[X1]]2748; CHECK-NEXT: store <2 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82749; CHECK-NEXT: ret <2 x i64> [[TMP7]]2750;2751 %1 = call <2 x i64> @llvm.x86.avx512.vpermi2var.q.128(<2 x i64> %x1, <2 x i64> %x0, <2 x i64> %x2)2752 %2 = bitcast i8 %x3 to <8 x i1>2753 %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <2 x i32> <i32 0, i32 1>2754 %3 = select <2 x i1> %extract, <2 x i64> %1, <2 x i64> %x12755 ret <2 x i64> %32756}2757 2758define <2 x i64>@test_int_x86_avx512_maskz_vpermt2var_q_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) #0 {2759;2760; CHECK-LABEL: define <2 x i64> @test_int_x86_avx512_maskz_vpermt2var_q_128(2761; CHECK-SAME: <2 x i64> [[X0:%.*]], <2 x i64> [[X1:%.*]], <2 x i64> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {2762; CHECK-NEXT: [[TMP8:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 82763; CHECK-NEXT: [[TMP9:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 82764; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 82765; CHECK-NEXT: [[TMP11:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 82766; CHECK-NEXT: call void @llvm.donothing()2767; CHECK-NEXT: [[TMP14:%.*]] = trunc <2 x i64> [[TMP3]] to <2 x i1>2768; CHECK-NEXT: [[TMP13:%.*]] = call <2 x i64> @llvm.x86.avx512.vpermi2var.q.128(<2 x i64> [[TMP8]], <2 x i64> [[X0]], <2 x i64> [[TMP9]])2769; CHECK-NEXT: [[TMP15:%.*]] = bitcast <2 x i1> [[TMP14]] to i22770; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i2 [[TMP15]], 02771; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]2772; CHECK: [[BB8]]:2773; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]2774; CHECK-NEXT: unreachable2775; CHECK: [[BB9]]:2776; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i64> @llvm.x86.avx512.vpermi2var.q.128(<2 x i64> [[X1]], <2 x i64> [[X0]], <2 x i64> [[X2]])2777; CHECK-NEXT: [[TMP10:%.*]] = bitcast i8 [[TMP11]] to <8 x i1>2778; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[X3]] to <8 x i1>2779; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP10]], <8 x i1> [[TMP10]], <2 x i32> <i32 0, i32 1>2780; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> [[TMP2]], <2 x i32> <i32 0, i32 1>2781; CHECK-NEXT: [[TMP12:%.*]] = select <2 x i1> [[EXTRACT]], <2 x i64> [[TMP13]], <2 x i64> zeroinitializer2782; CHECK-NEXT: [[TMP4:%.*]] = xor <2 x i64> [[TMP1]], zeroinitializer2783; CHECK-NEXT: [[TMP5:%.*]] = or <2 x i64> [[TMP4]], [[TMP13]]2784; CHECK-NEXT: [[TMP6:%.*]] = or <2 x i64> [[TMP5]], zeroinitializer2785; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <2 x i1> [[_MSPROP]], <2 x i64> [[TMP6]], <2 x i64> [[TMP12]]2786; CHECK-NEXT: [[TMP7:%.*]] = select <2 x i1> [[EXTRACT]], <2 x i64> [[TMP1]], <2 x i64> zeroinitializer2787; CHECK-NEXT: store <2 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82788; CHECK-NEXT: ret <2 x i64> [[TMP7]]2789;2790 %1 = call <2 x i64> @llvm.x86.avx512.vpermi2var.q.128(<2 x i64> %x1, <2 x i64> %x0, <2 x i64> %x2)2791 %2 = bitcast i8 %x3 to <8 x i1>2792 %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <2 x i32> <i32 0, i32 1>2793 %3 = select <2 x i1> %extract, <2 x i64> %1, <2 x i64> zeroinitializer2794 ret <2 x i64> %32795}2796 2797declare <4 x i64> @llvm.x86.avx512.vpermi2var.q.256(<4 x i64>, <4 x i64>, <4 x i64>)2798 2799define <4 x i64>@test_int_x86_avx512_vpermi2var_q_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2) #0 {2800; CHECK-LABEL: define <4 x i64> @test_int_x86_avx512_vpermi2var_q_256(2801; CHECK-SAME: <4 x i64> [[X0:%.*]], <4 x i64> [[X1:%.*]], <4 x i64> [[X2:%.*]]) #[[ATTR0]] {2802; CHECK-NEXT: [[TMP6:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 82803; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82804; CHECK-NEXT: [[TMP8:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 82805; CHECK-NEXT: call void @llvm.donothing()2806; CHECK-NEXT: [[TMP3:%.*]] = trunc <4 x i64> [[TMP8]] to <4 x i2>2807; CHECK-NEXT: [[TMP4:%.*]] = call <4 x i64> @llvm.x86.avx512.vpermi2var.q.256(<4 x i64> [[TMP6]], <4 x i64> [[X1]], <4 x i64> [[TMP5]])2808; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i2> [[TMP3]] to i82809; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i8 [[TMP7]], 02810; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]2811; CHECK: [[BB7]]:2812; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]2813; CHECK-NEXT: unreachable2814; CHECK: [[BB8]]:2815; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i64> @llvm.x86.avx512.vpermi2var.q.256(<4 x i64> [[X0]], <4 x i64> [[X1]], <4 x i64> [[X2]])2816; CHECK-NEXT: store <4 x i64> [[TMP4]], ptr @__msan_retval_tls, align 82817; CHECK-NEXT: ret <4 x i64> [[TMP1]]2818;2819 %1 = call <4 x i64> @llvm.x86.avx512.vpermi2var.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2)2820 ret <4 x i64> %12821}2822 2823define <4 x i64>@test_int_x86_avx512_mask_vpermi2var_q_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3) #0 {2824;2825; CHECK-LABEL: define <4 x i64> @test_int_x86_avx512_mask_vpermi2var_q_256(2826; CHECK-SAME: <4 x i64> [[X0:%.*]], <4 x i64> [[X1:%.*]], <4 x i64> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {2827; CHECK-NEXT: [[TMP8:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 82828; CHECK-NEXT: [[TMP6:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82829; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 82830; CHECK-NEXT: [[TMP11:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 82831; CHECK-NEXT: call void @llvm.donothing()2832; CHECK-NEXT: [[TMP9:%.*]] = trunc <4 x i64> [[TMP3]] to <4 x i2>2833; CHECK-NEXT: [[TMP5:%.*]] = call <4 x i64> @llvm.x86.avx512.vpermi2var.q.256(<4 x i64> [[TMP8]], <4 x i64> [[X1]], <4 x i64> [[TMP6]])2834; CHECK-NEXT: [[TMP13:%.*]] = bitcast <4 x i2> [[TMP9]] to i82835; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i8 [[TMP13]], 02836; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]2837; CHECK: [[BB8]]:2838; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]2839; CHECK-NEXT: unreachable2840; CHECK: [[BB9]]:2841; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i64> @llvm.x86.avx512.vpermi2var.q.256(<4 x i64> [[X0]], <4 x i64> [[X1]], <4 x i64> [[X2]])2842; CHECK-NEXT: [[TMP10:%.*]] = bitcast i8 [[TMP11]] to <8 x i1>2843; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[X3]] to <8 x i1>2844; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP10]], <8 x i1> [[TMP10]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>2845; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> [[TMP2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>2846; CHECK-NEXT: [[TMP12:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i64> [[TMP5]], <4 x i64> [[TMP3]]2847; CHECK-NEXT: [[TMP4:%.*]] = xor <4 x i64> [[TMP1]], [[X1]]2848; CHECK-NEXT: [[TMP14:%.*]] = or <4 x i64> [[TMP4]], [[TMP5]]2849; CHECK-NEXT: [[TMP15:%.*]] = or <4 x i64> [[TMP14]], [[TMP3]]2850; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP]], <4 x i64> [[TMP15]], <4 x i64> [[TMP12]]2851; CHECK-NEXT: [[TMP7:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i64> [[TMP1]], <4 x i64> [[X1]]2852; CHECK-NEXT: store <4 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82853; CHECK-NEXT: ret <4 x i64> [[TMP7]]2854;2855 %1 = call <4 x i64> @llvm.x86.avx512.vpermi2var.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2)2856 %2 = bitcast i8 %x3 to <8 x i1>2857 %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>2858 %3 = select <4 x i1> %extract, <4 x i64> %1, <4 x i64> %x12859 ret <4 x i64> %32860}2861 2862define <4 x i64>@test_int_x86_avx512_vpermt2var_q_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2) #0 {2863; CHECK-LABEL: define <4 x i64> @test_int_x86_avx512_vpermt2var_q_256(2864; CHECK-SAME: <4 x i64> [[X0:%.*]], <4 x i64> [[X1:%.*]], <4 x i64> [[X2:%.*]]) #[[ATTR0]] {2865; CHECK-NEXT: [[TMP6:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 82866; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82867; CHECK-NEXT: [[TMP8:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 82868; CHECK-NEXT: call void @llvm.donothing()2869; CHECK-NEXT: [[TMP3:%.*]] = trunc <4 x i64> [[TMP8]] to <4 x i2>2870; CHECK-NEXT: [[TMP4:%.*]] = call <4 x i64> @llvm.x86.avx512.vpermi2var.q.256(<4 x i64> [[TMP6]], <4 x i64> [[X0]], <4 x i64> [[TMP5]])2871; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i2> [[TMP3]] to i82872; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i8 [[TMP7]], 02873; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]2874; CHECK: [[BB7]]:2875; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]2876; CHECK-NEXT: unreachable2877; CHECK: [[BB8]]:2878; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i64> @llvm.x86.avx512.vpermi2var.q.256(<4 x i64> [[X1]], <4 x i64> [[X0]], <4 x i64> [[X2]])2879; CHECK-NEXT: store <4 x i64> [[TMP4]], ptr @__msan_retval_tls, align 82880; CHECK-NEXT: ret <4 x i64> [[TMP1]]2881;2882 %1 = call <4 x i64> @llvm.x86.avx512.vpermi2var.q.256(<4 x i64> %x1, <4 x i64> %x0, <4 x i64> %x2)2883 ret <4 x i64> %12884}2885 2886define <4 x i64>@test_int_x86_avx512_mask_vpermt2var_q_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3) #0 {2887;2888; CHECK-LABEL: define <4 x i64> @test_int_x86_avx512_mask_vpermt2var_q_256(2889; CHECK-SAME: <4 x i64> [[X0:%.*]], <4 x i64> [[X1:%.*]], <4 x i64> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {2890; CHECK-NEXT: [[TMP8:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 82891; CHECK-NEXT: [[TMP6:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82892; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 82893; CHECK-NEXT: [[TMP11:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 82894; CHECK-NEXT: call void @llvm.donothing()2895; CHECK-NEXT: [[TMP9:%.*]] = trunc <4 x i64> [[TMP3]] to <4 x i2>2896; CHECK-NEXT: [[TMP5:%.*]] = call <4 x i64> @llvm.x86.avx512.vpermi2var.q.256(<4 x i64> [[TMP8]], <4 x i64> [[X0]], <4 x i64> [[TMP6]])2897; CHECK-NEXT: [[TMP13:%.*]] = bitcast <4 x i2> [[TMP9]] to i82898; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i8 [[TMP13]], 02899; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]2900; CHECK: [[BB8]]:2901; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]2902; CHECK-NEXT: unreachable2903; CHECK: [[BB9]]:2904; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i64> @llvm.x86.avx512.vpermi2var.q.256(<4 x i64> [[X1]], <4 x i64> [[X0]], <4 x i64> [[X2]])2905; CHECK-NEXT: [[TMP10:%.*]] = bitcast i8 [[TMP11]] to <8 x i1>2906; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[X3]] to <8 x i1>2907; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP10]], <8 x i1> [[TMP10]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>2908; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> [[TMP2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>2909; CHECK-NEXT: [[TMP12:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i64> [[TMP5]], <4 x i64> [[TMP8]]2910; CHECK-NEXT: [[TMP4:%.*]] = xor <4 x i64> [[TMP1]], [[X1]]2911; CHECK-NEXT: [[TMP14:%.*]] = or <4 x i64> [[TMP4]], [[TMP5]]2912; CHECK-NEXT: [[TMP15:%.*]] = or <4 x i64> [[TMP14]], [[TMP8]]2913; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP]], <4 x i64> [[TMP15]], <4 x i64> [[TMP12]]2914; CHECK-NEXT: [[TMP7:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i64> [[TMP1]], <4 x i64> [[X1]]2915; CHECK-NEXT: store <4 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82916; CHECK-NEXT: ret <4 x i64> [[TMP7]]2917;2918 %1 = call <4 x i64> @llvm.x86.avx512.vpermi2var.q.256(<4 x i64> %x1, <4 x i64> %x0, <4 x i64> %x2)2919 %2 = bitcast i8 %x3 to <8 x i1>2920 %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>2921 %3 = select <4 x i1> %extract, <4 x i64> %1, <4 x i64> %x12922 ret <4 x i64> %32923}2924 2925define <4 x i64>@test_int_x86_avx512_maskz_vpermt2var_q_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3) #0 {2926;2927; CHECK-LABEL: define <4 x i64> @test_int_x86_avx512_maskz_vpermt2var_q_256(2928; CHECK-SAME: <4 x i64> [[X0:%.*]], <4 x i64> [[X1:%.*]], <4 x i64> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {2929; CHECK-NEXT: [[TMP8:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 82930; CHECK-NEXT: [[TMP9:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 82931; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 82932; CHECK-NEXT: [[TMP11:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 82933; CHECK-NEXT: call void @llvm.donothing()2934; CHECK-NEXT: [[TMP14:%.*]] = trunc <4 x i64> [[TMP3]] to <4 x i2>2935; CHECK-NEXT: [[TMP13:%.*]] = call <4 x i64> @llvm.x86.avx512.vpermi2var.q.256(<4 x i64> [[TMP8]], <4 x i64> [[X0]], <4 x i64> [[TMP9]])2936; CHECK-NEXT: [[TMP15:%.*]] = bitcast <4 x i2> [[TMP14]] to i82937; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i8 [[TMP15]], 02938; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]2939; CHECK: [[BB8]]:2940; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]2941; CHECK-NEXT: unreachable2942; CHECK: [[BB9]]:2943; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i64> @llvm.x86.avx512.vpermi2var.q.256(<4 x i64> [[X1]], <4 x i64> [[X0]], <4 x i64> [[X2]])2944; CHECK-NEXT: [[TMP10:%.*]] = bitcast i8 [[TMP11]] to <8 x i1>2945; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[X3]] to <8 x i1>2946; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP10]], <8 x i1> [[TMP10]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>2947; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> [[TMP2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>2948; CHECK-NEXT: [[TMP12:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i64> [[TMP13]], <4 x i64> zeroinitializer2949; CHECK-NEXT: [[TMP4:%.*]] = xor <4 x i64> [[TMP1]], zeroinitializer2950; CHECK-NEXT: [[TMP5:%.*]] = or <4 x i64> [[TMP4]], [[TMP13]]2951; CHECK-NEXT: [[TMP6:%.*]] = or <4 x i64> [[TMP5]], zeroinitializer2952; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP]], <4 x i64> [[TMP6]], <4 x i64> [[TMP12]]2953; CHECK-NEXT: [[TMP7:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i64> [[TMP1]], <4 x i64> zeroinitializer2954; CHECK-NEXT: store <4 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 82955; CHECK-NEXT: ret <4 x i64> [[TMP7]]2956;2957 %1 = call <4 x i64> @llvm.x86.avx512.vpermi2var.q.256(<4 x i64> %x1, <4 x i64> %x0, <4 x i64> %x2)2958 %2 = bitcast i8 %x3 to <8 x i1>2959 %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>2960 %3 = select <4 x i1> %extract, <4 x i64> %1, <4 x i64> zeroinitializer2961 ret <4 x i64> %32962}2963 2964declare <2 x double> @llvm.x86.avx512.mask.scalef.pd.128(<2 x double>, <2 x double>, <2 x double>, i8)2965 2966define <2 x double>@test_int_x86_avx512_scalef_pd_128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2) #0 {2967; CHECK-LABEL: define <2 x double> @test_int_x86_avx512_scalef_pd_128(2968; CHECK-SAME: <2 x double> [[X0:%.*]], <2 x double> [[X1:%.*]], <2 x double> [[X2:%.*]]) #[[ATTR0]] {2969; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 82970; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 82971; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 82972; CHECK-NEXT: call void @llvm.donothing()2973; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP1]] to i1282974; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 02975; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP2]] to i1282976; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 02977; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]2978; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i64> [[TMP3]] to i1282979; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP6]], 02980; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]2981; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]2982; CHECK: [[BB7]]:2983; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]2984; CHECK-NEXT: unreachable2985; CHECK: [[BB8]]:2986; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx512.mask.scalef.pd.128(<2 x double> [[X0]], <2 x double> [[X1]], <2 x double> [[X2]], i8 -1)2987; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 82988; CHECK-NEXT: ret <2 x double> [[RES]]2989;2990 %res = call <2 x double> @llvm.x86.avx512.mask.scalef.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 -1)2991 ret <2 x double> %res2992}2993 2994define <2 x double>@test_int_x86_avx512_mask_scalef_pd_128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) #0 {2995;2996; CHECK-LABEL: define <2 x double> @test_int_x86_avx512_mask_scalef_pd_128(2997; CHECK-SAME: <2 x double> [[X0:%.*]], <2 x double> [[X1:%.*]], <2 x double> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {2998; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 82999; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83000; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 83001; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 83002; CHECK-NEXT: call void @llvm.donothing()3003; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP1]] to i1283004; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 03005; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i64> [[TMP2]] to i1283006; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP6]], 03007; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3008; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i64> [[TMP3]] to i1283009; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 03010; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]3011; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 03012; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]3013; CHECK-NEXT: br i1 [[_MSOR5]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]3014; CHECK: [[BB8]]:3015; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3016; CHECK-NEXT: unreachable3017; CHECK: [[BB9]]:3018; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx512.mask.scalef.pd.128(<2 x double> [[X0]], <2 x double> [[X1]], <2 x double> [[X2]], i8 [[X3]])3019; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 83020; CHECK-NEXT: ret <2 x double> [[RES]]3021;3022 %res = call <2 x double> @llvm.x86.avx512.mask.scalef.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3)3023 ret <2 x double> %res3024}3025 3026declare <4 x double> @llvm.x86.avx512.mask.scalef.pd.256(<4 x double>, <4 x double>, <4 x double>, i8)3027 3028define <4 x double>@test_int_x86_avx512_scalef_pd_256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2) #0 {3029; CHECK-LABEL: define <4 x double> @test_int_x86_avx512_scalef_pd_256(3030; CHECK-SAME: <4 x double> [[X0:%.*]], <4 x double> [[X1:%.*]], <4 x double> [[X2:%.*]]) #[[ATTR0]] {3031; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 83032; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 83033; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 83034; CHECK-NEXT: call void @llvm.donothing()3035; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i64> [[TMP1]] to i2563036; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP4]], 03037; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i64> [[TMP2]] to i2563038; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP5]], 03039; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3040; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i64> [[TMP3]] to i2563041; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i256 [[TMP6]], 03042; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]3043; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]3044; CHECK: [[BB7]]:3045; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3046; CHECK-NEXT: unreachable3047; CHECK: [[BB8]]:3048; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.x86.avx512.mask.scalef.pd.256(<4 x double> [[X0]], <4 x double> [[X1]], <4 x double> [[X2]], i8 -1)3049; CHECK-NEXT: store <4 x i64> zeroinitializer, ptr @__msan_retval_tls, align 83050; CHECK-NEXT: ret <4 x double> [[RES]]3051;3052 %res = call <4 x double> @llvm.x86.avx512.mask.scalef.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 -1)3053 ret <4 x double> %res3054}3055 3056define <4 x double>@test_int_x86_avx512_mask_scalef_pd_256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) #0 {3057;3058; CHECK-LABEL: define <4 x double> @test_int_x86_avx512_mask_scalef_pd_256(3059; CHECK-SAME: <4 x double> [[X0:%.*]], <4 x double> [[X1:%.*]], <4 x double> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {3060; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 83061; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 83062; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 83063; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 83064; CHECK-NEXT: call void @llvm.donothing()3065; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i64> [[TMP1]] to i2563066; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP5]], 03067; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i64> [[TMP2]] to i2563068; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP6]], 03069; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3070; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i64> [[TMP3]] to i2563071; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i256 [[TMP7]], 03072; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]3073; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 03074; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]3075; CHECK-NEXT: br i1 [[_MSOR5]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]3076; CHECK: [[BB8]]:3077; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3078; CHECK-NEXT: unreachable3079; CHECK: [[BB9]]:3080; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.x86.avx512.mask.scalef.pd.256(<4 x double> [[X0]], <4 x double> [[X1]], <4 x double> [[X2]], i8 [[X3]])3081; CHECK-NEXT: store <4 x i64> zeroinitializer, ptr @__msan_retval_tls, align 83082; CHECK-NEXT: ret <4 x double> [[RES]]3083;3084 %res = call <4 x double> @llvm.x86.avx512.mask.scalef.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3)3085 ret <4 x double> %res3086}3087 3088declare <4 x float> @llvm.x86.avx512.mask.scalef.ps.128(<4 x float>, <4 x float>, <4 x float>, i8)3089 3090define <4 x float>@test_int_x86_avx512_scalef_ps_128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2) #0 {3091; CHECK-LABEL: define <4 x float> @test_int_x86_avx512_scalef_ps_128(3092; CHECK-SAME: <4 x float> [[X0:%.*]], <4 x float> [[X1:%.*]], <4 x float> [[X2:%.*]]) #[[ATTR0]] {3093; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 83094; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83095; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 83096; CHECK-NEXT: call void @llvm.donothing()3097; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP1]] to i1283098; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 03099; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP2]] to i1283100; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 03101; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3102; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i32> [[TMP3]] to i1283103; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP6]], 03104; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]3105; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]3106; CHECK: [[BB7]]:3107; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3108; CHECK-NEXT: unreachable3109; CHECK: [[BB8]]:3110; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.mask.scalef.ps.128(<4 x float> [[X0]], <4 x float> [[X1]], <4 x float> [[X2]], i8 -1)3111; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 83112; CHECK-NEXT: ret <4 x float> [[RES]]3113;3114 %res = call <4 x float> @llvm.x86.avx512.mask.scalef.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 -1)3115 ret <4 x float> %res3116}3117 3118define <4 x float>@test_int_x86_avx512_mask_scalef_ps_128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) #0 {3119;3120; CHECK-LABEL: define <4 x float> @test_int_x86_avx512_mask_scalef_ps_128(3121; CHECK-SAME: <4 x float> [[X0:%.*]], <4 x float> [[X1:%.*]], <4 x float> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {3122; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 83123; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83124; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 83125; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 83126; CHECK-NEXT: call void @llvm.donothing()3127; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP1]] to i1283128; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 03129; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i32> [[TMP2]] to i1283130; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP6]], 03131; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3132; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i32> [[TMP3]] to i1283133; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 03134; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]3135; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 03136; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]3137; CHECK-NEXT: br i1 [[_MSOR5]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]3138; CHECK: [[BB8]]:3139; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3140; CHECK-NEXT: unreachable3141; CHECK: [[BB9]]:3142; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.mask.scalef.ps.128(<4 x float> [[X0]], <4 x float> [[X1]], <4 x float> [[X2]], i8 [[X3]])3143; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 83144; CHECK-NEXT: ret <4 x float> [[RES]]3145;3146 %res = call <4 x float> @llvm.x86.avx512.mask.scalef.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3)3147 ret <4 x float> %res3148}3149 3150declare <8 x float> @llvm.x86.avx512.mask.scalef.ps.256(<8 x float>, <8 x float>, <8 x float>, i8)3151 3152define <8 x float>@test_int_x86_avx512_scalef_ps_256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2) #0 {3153; CHECK-LABEL: define <8 x float> @test_int_x86_avx512_scalef_ps_256(3154; CHECK-SAME: <8 x float> [[X0:%.*]], <8 x float> [[X1:%.*]], <8 x float> [[X2:%.*]]) #[[ATTR0]] {3155; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 83156; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 83157; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 83158; CHECK-NEXT: call void @llvm.donothing()3159; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i32> [[TMP1]] to i2563160; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP4]], 03161; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i32> [[TMP2]] to i2563162; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP5]], 03163; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3164; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i32> [[TMP3]] to i2563165; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i256 [[TMP6]], 03166; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]3167; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]3168; CHECK: [[BB7]]:3169; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3170; CHECK-NEXT: unreachable3171; CHECK: [[BB8]]:3172; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx512.mask.scalef.ps.256(<8 x float> [[X0]], <8 x float> [[X1]], <8 x float> [[X2]], i8 -1)3173; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 83174; CHECK-NEXT: ret <8 x float> [[RES]]3175;3176 %res = call <8 x float> @llvm.x86.avx512.mask.scalef.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 -1)3177 ret <8 x float> %res3178}3179 3180define <8 x float>@test_int_x86_avx512_mask_scalef_ps_256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) #0 {3181;3182; CHECK-LABEL: define <8 x float> @test_int_x86_avx512_mask_scalef_ps_256(3183; CHECK-SAME: <8 x float> [[X0:%.*]], <8 x float> [[X1:%.*]], <8 x float> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {3184; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 83185; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 83186; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 83187; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 83188; CHECK-NEXT: call void @llvm.donothing()3189; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i32> [[TMP1]] to i2563190; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP5]], 03191; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i32> [[TMP2]] to i2563192; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP6]], 03193; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3194; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i32> [[TMP3]] to i2563195; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i256 [[TMP7]], 03196; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]3197; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 03198; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]3199; CHECK-NEXT: br i1 [[_MSOR5]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]3200; CHECK: [[BB8]]:3201; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3202; CHECK-NEXT: unreachable3203; CHECK: [[BB9]]:3204; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx512.mask.scalef.ps.256(<8 x float> [[X0]], <8 x float> [[X1]], <8 x float> [[X2]], i8 [[X3]])3205; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 83206; CHECK-NEXT: ret <8 x float> [[RES]]3207;3208 %res = call <8 x float> @llvm.x86.avx512.mask.scalef.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3)3209 ret <8 x float> %res3210}3211 3212declare <16 x i8> @llvm.x86.avx512.mask.pmov.qb.128(<2 x i64>, <16 x i8>, i8)3213 3214define <16 x i8>@test_int_x86_avx512_mask_pmov_qb_128(<2 x i64> %x0, <16 x i8> %x1, i8 %x2) #0 {3215;3216; CHECK-LABEL: define <16 x i8> @test_int_x86_avx512_mask_pmov_qb_128(3217; CHECK-SAME: <2 x i64> [[X0:%.*]], <16 x i8> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {3218; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 83219; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83220; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 83221; CHECK-NEXT: call void @llvm.donothing()3222; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP1]] to i1283223; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 03224; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to i1283225; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 03226; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3227; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]3228; CHECK: [[BB6]]:3229; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3230; CHECK-NEXT: unreachable3231; CHECK: [[BB7]]:3232; CHECK-NEXT: [[RES0:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmov.qb.128(<2 x i64> [[X0]], <16 x i8> [[X1]], i8 -1)3233; CHECK-NEXT: [[TMP8:%.*]] = bitcast <2 x i64> [[TMP1]] to i1283234; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP8]], 03235; CHECK-NEXT: [[TMP9:%.*]] = bitcast <16 x i8> [[TMP2]] to i1283236; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP9]], 03237; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]3238; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 03239; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]3240; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB10:.*]], label %[[BB11:.*]], !prof [[PROF1]]3241; CHECK: [[BB10]]:3242; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3243; CHECK-NEXT: unreachable3244; CHECK: [[BB11]]:3245; CHECK-NEXT: [[RES1:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmov.qb.128(<2 x i64> [[X0]], <16 x i8> [[X1]], i8 [[X2]])3246; CHECK-NEXT: [[TMP12:%.*]] = bitcast <2 x i64> [[TMP1]] to i1283247; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i128 [[TMP12]], 03248; CHECK-NEXT: [[_MSCMP8:%.*]] = icmp ne i8 [[TMP3]], 03249; CHECK-NEXT: [[_MSOR9:%.*]] = or i1 [[_MSCMP7]], [[_MSCMP8]]3250; CHECK-NEXT: br i1 [[_MSOR9]], label %[[BB13:.*]], label %[[BB14:.*]], !prof [[PROF1]]3251; CHECK: [[BB13]]:3252; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3253; CHECK-NEXT: unreachable3254; CHECK: [[BB14]]:3255; CHECK-NEXT: [[RES2:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmov.qb.128(<2 x i64> [[X0]], <16 x i8> zeroinitializer, i8 [[X2]])3256; CHECK-NEXT: [[RES3:%.*]] = add <16 x i8> [[RES0]], [[RES1]]3257; CHECK-NEXT: [[RES4:%.*]] = add <16 x i8> [[RES3]], [[RES2]]3258; CHECK-NEXT: store <16 x i8> zeroinitializer, ptr @__msan_retval_tls, align 83259; CHECK-NEXT: ret <16 x i8> [[RES4]]3260;3261 %res0 = call <16 x i8> @llvm.x86.avx512.mask.pmov.qb.128(<2 x i64> %x0, <16 x i8> %x1, i8 -1)3262 %res1 = call <16 x i8> @llvm.x86.avx512.mask.pmov.qb.128(<2 x i64> %x0, <16 x i8> %x1, i8 %x2)3263 %res2 = call <16 x i8> @llvm.x86.avx512.mask.pmov.qb.128(<2 x i64> %x0, <16 x i8> zeroinitializer, i8 %x2)3264 %res3 = add <16 x i8> %res0, %res13265 %res4 = add <16 x i8> %res3, %res23266 ret <16 x i8> %res43267}3268 3269declare void @llvm.x86.avx512.mask.pmov.qb.mem.128(ptr %ptr, <2 x i64>, i8)3270 3271define void @test_int_x86_avx512_mask_pmov_qb_mem_128(ptr %ptr, <2 x i64> %x1, i8 %x2) #0 {3272;3273; CHECK-LABEL: define void @test_int_x86_avx512_mask_pmov_qb_mem_128(3274; CHECK-SAME: ptr [[PTR:%.*]], <2 x i64> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {3275; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 83276; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83277; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 83278; CHECK-NEXT: call void @llvm.donothing()3279; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03280; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP2]] to i1283281; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 03282; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3283; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]3284; CHECK: [[BB5]]:3285; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3286; CHECK-NEXT: unreachable3287; CHECK: [[BB6]]:3288; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmov.qb.mem.128(ptr [[PTR]], <2 x i64> [[X1]], i8 -1)3289; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 03290; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i64> [[TMP2]] to i1283291; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP7]], 03292; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]3293; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 03294; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]3295; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]3296; CHECK: [[BB8]]:3297; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3298; CHECK-NEXT: unreachable3299; CHECK: [[BB9]]:3300; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmov.qb.mem.128(ptr [[PTR]], <2 x i64> [[X1]], i8 [[X2]])3301; CHECK-NEXT: ret void3302;3303 call void @llvm.x86.avx512.mask.pmov.qb.mem.128(ptr %ptr, <2 x i64> %x1, i8 -1)3304 call void @llvm.x86.avx512.mask.pmov.qb.mem.128(ptr %ptr, <2 x i64> %x1, i8 %x2)3305 ret void3306}3307 3308declare <16 x i8> @llvm.x86.avx512.mask.pmovs.qb.128(<2 x i64>, <16 x i8>, i8)3309 3310define <16 x i8>@test_int_x86_avx512_mask_pmovs_qb_128(<2 x i64> %x0, <16 x i8> %x1, i8 %x2) #0 {3311;3312; CHECK-LABEL: define <16 x i8> @test_int_x86_avx512_mask_pmovs_qb_128(3313; CHECK-SAME: <2 x i64> [[X0:%.*]], <16 x i8> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {3314; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 83315; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83316; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 83317; CHECK-NEXT: call void @llvm.donothing()3318; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP1]] to i1283319; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 03320; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to i1283321; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 03322; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3323; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]3324; CHECK: [[BB6]]:3325; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3326; CHECK-NEXT: unreachable3327; CHECK: [[BB7]]:3328; CHECK-NEXT: [[RES0:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmovs.qb.128(<2 x i64> [[X0]], <16 x i8> [[X1]], i8 -1)3329; CHECK-NEXT: [[TMP8:%.*]] = bitcast <2 x i64> [[TMP1]] to i1283330; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP8]], 03331; CHECK-NEXT: [[TMP9:%.*]] = bitcast <16 x i8> [[TMP2]] to i1283332; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP9]], 03333; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]3334; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 03335; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]3336; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB10:.*]], label %[[BB11:.*]], !prof [[PROF1]]3337; CHECK: [[BB10]]:3338; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3339; CHECK-NEXT: unreachable3340; CHECK: [[BB11]]:3341; CHECK-NEXT: [[RES1:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmovs.qb.128(<2 x i64> [[X0]], <16 x i8> [[X1]], i8 [[X2]])3342; CHECK-NEXT: [[TMP12:%.*]] = bitcast <2 x i64> [[TMP1]] to i1283343; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i128 [[TMP12]], 03344; CHECK-NEXT: [[_MSCMP8:%.*]] = icmp ne i8 [[TMP3]], 03345; CHECK-NEXT: [[_MSOR9:%.*]] = or i1 [[_MSCMP7]], [[_MSCMP8]]3346; CHECK-NEXT: br i1 [[_MSOR9]], label %[[BB13:.*]], label %[[BB14:.*]], !prof [[PROF1]]3347; CHECK: [[BB13]]:3348; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3349; CHECK-NEXT: unreachable3350; CHECK: [[BB14]]:3351; CHECK-NEXT: [[RES2:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmovs.qb.128(<2 x i64> [[X0]], <16 x i8> zeroinitializer, i8 [[X2]])3352; CHECK-NEXT: [[RES3:%.*]] = add <16 x i8> [[RES0]], [[RES1]]3353; CHECK-NEXT: [[RES4:%.*]] = add <16 x i8> [[RES3]], [[RES2]]3354; CHECK-NEXT: store <16 x i8> zeroinitializer, ptr @__msan_retval_tls, align 83355; CHECK-NEXT: ret <16 x i8> [[RES4]]3356;3357 %res0 = call <16 x i8> @llvm.x86.avx512.mask.pmovs.qb.128(<2 x i64> %x0, <16 x i8> %x1, i8 -1)3358 %res1 = call <16 x i8> @llvm.x86.avx512.mask.pmovs.qb.128(<2 x i64> %x0, <16 x i8> %x1, i8 %x2)3359 %res2 = call <16 x i8> @llvm.x86.avx512.mask.pmovs.qb.128(<2 x i64> %x0, <16 x i8> zeroinitializer, i8 %x2)3360 %res3 = add <16 x i8> %res0, %res13361 %res4 = add <16 x i8> %res3, %res23362 ret <16 x i8> %res43363}3364 3365declare void @llvm.x86.avx512.mask.pmovs.qb.mem.128(ptr %ptr, <2 x i64>, i8)3366 3367define void @test_int_x86_avx512_mask_pmovs_qb_mem_128(ptr %ptr, <2 x i64> %x1, i8 %x2) #0 {3368;3369; CHECK-LABEL: define void @test_int_x86_avx512_mask_pmovs_qb_mem_128(3370; CHECK-SAME: ptr [[PTR:%.*]], <2 x i64> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {3371; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 83372; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83373; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 83374; CHECK-NEXT: call void @llvm.donothing()3375; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03376; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP2]] to i1283377; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 03378; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3379; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]3380; CHECK: [[BB5]]:3381; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3382; CHECK-NEXT: unreachable3383; CHECK: [[BB6]]:3384; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovs.qb.mem.128(ptr [[PTR]], <2 x i64> [[X1]], i8 -1)3385; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 03386; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i64> [[TMP2]] to i1283387; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP7]], 03388; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]3389; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 03390; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]3391; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]3392; CHECK: [[BB8]]:3393; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3394; CHECK-NEXT: unreachable3395; CHECK: [[BB9]]:3396; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovs.qb.mem.128(ptr [[PTR]], <2 x i64> [[X1]], i8 [[X2]])3397; CHECK-NEXT: ret void3398;3399 call void @llvm.x86.avx512.mask.pmovs.qb.mem.128(ptr %ptr, <2 x i64> %x1, i8 -1)3400 call void @llvm.x86.avx512.mask.pmovs.qb.mem.128(ptr %ptr, <2 x i64> %x1, i8 %x2)3401 ret void3402}3403 3404declare <16 x i8> @llvm.x86.avx512.mask.pmovus.qb.128(<2 x i64>, <16 x i8>, i8)3405 3406define <16 x i8>@test_int_x86_avx512_mask_pmovus_qb_128(<2 x i64> %x0, <16 x i8> %x1, i8 %x2) #0 {3407;3408; CHECK-LABEL: define <16 x i8> @test_int_x86_avx512_mask_pmovus_qb_128(3409; CHECK-SAME: <2 x i64> [[X0:%.*]], <16 x i8> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {3410; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 83411; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83412; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 83413; CHECK-NEXT: call void @llvm.donothing()3414; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP1]] to i1283415; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 03416; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to i1283417; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 03418; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3419; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]3420; CHECK: [[BB6]]:3421; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3422; CHECK-NEXT: unreachable3423; CHECK: [[BB7]]:3424; CHECK-NEXT: [[RES0:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmovus.qb.128(<2 x i64> [[X0]], <16 x i8> [[X1]], i8 -1)3425; CHECK-NEXT: [[TMP8:%.*]] = bitcast <2 x i64> [[TMP1]] to i1283426; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP8]], 03427; CHECK-NEXT: [[TMP9:%.*]] = bitcast <16 x i8> [[TMP2]] to i1283428; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP9]], 03429; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]3430; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 03431; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]3432; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB10:.*]], label %[[BB11:.*]], !prof [[PROF1]]3433; CHECK: [[BB10]]:3434; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3435; CHECK-NEXT: unreachable3436; CHECK: [[BB11]]:3437; CHECK-NEXT: [[RES1:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmovus.qb.128(<2 x i64> [[X0]], <16 x i8> [[X1]], i8 [[X2]])3438; CHECK-NEXT: [[TMP12:%.*]] = bitcast <2 x i64> [[TMP1]] to i1283439; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i128 [[TMP12]], 03440; CHECK-NEXT: [[_MSCMP8:%.*]] = icmp ne i8 [[TMP3]], 03441; CHECK-NEXT: [[_MSOR9:%.*]] = or i1 [[_MSCMP7]], [[_MSCMP8]]3442; CHECK-NEXT: br i1 [[_MSOR9]], label %[[BB13:.*]], label %[[BB14:.*]], !prof [[PROF1]]3443; CHECK: [[BB13]]:3444; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3445; CHECK-NEXT: unreachable3446; CHECK: [[BB14]]:3447; CHECK-NEXT: [[RES2:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmovus.qb.128(<2 x i64> [[X0]], <16 x i8> zeroinitializer, i8 [[X2]])3448; CHECK-NEXT: [[RES3:%.*]] = add <16 x i8> [[RES0]], [[RES1]]3449; CHECK-NEXT: [[RES4:%.*]] = add <16 x i8> [[RES3]], [[RES2]]3450; CHECK-NEXT: store <16 x i8> zeroinitializer, ptr @__msan_retval_tls, align 83451; CHECK-NEXT: ret <16 x i8> [[RES4]]3452;3453 %res0 = call <16 x i8> @llvm.x86.avx512.mask.pmovus.qb.128(<2 x i64> %x0, <16 x i8> %x1, i8 -1)3454 %res1 = call <16 x i8> @llvm.x86.avx512.mask.pmovus.qb.128(<2 x i64> %x0, <16 x i8> %x1, i8 %x2)3455 %res2 = call <16 x i8> @llvm.x86.avx512.mask.pmovus.qb.128(<2 x i64> %x0, <16 x i8> zeroinitializer, i8 %x2)3456 %res3 = add <16 x i8> %res0, %res13457 %res4 = add <16 x i8> %res3, %res23458 ret <16 x i8> %res43459}3460 3461declare void @llvm.x86.avx512.mask.pmovus.qb.mem.128(ptr %ptr, <2 x i64>, i8)3462 3463define void @test_int_x86_avx512_mask_pmovus_qb_mem_128(ptr %ptr, <2 x i64> %x1, i8 %x2) #0 {3464;3465; CHECK-LABEL: define void @test_int_x86_avx512_mask_pmovus_qb_mem_128(3466; CHECK-SAME: ptr [[PTR:%.*]], <2 x i64> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {3467; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 83468; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83469; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 83470; CHECK-NEXT: call void @llvm.donothing()3471; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03472; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP2]] to i1283473; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 03474; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3475; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]3476; CHECK: [[BB5]]:3477; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3478; CHECK-NEXT: unreachable3479; CHECK: [[BB6]]:3480; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovus.qb.mem.128(ptr [[PTR]], <2 x i64> [[X1]], i8 -1)3481; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 03482; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i64> [[TMP2]] to i1283483; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP7]], 03484; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]3485; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 03486; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]3487; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]3488; CHECK: [[BB8]]:3489; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3490; CHECK-NEXT: unreachable3491; CHECK: [[BB9]]:3492; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovus.qb.mem.128(ptr [[PTR]], <2 x i64> [[X1]], i8 [[X2]])3493; CHECK-NEXT: ret void3494;3495 call void @llvm.x86.avx512.mask.pmovus.qb.mem.128(ptr %ptr, <2 x i64> %x1, i8 -1)3496 call void @llvm.x86.avx512.mask.pmovus.qb.mem.128(ptr %ptr, <2 x i64> %x1, i8 %x2)3497 ret void3498}3499 3500declare <16 x i8> @llvm.x86.avx512.mask.pmov.qb.256(<4 x i64>, <16 x i8>, i8)3501 3502define <16 x i8>@test_int_x86_avx512_mask_pmov_qb_256(<4 x i64> %x0, <16 x i8> %x1, i8 %x2) #0 {3503;3504; CHECK-LABEL: define <16 x i8> @test_int_x86_avx512_mask_pmov_qb_256(3505; CHECK-SAME: <4 x i64> [[X0:%.*]], <16 x i8> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {3506; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 83507; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 83508; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 83509; CHECK-NEXT: call void @llvm.donothing()3510; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i64> [[TMP1]] to i2563511; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP4]], 03512; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to i1283513; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 03514; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3515; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]3516; CHECK: [[BB6]]:3517; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3518; CHECK-NEXT: unreachable3519; CHECK: [[BB7]]:3520; CHECK-NEXT: [[RES0:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmov.qb.256(<4 x i64> [[X0]], <16 x i8> [[X1]], i8 -1)3521; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x i64> [[TMP1]] to i2563522; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i256 [[TMP8]], 03523; CHECK-NEXT: [[TMP9:%.*]] = bitcast <16 x i8> [[TMP2]] to i1283524; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP9]], 03525; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]3526; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 03527; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]3528; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB10:.*]], label %[[BB11:.*]], !prof [[PROF1]]3529; CHECK: [[BB10]]:3530; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3531; CHECK-NEXT: unreachable3532; CHECK: [[BB11]]:3533; CHECK-NEXT: [[RES1:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmov.qb.256(<4 x i64> [[X0]], <16 x i8> [[X1]], i8 [[X2]])3534; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i64> [[TMP1]] to i2563535; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i256 [[TMP12]], 03536; CHECK-NEXT: [[_MSCMP8:%.*]] = icmp ne i8 [[TMP3]], 03537; CHECK-NEXT: [[_MSOR9:%.*]] = or i1 [[_MSCMP7]], [[_MSCMP8]]3538; CHECK-NEXT: br i1 [[_MSOR9]], label %[[BB13:.*]], label %[[BB14:.*]], !prof [[PROF1]]3539; CHECK: [[BB13]]:3540; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3541; CHECK-NEXT: unreachable3542; CHECK: [[BB14]]:3543; CHECK-NEXT: [[RES2:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmov.qb.256(<4 x i64> [[X0]], <16 x i8> zeroinitializer, i8 [[X2]])3544; CHECK-NEXT: [[RES3:%.*]] = add <16 x i8> [[RES0]], [[RES1]]3545; CHECK-NEXT: [[RES4:%.*]] = add <16 x i8> [[RES3]], [[RES2]]3546; CHECK-NEXT: store <16 x i8> zeroinitializer, ptr @__msan_retval_tls, align 83547; CHECK-NEXT: ret <16 x i8> [[RES4]]3548;3549 %res0 = call <16 x i8> @llvm.x86.avx512.mask.pmov.qb.256(<4 x i64> %x0, <16 x i8> %x1, i8 -1)3550 %res1 = call <16 x i8> @llvm.x86.avx512.mask.pmov.qb.256(<4 x i64> %x0, <16 x i8> %x1, i8 %x2)3551 %res2 = call <16 x i8> @llvm.x86.avx512.mask.pmov.qb.256(<4 x i64> %x0, <16 x i8> zeroinitializer, i8 %x2)3552 %res3 = add <16 x i8> %res0, %res13553 %res4 = add <16 x i8> %res3, %res23554 ret <16 x i8> %res43555}3556 3557declare void @llvm.x86.avx512.mask.pmov.qb.mem.256(ptr %ptr, <4 x i64>, i8)3558 3559define void @test_int_x86_avx512_mask_pmov_qb_mem_256(ptr %ptr, <4 x i64> %x1, i8 %x2) #0 {3560;3561; CHECK-LABEL: define void @test_int_x86_avx512_mask_pmov_qb_mem_256(3562; CHECK-SAME: ptr [[PTR:%.*]], <4 x i64> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {3563; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 83564; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83565; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 83566; CHECK-NEXT: call void @llvm.donothing()3567; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03568; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i64> [[TMP2]] to i2563569; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP4]], 03570; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3571; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]3572; CHECK: [[BB5]]:3573; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3574; CHECK-NEXT: unreachable3575; CHECK: [[BB6]]:3576; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmov.qb.mem.256(ptr [[PTR]], <4 x i64> [[X1]], i8 -1)3577; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 03578; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i64> [[TMP2]] to i2563579; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i256 [[TMP7]], 03580; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]3581; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 03582; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]3583; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]3584; CHECK: [[BB8]]:3585; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3586; CHECK-NEXT: unreachable3587; CHECK: [[BB9]]:3588; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmov.qb.mem.256(ptr [[PTR]], <4 x i64> [[X1]], i8 [[X2]])3589; CHECK-NEXT: ret void3590;3591 call void @llvm.x86.avx512.mask.pmov.qb.mem.256(ptr %ptr, <4 x i64> %x1, i8 -1)3592 call void @llvm.x86.avx512.mask.pmov.qb.mem.256(ptr %ptr, <4 x i64> %x1, i8 %x2)3593 ret void3594}3595 3596declare <16 x i8> @llvm.x86.avx512.mask.pmovs.qb.256(<4 x i64>, <16 x i8>, i8)3597 3598define <16 x i8>@test_int_x86_avx512_mask_pmovs_qb_256(<4 x i64> %x0, <16 x i8> %x1, i8 %x2) #0 {3599;3600; CHECK-LABEL: define <16 x i8> @test_int_x86_avx512_mask_pmovs_qb_256(3601; CHECK-SAME: <4 x i64> [[X0:%.*]], <16 x i8> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {3602; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 83603; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 83604; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 83605; CHECK-NEXT: call void @llvm.donothing()3606; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i64> [[TMP1]] to i2563607; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP4]], 03608; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to i1283609; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 03610; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3611; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]3612; CHECK: [[BB6]]:3613; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3614; CHECK-NEXT: unreachable3615; CHECK: [[BB7]]:3616; CHECK-NEXT: [[RES0:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmovs.qb.256(<4 x i64> [[X0]], <16 x i8> [[X1]], i8 -1)3617; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x i64> [[TMP1]] to i2563618; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i256 [[TMP8]], 03619; CHECK-NEXT: [[TMP9:%.*]] = bitcast <16 x i8> [[TMP2]] to i1283620; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP9]], 03621; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]3622; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 03623; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]3624; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB10:.*]], label %[[BB11:.*]], !prof [[PROF1]]3625; CHECK: [[BB10]]:3626; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3627; CHECK-NEXT: unreachable3628; CHECK: [[BB11]]:3629; CHECK-NEXT: [[RES1:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmovs.qb.256(<4 x i64> [[X0]], <16 x i8> [[X1]], i8 [[X2]])3630; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i64> [[TMP1]] to i2563631; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i256 [[TMP12]], 03632; CHECK-NEXT: [[_MSCMP8:%.*]] = icmp ne i8 [[TMP3]], 03633; CHECK-NEXT: [[_MSOR9:%.*]] = or i1 [[_MSCMP7]], [[_MSCMP8]]3634; CHECK-NEXT: br i1 [[_MSOR9]], label %[[BB13:.*]], label %[[BB14:.*]], !prof [[PROF1]]3635; CHECK: [[BB13]]:3636; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3637; CHECK-NEXT: unreachable3638; CHECK: [[BB14]]:3639; CHECK-NEXT: [[RES2:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmovs.qb.256(<4 x i64> [[X0]], <16 x i8> zeroinitializer, i8 [[X2]])3640; CHECK-NEXT: [[RES3:%.*]] = add <16 x i8> [[RES0]], [[RES1]]3641; CHECK-NEXT: [[RES4:%.*]] = add <16 x i8> [[RES3]], [[RES2]]3642; CHECK-NEXT: store <16 x i8> zeroinitializer, ptr @__msan_retval_tls, align 83643; CHECK-NEXT: ret <16 x i8> [[RES4]]3644;3645 %res0 = call <16 x i8> @llvm.x86.avx512.mask.pmovs.qb.256(<4 x i64> %x0, <16 x i8> %x1, i8 -1)3646 %res1 = call <16 x i8> @llvm.x86.avx512.mask.pmovs.qb.256(<4 x i64> %x0, <16 x i8> %x1, i8 %x2)3647 %res2 = call <16 x i8> @llvm.x86.avx512.mask.pmovs.qb.256(<4 x i64> %x0, <16 x i8> zeroinitializer, i8 %x2)3648 %res3 = add <16 x i8> %res0, %res13649 %res4 = add <16 x i8> %res3, %res23650 ret <16 x i8> %res43651}3652 3653declare void @llvm.x86.avx512.mask.pmovs.qb.mem.256(ptr %ptr, <4 x i64>, i8)3654 3655define void @test_int_x86_avx512_mask_pmovs_qb_mem_256(ptr %ptr, <4 x i64> %x1, i8 %x2) #0 {3656;3657; CHECK-LABEL: define void @test_int_x86_avx512_mask_pmovs_qb_mem_256(3658; CHECK-SAME: ptr [[PTR:%.*]], <4 x i64> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {3659; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 83660; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83661; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 83662; CHECK-NEXT: call void @llvm.donothing()3663; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03664; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i64> [[TMP2]] to i2563665; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP4]], 03666; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3667; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]3668; CHECK: [[BB5]]:3669; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3670; CHECK-NEXT: unreachable3671; CHECK: [[BB6]]:3672; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovs.qb.mem.256(ptr [[PTR]], <4 x i64> [[X1]], i8 -1)3673; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 03674; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i64> [[TMP2]] to i2563675; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i256 [[TMP7]], 03676; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]3677; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 03678; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]3679; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]3680; CHECK: [[BB8]]:3681; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3682; CHECK-NEXT: unreachable3683; CHECK: [[BB9]]:3684; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovs.qb.mem.256(ptr [[PTR]], <4 x i64> [[X1]], i8 [[X2]])3685; CHECK-NEXT: ret void3686;3687 call void @llvm.x86.avx512.mask.pmovs.qb.mem.256(ptr %ptr, <4 x i64> %x1, i8 -1)3688 call void @llvm.x86.avx512.mask.pmovs.qb.mem.256(ptr %ptr, <4 x i64> %x1, i8 %x2)3689 ret void3690}3691 3692declare <16 x i8> @llvm.x86.avx512.mask.pmovus.qb.256(<4 x i64>, <16 x i8>, i8)3693 3694define <16 x i8>@test_int_x86_avx512_mask_pmovus_qb_256(<4 x i64> %x0, <16 x i8> %x1, i8 %x2) #0 {3695;3696; CHECK-LABEL: define <16 x i8> @test_int_x86_avx512_mask_pmovus_qb_256(3697; CHECK-SAME: <4 x i64> [[X0:%.*]], <16 x i8> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {3698; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 83699; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 83700; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 83701; CHECK-NEXT: call void @llvm.donothing()3702; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i64> [[TMP1]] to i2563703; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP4]], 03704; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to i1283705; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 03706; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3707; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]3708; CHECK: [[BB6]]:3709; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3710; CHECK-NEXT: unreachable3711; CHECK: [[BB7]]:3712; CHECK-NEXT: [[RES0:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmovus.qb.256(<4 x i64> [[X0]], <16 x i8> [[X1]], i8 -1)3713; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x i64> [[TMP1]] to i2563714; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i256 [[TMP8]], 03715; CHECK-NEXT: [[TMP9:%.*]] = bitcast <16 x i8> [[TMP2]] to i1283716; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP9]], 03717; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]3718; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 03719; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]3720; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB10:.*]], label %[[BB11:.*]], !prof [[PROF1]]3721; CHECK: [[BB10]]:3722; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3723; CHECK-NEXT: unreachable3724; CHECK: [[BB11]]:3725; CHECK-NEXT: [[RES1:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmovus.qb.256(<4 x i64> [[X0]], <16 x i8> [[X1]], i8 [[X2]])3726; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i64> [[TMP1]] to i2563727; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i256 [[TMP12]], 03728; CHECK-NEXT: [[_MSCMP8:%.*]] = icmp ne i8 [[TMP3]], 03729; CHECK-NEXT: [[_MSOR9:%.*]] = or i1 [[_MSCMP7]], [[_MSCMP8]]3730; CHECK-NEXT: br i1 [[_MSOR9]], label %[[BB13:.*]], label %[[BB14:.*]], !prof [[PROF1]]3731; CHECK: [[BB13]]:3732; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3733; CHECK-NEXT: unreachable3734; CHECK: [[BB14]]:3735; CHECK-NEXT: [[RES2:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmovus.qb.256(<4 x i64> [[X0]], <16 x i8> zeroinitializer, i8 [[X2]])3736; CHECK-NEXT: [[RES3:%.*]] = add <16 x i8> [[RES0]], [[RES1]]3737; CHECK-NEXT: [[RES4:%.*]] = add <16 x i8> [[RES3]], [[RES2]]3738; CHECK-NEXT: store <16 x i8> zeroinitializer, ptr @__msan_retval_tls, align 83739; CHECK-NEXT: ret <16 x i8> [[RES4]]3740;3741 %res0 = call <16 x i8> @llvm.x86.avx512.mask.pmovus.qb.256(<4 x i64> %x0, <16 x i8> %x1, i8 -1)3742 %res1 = call <16 x i8> @llvm.x86.avx512.mask.pmovus.qb.256(<4 x i64> %x0, <16 x i8> %x1, i8 %x2)3743 %res2 = call <16 x i8> @llvm.x86.avx512.mask.pmovus.qb.256(<4 x i64> %x0, <16 x i8> zeroinitializer, i8 %x2)3744 %res3 = add <16 x i8> %res0, %res13745 %res4 = add <16 x i8> %res3, %res23746 ret <16 x i8> %res43747}3748 3749declare void @llvm.x86.avx512.mask.pmovus.qb.mem.256(ptr %ptr, <4 x i64>, i8)3750 3751define void @test_int_x86_avx512_mask_pmovus_qb_mem_256(ptr %ptr, <4 x i64> %x1, i8 %x2) #0 {3752;3753; CHECK-LABEL: define void @test_int_x86_avx512_mask_pmovus_qb_mem_256(3754; CHECK-SAME: ptr [[PTR:%.*]], <4 x i64> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {3755; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 83756; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83757; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 83758; CHECK-NEXT: call void @llvm.donothing()3759; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03760; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i64> [[TMP2]] to i2563761; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP4]], 03762; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3763; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]3764; CHECK: [[BB5]]:3765; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3766; CHECK-NEXT: unreachable3767; CHECK: [[BB6]]:3768; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovus.qb.mem.256(ptr [[PTR]], <4 x i64> [[X1]], i8 -1)3769; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 03770; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i64> [[TMP2]] to i2563771; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i256 [[TMP7]], 03772; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]3773; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 03774; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]3775; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]3776; CHECK: [[BB8]]:3777; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3778; CHECK-NEXT: unreachable3779; CHECK: [[BB9]]:3780; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovus.qb.mem.256(ptr [[PTR]], <4 x i64> [[X1]], i8 [[X2]])3781; CHECK-NEXT: ret void3782;3783 call void @llvm.x86.avx512.mask.pmovus.qb.mem.256(ptr %ptr, <4 x i64> %x1, i8 -1)3784 call void @llvm.x86.avx512.mask.pmovus.qb.mem.256(ptr %ptr, <4 x i64> %x1, i8 %x2)3785 ret void3786}3787 3788declare <8 x i16> @llvm.x86.avx512.mask.pmov.qw.128(<2 x i64>, <8 x i16>, i8)3789 3790define <8 x i16>@test_int_x86_avx512_mask_pmov_qw_128(<2 x i64> %x0, <8 x i16> %x1, i8 %x2) #0 {3791;3792; CHECK-LABEL: define <8 x i16> @test_int_x86_avx512_mask_pmov_qw_128(3793; CHECK-SAME: <2 x i64> [[X0:%.*]], <8 x i16> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {3794; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 83795; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83796; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 83797; CHECK-NEXT: call void @llvm.donothing()3798; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP1]] to i1283799; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 03800; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP2]] to i1283801; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 03802; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3803; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]3804; CHECK: [[BB6]]:3805; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3806; CHECK-NEXT: unreachable3807; CHECK: [[BB7]]:3808; CHECK-NEXT: [[RES0:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmov.qw.128(<2 x i64> [[X0]], <8 x i16> [[X1]], i8 -1)3809; CHECK-NEXT: [[TMP8:%.*]] = bitcast <2 x i64> [[TMP1]] to i1283810; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP8]], 03811; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i16> [[TMP2]] to i1283812; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP9]], 03813; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]3814; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 03815; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]3816; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB10:.*]], label %[[BB11:.*]], !prof [[PROF1]]3817; CHECK: [[BB10]]:3818; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3819; CHECK-NEXT: unreachable3820; CHECK: [[BB11]]:3821; CHECK-NEXT: [[RES1:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmov.qw.128(<2 x i64> [[X0]], <8 x i16> [[X1]], i8 [[X2]])3822; CHECK-NEXT: [[TMP12:%.*]] = bitcast <2 x i64> [[TMP1]] to i1283823; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i128 [[TMP12]], 03824; CHECK-NEXT: [[_MSCMP8:%.*]] = icmp ne i8 [[TMP3]], 03825; CHECK-NEXT: [[_MSOR9:%.*]] = or i1 [[_MSCMP7]], [[_MSCMP8]]3826; CHECK-NEXT: br i1 [[_MSOR9]], label %[[BB13:.*]], label %[[BB14:.*]], !prof [[PROF1]]3827; CHECK: [[BB13]]:3828; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3829; CHECK-NEXT: unreachable3830; CHECK: [[BB14]]:3831; CHECK-NEXT: [[RES2:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmov.qw.128(<2 x i64> [[X0]], <8 x i16> zeroinitializer, i8 [[X2]])3832; CHECK-NEXT: [[RES3:%.*]] = add <8 x i16> [[RES0]], [[RES1]]3833; CHECK-NEXT: [[RES4:%.*]] = add <8 x i16> [[RES3]], [[RES2]]3834; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 83835; CHECK-NEXT: ret <8 x i16> [[RES4]]3836;3837 %res0 = call <8 x i16> @llvm.x86.avx512.mask.pmov.qw.128(<2 x i64> %x0, <8 x i16> %x1, i8 -1)3838 %res1 = call <8 x i16> @llvm.x86.avx512.mask.pmov.qw.128(<2 x i64> %x0, <8 x i16> %x1, i8 %x2)3839 %res2 = call <8 x i16> @llvm.x86.avx512.mask.pmov.qw.128(<2 x i64> %x0, <8 x i16> zeroinitializer, i8 %x2)3840 %res3 = add <8 x i16> %res0, %res13841 %res4 = add <8 x i16> %res3, %res23842 ret <8 x i16> %res43843}3844 3845declare void @llvm.x86.avx512.mask.pmov.qw.mem.128(ptr %ptr, <2 x i64>, i8)3846 3847define void @test_int_x86_avx512_mask_pmov_qw_mem_128(ptr %ptr, <2 x i64> %x1, i8 %x2) #0 {3848;3849; CHECK-LABEL: define void @test_int_x86_avx512_mask_pmov_qw_mem_128(3850; CHECK-SAME: ptr [[PTR:%.*]], <2 x i64> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {3851; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 83852; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83853; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 83854; CHECK-NEXT: call void @llvm.donothing()3855; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03856; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP2]] to i1283857; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 03858; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3859; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]3860; CHECK: [[BB5]]:3861; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3862; CHECK-NEXT: unreachable3863; CHECK: [[BB6]]:3864; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmov.qw.mem.128(ptr [[PTR]], <2 x i64> [[X1]], i8 -1)3865; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 03866; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i64> [[TMP2]] to i1283867; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP7]], 03868; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]3869; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 03870; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]3871; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]3872; CHECK: [[BB8]]:3873; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3874; CHECK-NEXT: unreachable3875; CHECK: [[BB9]]:3876; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmov.qw.mem.128(ptr [[PTR]], <2 x i64> [[X1]], i8 [[X2]])3877; CHECK-NEXT: ret void3878;3879 call void @llvm.x86.avx512.mask.pmov.qw.mem.128(ptr %ptr, <2 x i64> %x1, i8 -1)3880 call void @llvm.x86.avx512.mask.pmov.qw.mem.128(ptr %ptr, <2 x i64> %x1, i8 %x2)3881 ret void3882}3883 3884declare <8 x i16> @llvm.x86.avx512.mask.pmovs.qw.128(<2 x i64>, <8 x i16>, i8)3885 3886define <8 x i16>@test_int_x86_avx512_mask_pmovs_qw_128(<2 x i64> %x0, <8 x i16> %x1, i8 %x2) #0 {3887;3888; CHECK-LABEL: define <8 x i16> @test_int_x86_avx512_mask_pmovs_qw_128(3889; CHECK-SAME: <2 x i64> [[X0:%.*]], <8 x i16> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {3890; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 83891; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83892; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 83893; CHECK-NEXT: call void @llvm.donothing()3894; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP1]] to i1283895; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 03896; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP2]] to i1283897; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 03898; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3899; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]3900; CHECK: [[BB6]]:3901; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3902; CHECK-NEXT: unreachable3903; CHECK: [[BB7]]:3904; CHECK-NEXT: [[RES0:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmovs.qw.128(<2 x i64> [[X0]], <8 x i16> [[X1]], i8 -1)3905; CHECK-NEXT: [[TMP8:%.*]] = bitcast <2 x i64> [[TMP1]] to i1283906; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP8]], 03907; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i16> [[TMP2]] to i1283908; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP9]], 03909; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]3910; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 03911; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]3912; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB10:.*]], label %[[BB11:.*]], !prof [[PROF1]]3913; CHECK: [[BB10]]:3914; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3915; CHECK-NEXT: unreachable3916; CHECK: [[BB11]]:3917; CHECK-NEXT: [[RES1:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmovs.qw.128(<2 x i64> [[X0]], <8 x i16> [[X1]], i8 [[X2]])3918; CHECK-NEXT: [[TMP12:%.*]] = bitcast <2 x i64> [[TMP1]] to i1283919; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i128 [[TMP12]], 03920; CHECK-NEXT: [[_MSCMP8:%.*]] = icmp ne i8 [[TMP3]], 03921; CHECK-NEXT: [[_MSOR9:%.*]] = or i1 [[_MSCMP7]], [[_MSCMP8]]3922; CHECK-NEXT: br i1 [[_MSOR9]], label %[[BB13:.*]], label %[[BB14:.*]], !prof [[PROF1]]3923; CHECK: [[BB13]]:3924; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3925; CHECK-NEXT: unreachable3926; CHECK: [[BB14]]:3927; CHECK-NEXT: [[RES2:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmovs.qw.128(<2 x i64> [[X0]], <8 x i16> zeroinitializer, i8 [[X2]])3928; CHECK-NEXT: [[RES3:%.*]] = add <8 x i16> [[RES0]], [[RES1]]3929; CHECK-NEXT: [[RES4:%.*]] = add <8 x i16> [[RES3]], [[RES2]]3930; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 83931; CHECK-NEXT: ret <8 x i16> [[RES4]]3932;3933 %res0 = call <8 x i16> @llvm.x86.avx512.mask.pmovs.qw.128(<2 x i64> %x0, <8 x i16> %x1, i8 -1)3934 %res1 = call <8 x i16> @llvm.x86.avx512.mask.pmovs.qw.128(<2 x i64> %x0, <8 x i16> %x1, i8 %x2)3935 %res2 = call <8 x i16> @llvm.x86.avx512.mask.pmovs.qw.128(<2 x i64> %x0, <8 x i16> zeroinitializer, i8 %x2)3936 %res3 = add <8 x i16> %res0, %res13937 %res4 = add <8 x i16> %res3, %res23938 ret <8 x i16> %res43939}3940 3941declare void @llvm.x86.avx512.mask.pmovs.qw.mem.128(ptr %ptr, <2 x i64>, i8)3942 3943define void @test_int_x86_avx512_mask_pmovs_qw_mem_128(ptr %ptr, <2 x i64> %x1, i8 %x2) #0 {3944;3945; CHECK-LABEL: define void @test_int_x86_avx512_mask_pmovs_qw_mem_128(3946; CHECK-SAME: ptr [[PTR:%.*]], <2 x i64> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {3947; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 83948; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83949; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 83950; CHECK-NEXT: call void @llvm.donothing()3951; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03952; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP2]] to i1283953; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 03954; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3955; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]3956; CHECK: [[BB5]]:3957; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3958; CHECK-NEXT: unreachable3959; CHECK: [[BB6]]:3960; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovs.qw.mem.128(ptr [[PTR]], <2 x i64> [[X1]], i8 -1)3961; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 03962; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i64> [[TMP2]] to i1283963; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP7]], 03964; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]3965; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 03966; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]3967; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]3968; CHECK: [[BB8]]:3969; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3970; CHECK-NEXT: unreachable3971; CHECK: [[BB9]]:3972; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovs.qw.mem.128(ptr [[PTR]], <2 x i64> [[X1]], i8 [[X2]])3973; CHECK-NEXT: ret void3974;3975 call void @llvm.x86.avx512.mask.pmovs.qw.mem.128(ptr %ptr, <2 x i64> %x1, i8 -1)3976 call void @llvm.x86.avx512.mask.pmovs.qw.mem.128(ptr %ptr, <2 x i64> %x1, i8 %x2)3977 ret void3978}3979 3980declare <8 x i16> @llvm.x86.avx512.mask.pmovus.qw.128(<2 x i64>, <8 x i16>, i8)3981 3982define <8 x i16>@test_int_x86_avx512_mask_pmovus_qw_128(<2 x i64> %x0, <8 x i16> %x1, i8 %x2) #0 {3983;3984; CHECK-LABEL: define <8 x i16> @test_int_x86_avx512_mask_pmovus_qw_128(3985; CHECK-SAME: <2 x i64> [[X0:%.*]], <8 x i16> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {3986; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 83987; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83988; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 83989; CHECK-NEXT: call void @llvm.donothing()3990; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP1]] to i1283991; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 03992; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP2]] to i1283993; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 03994; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3995; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]3996; CHECK: [[BB6]]:3997; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3998; CHECK-NEXT: unreachable3999; CHECK: [[BB7]]:4000; CHECK-NEXT: [[RES0:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmovus.qw.128(<2 x i64> [[X0]], <8 x i16> [[X1]], i8 -1)4001; CHECK-NEXT: [[TMP8:%.*]] = bitcast <2 x i64> [[TMP1]] to i1284002; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP8]], 04003; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i16> [[TMP2]] to i1284004; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP9]], 04005; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]4006; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 04007; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]4008; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB10:.*]], label %[[BB11:.*]], !prof [[PROF1]]4009; CHECK: [[BB10]]:4010; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]4011; CHECK-NEXT: unreachable4012; CHECK: [[BB11]]:4013; CHECK-NEXT: [[RES1:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmovus.qw.128(<2 x i64> [[X0]], <8 x i16> [[X1]], i8 [[X2]])4014; CHECK-NEXT: [[TMP12:%.*]] = bitcast <2 x i64> [[TMP1]] to i1284015; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i128 [[TMP12]], 04016; CHECK-NEXT: [[_MSCMP8:%.*]] = icmp ne i8 [[TMP3]], 04017; CHECK-NEXT: [[_MSOR9:%.*]] = or i1 [[_MSCMP7]], [[_MSCMP8]]4018; CHECK-NEXT: br i1 [[_MSOR9]], label %[[BB13:.*]], label %[[BB14:.*]], !prof [[PROF1]]4019; CHECK: [[BB13]]:4020; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]4021; CHECK-NEXT: unreachable4022; CHECK: [[BB14]]:4023; CHECK-NEXT: [[RES2:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmovus.qw.128(<2 x i64> [[X0]], <8 x i16> zeroinitializer, i8 [[X2]])4024; CHECK-NEXT: [[RES3:%.*]] = add <8 x i16> [[RES0]], [[RES1]]4025; CHECK-NEXT: [[RES4:%.*]] = add <8 x i16> [[RES3]], [[RES2]]4026; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 84027; CHECK-NEXT: ret <8 x i16> [[RES4]]4028;4029 %res0 = call <8 x i16> @llvm.x86.avx512.mask.pmovus.qw.128(<2 x i64> %x0, <8 x i16> %x1, i8 -1)4030 %res1 = call <8 x i16> @llvm.x86.avx512.mask.pmovus.qw.128(<2 x i64> %x0, <8 x i16> %x1, i8 %x2)4031 %res2 = call <8 x i16> @llvm.x86.avx512.mask.pmovus.qw.128(<2 x i64> %x0, <8 x i16> zeroinitializer, i8 %x2)4032 %res3 = add <8 x i16> %res0, %res14033 %res4 = add <8 x i16> %res3, %res24034 ret <8 x i16> %res44035}4036 4037declare void @llvm.x86.avx512.mask.pmovus.qw.mem.128(ptr %ptr, <2 x i64>, i8)4038 4039define void @test_int_x86_avx512_mask_pmovus_qw_mem_128(ptr %ptr, <2 x i64> %x1, i8 %x2) #0 {4040;4041; CHECK-LABEL: define void @test_int_x86_avx512_mask_pmovus_qw_mem_128(4042; CHECK-SAME: ptr [[PTR:%.*]], <2 x i64> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {4043; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 84044; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 84045; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 84046; CHECK-NEXT: call void @llvm.donothing()4047; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 04048; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP2]] to i1284049; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 04050; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]4051; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]4052; CHECK: [[BB5]]:4053; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]4054; CHECK-NEXT: unreachable4055; CHECK: [[BB6]]:4056; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovus.qw.mem.128(ptr [[PTR]], <2 x i64> [[X1]], i8 -1)4057; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 04058; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i64> [[TMP2]] to i1284059; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP7]], 04060; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]4061; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 04062; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]4063; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]4064; CHECK: [[BB8]]:4065; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]4066; CHECK-NEXT: unreachable4067; CHECK: [[BB9]]:4068; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovus.qw.mem.128(ptr [[PTR]], <2 x i64> [[X1]], i8 [[X2]])4069; CHECK-NEXT: ret void4070;4071 call void @llvm.x86.avx512.mask.pmovus.qw.mem.128(ptr %ptr, <2 x i64> %x1, i8 -1)4072 call void @llvm.x86.avx512.mask.pmovus.qw.mem.128(ptr %ptr, <2 x i64> %x1, i8 %x2)4073 ret void4074}4075 4076declare <8 x i16> @llvm.x86.avx512.mask.pmov.qw.256(<4 x i64>, <8 x i16>, i8)4077 4078define <8 x i16>@test_int_x86_avx512_mask_pmov_qw_256(<4 x i64> %x0, <8 x i16> %x1, i8 %x2) #0 {4079;4080; CHECK-LABEL: define <8 x i16> @test_int_x86_avx512_mask_pmov_qw_256(4081; CHECK-SAME: <4 x i64> [[X0:%.*]], <8 x i16> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {4082; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 84083; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 84084; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 84085; CHECK-NEXT: call void @llvm.donothing()4086; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i64> [[TMP1]] to i2564087; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP4]], 04088; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP2]] to i1284089; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 04090; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]4091; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]4092; CHECK: [[BB6]]:4093; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]4094; CHECK-NEXT: unreachable4095; CHECK: [[BB7]]:4096; CHECK-NEXT: [[RES0:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmov.qw.256(<4 x i64> [[X0]], <8 x i16> [[X1]], i8 -1)4097; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x i64> [[TMP1]] to i2564098; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i256 [[TMP8]], 04099; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i16> [[TMP2]] to i1284100; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP9]], 04101; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]4102; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 04103; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]4104; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB10:.*]], label %[[BB11:.*]], !prof [[PROF1]]4105; CHECK: [[BB10]]:4106; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]4107; CHECK-NEXT: unreachable4108; CHECK: [[BB11]]:4109; CHECK-NEXT: [[RES1:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmov.qw.256(<4 x i64> [[X0]], <8 x i16> [[X1]], i8 [[X2]])4110; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i64> [[TMP1]] to i2564111; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i256 [[TMP12]], 04112; CHECK-NEXT: [[_MSCMP8:%.*]] = icmp ne i8 [[TMP3]], 04113; CHECK-NEXT: [[_MSOR9:%.*]] = or i1 [[_MSCMP7]], [[_MSCMP8]]4114; CHECK-NEXT: br i1 [[_MSOR9]], label %[[BB13:.*]], label %[[BB14:.*]], !prof [[PROF1]]4115; CHECK: [[BB13]]:4116; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]4117; CHECK-NEXT: unreachable4118; CHECK: [[BB14]]:4119; CHECK-NEXT: [[RES2:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmov.qw.256(<4 x i64> [[X0]], <8 x i16> zeroinitializer, i8 [[X2]])4120; CHECK-NEXT: [[RES3:%.*]] = add <8 x i16> [[RES0]], [[RES1]]4121; CHECK-NEXT: [[RES4:%.*]] = add <8 x i16> [[RES3]], [[RES2]]4122; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 84123; CHECK-NEXT: ret <8 x i16> [[RES4]]4124;4125 %res0 = call <8 x i16> @llvm.x86.avx512.mask.pmov.qw.256(<4 x i64> %x0, <8 x i16> %x1, i8 -1)4126 %res1 = call <8 x i16> @llvm.x86.avx512.mask.pmov.qw.256(<4 x i64> %x0, <8 x i16> %x1, i8 %x2)4127 %res2 = call <8 x i16> @llvm.x86.avx512.mask.pmov.qw.256(<4 x i64> %x0, <8 x i16> zeroinitializer, i8 %x2)4128 %res3 = add <8 x i16> %res0, %res14129 %res4 = add <8 x i16> %res3, %res24130 ret <8 x i16> %res44131}4132 4133declare void @llvm.x86.avx512.mask.pmov.qw.mem.256(ptr %ptr, <4 x i64>, i8)4134 4135define void @test_int_x86_avx512_mask_pmov_qw_mem_256(ptr %ptr, <4 x i64> %x1, i8 %x2) #0 {4136;4137; CHECK-LABEL: define void @test_int_x86_avx512_mask_pmov_qw_mem_256(4138; CHECK-SAME: ptr [[PTR:%.*]], <4 x i64> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {4139; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 84140; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 84141; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 84142; CHECK-NEXT: call void @llvm.donothing()4143; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 04144; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i64> [[TMP2]] to i2564145; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP4]], 04146; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]4147; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]4148; CHECK: [[BB5]]:4149; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]4150; CHECK-NEXT: unreachable4151; CHECK: [[BB6]]:4152; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmov.qw.mem.256(ptr [[PTR]], <4 x i64> [[X1]], i8 -1)4153; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 04154; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i64> [[TMP2]] to i2564155; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i256 [[TMP7]], 04156; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]4157; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 04158; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]4159; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]4160; CHECK: [[BB8]]:4161; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]4162; CHECK-NEXT: unreachable4163; CHECK: [[BB9]]:4164; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmov.qw.mem.256(ptr [[PTR]], <4 x i64> [[X1]], i8 [[X2]])4165; CHECK-NEXT: ret void4166;4167 call void @llvm.x86.avx512.mask.pmov.qw.mem.256(ptr %ptr, <4 x i64> %x1, i8 -1)4168 call void @llvm.x86.avx512.mask.pmov.qw.mem.256(ptr %ptr, <4 x i64> %x1, i8 %x2)4169 ret void4170}4171 4172declare <8 x i16> @llvm.x86.avx512.mask.pmovs.qw.256(<4 x i64>, <8 x i16>, i8)4173 4174define <8 x i16>@test_int_x86_avx512_mask_pmovs_qw_256(<4 x i64> %x0, <8 x i16> %x1, i8 %x2) #0 {4175;4176; CHECK-LABEL: define <8 x i16> @test_int_x86_avx512_mask_pmovs_qw_256(4177; CHECK-SAME: <4 x i64> [[X0:%.*]], <8 x i16> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {4178; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 84179; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 84180; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 84181; CHECK-NEXT: call void @llvm.donothing()4182; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i64> [[TMP1]] to i2564183; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP4]], 04184; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP2]] to i1284185; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 04186; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]4187; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]4188; CHECK: [[BB6]]:4189; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]4190; CHECK-NEXT: unreachable4191; CHECK: [[BB7]]:4192; CHECK-NEXT: [[RES0:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmovs.qw.256(<4 x i64> [[X0]], <8 x i16> [[X1]], i8 -1)4193; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x i64> [[TMP1]] to i2564194; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i256 [[TMP8]], 04195; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i16> [[TMP2]] to i1284196; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP9]], 04197; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]4198; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 04199; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]4200; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB10:.*]], label %[[BB11:.*]], !prof [[PROF1]]4201; CHECK: [[BB10]]:4202; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]4203; CHECK-NEXT: unreachable4204; CHECK: [[BB11]]:4205; CHECK-NEXT: [[RES1:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmovs.qw.256(<4 x i64> [[X0]], <8 x i16> [[X1]], i8 [[X2]])4206; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i64> [[TMP1]] to i2564207; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i256 [[TMP12]], 04208; CHECK-NEXT: [[_MSCMP8:%.*]] = icmp ne i8 [[TMP3]], 04209; CHECK-NEXT: [[_MSOR9:%.*]] = or i1 [[_MSCMP7]], [[_MSCMP8]]4210; CHECK-NEXT: br i1 [[_MSOR9]], label %[[BB13:.*]], label %[[BB14:.*]], !prof [[PROF1]]4211; CHECK: [[BB13]]:4212; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]4213; CHECK-NEXT: unreachable4214; CHECK: [[BB14]]:4215; CHECK-NEXT: [[RES2:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmovs.qw.256(<4 x i64> [[X0]], <8 x i16> zeroinitializer, i8 [[X2]])4216; CHECK-NEXT: [[RES3:%.*]] = add <8 x i16> [[RES0]], [[RES1]]4217; CHECK-NEXT: [[RES4:%.*]] = add <8 x i16> [[RES3]], [[RES2]]4218; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 84219; CHECK-NEXT: ret <8 x i16> [[RES4]]4220;4221 %res0 = call <8 x i16> @llvm.x86.avx512.mask.pmovs.qw.256(<4 x i64> %x0, <8 x i16> %x1, i8 -1)4222 %res1 = call <8 x i16> @llvm.x86.avx512.mask.pmovs.qw.256(<4 x i64> %x0, <8 x i16> %x1, i8 %x2)4223 %res2 = call <8 x i16> @llvm.x86.avx512.mask.pmovs.qw.256(<4 x i64> %x0, <8 x i16> zeroinitializer, i8 %x2)4224 %res3 = add <8 x i16> %res0, %res14225 %res4 = add <8 x i16> %res3, %res24226 ret <8 x i16> %res44227}4228 4229declare void @llvm.x86.avx512.mask.pmovs.qw.mem.256(ptr %ptr, <4 x i64>, i8)4230 4231define void @test_int_x86_avx512_mask_pmovs_qw_mem_256(ptr %ptr, <4 x i64> %x1, i8 %x2) #0 {4232;4233; CHECK-LABEL: define void @test_int_x86_avx512_mask_pmovs_qw_mem_256(4234; CHECK-SAME: ptr [[PTR:%.*]], <4 x i64> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {4235; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 84236; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 84237; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 84238; CHECK-NEXT: call void @llvm.donothing()4239; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 04240; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i64> [[TMP2]] to i2564241; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP4]], 04242; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]4243; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]4244; CHECK: [[BB5]]:4245; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]4246; CHECK-NEXT: unreachable4247; CHECK: [[BB6]]:4248; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovs.qw.mem.256(ptr [[PTR]], <4 x i64> [[X1]], i8 -1)4249; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 04250; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i64> [[TMP2]] to i2564251; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i256 [[TMP7]], 04252; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]4253; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 04254; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]4255; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]4256; CHECK: [[BB8]]:4257; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]4258; CHECK-NEXT: unreachable4259; CHECK: [[BB9]]:4260; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovs.qw.mem.256(ptr [[PTR]], <4 x i64> [[X1]], i8 [[X2]])4261; CHECK-NEXT: ret void4262;4263 call void @llvm.x86.avx512.mask.pmovs.qw.mem.256(ptr %ptr, <4 x i64> %x1, i8 -1)4264 call void @llvm.x86.avx512.mask.pmovs.qw.mem.256(ptr %ptr, <4 x i64> %x1, i8 %x2)4265 ret void4266}4267 4268declare <8 x i16> @llvm.x86.avx512.mask.pmovus.qw.256(<4 x i64>, <8 x i16>, i8)4269 4270define <8 x i16>@test_int_x86_avx512_mask_pmovus_qw_256(<4 x i64> %x0, <8 x i16> %x1, i8 %x2) #0 {4271;4272; CHECK-LABEL: define <8 x i16> @test_int_x86_avx512_mask_pmovus_qw_256(4273; CHECK-SAME: <4 x i64> [[X0:%.*]], <8 x i16> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {4274; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 84275; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 84276; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 84277; CHECK-NEXT: call void @llvm.donothing()4278; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i64> [[TMP1]] to i2564279; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP4]], 04280; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP2]] to i1284281; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 04282; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]4283; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]4284; CHECK: [[BB6]]:4285; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]4286; CHECK-NEXT: unreachable4287; CHECK: [[BB7]]:4288; CHECK-NEXT: [[RES0:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmovus.qw.256(<4 x i64> [[X0]], <8 x i16> [[X1]], i8 -1)4289; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x i64> [[TMP1]] to i2564290; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i256 [[TMP8]], 04291; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i16> [[TMP2]] to i1284292; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP9]], 04293; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]4294; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 04295; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]4296; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB10:.*]], label %[[BB11:.*]], !prof [[PROF1]]4297; CHECK: [[BB10]]:4298; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]4299; CHECK-NEXT: unreachable4300; CHECK: [[BB11]]:4301; CHECK-NEXT: [[RES1:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmovus.qw.256(<4 x i64> [[X0]], <8 x i16> [[X1]], i8 [[X2]])4302; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i64> [[TMP1]] to i2564303; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i256 [[TMP12]], 04304; CHECK-NEXT: [[_MSCMP8:%.*]] = icmp ne i8 [[TMP3]], 04305; CHECK-NEXT: [[_MSOR9:%.*]] = or i1 [[_MSCMP7]], [[_MSCMP8]]4306; CHECK-NEXT: br i1 [[_MSOR9]], label %[[BB13:.*]], label %[[BB14:.*]], !prof [[PROF1]]4307; CHECK: [[BB13]]:4308; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]4309; CHECK-NEXT: unreachable4310; CHECK: [[BB14]]:4311; CHECK-NEXT: [[RES2:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmovus.qw.256(<4 x i64> [[X0]], <8 x i16> zeroinitializer, i8 [[X2]])4312; CHECK-NEXT: [[RES3:%.*]] = add <8 x i16> [[RES0]], [[RES1]]4313; CHECK-NEXT: [[RES4:%.*]] = add <8 x i16> [[RES3]], [[RES2]]4314; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 84315; CHECK-NEXT: ret <8 x i16> [[RES4]]4316;4317 %res0 = call <8 x i16> @llvm.x86.avx512.mask.pmovus.qw.256(<4 x i64> %x0, <8 x i16> %x1, i8 -1)4318 %res1 = call <8 x i16> @llvm.x86.avx512.mask.pmovus.qw.256(<4 x i64> %x0, <8 x i16> %x1, i8 %x2)4319 %res2 = call <8 x i16> @llvm.x86.avx512.mask.pmovus.qw.256(<4 x i64> %x0, <8 x i16> zeroinitializer, i8 %x2)4320 %res3 = add <8 x i16> %res0, %res14321 %res4 = add <8 x i16> %res3, %res24322 ret <8 x i16> %res44323}4324 4325declare void @llvm.x86.avx512.mask.pmovus.qw.mem.256(ptr %ptr, <4 x i64>, i8)4326 4327define void @test_int_x86_avx512_mask_pmovus_qw_mem_256(ptr %ptr, <4 x i64> %x1, i8 %x2) #0 {4328;4329; CHECK-LABEL: define void @test_int_x86_avx512_mask_pmovus_qw_mem_256(4330; CHECK-SAME: ptr [[PTR:%.*]], <4 x i64> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {4331; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 84332; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 84333; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 84334; CHECK-NEXT: call void @llvm.donothing()4335; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 04336; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i64> [[TMP2]] to i2564337; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP4]], 04338; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]4339; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]4340; CHECK: [[BB5]]:4341; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]4342; CHECK-NEXT: unreachable4343; CHECK: [[BB6]]:4344; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovus.qw.mem.256(ptr [[PTR]], <4 x i64> [[X1]], i8 -1)4345; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 04346; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i64> [[TMP2]] to i2564347; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i256 [[TMP7]], 04348; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]4349; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 04350; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]4351; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]4352; CHECK: [[BB8]]:4353; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]4354; CHECK-NEXT: unreachable4355; CHECK: [[BB9]]:4356; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovus.qw.mem.256(ptr [[PTR]], <4 x i64> [[X1]], i8 [[X2]])4357; CHECK-NEXT: ret void4358;4359 call void @llvm.x86.avx512.mask.pmovus.qw.mem.256(ptr %ptr, <4 x i64> %x1, i8 -1)4360 call void @llvm.x86.avx512.mask.pmovus.qw.mem.256(ptr %ptr, <4 x i64> %x1, i8 %x2)4361 ret void4362}4363 4364declare <4 x i32> @llvm.x86.avx512.mask.pmov.qd.128(<2 x i64>, <4 x i32>, i8)4365 4366define <4 x i32>@test_int_x86_avx512_mask_pmov_qd_128(<2 x i64> %x0, <4 x i32> %x1, i8 %x2) #0 {4367;4368; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_mask_pmov_qd_128(4369; CHECK-SAME: <2 x i64> [[X0:%.*]], <4 x i32> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {4370; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 84371; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84372; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 84373; CHECK-NEXT: call void @llvm.donothing()4374; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP1]] to i1284375; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 04376; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP2]] to i1284377; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 04378; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]4379; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]4380; CHECK: [[BB6]]:4381; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]4382; CHECK-NEXT: unreachable4383; CHECK: [[BB7]]:4384; CHECK-NEXT: [[RES0:%.*]] = call <4 x i32> @llvm.x86.avx512.mask.pmov.qd.128(<2 x i64> [[X0]], <4 x i32> [[X1]], i8 -1)4385; CHECK-NEXT: [[TMP8:%.*]] = bitcast <2 x i64> [[TMP1]] to i1284386; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP8]], 04387; CHECK-NEXT: [[TMP9:%.*]] = bitcast <4 x i32> [[TMP2]] to i1284388; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP9]], 04389; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]4390; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 04391; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]4392; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB10:.*]], label %[[BB11:.*]], !prof [[PROF1]]4393; CHECK: [[BB10]]:4394; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]4395; CHECK-NEXT: unreachable4396; CHECK: [[BB11]]:4397; CHECK-NEXT: [[RES1:%.*]] = call <4 x i32> @llvm.x86.avx512.mask.pmov.qd.128(<2 x i64> [[X0]], <4 x i32> [[X1]], i8 [[X2]])4398; CHECK-NEXT: [[TMP12:%.*]] = bitcast <2 x i64> [[TMP1]] to i1284399; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i128 [[TMP12]], 04400; CHECK-NEXT: [[_MSCMP8:%.*]] = icmp ne i8 [[TMP3]], 04401; CHECK-NEXT: [[_MSOR9:%.*]] = or i1 [[_MSCMP7]], [[_MSCMP8]]4402; CHECK-NEXT: br i1 [[_MSOR9]], label %[[BB13:.*]], label %[[BB14:.*]], !prof [[PROF1]]4403; CHECK: [[BB13]]:4404; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]4405; CHECK-NEXT: unreachable4406; CHECK: [[BB14]]:4407; CHECK-NEXT: [[RES2:%.*]] = call <4 x i32> @llvm.x86.avx512.mask.pmov.qd.128(<2 x i64> [[X0]], <4 x i32> zeroinitializer, i8 [[X2]])4408; CHECK-NEXT: [[RES3:%.*]] = add <4 x i32> [[RES0]], [[RES1]]4409; CHECK-NEXT: [[RES4:%.*]] = add <4 x i32> [[RES3]], [[RES2]]4410; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 84411; CHECK-NEXT: ret <4 x i32> [[RES4]]4412;4413 %res0 = call <4 x i32> @llvm.x86.avx512.mask.pmov.qd.128(<2 x i64> %x0, <4 x i32> %x1, i8 -1)4414 %res1 = call <4 x i32> @llvm.x86.avx512.mask.pmov.qd.128(<2 x i64> %x0, <4 x i32> %x1, i8 %x2)4415 %res2 = call <4 x i32> @llvm.x86.avx512.mask.pmov.qd.128(<2 x i64> %x0, <4 x i32> zeroinitializer, i8 %x2)4416 %res3 = add <4 x i32> %res0, %res14417 %res4 = add <4 x i32> %res3, %res24418 ret <4 x i32> %res44419}4420 4421declare void @llvm.x86.avx512.mask.pmov.qd.mem.128(ptr %ptr, <2 x i64>, i8)4422 4423define void @test_int_x86_avx512_mask_pmov_qd_mem_128(ptr %ptr, <2 x i64> %x1, i8 %x2) #0 {4424;4425; CHECK-LABEL: define void @test_int_x86_avx512_mask_pmov_qd_mem_128(4426; CHECK-SAME: ptr [[PTR:%.*]], <2 x i64> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {4427; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 84428; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 84429; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 84430; CHECK-NEXT: call void @llvm.donothing()4431; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 04432; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP2]] to i1284433; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 04434; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]4435; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]4436; CHECK: [[BB5]]:4437; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]4438; CHECK-NEXT: unreachable4439; CHECK: [[BB6]]:4440; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmov.qd.mem.128(ptr [[PTR]], <2 x i64> [[X1]], i8 -1)4441; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 04442; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i64> [[TMP2]] to i1284443; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP7]], 04444; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]4445; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 04446; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]4447; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]4448; CHECK: [[BB8]]:4449; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]4450; CHECK-NEXT: unreachable4451; CHECK: [[BB9]]:4452; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmov.qd.mem.128(ptr [[PTR]], <2 x i64> [[X1]], i8 [[X2]])4453; CHECK-NEXT: ret void4454;4455 call void @llvm.x86.avx512.mask.pmov.qd.mem.128(ptr %ptr, <2 x i64> %x1, i8 -1)4456 call void @llvm.x86.avx512.mask.pmov.qd.mem.128(ptr %ptr, <2 x i64> %x1, i8 %x2)4457 ret void4458}4459 4460declare <4 x i32> @llvm.x86.avx512.mask.pmovs.qd.128(<2 x i64>, <4 x i32>, i8)4461 4462define <4 x i32>@test_int_x86_avx512_mask_pmovs_qd_128(<2 x i64> %x0, <4 x i32> %x1, i8 %x2) #0 {4463;4464; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_mask_pmovs_qd_128(4465; CHECK-SAME: <2 x i64> [[X0:%.*]], <4 x i32> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {4466; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 84467; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84468; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 84469; CHECK-NEXT: call void @llvm.donothing()4470; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP1]] to i1284471; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 04472; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP2]] to i1284473; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 04474; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]4475; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]4476; CHECK: [[BB6]]:4477; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]4478; CHECK-NEXT: unreachable4479; CHECK: [[BB7]]:4480; CHECK-NEXT: [[RES0:%.*]] = call <4 x i32> @llvm.x86.avx512.mask.pmovs.qd.128(<2 x i64> [[X0]], <4 x i32> [[X1]], i8 -1)4481; CHECK-NEXT: [[TMP8:%.*]] = bitcast <2 x i64> [[TMP1]] to i1284482; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP8]], 04483; CHECK-NEXT: [[TMP9:%.*]] = bitcast <4 x i32> [[TMP2]] to i1284484; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP9]], 04485; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]4486; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 04487; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]4488; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB10:.*]], label %[[BB11:.*]], !prof [[PROF1]]4489; CHECK: [[BB10]]:4490; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]4491; CHECK-NEXT: unreachable4492; CHECK: [[BB11]]:4493; CHECK-NEXT: [[RES1:%.*]] = call <4 x i32> @llvm.x86.avx512.mask.pmovs.qd.128(<2 x i64> [[X0]], <4 x i32> [[X1]], i8 [[X2]])4494; CHECK-NEXT: [[TMP12:%.*]] = bitcast <2 x i64> [[TMP1]] to i1284495; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i128 [[TMP12]], 04496; CHECK-NEXT: [[_MSCMP8:%.*]] = icmp ne i8 [[TMP3]], 04497; CHECK-NEXT: [[_MSOR9:%.*]] = or i1 [[_MSCMP7]], [[_MSCMP8]]4498; CHECK-NEXT: br i1 [[_MSOR9]], label %[[BB13:.*]], label %[[BB14:.*]], !prof [[PROF1]]4499; CHECK: [[BB13]]:4500; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]4501; CHECK-NEXT: unreachable4502; CHECK: [[BB14]]:4503; CHECK-NEXT: [[RES2:%.*]] = call <4 x i32> @llvm.x86.avx512.mask.pmovs.qd.128(<2 x i64> [[X0]], <4 x i32> zeroinitializer, i8 [[X2]])4504; CHECK-NEXT: [[RES3:%.*]] = add <4 x i32> [[RES0]], [[RES1]]4505; CHECK-NEXT: [[RES4:%.*]] = add <4 x i32> [[RES3]], [[RES2]]4506; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 84507; CHECK-NEXT: ret <4 x i32> [[RES4]]4508;4509 %res0 = call <4 x i32> @llvm.x86.avx512.mask.pmovs.qd.128(<2 x i64> %x0, <4 x i32> %x1, i8 -1)4510 %res1 = call <4 x i32> @llvm.x86.avx512.mask.pmovs.qd.128(<2 x i64> %x0, <4 x i32> %x1, i8 %x2)4511 %res2 = call <4 x i32> @llvm.x86.avx512.mask.pmovs.qd.128(<2 x i64> %x0, <4 x i32> zeroinitializer, i8 %x2)4512 %res3 = add <4 x i32> %res0, %res14513 %res4 = add <4 x i32> %res3, %res24514 ret <4 x i32> %res44515}4516 4517declare void @llvm.x86.avx512.mask.pmovs.qd.mem.128(ptr %ptr, <2 x i64>, i8)4518 4519define void @test_int_x86_avx512_mask_pmovs_qd_mem_128(ptr %ptr, <2 x i64> %x1, i8 %x2) #0 {4520;4521; CHECK-LABEL: define void @test_int_x86_avx512_mask_pmovs_qd_mem_128(4522; CHECK-SAME: ptr [[PTR:%.*]], <2 x i64> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {4523; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 84524; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 84525; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 84526; CHECK-NEXT: call void @llvm.donothing()4527; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 04528; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP2]] to i1284529; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 04530; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]4531; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]4532; CHECK: [[BB5]]:4533; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]4534; CHECK-NEXT: unreachable4535; CHECK: [[BB6]]:4536; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovs.qd.mem.128(ptr [[PTR]], <2 x i64> [[X1]], i8 -1)4537; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 04538; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i64> [[TMP2]] to i1284539; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP7]], 04540; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]4541; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 04542; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]4543; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]4544; CHECK: [[BB8]]:4545; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]4546; CHECK-NEXT: unreachable4547; CHECK: [[BB9]]:4548; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovs.qd.mem.128(ptr [[PTR]], <2 x i64> [[X1]], i8 [[X2]])4549; CHECK-NEXT: ret void4550;4551 call void @llvm.x86.avx512.mask.pmovs.qd.mem.128(ptr %ptr, <2 x i64> %x1, i8 -1)4552 call void @llvm.x86.avx512.mask.pmovs.qd.mem.128(ptr %ptr, <2 x i64> %x1, i8 %x2)4553 ret void4554}4555 4556declare <4 x i32> @llvm.x86.avx512.mask.pmovus.qd.128(<2 x i64>, <4 x i32>, i8)4557 4558define <4 x i32>@test_int_x86_avx512_mask_pmovus_qd_128(<2 x i64> %x0, <4 x i32> %x1, i8 %x2) #0 {4559;4560; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_mask_pmovus_qd_128(4561; CHECK-SAME: <2 x i64> [[X0:%.*]], <4 x i32> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {4562; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 84563; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84564; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 84565; CHECK-NEXT: call void @llvm.donothing()4566; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP1]] to i1284567; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 04568; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP2]] to i1284569; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 04570; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]4571; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]4572; CHECK: [[BB6]]:4573; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]4574; CHECK-NEXT: unreachable4575; CHECK: [[BB7]]:4576; CHECK-NEXT: [[RES0:%.*]] = call <4 x i32> @llvm.x86.avx512.mask.pmovus.qd.128(<2 x i64> [[X0]], <4 x i32> [[X1]], i8 -1)4577; CHECK-NEXT: [[TMP8:%.*]] = bitcast <2 x i64> [[TMP1]] to i1284578; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP8]], 04579; CHECK-NEXT: [[TMP9:%.*]] = bitcast <4 x i32> [[TMP2]] to i1284580; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP9]], 04581; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]4582; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 04583; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]4584; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB10:.*]], label %[[BB11:.*]], !prof [[PROF1]]4585; CHECK: [[BB10]]:4586; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]4587; CHECK-NEXT: unreachable4588; CHECK: [[BB11]]:4589; CHECK-NEXT: [[RES1:%.*]] = call <4 x i32> @llvm.x86.avx512.mask.pmovus.qd.128(<2 x i64> [[X0]], <4 x i32> [[X1]], i8 [[X2]])4590; CHECK-NEXT: [[TMP12:%.*]] = bitcast <2 x i64> [[TMP1]] to i1284591; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i128 [[TMP12]], 04592; CHECK-NEXT: [[_MSCMP8:%.*]] = icmp ne i8 [[TMP3]], 04593; CHECK-NEXT: [[_MSOR9:%.*]] = or i1 [[_MSCMP7]], [[_MSCMP8]]4594; CHECK-NEXT: br i1 [[_MSOR9]], label %[[BB13:.*]], label %[[BB14:.*]], !prof [[PROF1]]4595; CHECK: [[BB13]]:4596; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]4597; CHECK-NEXT: unreachable4598; CHECK: [[BB14]]:4599; CHECK-NEXT: [[RES2:%.*]] = call <4 x i32> @llvm.x86.avx512.mask.pmovus.qd.128(<2 x i64> [[X0]], <4 x i32> zeroinitializer, i8 [[X2]])4600; CHECK-NEXT: [[RES3:%.*]] = add <4 x i32> [[RES0]], [[RES1]]4601; CHECK-NEXT: [[RES4:%.*]] = add <4 x i32> [[RES3]], [[RES2]]4602; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 84603; CHECK-NEXT: ret <4 x i32> [[RES4]]4604;4605 %res0 = call <4 x i32> @llvm.x86.avx512.mask.pmovus.qd.128(<2 x i64> %x0, <4 x i32> %x1, i8 -1)4606 %res1 = call <4 x i32> @llvm.x86.avx512.mask.pmovus.qd.128(<2 x i64> %x0, <4 x i32> %x1, i8 %x2)4607 %res2 = call <4 x i32> @llvm.x86.avx512.mask.pmovus.qd.128(<2 x i64> %x0, <4 x i32> zeroinitializer, i8 %x2)4608 %res3 = add <4 x i32> %res0, %res14609 %res4 = add <4 x i32> %res3, %res24610 ret <4 x i32> %res44611}4612 4613declare void @llvm.x86.avx512.mask.pmovus.qd.mem.128(ptr %ptr, <2 x i64>, i8)4614 4615define void @test_int_x86_avx512_mask_pmovus_qd_mem_128(ptr %ptr, <2 x i64> %x1, i8 %x2) #0 {4616;4617; CHECK-LABEL: define void @test_int_x86_avx512_mask_pmovus_qd_mem_128(4618; CHECK-SAME: ptr [[PTR:%.*]], <2 x i64> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {4619; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 84620; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 84621; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 84622; CHECK-NEXT: call void @llvm.donothing()4623; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 04624; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP2]] to i1284625; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 04626; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]4627; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]4628; CHECK: [[BB5]]:4629; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]4630; CHECK-NEXT: unreachable4631; CHECK: [[BB6]]:4632; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovus.qd.mem.128(ptr [[PTR]], <2 x i64> [[X1]], i8 -1)4633; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 04634; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i64> [[TMP2]] to i1284635; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP7]], 04636; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]4637; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 04638; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]4639; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]4640; CHECK: [[BB8]]:4641; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]4642; CHECK-NEXT: unreachable4643; CHECK: [[BB9]]:4644; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovus.qd.mem.128(ptr [[PTR]], <2 x i64> [[X1]], i8 [[X2]])4645; CHECK-NEXT: ret void4646;4647 call void @llvm.x86.avx512.mask.pmovus.qd.mem.128(ptr %ptr, <2 x i64> %x1, i8 -1)4648 call void @llvm.x86.avx512.mask.pmovus.qd.mem.128(ptr %ptr, <2 x i64> %x1, i8 %x2)4649 ret void4650}4651 4652define <4 x i32>@test_int_x86_avx512_pmov_qd_256(<4 x i64> %x0) #0 {4653; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_pmov_qd_256(4654; CHECK-SAME: <4 x i64> [[X0:%.*]]) #[[ATTR0]] {4655; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 84656; CHECK-NEXT: call void @llvm.donothing()4657; CHECK-NEXT: [[_MSPROP:%.*]] = trunc <4 x i64> [[TMP2]] to <4 x i32>4658; CHECK-NEXT: [[TMP1:%.*]] = trunc <4 x i64> [[X0]] to <4 x i32>4659; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 84660; CHECK-NEXT: ret <4 x i32> [[TMP1]]4661;4662 %1 = trunc <4 x i64> %x0 to <4 x i32>4663 ret <4 x i32> %14664}4665 4666define <4 x i32>@test_int_x86_avx512_mask_pmov_qd_256(<4 x i64> %x0, <4 x i32> %x1, i8 %x2) #0 {4667;4668; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_mask_pmov_qd_256(4669; CHECK-SAME: <4 x i64> [[X0:%.*]], <4 x i32> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {4670; CHECK-NEXT: [[TMP6:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 84671; CHECK-NEXT: [[TMP8:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 84672; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 84673; CHECK-NEXT: call void @llvm.donothing()4674; CHECK-NEXT: [[_MSPROP:%.*]] = trunc <4 x i64> [[TMP6]] to <4 x i32>4675; CHECK-NEXT: [[TMP1:%.*]] = trunc <4 x i64> [[X0]] to <4 x i32>4676; CHECK-NEXT: [[TMP5:%.*]] = bitcast i8 [[TMP8]] to <8 x i1>4677; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[X2]] to <8 x i1>4678; CHECK-NEXT: [[_MSPROP1:%.*]] = shufflevector <8 x i1> [[TMP5]], <8 x i1> [[TMP5]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>4679; CHECK-NEXT: [[EXTRACT1:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> [[TMP2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>4680; CHECK-NEXT: [[TMP11:%.*]] = select <4 x i1> [[EXTRACT1]], <4 x i32> [[_MSPROP]], <4 x i32> [[TMP3]]4681; CHECK-NEXT: [[TMP4:%.*]] = xor <4 x i32> [[TMP1]], [[X1]]4682; CHECK-NEXT: [[TMP9:%.*]] = or <4 x i32> [[TMP4]], [[_MSPROP]]4683; CHECK-NEXT: [[TMP10:%.*]] = or <4 x i32> [[TMP9]], [[TMP3]]4684; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP1]], <4 x i32> [[TMP10]], <4 x i32> [[TMP11]]4685; CHECK-NEXT: [[TMP7:%.*]] = select <4 x i1> [[EXTRACT1]], <4 x i32> [[TMP1]], <4 x i32> [[X1]]4686; CHECK-NEXT: store <4 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 84687; CHECK-NEXT: ret <4 x i32> [[TMP7]]4688;4689 %1 = trunc <4 x i64> %x0 to <4 x i32>4690 %2 = bitcast i8 %x2 to <8 x i1>4691 %extract1 = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>4692 %3 = select <4 x i1> %extract1, <4 x i32> %1, <4 x i32> %x14693 ret <4 x i32> %34694}4695 4696define <4 x i32>@test_int_x86_avx512_maskz_pmov_qd_256(<4 x i64> %x0, i8 %x2) #0 {4697;4698; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_maskz_pmov_qd_256(4699; CHECK-SAME: <4 x i64> [[X0:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {4700; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 84701; CHECK-NEXT: [[TMP8:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 84702; CHECK-NEXT: call void @llvm.donothing()4703; CHECK-NEXT: [[_MSPROP:%.*]] = trunc <4 x i64> [[TMP3]] to <4 x i32>4704; CHECK-NEXT: [[TMP1:%.*]] = trunc <4 x i64> [[X0]] to <4 x i32>4705; CHECK-NEXT: [[TMP9:%.*]] = bitcast i8 [[TMP8]] to <8 x i1>4706; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[X2]] to <8 x i1>4707; CHECK-NEXT: [[_MSPROP1:%.*]] = shufflevector <8 x i1> [[TMP9]], <8 x i1> [[TMP9]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>4708; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> [[TMP2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>4709; CHECK-NEXT: [[TMP10:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i32> [[_MSPROP]], <4 x i32> zeroinitializer4710; CHECK-NEXT: [[TMP4:%.*]] = xor <4 x i32> [[TMP1]], zeroinitializer4711; CHECK-NEXT: [[TMP5:%.*]] = or <4 x i32> [[TMP4]], [[_MSPROP]]4712; CHECK-NEXT: [[TMP6:%.*]] = or <4 x i32> [[TMP5]], zeroinitializer4713; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP1]], <4 x i32> [[TMP6]], <4 x i32> [[TMP10]]4714; CHECK-NEXT: [[TMP7:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i32> [[TMP1]], <4 x i32> zeroinitializer4715; CHECK-NEXT: store <4 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 84716; CHECK-NEXT: ret <4 x i32> [[TMP7]]4717;4718 %1 = trunc <4 x i64> %x0 to <4 x i32>4719 %2 = bitcast i8 %x2 to <8 x i1>4720 %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>4721 %3 = select <4 x i1> %extract, <4 x i32> %1, <4 x i32> zeroinitializer4722 ret <4 x i32> %34723}4724 4725declare void @llvm.x86.avx512.mask.pmov.qd.mem.256(ptr %ptr, <4 x i64>, i8)4726 4727define void @test_int_x86_avx512_mask_pmov_qd_mem_256(ptr %ptr, <4 x i64> %x1, i8 %x2) #0 {4728;4729; CHECK-LABEL: define void @test_int_x86_avx512_mask_pmov_qd_mem_256(4730; CHECK-SAME: ptr [[PTR:%.*]], <4 x i64> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {4731; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 84732; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 84733; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 84734; CHECK-NEXT: call void @llvm.donothing()4735; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 04736; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i64> [[TMP2]] to i2564737; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP4]], 04738; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]4739; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]4740; CHECK: [[BB5]]:4741; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]4742; CHECK-NEXT: unreachable4743; CHECK: [[BB6]]:4744; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmov.qd.mem.256(ptr [[PTR]], <4 x i64> [[X1]], i8 -1)4745; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 04746; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i64> [[TMP2]] to i2564747; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i256 [[TMP7]], 04748; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]4749; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 04750; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]4751; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]4752; CHECK: [[BB8]]:4753; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]4754; CHECK-NEXT: unreachable4755; CHECK: [[BB9]]:4756; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmov.qd.mem.256(ptr [[PTR]], <4 x i64> [[X1]], i8 [[X2]])4757; CHECK-NEXT: ret void4758;4759 call void @llvm.x86.avx512.mask.pmov.qd.mem.256(ptr %ptr, <4 x i64> %x1, i8 -1)4760 call void @llvm.x86.avx512.mask.pmov.qd.mem.256(ptr %ptr, <4 x i64> %x1, i8 %x2)4761 ret void4762}4763 4764declare <4 x i32> @llvm.x86.avx512.mask.pmovs.qd.256(<4 x i64>, <4 x i32>, i8)4765 4766define <4 x i32>@test_int_x86_avx512_pmovs_qd_256(<4 x i64> %x0, <4 x i32> %x1) #0 {4767; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_pmovs_qd_256(4768; CHECK-SAME: <4 x i64> [[X0:%.*]], <4 x i32> [[X1:%.*]]) #[[ATTR0]] {4769; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 84770; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 84771; CHECK-NEXT: call void @llvm.donothing()4772; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i64> [[TMP1]] to i2564773; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP3]], 04774; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i1284775; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 04776; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]4777; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]4778; CHECK: [[BB5]]:4779; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]4780; CHECK-NEXT: unreachable4781; CHECK: [[BB6]]:4782; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx512.mask.pmovs.qd.256(<4 x i64> [[X0]], <4 x i32> [[X1]], i8 -1)4783; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 84784; CHECK-NEXT: ret <4 x i32> [[RES]]4785;4786 %res = call <4 x i32> @llvm.x86.avx512.mask.pmovs.qd.256(<4 x i64> %x0, <4 x i32> %x1, i8 -1)4787 ret <4 x i32> %res4788}4789 4790define <4 x i32>@test_int_x86_avx512_mask_pmovs_qd_256(<4 x i64> %x0, <4 x i32> %x1, i8 %x2) #0 {4791;4792; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_mask_pmovs_qd_256(4793; CHECK-SAME: <4 x i64> [[X0:%.*]], <4 x i32> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {4794; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 84795; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 84796; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 84797; CHECK-NEXT: call void @llvm.donothing()4798; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i64> [[TMP1]] to i2564799; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP4]], 04800; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP2]] to i1284801; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 04802; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]4803; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 04804; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]4805; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]4806; CHECK: [[BB6]]:4807; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]4808; CHECK-NEXT: unreachable4809; CHECK: [[BB7]]:4810; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx512.mask.pmovs.qd.256(<4 x i64> [[X0]], <4 x i32> [[X1]], i8 [[X2]])4811; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 84812; CHECK-NEXT: ret <4 x i32> [[RES]]4813;4814 %res = call <4 x i32> @llvm.x86.avx512.mask.pmovs.qd.256(<4 x i64> %x0, <4 x i32> %x1, i8 %x2)4815 ret <4 x i32> %res4816}4817 4818define <4 x i32>@test_int_x86_avx512_maskz_pmovs_qd_256(<4 x i64> %x0, i8 %x2) #0 {4819;4820; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_maskz_pmovs_qd_256(4821; CHECK-SAME: <4 x i64> [[X0:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {4822; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 84823; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 84824; CHECK-NEXT: call void @llvm.donothing()4825; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i64> [[TMP1]] to i2564826; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP3]], 04827; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i8 [[TMP2]], 04828; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]4829; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]4830; CHECK: [[BB4]]:4831; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]4832; CHECK-NEXT: unreachable4833; CHECK: [[BB5]]:4834; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx512.mask.pmovs.qd.256(<4 x i64> [[X0]], <4 x i32> zeroinitializer, i8 [[X2]])4835; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 84836; CHECK-NEXT: ret <4 x i32> [[RES]]4837;4838 %res = call <4 x i32> @llvm.x86.avx512.mask.pmovs.qd.256(<4 x i64> %x0, <4 x i32> zeroinitializer, i8 %x2)4839 ret <4 x i32> %res4840}4841 4842declare void @llvm.x86.avx512.mask.pmovs.qd.mem.256(ptr %ptr, <4 x i64>, i8)4843 4844define void @test_int_x86_avx512_mask_pmovs_qd_mem_256(ptr %ptr, <4 x i64> %x1, i8 %x2) #0 {4845;4846; CHECK-LABEL: define void @test_int_x86_avx512_mask_pmovs_qd_mem_256(4847; CHECK-SAME: ptr [[PTR:%.*]], <4 x i64> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {4848; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 84849; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 84850; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 84851; CHECK-NEXT: call void @llvm.donothing()4852; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 04853; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i64> [[TMP2]] to i2564854; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP4]], 04855; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]4856; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]4857; CHECK: [[BB5]]:4858; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]4859; CHECK-NEXT: unreachable4860; CHECK: [[BB6]]:4861; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovs.qd.mem.256(ptr [[PTR]], <4 x i64> [[X1]], i8 -1)4862; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 04863; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i64> [[TMP2]] to i2564864; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i256 [[TMP7]], 04865; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]4866; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 04867; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]4868; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]4869; CHECK: [[BB8]]:4870; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]4871; CHECK-NEXT: unreachable4872; CHECK: [[BB9]]:4873; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovs.qd.mem.256(ptr [[PTR]], <4 x i64> [[X1]], i8 [[X2]])4874; CHECK-NEXT: ret void4875;4876 call void @llvm.x86.avx512.mask.pmovs.qd.mem.256(ptr %ptr, <4 x i64> %x1, i8 -1)4877 call void @llvm.x86.avx512.mask.pmovs.qd.mem.256(ptr %ptr, <4 x i64> %x1, i8 %x2)4878 ret void4879}4880 4881declare <4 x i32> @llvm.x86.avx512.mask.pmovus.qd.256(<4 x i64>, <4 x i32>, i8)4882 4883define <4 x i32>@test_int_x86_avx512_pmovus_qd_256(<4 x i64> %x0, <4 x i32> %x1) #0 {4884; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_pmovus_qd_256(4885; CHECK-SAME: <4 x i64> [[X0:%.*]], <4 x i32> [[X1:%.*]]) #[[ATTR0]] {4886; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 84887; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 84888; CHECK-NEXT: call void @llvm.donothing()4889; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i64> [[TMP1]] to i2564890; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP3]], 04891; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i1284892; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 04893; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]4894; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]4895; CHECK: [[BB5]]:4896; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]4897; CHECK-NEXT: unreachable4898; CHECK: [[BB6]]:4899; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx512.mask.pmovus.qd.256(<4 x i64> [[X0]], <4 x i32> [[X1]], i8 -1)4900; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 84901; CHECK-NEXT: ret <4 x i32> [[RES]]4902;4903 %res = call <4 x i32> @llvm.x86.avx512.mask.pmovus.qd.256(<4 x i64> %x0, <4 x i32> %x1, i8 -1)4904 ret <4 x i32> %res4905}4906 4907define <4 x i32>@test_int_x86_avx512_mask_pmovus_qd_256(<4 x i64> %x0, <4 x i32> %x1, i8 %x2) #0 {4908;4909; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_mask_pmovus_qd_256(4910; CHECK-SAME: <4 x i64> [[X0:%.*]], <4 x i32> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {4911; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 84912; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 84913; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 84914; CHECK-NEXT: call void @llvm.donothing()4915; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i64> [[TMP1]] to i2564916; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP4]], 04917; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP2]] to i1284918; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 04919; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]4920; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 04921; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]4922; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]4923; CHECK: [[BB6]]:4924; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]4925; CHECK-NEXT: unreachable4926; CHECK: [[BB7]]:4927; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx512.mask.pmovus.qd.256(<4 x i64> [[X0]], <4 x i32> [[X1]], i8 [[X2]])4928; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 84929; CHECK-NEXT: ret <4 x i32> [[RES]]4930;4931 %res = call <4 x i32> @llvm.x86.avx512.mask.pmovus.qd.256(<4 x i64> %x0, <4 x i32> %x1, i8 %x2)4932 ret <4 x i32> %res4933}4934 4935define <4 x i32>@test_int_x86_avx512_maskz_pmovus_qd_256(<4 x i64> %x0, i8 %x2) #0 {4936;4937; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_maskz_pmovus_qd_256(4938; CHECK-SAME: <4 x i64> [[X0:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {4939; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 84940; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 84941; CHECK-NEXT: call void @llvm.donothing()4942; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i64> [[TMP1]] to i2564943; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP3]], 04944; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i8 [[TMP2]], 04945; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]4946; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]4947; CHECK: [[BB4]]:4948; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]4949; CHECK-NEXT: unreachable4950; CHECK: [[BB5]]:4951; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx512.mask.pmovus.qd.256(<4 x i64> [[X0]], <4 x i32> zeroinitializer, i8 [[X2]])4952; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 84953; CHECK-NEXT: ret <4 x i32> [[RES]]4954;4955 %res = call <4 x i32> @llvm.x86.avx512.mask.pmovus.qd.256(<4 x i64> %x0, <4 x i32> zeroinitializer, i8 %x2)4956 ret <4 x i32> %res4957}4958 4959declare void @llvm.x86.avx512.mask.pmovus.qd.mem.256(ptr %ptr, <4 x i64>, i8)4960 4961define void @test_int_x86_avx512_mask_pmovus_qd_mem_256(ptr %ptr, <4 x i64> %x1, i8 %x2) #0 {4962;4963; CHECK-LABEL: define void @test_int_x86_avx512_mask_pmovus_qd_mem_256(4964; CHECK-SAME: ptr [[PTR:%.*]], <4 x i64> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {4965; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 84966; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 84967; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 84968; CHECK-NEXT: call void @llvm.donothing()4969; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 04970; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i64> [[TMP2]] to i2564971; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP4]], 04972; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]4973; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]4974; CHECK: [[BB5]]:4975; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]4976; CHECK-NEXT: unreachable4977; CHECK: [[BB6]]:4978; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovus.qd.mem.256(ptr [[PTR]], <4 x i64> [[X1]], i8 -1)4979; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 04980; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i64> [[TMP2]] to i2564981; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i256 [[TMP7]], 04982; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]4983; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 04984; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]4985; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]4986; CHECK: [[BB8]]:4987; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]4988; CHECK-NEXT: unreachable4989; CHECK: [[BB9]]:4990; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovus.qd.mem.256(ptr [[PTR]], <4 x i64> [[X1]], i8 [[X2]])4991; CHECK-NEXT: ret void4992;4993 call void @llvm.x86.avx512.mask.pmovus.qd.mem.256(ptr %ptr, <4 x i64> %x1, i8 -1)4994 call void @llvm.x86.avx512.mask.pmovus.qd.mem.256(ptr %ptr, <4 x i64> %x1, i8 %x2)4995 ret void4996}4997 4998declare <16 x i8> @llvm.x86.avx512.mask.pmov.db.128(<4 x i32>, <16 x i8>, i8)4999 5000define <16 x i8>@test_int_x86_avx512_mask_pmov_db_128(<4 x i32> %x0, <16 x i8> %x1, i8 %x2) #0 {5001;5002; CHECK-LABEL: define <16 x i8> @test_int_x86_avx512_mask_pmov_db_128(5003; CHECK-SAME: <4 x i32> [[X0:%.*]], <16 x i8> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {5004; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 85005; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 85006; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 85007; CHECK-NEXT: call void @llvm.donothing()5008; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP1]] to i1285009; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 05010; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to i1285011; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 05012; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]5013; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]5014; CHECK: [[BB6]]:5015; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5016; CHECK-NEXT: unreachable5017; CHECK: [[BB7]]:5018; CHECK-NEXT: [[RES0:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmov.db.128(<4 x i32> [[X0]], <16 x i8> [[X1]], i8 -1)5019; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x i32> [[TMP1]] to i1285020; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP8]], 05021; CHECK-NEXT: [[TMP9:%.*]] = bitcast <16 x i8> [[TMP2]] to i1285022; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP9]], 05023; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]5024; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 05025; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]5026; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB10:.*]], label %[[BB11:.*]], !prof [[PROF1]]5027; CHECK: [[BB10]]:5028; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5029; CHECK-NEXT: unreachable5030; CHECK: [[BB11]]:5031; CHECK-NEXT: [[RES1:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmov.db.128(<4 x i32> [[X0]], <16 x i8> [[X1]], i8 [[X2]])5032; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i32> [[TMP1]] to i1285033; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i128 [[TMP12]], 05034; CHECK-NEXT: [[_MSCMP8:%.*]] = icmp ne i8 [[TMP3]], 05035; CHECK-NEXT: [[_MSOR9:%.*]] = or i1 [[_MSCMP7]], [[_MSCMP8]]5036; CHECK-NEXT: br i1 [[_MSOR9]], label %[[BB13:.*]], label %[[BB14:.*]], !prof [[PROF1]]5037; CHECK: [[BB13]]:5038; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5039; CHECK-NEXT: unreachable5040; CHECK: [[BB14]]:5041; CHECK-NEXT: [[RES2:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmov.db.128(<4 x i32> [[X0]], <16 x i8> zeroinitializer, i8 [[X2]])5042; CHECK-NEXT: [[RES3:%.*]] = add <16 x i8> [[RES0]], [[RES1]]5043; CHECK-NEXT: [[RES4:%.*]] = add <16 x i8> [[RES3]], [[RES2]]5044; CHECK-NEXT: store <16 x i8> zeroinitializer, ptr @__msan_retval_tls, align 85045; CHECK-NEXT: ret <16 x i8> [[RES4]]5046;5047 %res0 = call <16 x i8> @llvm.x86.avx512.mask.pmov.db.128(<4 x i32> %x0, <16 x i8> %x1, i8 -1)5048 %res1 = call <16 x i8> @llvm.x86.avx512.mask.pmov.db.128(<4 x i32> %x0, <16 x i8> %x1, i8 %x2)5049 %res2 = call <16 x i8> @llvm.x86.avx512.mask.pmov.db.128(<4 x i32> %x0, <16 x i8> zeroinitializer, i8 %x2)5050 %res3 = add <16 x i8> %res0, %res15051 %res4 = add <16 x i8> %res3, %res25052 ret <16 x i8> %res45053}5054 5055declare void @llvm.x86.avx512.mask.pmov.db.mem.128(ptr %ptr, <4 x i32>, i8)5056 5057define void @test_int_x86_avx512_mask_pmov_db_mem_128(ptr %ptr, <4 x i32> %x1, i8 %x2) #0 {5058;5059; CHECK-LABEL: define void @test_int_x86_avx512_mask_pmov_db_mem_128(5060; CHECK-SAME: ptr [[PTR:%.*]], <4 x i32> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {5061; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 85062; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 85063; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 85064; CHECK-NEXT: call void @llvm.donothing()5065; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05066; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i1285067; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 05068; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]5069; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]5070; CHECK: [[BB5]]:5071; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5072; CHECK-NEXT: unreachable5073; CHECK: [[BB6]]:5074; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmov.db.mem.128(ptr [[PTR]], <4 x i32> [[X1]], i8 -1)5075; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 05076; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i32> [[TMP2]] to i1285077; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP7]], 05078; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]5079; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 05080; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]5081; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]5082; CHECK: [[BB8]]:5083; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5084; CHECK-NEXT: unreachable5085; CHECK: [[BB9]]:5086; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmov.db.mem.128(ptr [[PTR]], <4 x i32> [[X1]], i8 [[X2]])5087; CHECK-NEXT: ret void5088;5089 call void @llvm.x86.avx512.mask.pmov.db.mem.128(ptr %ptr, <4 x i32> %x1, i8 -1)5090 call void @llvm.x86.avx512.mask.pmov.db.mem.128(ptr %ptr, <4 x i32> %x1, i8 %x2)5091 ret void5092}5093 5094declare <16 x i8> @llvm.x86.avx512.mask.pmovs.db.128(<4 x i32>, <16 x i8>, i8)5095 5096define <16 x i8>@test_int_x86_avx512_mask_pmovs_db_128(<4 x i32> %x0, <16 x i8> %x1, i8 %x2) #0 {5097;5098; CHECK-LABEL: define <16 x i8> @test_int_x86_avx512_mask_pmovs_db_128(5099; CHECK-SAME: <4 x i32> [[X0:%.*]], <16 x i8> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {5100; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 85101; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 85102; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 85103; CHECK-NEXT: call void @llvm.donothing()5104; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP1]] to i1285105; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 05106; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to i1285107; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 05108; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]5109; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]5110; CHECK: [[BB6]]:5111; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5112; CHECK-NEXT: unreachable5113; CHECK: [[BB7]]:5114; CHECK-NEXT: [[RES0:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmovs.db.128(<4 x i32> [[X0]], <16 x i8> [[X1]], i8 -1)5115; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x i32> [[TMP1]] to i1285116; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP8]], 05117; CHECK-NEXT: [[TMP9:%.*]] = bitcast <16 x i8> [[TMP2]] to i1285118; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP9]], 05119; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]5120; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 05121; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]5122; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB10:.*]], label %[[BB11:.*]], !prof [[PROF1]]5123; CHECK: [[BB10]]:5124; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5125; CHECK-NEXT: unreachable5126; CHECK: [[BB11]]:5127; CHECK-NEXT: [[RES1:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmovs.db.128(<4 x i32> [[X0]], <16 x i8> [[X1]], i8 [[X2]])5128; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i32> [[TMP1]] to i1285129; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i128 [[TMP12]], 05130; CHECK-NEXT: [[_MSCMP8:%.*]] = icmp ne i8 [[TMP3]], 05131; CHECK-NEXT: [[_MSOR9:%.*]] = or i1 [[_MSCMP7]], [[_MSCMP8]]5132; CHECK-NEXT: br i1 [[_MSOR9]], label %[[BB13:.*]], label %[[BB14:.*]], !prof [[PROF1]]5133; CHECK: [[BB13]]:5134; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5135; CHECK-NEXT: unreachable5136; CHECK: [[BB14]]:5137; CHECK-NEXT: [[RES2:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmovs.db.128(<4 x i32> [[X0]], <16 x i8> zeroinitializer, i8 [[X2]])5138; CHECK-NEXT: [[RES3:%.*]] = add <16 x i8> [[RES0]], [[RES1]]5139; CHECK-NEXT: [[RES4:%.*]] = add <16 x i8> [[RES3]], [[RES2]]5140; CHECK-NEXT: store <16 x i8> zeroinitializer, ptr @__msan_retval_tls, align 85141; CHECK-NEXT: ret <16 x i8> [[RES4]]5142;5143 %res0 = call <16 x i8> @llvm.x86.avx512.mask.pmovs.db.128(<4 x i32> %x0, <16 x i8> %x1, i8 -1)5144 %res1 = call <16 x i8> @llvm.x86.avx512.mask.pmovs.db.128(<4 x i32> %x0, <16 x i8> %x1, i8 %x2)5145 %res2 = call <16 x i8> @llvm.x86.avx512.mask.pmovs.db.128(<4 x i32> %x0, <16 x i8> zeroinitializer, i8 %x2)5146 %res3 = add <16 x i8> %res0, %res15147 %res4 = add <16 x i8> %res3, %res25148 ret <16 x i8> %res45149}5150 5151declare void @llvm.x86.avx512.mask.pmovs.db.mem.128(ptr %ptr, <4 x i32>, i8)5152 5153define void @test_int_x86_avx512_mask_pmovs_db_mem_128(ptr %ptr, <4 x i32> %x1, i8 %x2) #0 {5154;5155; CHECK-LABEL: define void @test_int_x86_avx512_mask_pmovs_db_mem_128(5156; CHECK-SAME: ptr [[PTR:%.*]], <4 x i32> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {5157; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 85158; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 85159; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 85160; CHECK-NEXT: call void @llvm.donothing()5161; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05162; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i1285163; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 05164; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]5165; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]5166; CHECK: [[BB5]]:5167; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5168; CHECK-NEXT: unreachable5169; CHECK: [[BB6]]:5170; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovs.db.mem.128(ptr [[PTR]], <4 x i32> [[X1]], i8 -1)5171; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 05172; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i32> [[TMP2]] to i1285173; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP7]], 05174; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]5175; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 05176; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]5177; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]5178; CHECK: [[BB8]]:5179; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5180; CHECK-NEXT: unreachable5181; CHECK: [[BB9]]:5182; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovs.db.mem.128(ptr [[PTR]], <4 x i32> [[X1]], i8 [[X2]])5183; CHECK-NEXT: ret void5184;5185 call void @llvm.x86.avx512.mask.pmovs.db.mem.128(ptr %ptr, <4 x i32> %x1, i8 -1)5186 call void @llvm.x86.avx512.mask.pmovs.db.mem.128(ptr %ptr, <4 x i32> %x1, i8 %x2)5187 ret void5188}5189 5190declare <16 x i8> @llvm.x86.avx512.mask.pmovus.db.128(<4 x i32>, <16 x i8>, i8)5191 5192define <16 x i8>@test_int_x86_avx512_mask_pmovus_db_128(<4 x i32> %x0, <16 x i8> %x1, i8 %x2) #0 {5193;5194; CHECK-LABEL: define <16 x i8> @test_int_x86_avx512_mask_pmovus_db_128(5195; CHECK-SAME: <4 x i32> [[X0:%.*]], <16 x i8> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {5196; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 85197; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 85198; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 85199; CHECK-NEXT: call void @llvm.donothing()5200; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP1]] to i1285201; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 05202; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to i1285203; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 05204; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]5205; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]5206; CHECK: [[BB6]]:5207; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5208; CHECK-NEXT: unreachable5209; CHECK: [[BB7]]:5210; CHECK-NEXT: [[RES0:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmovus.db.128(<4 x i32> [[X0]], <16 x i8> [[X1]], i8 -1)5211; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x i32> [[TMP1]] to i1285212; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP8]], 05213; CHECK-NEXT: [[TMP9:%.*]] = bitcast <16 x i8> [[TMP2]] to i1285214; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP9]], 05215; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]5216; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 05217; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]5218; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB10:.*]], label %[[BB11:.*]], !prof [[PROF1]]5219; CHECK: [[BB10]]:5220; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5221; CHECK-NEXT: unreachable5222; CHECK: [[BB11]]:5223; CHECK-NEXT: [[RES1:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmovus.db.128(<4 x i32> [[X0]], <16 x i8> [[X1]], i8 [[X2]])5224; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i32> [[TMP1]] to i1285225; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i128 [[TMP12]], 05226; CHECK-NEXT: [[_MSCMP8:%.*]] = icmp ne i8 [[TMP3]], 05227; CHECK-NEXT: [[_MSOR9:%.*]] = or i1 [[_MSCMP7]], [[_MSCMP8]]5228; CHECK-NEXT: br i1 [[_MSOR9]], label %[[BB13:.*]], label %[[BB14:.*]], !prof [[PROF1]]5229; CHECK: [[BB13]]:5230; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5231; CHECK-NEXT: unreachable5232; CHECK: [[BB14]]:5233; CHECK-NEXT: [[RES2:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmovus.db.128(<4 x i32> [[X0]], <16 x i8> zeroinitializer, i8 [[X2]])5234; CHECK-NEXT: [[RES3:%.*]] = add <16 x i8> [[RES0]], [[RES1]]5235; CHECK-NEXT: [[RES4:%.*]] = add <16 x i8> [[RES3]], [[RES2]]5236; CHECK-NEXT: store <16 x i8> zeroinitializer, ptr @__msan_retval_tls, align 85237; CHECK-NEXT: ret <16 x i8> [[RES4]]5238;5239 %res0 = call <16 x i8> @llvm.x86.avx512.mask.pmovus.db.128(<4 x i32> %x0, <16 x i8> %x1, i8 -1)5240 %res1 = call <16 x i8> @llvm.x86.avx512.mask.pmovus.db.128(<4 x i32> %x0, <16 x i8> %x1, i8 %x2)5241 %res2 = call <16 x i8> @llvm.x86.avx512.mask.pmovus.db.128(<4 x i32> %x0, <16 x i8> zeroinitializer, i8 %x2)5242 %res3 = add <16 x i8> %res0, %res15243 %res4 = add <16 x i8> %res3, %res25244 ret <16 x i8> %res45245}5246 5247declare void @llvm.x86.avx512.mask.pmovus.db.mem.128(ptr %ptr, <4 x i32>, i8)5248 5249define void @test_int_x86_avx512_mask_pmovus_db_mem_128(ptr %ptr, <4 x i32> %x1, i8 %x2) #0 {5250;5251; CHECK-LABEL: define void @test_int_x86_avx512_mask_pmovus_db_mem_128(5252; CHECK-SAME: ptr [[PTR:%.*]], <4 x i32> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {5253; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 85254; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 85255; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 85256; CHECK-NEXT: call void @llvm.donothing()5257; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05258; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i1285259; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 05260; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]5261; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]5262; CHECK: [[BB5]]:5263; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5264; CHECK-NEXT: unreachable5265; CHECK: [[BB6]]:5266; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovus.db.mem.128(ptr [[PTR]], <4 x i32> [[X1]], i8 -1)5267; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 05268; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i32> [[TMP2]] to i1285269; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP7]], 05270; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]5271; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 05272; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]5273; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]5274; CHECK: [[BB8]]:5275; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5276; CHECK-NEXT: unreachable5277; CHECK: [[BB9]]:5278; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovus.db.mem.128(ptr [[PTR]], <4 x i32> [[X1]], i8 [[X2]])5279; CHECK-NEXT: ret void5280;5281 call void @llvm.x86.avx512.mask.pmovus.db.mem.128(ptr %ptr, <4 x i32> %x1, i8 -1)5282 call void @llvm.x86.avx512.mask.pmovus.db.mem.128(ptr %ptr, <4 x i32> %x1, i8 %x2)5283 ret void5284}5285 5286declare <16 x i8> @llvm.x86.avx512.mask.pmov.db.256(<8 x i32>, <16 x i8>, i8)5287 5288define <16 x i8>@test_int_x86_avx512_mask_pmov_db_256(<8 x i32> %x0, <16 x i8> %x1, i8 %x2) #0 {5289;5290; CHECK-LABEL: define <16 x i8> @test_int_x86_avx512_mask_pmov_db_256(5291; CHECK-SAME: <8 x i32> [[X0:%.*]], <16 x i8> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {5292; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 85293; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 85294; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 85295; CHECK-NEXT: call void @llvm.donothing()5296; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i32> [[TMP1]] to i2565297; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP4]], 05298; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to i1285299; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 05300; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]5301; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]5302; CHECK: [[BB6]]:5303; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5304; CHECK-NEXT: unreachable5305; CHECK: [[BB7]]:5306; CHECK-NEXT: [[RES0:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmov.db.256(<8 x i32> [[X0]], <16 x i8> [[X1]], i8 -1)5307; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i32> [[TMP1]] to i2565308; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i256 [[TMP8]], 05309; CHECK-NEXT: [[TMP9:%.*]] = bitcast <16 x i8> [[TMP2]] to i1285310; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP9]], 05311; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]5312; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 05313; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]5314; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB10:.*]], label %[[BB11:.*]], !prof [[PROF1]]5315; CHECK: [[BB10]]:5316; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5317; CHECK-NEXT: unreachable5318; CHECK: [[BB11]]:5319; CHECK-NEXT: [[RES1:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmov.db.256(<8 x i32> [[X0]], <16 x i8> [[X1]], i8 [[X2]])5320; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x i32> [[TMP1]] to i2565321; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i256 [[TMP12]], 05322; CHECK-NEXT: [[_MSCMP8:%.*]] = icmp ne i8 [[TMP3]], 05323; CHECK-NEXT: [[_MSOR9:%.*]] = or i1 [[_MSCMP7]], [[_MSCMP8]]5324; CHECK-NEXT: br i1 [[_MSOR9]], label %[[BB13:.*]], label %[[BB14:.*]], !prof [[PROF1]]5325; CHECK: [[BB13]]:5326; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5327; CHECK-NEXT: unreachable5328; CHECK: [[BB14]]:5329; CHECK-NEXT: [[RES2:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmov.db.256(<8 x i32> [[X0]], <16 x i8> zeroinitializer, i8 [[X2]])5330; CHECK-NEXT: [[RES3:%.*]] = add <16 x i8> [[RES0]], [[RES1]]5331; CHECK-NEXT: [[RES4:%.*]] = add <16 x i8> [[RES3]], [[RES2]]5332; CHECK-NEXT: store <16 x i8> zeroinitializer, ptr @__msan_retval_tls, align 85333; CHECK-NEXT: ret <16 x i8> [[RES4]]5334;5335 %res0 = call <16 x i8> @llvm.x86.avx512.mask.pmov.db.256(<8 x i32> %x0, <16 x i8> %x1, i8 -1)5336 %res1 = call <16 x i8> @llvm.x86.avx512.mask.pmov.db.256(<8 x i32> %x0, <16 x i8> %x1, i8 %x2)5337 %res2 = call <16 x i8> @llvm.x86.avx512.mask.pmov.db.256(<8 x i32> %x0, <16 x i8> zeroinitializer, i8 %x2)5338 %res3 = add <16 x i8> %res0, %res15339 %res4 = add <16 x i8> %res3, %res25340 ret <16 x i8> %res45341}5342 5343declare void @llvm.x86.avx512.mask.pmov.db.mem.256(ptr %ptr, <8 x i32>, i8)5344 5345define void @test_int_x86_avx512_mask_pmov_db_mem_256(ptr %ptr, <8 x i32> %x1, i8 %x2) #0 {5346;5347; CHECK-LABEL: define void @test_int_x86_avx512_mask_pmov_db_mem_256(5348; CHECK-SAME: ptr [[PTR:%.*]], <8 x i32> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {5349; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 85350; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 85351; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 85352; CHECK-NEXT: call void @llvm.donothing()5353; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05354; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i32> [[TMP2]] to i2565355; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP4]], 05356; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]5357; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]5358; CHECK: [[BB5]]:5359; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5360; CHECK-NEXT: unreachable5361; CHECK: [[BB6]]:5362; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmov.db.mem.256(ptr [[PTR]], <8 x i32> [[X1]], i8 -1)5363; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 05364; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i32> [[TMP2]] to i2565365; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i256 [[TMP7]], 05366; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]5367; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 05368; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]5369; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]5370; CHECK: [[BB8]]:5371; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5372; CHECK-NEXT: unreachable5373; CHECK: [[BB9]]:5374; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmov.db.mem.256(ptr [[PTR]], <8 x i32> [[X1]], i8 [[X2]])5375; CHECK-NEXT: ret void5376;5377 call void @llvm.x86.avx512.mask.pmov.db.mem.256(ptr %ptr, <8 x i32> %x1, i8 -1)5378 call void @llvm.x86.avx512.mask.pmov.db.mem.256(ptr %ptr, <8 x i32> %x1, i8 %x2)5379 ret void5380}5381 5382declare <16 x i8> @llvm.x86.avx512.mask.pmovs.db.256(<8 x i32>, <16 x i8>, i8)5383 5384define <16 x i8>@test_int_x86_avx512_mask_pmovs_db_256(<8 x i32> %x0, <16 x i8> %x1, i8 %x2) #0 {5385;5386; CHECK-LABEL: define <16 x i8> @test_int_x86_avx512_mask_pmovs_db_256(5387; CHECK-SAME: <8 x i32> [[X0:%.*]], <16 x i8> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {5388; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 85389; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 85390; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 85391; CHECK-NEXT: call void @llvm.donothing()5392; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i32> [[TMP1]] to i2565393; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP4]], 05394; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to i1285395; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 05396; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]5397; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]5398; CHECK: [[BB6]]:5399; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5400; CHECK-NEXT: unreachable5401; CHECK: [[BB7]]:5402; CHECK-NEXT: [[RES0:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmovs.db.256(<8 x i32> [[X0]], <16 x i8> [[X1]], i8 -1)5403; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i32> [[TMP1]] to i2565404; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i256 [[TMP8]], 05405; CHECK-NEXT: [[TMP9:%.*]] = bitcast <16 x i8> [[TMP2]] to i1285406; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP9]], 05407; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]5408; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 05409; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]5410; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB10:.*]], label %[[BB11:.*]], !prof [[PROF1]]5411; CHECK: [[BB10]]:5412; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5413; CHECK-NEXT: unreachable5414; CHECK: [[BB11]]:5415; CHECK-NEXT: [[RES1:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmovs.db.256(<8 x i32> [[X0]], <16 x i8> [[X1]], i8 [[X2]])5416; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x i32> [[TMP1]] to i2565417; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i256 [[TMP12]], 05418; CHECK-NEXT: [[_MSCMP8:%.*]] = icmp ne i8 [[TMP3]], 05419; CHECK-NEXT: [[_MSOR9:%.*]] = or i1 [[_MSCMP7]], [[_MSCMP8]]5420; CHECK-NEXT: br i1 [[_MSOR9]], label %[[BB13:.*]], label %[[BB14:.*]], !prof [[PROF1]]5421; CHECK: [[BB13]]:5422; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5423; CHECK-NEXT: unreachable5424; CHECK: [[BB14]]:5425; CHECK-NEXT: [[RES2:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmovs.db.256(<8 x i32> [[X0]], <16 x i8> zeroinitializer, i8 [[X2]])5426; CHECK-NEXT: [[RES3:%.*]] = add <16 x i8> [[RES0]], [[RES1]]5427; CHECK-NEXT: [[RES4:%.*]] = add <16 x i8> [[RES3]], [[RES2]]5428; CHECK-NEXT: store <16 x i8> zeroinitializer, ptr @__msan_retval_tls, align 85429; CHECK-NEXT: ret <16 x i8> [[RES4]]5430;5431 %res0 = call <16 x i8> @llvm.x86.avx512.mask.pmovs.db.256(<8 x i32> %x0, <16 x i8> %x1, i8 -1)5432 %res1 = call <16 x i8> @llvm.x86.avx512.mask.pmovs.db.256(<8 x i32> %x0, <16 x i8> %x1, i8 %x2)5433 %res2 = call <16 x i8> @llvm.x86.avx512.mask.pmovs.db.256(<8 x i32> %x0, <16 x i8> zeroinitializer, i8 %x2)5434 %res3 = add <16 x i8> %res0, %res15435 %res4 = add <16 x i8> %res3, %res25436 ret <16 x i8> %res45437}5438 5439declare void @llvm.x86.avx512.mask.pmovs.db.mem.256(ptr %ptr, <8 x i32>, i8)5440 5441define void @test_int_x86_avx512_mask_pmovs_db_mem_256(ptr %ptr, <8 x i32> %x1, i8 %x2) #0 {5442;5443; CHECK-LABEL: define void @test_int_x86_avx512_mask_pmovs_db_mem_256(5444; CHECK-SAME: ptr [[PTR:%.*]], <8 x i32> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {5445; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 85446; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 85447; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 85448; CHECK-NEXT: call void @llvm.donothing()5449; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05450; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i32> [[TMP2]] to i2565451; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP4]], 05452; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]5453; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]5454; CHECK: [[BB5]]:5455; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5456; CHECK-NEXT: unreachable5457; CHECK: [[BB6]]:5458; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovs.db.mem.256(ptr [[PTR]], <8 x i32> [[X1]], i8 -1)5459; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 05460; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i32> [[TMP2]] to i2565461; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i256 [[TMP7]], 05462; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]5463; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 05464; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]5465; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]5466; CHECK: [[BB8]]:5467; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5468; CHECK-NEXT: unreachable5469; CHECK: [[BB9]]:5470; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovs.db.mem.256(ptr [[PTR]], <8 x i32> [[X1]], i8 [[X2]])5471; CHECK-NEXT: ret void5472;5473 call void @llvm.x86.avx512.mask.pmovs.db.mem.256(ptr %ptr, <8 x i32> %x1, i8 -1)5474 call void @llvm.x86.avx512.mask.pmovs.db.mem.256(ptr %ptr, <8 x i32> %x1, i8 %x2)5475 ret void5476}5477 5478declare <16 x i8> @llvm.x86.avx512.mask.pmovus.db.256(<8 x i32>, <16 x i8>, i8)5479 5480define <16 x i8>@test_int_x86_avx512_mask_pmovus_db_256(<8 x i32> %x0, <16 x i8> %x1, i8 %x2) #0 {5481;5482; CHECK-LABEL: define <16 x i8> @test_int_x86_avx512_mask_pmovus_db_256(5483; CHECK-SAME: <8 x i32> [[X0:%.*]], <16 x i8> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {5484; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 85485; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 85486; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 85487; CHECK-NEXT: call void @llvm.donothing()5488; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i32> [[TMP1]] to i2565489; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP4]], 05490; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to i1285491; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 05492; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]5493; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]5494; CHECK: [[BB6]]:5495; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5496; CHECK-NEXT: unreachable5497; CHECK: [[BB7]]:5498; CHECK-NEXT: [[RES0:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmovus.db.256(<8 x i32> [[X0]], <16 x i8> [[X1]], i8 -1)5499; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i32> [[TMP1]] to i2565500; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i256 [[TMP8]], 05501; CHECK-NEXT: [[TMP9:%.*]] = bitcast <16 x i8> [[TMP2]] to i1285502; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP9]], 05503; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]5504; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 05505; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]5506; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB10:.*]], label %[[BB11:.*]], !prof [[PROF1]]5507; CHECK: [[BB10]]:5508; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5509; CHECK-NEXT: unreachable5510; CHECK: [[BB11]]:5511; CHECK-NEXT: [[RES1:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmovus.db.256(<8 x i32> [[X0]], <16 x i8> [[X1]], i8 [[X2]])5512; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x i32> [[TMP1]] to i2565513; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i256 [[TMP12]], 05514; CHECK-NEXT: [[_MSCMP8:%.*]] = icmp ne i8 [[TMP3]], 05515; CHECK-NEXT: [[_MSOR9:%.*]] = or i1 [[_MSCMP7]], [[_MSCMP8]]5516; CHECK-NEXT: br i1 [[_MSOR9]], label %[[BB13:.*]], label %[[BB14:.*]], !prof [[PROF1]]5517; CHECK: [[BB13]]:5518; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5519; CHECK-NEXT: unreachable5520; CHECK: [[BB14]]:5521; CHECK-NEXT: [[RES2:%.*]] = call <16 x i8> @llvm.x86.avx512.mask.pmovus.db.256(<8 x i32> [[X0]], <16 x i8> zeroinitializer, i8 [[X2]])5522; CHECK-NEXT: [[RES3:%.*]] = add <16 x i8> [[RES0]], [[RES1]]5523; CHECK-NEXT: [[RES4:%.*]] = add <16 x i8> [[RES3]], [[RES2]]5524; CHECK-NEXT: store <16 x i8> zeroinitializer, ptr @__msan_retval_tls, align 85525; CHECK-NEXT: ret <16 x i8> [[RES4]]5526;5527 %res0 = call <16 x i8> @llvm.x86.avx512.mask.pmovus.db.256(<8 x i32> %x0, <16 x i8> %x1, i8 -1)5528 %res1 = call <16 x i8> @llvm.x86.avx512.mask.pmovus.db.256(<8 x i32> %x0, <16 x i8> %x1, i8 %x2)5529 %res2 = call <16 x i8> @llvm.x86.avx512.mask.pmovus.db.256(<8 x i32> %x0, <16 x i8> zeroinitializer, i8 %x2)5530 %res3 = add <16 x i8> %res0, %res15531 %res4 = add <16 x i8> %res3, %res25532 ret <16 x i8> %res45533}5534 5535declare void @llvm.x86.avx512.mask.pmovus.db.mem.256(ptr %ptr, <8 x i32>, i8)5536 5537define void @test_int_x86_avx512_mask_pmovus_db_mem_256(ptr %ptr, <8 x i32> %x1, i8 %x2) #0 {5538;5539; CHECK-LABEL: define void @test_int_x86_avx512_mask_pmovus_db_mem_256(5540; CHECK-SAME: ptr [[PTR:%.*]], <8 x i32> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {5541; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 85542; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 85543; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 85544; CHECK-NEXT: call void @llvm.donothing()5545; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05546; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i32> [[TMP2]] to i2565547; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP4]], 05548; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]5549; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]5550; CHECK: [[BB5]]:5551; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5552; CHECK-NEXT: unreachable5553; CHECK: [[BB6]]:5554; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovus.db.mem.256(ptr [[PTR]], <8 x i32> [[X1]], i8 -1)5555; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 05556; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i32> [[TMP2]] to i2565557; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i256 [[TMP7]], 05558; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]5559; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 05560; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]5561; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]5562; CHECK: [[BB8]]:5563; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5564; CHECK-NEXT: unreachable5565; CHECK: [[BB9]]:5566; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovus.db.mem.256(ptr [[PTR]], <8 x i32> [[X1]], i8 [[X2]])5567; CHECK-NEXT: ret void5568;5569 call void @llvm.x86.avx512.mask.pmovus.db.mem.256(ptr %ptr, <8 x i32> %x1, i8 -1)5570 call void @llvm.x86.avx512.mask.pmovus.db.mem.256(ptr %ptr, <8 x i32> %x1, i8 %x2)5571 ret void5572}5573 5574declare <8 x i16> @llvm.x86.avx512.mask.pmov.dw.128(<4 x i32>, <8 x i16>, i8)5575 5576define <8 x i16>@test_int_x86_avx512_mask_pmov_dw_128(<4 x i32> %x0, <8 x i16> %x1, i8 %x2) #0 {5577;5578; CHECK-LABEL: define <8 x i16> @test_int_x86_avx512_mask_pmov_dw_128(5579; CHECK-SAME: <4 x i32> [[X0:%.*]], <8 x i16> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {5580; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 85581; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 85582; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 85583; CHECK-NEXT: call void @llvm.donothing()5584; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP1]] to i1285585; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 05586; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP2]] to i1285587; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 05588; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]5589; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]5590; CHECK: [[BB6]]:5591; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5592; CHECK-NEXT: unreachable5593; CHECK: [[BB7]]:5594; CHECK-NEXT: [[RES0:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmov.dw.128(<4 x i32> [[X0]], <8 x i16> [[X1]], i8 -1)5595; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x i32> [[TMP1]] to i1285596; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP8]], 05597; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i16> [[TMP2]] to i1285598; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP9]], 05599; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]5600; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 05601; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]5602; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB10:.*]], label %[[BB11:.*]], !prof [[PROF1]]5603; CHECK: [[BB10]]:5604; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5605; CHECK-NEXT: unreachable5606; CHECK: [[BB11]]:5607; CHECK-NEXT: [[RES1:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmov.dw.128(<4 x i32> [[X0]], <8 x i16> [[X1]], i8 [[X2]])5608; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i32> [[TMP1]] to i1285609; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i128 [[TMP12]], 05610; CHECK-NEXT: [[_MSCMP8:%.*]] = icmp ne i8 [[TMP3]], 05611; CHECK-NEXT: [[_MSOR9:%.*]] = or i1 [[_MSCMP7]], [[_MSCMP8]]5612; CHECK-NEXT: br i1 [[_MSOR9]], label %[[BB13:.*]], label %[[BB14:.*]], !prof [[PROF1]]5613; CHECK: [[BB13]]:5614; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5615; CHECK-NEXT: unreachable5616; CHECK: [[BB14]]:5617; CHECK-NEXT: [[RES2:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmov.dw.128(<4 x i32> [[X0]], <8 x i16> zeroinitializer, i8 [[X2]])5618; CHECK-NEXT: [[RES3:%.*]] = add <8 x i16> [[RES0]], [[RES1]]5619; CHECK-NEXT: [[RES4:%.*]] = add <8 x i16> [[RES3]], [[RES2]]5620; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 85621; CHECK-NEXT: ret <8 x i16> [[RES4]]5622;5623 %res0 = call <8 x i16> @llvm.x86.avx512.mask.pmov.dw.128(<4 x i32> %x0, <8 x i16> %x1, i8 -1)5624 %res1 = call <8 x i16> @llvm.x86.avx512.mask.pmov.dw.128(<4 x i32> %x0, <8 x i16> %x1, i8 %x2)5625 %res2 = call <8 x i16> @llvm.x86.avx512.mask.pmov.dw.128(<4 x i32> %x0, <8 x i16> zeroinitializer, i8 %x2)5626 %res3 = add <8 x i16> %res0, %res15627 %res4 = add <8 x i16> %res3, %res25628 ret <8 x i16> %res45629}5630 5631declare void @llvm.x86.avx512.mask.pmov.dw.mem.128(ptr %ptr, <4 x i32>, i8)5632 5633define void @test_int_x86_avx512_mask_pmov_dw_mem_128(ptr %ptr, <4 x i32> %x1, i8 %x2) #0 {5634;5635; CHECK-LABEL: define void @test_int_x86_avx512_mask_pmov_dw_mem_128(5636; CHECK-SAME: ptr [[PTR:%.*]], <4 x i32> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {5637; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 85638; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 85639; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 85640; CHECK-NEXT: call void @llvm.donothing()5641; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05642; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i1285643; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 05644; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]5645; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]5646; CHECK: [[BB5]]:5647; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5648; CHECK-NEXT: unreachable5649; CHECK: [[BB6]]:5650; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmov.dw.mem.128(ptr [[PTR]], <4 x i32> [[X1]], i8 -1)5651; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 05652; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i32> [[TMP2]] to i1285653; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP7]], 05654; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]5655; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 05656; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]5657; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]5658; CHECK: [[BB8]]:5659; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5660; CHECK-NEXT: unreachable5661; CHECK: [[BB9]]:5662; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmov.dw.mem.128(ptr [[PTR]], <4 x i32> [[X1]], i8 [[X2]])5663; CHECK-NEXT: ret void5664;5665 call void @llvm.x86.avx512.mask.pmov.dw.mem.128(ptr %ptr, <4 x i32> %x1, i8 -1)5666 call void @llvm.x86.avx512.mask.pmov.dw.mem.128(ptr %ptr, <4 x i32> %x1, i8 %x2)5667 ret void5668}5669 5670declare <8 x i16> @llvm.x86.avx512.mask.pmovs.dw.128(<4 x i32>, <8 x i16>, i8)5671 5672define <8 x i16>@test_int_x86_avx512_mask_pmovs_dw_128(<4 x i32> %x0, <8 x i16> %x1, i8 %x2) #0 {5673;5674; CHECK-LABEL: define <8 x i16> @test_int_x86_avx512_mask_pmovs_dw_128(5675; CHECK-SAME: <4 x i32> [[X0:%.*]], <8 x i16> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {5676; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 85677; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 85678; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 85679; CHECK-NEXT: call void @llvm.donothing()5680; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP1]] to i1285681; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 05682; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP2]] to i1285683; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 05684; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]5685; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]5686; CHECK: [[BB6]]:5687; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5688; CHECK-NEXT: unreachable5689; CHECK: [[BB7]]:5690; CHECK-NEXT: [[RES0:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmovs.dw.128(<4 x i32> [[X0]], <8 x i16> [[X1]], i8 -1)5691; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x i32> [[TMP1]] to i1285692; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP8]], 05693; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i16> [[TMP2]] to i1285694; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP9]], 05695; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]5696; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 05697; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]5698; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB10:.*]], label %[[BB11:.*]], !prof [[PROF1]]5699; CHECK: [[BB10]]:5700; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5701; CHECK-NEXT: unreachable5702; CHECK: [[BB11]]:5703; CHECK-NEXT: [[RES1:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmovs.dw.128(<4 x i32> [[X0]], <8 x i16> [[X1]], i8 [[X2]])5704; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i32> [[TMP1]] to i1285705; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i128 [[TMP12]], 05706; CHECK-NEXT: [[_MSCMP8:%.*]] = icmp ne i8 [[TMP3]], 05707; CHECK-NEXT: [[_MSOR9:%.*]] = or i1 [[_MSCMP7]], [[_MSCMP8]]5708; CHECK-NEXT: br i1 [[_MSOR9]], label %[[BB13:.*]], label %[[BB14:.*]], !prof [[PROF1]]5709; CHECK: [[BB13]]:5710; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5711; CHECK-NEXT: unreachable5712; CHECK: [[BB14]]:5713; CHECK-NEXT: [[RES2:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmovs.dw.128(<4 x i32> [[X0]], <8 x i16> zeroinitializer, i8 [[X2]])5714; CHECK-NEXT: [[RES3:%.*]] = add <8 x i16> [[RES0]], [[RES1]]5715; CHECK-NEXT: [[RES4:%.*]] = add <8 x i16> [[RES3]], [[RES2]]5716; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 85717; CHECK-NEXT: ret <8 x i16> [[RES4]]5718;5719 %res0 = call <8 x i16> @llvm.x86.avx512.mask.pmovs.dw.128(<4 x i32> %x0, <8 x i16> %x1, i8 -1)5720 %res1 = call <8 x i16> @llvm.x86.avx512.mask.pmovs.dw.128(<4 x i32> %x0, <8 x i16> %x1, i8 %x2)5721 %res2 = call <8 x i16> @llvm.x86.avx512.mask.pmovs.dw.128(<4 x i32> %x0, <8 x i16> zeroinitializer, i8 %x2)5722 %res3 = add <8 x i16> %res0, %res15723 %res4 = add <8 x i16> %res3, %res25724 ret <8 x i16> %res45725}5726 5727declare void @llvm.x86.avx512.mask.pmovs.dw.mem.128(ptr %ptr, <4 x i32>, i8)5728 5729define void @test_int_x86_avx512_mask_pmovs_dw_mem_128(ptr %ptr, <4 x i32> %x1, i8 %x2) #0 {5730;5731; CHECK-LABEL: define void @test_int_x86_avx512_mask_pmovs_dw_mem_128(5732; CHECK-SAME: ptr [[PTR:%.*]], <4 x i32> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {5733; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 85734; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 85735; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 85736; CHECK-NEXT: call void @llvm.donothing()5737; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05738; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i1285739; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 05740; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]5741; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]5742; CHECK: [[BB5]]:5743; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5744; CHECK-NEXT: unreachable5745; CHECK: [[BB6]]:5746; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovs.dw.mem.128(ptr [[PTR]], <4 x i32> [[X1]], i8 -1)5747; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 05748; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i32> [[TMP2]] to i1285749; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP7]], 05750; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]5751; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 05752; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]5753; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]5754; CHECK: [[BB8]]:5755; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5756; CHECK-NEXT: unreachable5757; CHECK: [[BB9]]:5758; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovs.dw.mem.128(ptr [[PTR]], <4 x i32> [[X1]], i8 [[X2]])5759; CHECK-NEXT: ret void5760;5761 call void @llvm.x86.avx512.mask.pmovs.dw.mem.128(ptr %ptr, <4 x i32> %x1, i8 -1)5762 call void @llvm.x86.avx512.mask.pmovs.dw.mem.128(ptr %ptr, <4 x i32> %x1, i8 %x2)5763 ret void5764}5765 5766declare <8 x i16> @llvm.x86.avx512.mask.pmovus.dw.128(<4 x i32>, <8 x i16>, i8)5767 5768define <8 x i16>@test_int_x86_avx512_mask_pmovus_dw_128(<4 x i32> %x0, <8 x i16> %x1, i8 %x2) #0 {5769;5770; CHECK-LABEL: define <8 x i16> @test_int_x86_avx512_mask_pmovus_dw_128(5771; CHECK-SAME: <4 x i32> [[X0:%.*]], <8 x i16> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {5772; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 85773; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 85774; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 85775; CHECK-NEXT: call void @llvm.donothing()5776; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP1]] to i1285777; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 05778; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP2]] to i1285779; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 05780; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]5781; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]5782; CHECK: [[BB6]]:5783; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5784; CHECK-NEXT: unreachable5785; CHECK: [[BB7]]:5786; CHECK-NEXT: [[RES0:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmovus.dw.128(<4 x i32> [[X0]], <8 x i16> [[X1]], i8 -1)5787; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x i32> [[TMP1]] to i1285788; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP8]], 05789; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i16> [[TMP2]] to i1285790; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP9]], 05791; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]5792; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 05793; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]5794; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB10:.*]], label %[[BB11:.*]], !prof [[PROF1]]5795; CHECK: [[BB10]]:5796; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5797; CHECK-NEXT: unreachable5798; CHECK: [[BB11]]:5799; CHECK-NEXT: [[RES1:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmovus.dw.128(<4 x i32> [[X0]], <8 x i16> [[X1]], i8 [[X2]])5800; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i32> [[TMP1]] to i1285801; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i128 [[TMP12]], 05802; CHECK-NEXT: [[_MSCMP8:%.*]] = icmp ne i8 [[TMP3]], 05803; CHECK-NEXT: [[_MSOR9:%.*]] = or i1 [[_MSCMP7]], [[_MSCMP8]]5804; CHECK-NEXT: br i1 [[_MSOR9]], label %[[BB13:.*]], label %[[BB14:.*]], !prof [[PROF1]]5805; CHECK: [[BB13]]:5806; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5807; CHECK-NEXT: unreachable5808; CHECK: [[BB14]]:5809; CHECK-NEXT: [[RES2:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmovus.dw.128(<4 x i32> [[X0]], <8 x i16> zeroinitializer, i8 [[X2]])5810; CHECK-NEXT: [[RES3:%.*]] = add <8 x i16> [[RES0]], [[RES1]]5811; CHECK-NEXT: [[RES4:%.*]] = add <8 x i16> [[RES3]], [[RES2]]5812; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 85813; CHECK-NEXT: ret <8 x i16> [[RES4]]5814;5815 %res0 = call <8 x i16> @llvm.x86.avx512.mask.pmovus.dw.128(<4 x i32> %x0, <8 x i16> %x1, i8 -1)5816 %res1 = call <8 x i16> @llvm.x86.avx512.mask.pmovus.dw.128(<4 x i32> %x0, <8 x i16> %x1, i8 %x2)5817 %res2 = call <8 x i16> @llvm.x86.avx512.mask.pmovus.dw.128(<4 x i32> %x0, <8 x i16> zeroinitializer, i8 %x2)5818 %res3 = add <8 x i16> %res0, %res15819 %res4 = add <8 x i16> %res3, %res25820 ret <8 x i16> %res45821}5822 5823declare void @llvm.x86.avx512.mask.pmovus.dw.mem.128(ptr %ptr, <4 x i32>, i8)5824 5825define void @test_int_x86_avx512_mask_pmovus_dw_mem_128(ptr %ptr, <4 x i32> %x1, i8 %x2) #0 {5826;5827; CHECK-LABEL: define void @test_int_x86_avx512_mask_pmovus_dw_mem_128(5828; CHECK-SAME: ptr [[PTR:%.*]], <4 x i32> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {5829; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 85830; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 85831; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 85832; CHECK-NEXT: call void @llvm.donothing()5833; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05834; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i1285835; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 05836; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]5837; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]5838; CHECK: [[BB5]]:5839; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5840; CHECK-NEXT: unreachable5841; CHECK: [[BB6]]:5842; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovus.dw.mem.128(ptr [[PTR]], <4 x i32> [[X1]], i8 -1)5843; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 05844; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i32> [[TMP2]] to i1285845; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP7]], 05846; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]5847; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 05848; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]5849; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]5850; CHECK: [[BB8]]:5851; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5852; CHECK-NEXT: unreachable5853; CHECK: [[BB9]]:5854; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovus.dw.mem.128(ptr [[PTR]], <4 x i32> [[X1]], i8 [[X2]])5855; CHECK-NEXT: ret void5856;5857 call void @llvm.x86.avx512.mask.pmovus.dw.mem.128(ptr %ptr, <4 x i32> %x1, i8 -1)5858 call void @llvm.x86.avx512.mask.pmovus.dw.mem.128(ptr %ptr, <4 x i32> %x1, i8 %x2)5859 ret void5860}5861 5862declare <8 x i16> @llvm.x86.avx512.mask.pmov.dw.256(<8 x i32>, <8 x i16>, i8)5863 5864define <8 x i16>@test_int_x86_avx512_mask_pmov_dw_256(<8 x i32> %x0, <8 x i16> %x1, i8 %x2) #0 {5865;5866; CHECK-LABEL: define <8 x i16> @test_int_x86_avx512_mask_pmov_dw_256(5867; CHECK-SAME: <8 x i32> [[X0:%.*]], <8 x i16> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {5868; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 85869; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 85870; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 85871; CHECK-NEXT: call void @llvm.donothing()5872; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i32> [[TMP1]] to i2565873; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP4]], 05874; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP2]] to i1285875; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 05876; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]5877; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]5878; CHECK: [[BB6]]:5879; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5880; CHECK-NEXT: unreachable5881; CHECK: [[BB7]]:5882; CHECK-NEXT: [[RES0:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmov.dw.256(<8 x i32> [[X0]], <8 x i16> [[X1]], i8 -1)5883; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i32> [[TMP1]] to i2565884; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i256 [[TMP8]], 05885; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i16> [[TMP2]] to i1285886; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP9]], 05887; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]5888; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 05889; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]5890; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB10:.*]], label %[[BB11:.*]], !prof [[PROF1]]5891; CHECK: [[BB10]]:5892; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5893; CHECK-NEXT: unreachable5894; CHECK: [[BB11]]:5895; CHECK-NEXT: [[RES1:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmov.dw.256(<8 x i32> [[X0]], <8 x i16> [[X1]], i8 [[X2]])5896; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x i32> [[TMP1]] to i2565897; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i256 [[TMP12]], 05898; CHECK-NEXT: [[_MSCMP8:%.*]] = icmp ne i8 [[TMP3]], 05899; CHECK-NEXT: [[_MSOR9:%.*]] = or i1 [[_MSCMP7]], [[_MSCMP8]]5900; CHECK-NEXT: br i1 [[_MSOR9]], label %[[BB13:.*]], label %[[BB14:.*]], !prof [[PROF1]]5901; CHECK: [[BB13]]:5902; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5903; CHECK-NEXT: unreachable5904; CHECK: [[BB14]]:5905; CHECK-NEXT: [[RES2:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmov.dw.256(<8 x i32> [[X0]], <8 x i16> zeroinitializer, i8 [[X2]])5906; CHECK-NEXT: [[RES3:%.*]] = add <8 x i16> [[RES0]], [[RES1]]5907; CHECK-NEXT: [[RES4:%.*]] = add <8 x i16> [[RES3]], [[RES2]]5908; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 85909; CHECK-NEXT: ret <8 x i16> [[RES4]]5910;5911 %res0 = call <8 x i16> @llvm.x86.avx512.mask.pmov.dw.256(<8 x i32> %x0, <8 x i16> %x1, i8 -1)5912 %res1 = call <8 x i16> @llvm.x86.avx512.mask.pmov.dw.256(<8 x i32> %x0, <8 x i16> %x1, i8 %x2)5913 %res2 = call <8 x i16> @llvm.x86.avx512.mask.pmov.dw.256(<8 x i32> %x0, <8 x i16> zeroinitializer, i8 %x2)5914 %res3 = add <8 x i16> %res0, %res15915 %res4 = add <8 x i16> %res3, %res25916 ret <8 x i16> %res45917}5918 5919declare void @llvm.x86.avx512.mask.pmov.dw.mem.256(ptr %ptr, <8 x i32>, i8)5920 5921define void @test_int_x86_avx512_mask_pmov_dw_mem_256(ptr %ptr, <8 x i32> %x1, i8 %x2) #0 {5922;5923; CHECK-LABEL: define void @test_int_x86_avx512_mask_pmov_dw_mem_256(5924; CHECK-SAME: ptr [[PTR:%.*]], <8 x i32> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {5925; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 85926; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 85927; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 85928; CHECK-NEXT: call void @llvm.donothing()5929; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05930; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i32> [[TMP2]] to i2565931; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP4]], 05932; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]5933; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]5934; CHECK: [[BB5]]:5935; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5936; CHECK-NEXT: unreachable5937; CHECK: [[BB6]]:5938; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmov.dw.mem.256(ptr [[PTR]], <8 x i32> [[X1]], i8 -1)5939; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 05940; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i32> [[TMP2]] to i2565941; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i256 [[TMP7]], 05942; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]5943; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 05944; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]5945; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]5946; CHECK: [[BB8]]:5947; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5948; CHECK-NEXT: unreachable5949; CHECK: [[BB9]]:5950; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmov.dw.mem.256(ptr [[PTR]], <8 x i32> [[X1]], i8 [[X2]])5951; CHECK-NEXT: ret void5952;5953 call void @llvm.x86.avx512.mask.pmov.dw.mem.256(ptr %ptr, <8 x i32> %x1, i8 -1)5954 call void @llvm.x86.avx512.mask.pmov.dw.mem.256(ptr %ptr, <8 x i32> %x1, i8 %x2)5955 ret void5956}5957 5958declare <8 x i16> @llvm.x86.avx512.mask.pmovs.dw.256(<8 x i32>, <8 x i16>, i8)5959 5960define <8 x i16>@test_int_x86_avx512_mask_pmovs_dw_256(<8 x i32> %x0, <8 x i16> %x1, i8 %x2) #0 {5961;5962; CHECK-LABEL: define <8 x i16> @test_int_x86_avx512_mask_pmovs_dw_256(5963; CHECK-SAME: <8 x i32> [[X0:%.*]], <8 x i16> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {5964; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 85965; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 85966; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 85967; CHECK-NEXT: call void @llvm.donothing()5968; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i32> [[TMP1]] to i2565969; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP4]], 05970; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP2]] to i1285971; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 05972; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]5973; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]5974; CHECK: [[BB6]]:5975; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5976; CHECK-NEXT: unreachable5977; CHECK: [[BB7]]:5978; CHECK-NEXT: [[RES0:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmovs.dw.256(<8 x i32> [[X0]], <8 x i16> [[X1]], i8 -1)5979; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i32> [[TMP1]] to i2565980; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i256 [[TMP8]], 05981; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i16> [[TMP2]] to i1285982; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP9]], 05983; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]5984; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 05985; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]5986; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB10:.*]], label %[[BB11:.*]], !prof [[PROF1]]5987; CHECK: [[BB10]]:5988; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5989; CHECK-NEXT: unreachable5990; CHECK: [[BB11]]:5991; CHECK-NEXT: [[RES1:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmovs.dw.256(<8 x i32> [[X0]], <8 x i16> [[X1]], i8 [[X2]])5992; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x i32> [[TMP1]] to i2565993; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i256 [[TMP12]], 05994; CHECK-NEXT: [[_MSCMP8:%.*]] = icmp ne i8 [[TMP3]], 05995; CHECK-NEXT: [[_MSOR9:%.*]] = or i1 [[_MSCMP7]], [[_MSCMP8]]5996; CHECK-NEXT: br i1 [[_MSOR9]], label %[[BB13:.*]], label %[[BB14:.*]], !prof [[PROF1]]5997; CHECK: [[BB13]]:5998; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]5999; CHECK-NEXT: unreachable6000; CHECK: [[BB14]]:6001; CHECK-NEXT: [[RES2:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmovs.dw.256(<8 x i32> [[X0]], <8 x i16> zeroinitializer, i8 [[X2]])6002; CHECK-NEXT: [[RES3:%.*]] = add <8 x i16> [[RES0]], [[RES1]]6003; CHECK-NEXT: [[RES4:%.*]] = add <8 x i16> [[RES3]], [[RES2]]6004; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 86005; CHECK-NEXT: ret <8 x i16> [[RES4]]6006;6007 %res0 = call <8 x i16> @llvm.x86.avx512.mask.pmovs.dw.256(<8 x i32> %x0, <8 x i16> %x1, i8 -1)6008 %res1 = call <8 x i16> @llvm.x86.avx512.mask.pmovs.dw.256(<8 x i32> %x0, <8 x i16> %x1, i8 %x2)6009 %res2 = call <8 x i16> @llvm.x86.avx512.mask.pmovs.dw.256(<8 x i32> %x0, <8 x i16> zeroinitializer, i8 %x2)6010 %res3 = add <8 x i16> %res0, %res16011 %res4 = add <8 x i16> %res3, %res26012 ret <8 x i16> %res46013}6014 6015declare void @llvm.x86.avx512.mask.pmovs.dw.mem.256(ptr %ptr, <8 x i32>, i8)6016 6017define void @test_int_x86_avx512_mask_pmovs_dw_mem_256(ptr %ptr, <8 x i32> %x1, i8 %x2) #0 {6018;6019; CHECK-LABEL: define void @test_int_x86_avx512_mask_pmovs_dw_mem_256(6020; CHECK-SAME: ptr [[PTR:%.*]], <8 x i32> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {6021; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 86022; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 86023; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 86024; CHECK-NEXT: call void @llvm.donothing()6025; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 06026; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i32> [[TMP2]] to i2566027; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP4]], 06028; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6029; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]6030; CHECK: [[BB5]]:6031; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]6032; CHECK-NEXT: unreachable6033; CHECK: [[BB6]]:6034; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovs.dw.mem.256(ptr [[PTR]], <8 x i32> [[X1]], i8 -1)6035; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 06036; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i32> [[TMP2]] to i2566037; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i256 [[TMP7]], 06038; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]6039; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 06040; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]6041; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]6042; CHECK: [[BB8]]:6043; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]6044; CHECK-NEXT: unreachable6045; CHECK: [[BB9]]:6046; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovs.dw.mem.256(ptr [[PTR]], <8 x i32> [[X1]], i8 [[X2]])6047; CHECK-NEXT: ret void6048;6049 call void @llvm.x86.avx512.mask.pmovs.dw.mem.256(ptr %ptr, <8 x i32> %x1, i8 -1)6050 call void @llvm.x86.avx512.mask.pmovs.dw.mem.256(ptr %ptr, <8 x i32> %x1, i8 %x2)6051 ret void6052}6053 6054declare <8 x i16> @llvm.x86.avx512.mask.pmovus.dw.256(<8 x i32>, <8 x i16>, i8)6055 6056define <8 x i16>@test_int_x86_avx512_mask_pmovus_dw_256(<8 x i32> %x0, <8 x i16> %x1, i8 %x2) #0 {6057;6058; CHECK-LABEL: define <8 x i16> @test_int_x86_avx512_mask_pmovus_dw_256(6059; CHECK-SAME: <8 x i32> [[X0:%.*]], <8 x i16> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {6060; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 86061; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 86062; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 86063; CHECK-NEXT: call void @llvm.donothing()6064; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i32> [[TMP1]] to i2566065; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP4]], 06066; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP2]] to i1286067; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 06068; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6069; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]6070; CHECK: [[BB6]]:6071; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]6072; CHECK-NEXT: unreachable6073; CHECK: [[BB7]]:6074; CHECK-NEXT: [[RES0:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmovus.dw.256(<8 x i32> [[X0]], <8 x i16> [[X1]], i8 -1)6075; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i32> [[TMP1]] to i2566076; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i256 [[TMP8]], 06077; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i16> [[TMP2]] to i1286078; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP9]], 06079; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]6080; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 06081; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]6082; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB10:.*]], label %[[BB11:.*]], !prof [[PROF1]]6083; CHECK: [[BB10]]:6084; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]6085; CHECK-NEXT: unreachable6086; CHECK: [[BB11]]:6087; CHECK-NEXT: [[RES1:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmovus.dw.256(<8 x i32> [[X0]], <8 x i16> [[X1]], i8 [[X2]])6088; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x i32> [[TMP1]] to i2566089; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i256 [[TMP12]], 06090; CHECK-NEXT: [[_MSCMP8:%.*]] = icmp ne i8 [[TMP3]], 06091; CHECK-NEXT: [[_MSOR9:%.*]] = or i1 [[_MSCMP7]], [[_MSCMP8]]6092; CHECK-NEXT: br i1 [[_MSOR9]], label %[[BB13:.*]], label %[[BB14:.*]], !prof [[PROF1]]6093; CHECK: [[BB13]]:6094; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]6095; CHECK-NEXT: unreachable6096; CHECK: [[BB14]]:6097; CHECK-NEXT: [[RES2:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.pmovus.dw.256(<8 x i32> [[X0]], <8 x i16> zeroinitializer, i8 [[X2]])6098; CHECK-NEXT: [[RES3:%.*]] = add <8 x i16> [[RES0]], [[RES1]]6099; CHECK-NEXT: [[RES4:%.*]] = add <8 x i16> [[RES3]], [[RES2]]6100; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 86101; CHECK-NEXT: ret <8 x i16> [[RES4]]6102;6103 %res0 = call <8 x i16> @llvm.x86.avx512.mask.pmovus.dw.256(<8 x i32> %x0, <8 x i16> %x1, i8 -1)6104 %res1 = call <8 x i16> @llvm.x86.avx512.mask.pmovus.dw.256(<8 x i32> %x0, <8 x i16> %x1, i8 %x2)6105 %res2 = call <8 x i16> @llvm.x86.avx512.mask.pmovus.dw.256(<8 x i32> %x0, <8 x i16> zeroinitializer, i8 %x2)6106 %res3 = add <8 x i16> %res0, %res16107 %res4 = add <8 x i16> %res3, %res26108 ret <8 x i16> %res46109}6110 6111declare void @llvm.x86.avx512.mask.pmovus.dw.mem.256(ptr %ptr, <8 x i32>, i8)6112 6113define void @test_int_x86_avx512_mask_pmovus_dw_mem_256(ptr %ptr, <8 x i32> %x1, i8 %x2) #0 {6114;6115; CHECK-LABEL: define void @test_int_x86_avx512_mask_pmovus_dw_mem_256(6116; CHECK-SAME: ptr [[PTR:%.*]], <8 x i32> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {6117; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 86118; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 86119; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 86120; CHECK-NEXT: call void @llvm.donothing()6121; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 06122; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i32> [[TMP2]] to i2566123; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP4]], 06124; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6125; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]6126; CHECK: [[BB5]]:6127; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]6128; CHECK-NEXT: unreachable6129; CHECK: [[BB6]]:6130; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovus.dw.mem.256(ptr [[PTR]], <8 x i32> [[X1]], i8 -1)6131; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 06132; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i32> [[TMP2]] to i2566133; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i256 [[TMP7]], 06134; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]6135; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 06136; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSOR4]], [[_MSCMP5]]6137; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]6138; CHECK: [[BB8]]:6139; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]6140; CHECK-NEXT: unreachable6141; CHECK: [[BB9]]:6142; CHECK-NEXT: call void @llvm.x86.avx512.mask.pmovus.dw.mem.256(ptr [[PTR]], <8 x i32> [[X1]], i8 [[X2]])6143; CHECK-NEXT: ret void6144;6145 call void @llvm.x86.avx512.mask.pmovus.dw.mem.256(ptr %ptr, <8 x i32> %x1, i8 -1)6146 call void @llvm.x86.avx512.mask.pmovus.dw.mem.256(ptr %ptr, <8 x i32> %x1, i8 %x2)6147 ret void6148}6149 6150declare <4 x i32> @llvm.x86.avx512.mask.cvtpd2dq.128(<2 x double>, <4 x i32>, i8)6151 6152define <4 x i32>@test_int_x86_avx512_mask_cvt_pd2dq_128(<2 x double> %x0, <4 x i32> %x1, i8 %x2) #0 {6153;6154; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_mask_cvt_pd2dq_128(6155; CHECK-SAME: <2 x double> [[X0:%.*]], <4 x i32> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {6156; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 86157; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 86158; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 86159; CHECK-NEXT: call void @llvm.donothing()6160; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP1]] to i1286161; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 06162; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP2]] to i1286163; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 06164; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6165; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 06166; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]6167; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]6168; CHECK: [[BB6]]:6169; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]6170; CHECK-NEXT: unreachable6171; CHECK: [[BB7]]:6172; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2dq.128(<2 x double> [[X0]], <4 x i32> [[X1]], i8 [[X2]])6173; CHECK-NEXT: [[TMP8:%.*]] = bitcast <2 x i64> [[TMP1]] to i1286174; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i128 [[TMP8]], 06175; CHECK-NEXT: [[TMP9:%.*]] = bitcast <4 x i32> [[TMP2]] to i1286176; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i128 [[TMP9]], 06177; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSCMP4]], [[_MSCMP5]]6178; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB10:.*]], label %[[BB11:.*]], !prof [[PROF1]]6179; CHECK: [[BB10]]:6180; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]6181; CHECK-NEXT: unreachable6182; CHECK: [[BB11]]:6183; CHECK-NEXT: [[RES1:%.*]] = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2dq.128(<2 x double> [[X0]], <4 x i32> [[X1]], i8 -1)6184; CHECK-NEXT: [[RES2:%.*]] = add <4 x i32> [[RES]], [[RES1]]6185; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 86186; CHECK-NEXT: ret <4 x i32> [[RES2]]6187;6188 %res = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2dq.128(<2 x double> %x0, <4 x i32> %x1, i8 %x2)6189 %res1 = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2dq.128(<2 x double> %x0, <4 x i32> %x1, i8 -1)6190 %res2 = add <4 x i32> %res, %res16191 ret <4 x i32> %res26192}6193 6194define <4 x i32>@test_int_x86_avx512_cvt_pd2dq_128_zext(<2 x double> %x0, <4 x i32> %x1) #0 {6195; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_cvt_pd2dq_128_zext(6196; CHECK-SAME: <2 x double> [[X0:%.*]], <4 x i32> [[X1:%.*]]) #[[ATTR0]] {6197; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 86198; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 86199; CHECK-NEXT: call void @llvm.donothing()6200; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP1]] to i1286201; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 06202; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i1286203; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 06204; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6205; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]6206; CHECK: [[BB5]]:6207; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]6208; CHECK-NEXT: unreachable6209; CHECK: [[BB6]]:6210; CHECK-NEXT: [[RES2:%.*]] = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2dq.128(<2 x double> [[X0]], <4 x i32> [[X1]], i8 -1)6211; CHECK-NEXT: [[RES3:%.*]] = shufflevector <4 x i32> [[RES2]], <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>6212; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 86213; CHECK-NEXT: ret <4 x i32> [[RES3]]6214;6215 %res2 = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2dq.128(<2 x double> %x0, <4 x i32> %x1, i8 -1)6216 %res3 = shufflevector <4 x i32> %res2, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>6217 ret <4 x i32> %res36218}6219 6220define <4 x i32>@test_int_x86_avx512_mask_cvt_pd2dq_128_zext(<2 x double> %x0, <4 x i32> %x1, i8 %x2) #0 {6221;6222; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_mask_cvt_pd2dq_128_zext(6223; CHECK-SAME: <2 x double> [[X0:%.*]], <4 x i32> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {6224; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 86225; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 86226; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 86227; CHECK-NEXT: call void @llvm.donothing()6228; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP1]] to i1286229; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 06230; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP2]] to i1286231; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 06232; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6233; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 06234; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]6235; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]6236; CHECK: [[BB6]]:6237; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]6238; CHECK-NEXT: unreachable6239; CHECK: [[BB7]]:6240; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2dq.128(<2 x double> [[X0]], <4 x i32> [[X1]], i8 [[X2]])6241; CHECK-NEXT: [[RES1:%.*]] = shufflevector <4 x i32> [[RES]], <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>6242; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 86243; CHECK-NEXT: ret <4 x i32> [[RES1]]6244;6245 %res = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2dq.128(<2 x double> %x0, <4 x i32> %x1, i8 %x2)6246 %res1 = shufflevector <4 x i32> %res, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>6247 ret <4 x i32> %res16248}6249 6250declare <4 x float> @llvm.x86.avx512.mask.cvtpd2ps(<2 x double>, <4 x float>, i8)6251 6252define <4 x float>@test_int_x86_avx512_cvt_pd2ps(<2 x double> %x0, <4 x float> %x1) #0 {6253; CHECK-LABEL: define <4 x float> @test_int_x86_avx512_cvt_pd2ps(6254; CHECK-SAME: <2 x double> [[X0:%.*]], <4 x float> [[X1:%.*]]) #[[ATTR0]] {6255; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 86256; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 86257; CHECK-NEXT: call void @llvm.donothing()6258; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP1]] to i1286259; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 06260; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i1286261; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 06262; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6263; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]6264; CHECK: [[BB5]]:6265; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]6266; CHECK-NEXT: unreachable6267; CHECK: [[BB6]]:6268; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.mask.cvtpd2ps(<2 x double> [[X0]], <4 x float> [[X1]], i8 -1)6269; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 86270; CHECK-NEXT: ret <4 x float> [[RES]]6271;6272 %res = call <4 x float> @llvm.x86.avx512.mask.cvtpd2ps(<2 x double> %x0, <4 x float> %x1, i8 -1)6273 ret <4 x float> %res6274}6275 6276define <4 x float>@test_int_x86_avx512_mask_cvt_pd2ps(<2 x double> %x0, <4 x float> %x1, i8 %x2) #0 {6277;6278; CHECK-LABEL: define <4 x float> @test_int_x86_avx512_mask_cvt_pd2ps(6279; CHECK-SAME: <2 x double> [[X0:%.*]], <4 x float> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {6280; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 86281; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 86282; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 86283; CHECK-NEXT: call void @llvm.donothing()6284; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP1]] to i1286285; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 06286; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP2]] to i1286287; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 06288; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6289; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 06290; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]6291; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]6292; CHECK: [[BB6]]:6293; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]6294; CHECK-NEXT: unreachable6295; CHECK: [[BB7]]:6296; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.mask.cvtpd2ps(<2 x double> [[X0]], <4 x float> [[X1]], i8 [[X2]])6297; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 86298; CHECK-NEXT: ret <4 x float> [[RES]]6299;6300 %res = call <4 x float> @llvm.x86.avx512.mask.cvtpd2ps(<2 x double> %x0, <4 x float> %x1, i8 %x2)6301 ret <4 x float> %res6302}6303 6304define <4 x float>@test_int_x86_avx512_cvt_pd2ps_zext(<2 x double> %x0, <4 x float> %x1) #0 {6305; CHECK-LABEL: define <4 x float> @test_int_x86_avx512_cvt_pd2ps_zext(6306; CHECK-SAME: <2 x double> [[X0:%.*]], <4 x float> [[X1:%.*]]) #[[ATTR0]] {6307; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 86308; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 86309; CHECK-NEXT: call void @llvm.donothing()6310; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP1]] to i1286311; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 06312; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i1286313; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 06314; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6315; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]6316; CHECK: [[BB5]]:6317; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]6318; CHECK-NEXT: unreachable6319; CHECK: [[BB6]]:6320; CHECK-NEXT: [[RES2:%.*]] = call <4 x float> @llvm.x86.avx512.mask.cvtpd2ps(<2 x double> [[X0]], <4 x float> [[X1]], i8 -1)6321; CHECK-NEXT: [[RES3:%.*]] = shufflevector <4 x float> [[RES2]], <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>6322; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 86323; CHECK-NEXT: ret <4 x float> [[RES3]]6324;6325 %res2 = call <4 x float> @llvm.x86.avx512.mask.cvtpd2ps(<2 x double> %x0, <4 x float> %x1, i8 -1)6326 %res3 = shufflevector <4 x float> %res2, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>6327 ret <4 x float> %res36328}6329 6330define <4 x float>@test_int_x86_avx512_mask_cvt_pd2ps_zext(<2 x double> %x0, <4 x float> %x1, i8 %x2) #0 {6331;6332; CHECK-LABEL: define <4 x float> @test_int_x86_avx512_mask_cvt_pd2ps_zext(6333; CHECK-SAME: <2 x double> [[X0:%.*]], <4 x float> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {6334; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 86335; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 86336; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 86337; CHECK-NEXT: call void @llvm.donothing()6338; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP1]] to i1286339; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 06340; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP2]] to i1286341; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 06342; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6343; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 06344; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]6345; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]6346; CHECK: [[BB6]]:6347; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]6348; CHECK-NEXT: unreachable6349; CHECK: [[BB7]]:6350; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.mask.cvtpd2ps(<2 x double> [[X0]], <4 x float> [[X1]], i8 [[X2]])6351; CHECK-NEXT: [[RES1:%.*]] = shufflevector <4 x float> [[RES]], <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>6352; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 86353; CHECK-NEXT: ret <4 x float> [[RES1]]6354;6355 %res = call <4 x float> @llvm.x86.avx512.mask.cvtpd2ps(<2 x double> %x0, <4 x float> %x1, i8 %x2)6356 %res1 = shufflevector <4 x float> %res, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>6357 ret <4 x float> %res16358}6359 6360declare <4 x i32> @llvm.x86.avx512.mask.cvtpd2udq.128(<2 x double>, <4 x i32>, i8)6361 6362define <4 x i32>@test_int_x86_avx512_cvt_pd2udq_128(<2 x double> %x0, <4 x i32> %x1) #0 {6363; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_cvt_pd2udq_128(6364; CHECK-SAME: <2 x double> [[X0:%.*]], <4 x i32> [[X1:%.*]]) #[[ATTR0]] {6365; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 86366; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 86367; CHECK-NEXT: call void @llvm.donothing()6368; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP1]] to i1286369; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 06370; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i1286371; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 06372; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6373; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]6374; CHECK: [[BB5]]:6375; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]6376; CHECK-NEXT: unreachable6377; CHECK: [[BB6]]:6378; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2udq.128(<2 x double> [[X0]], <4 x i32> [[X1]], i8 -1)6379; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 86380; CHECK-NEXT: ret <4 x i32> [[RES]]6381;6382 %res = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2udq.128(<2 x double> %x0, <4 x i32> %x1, i8 -1)6383 ret <4 x i32> %res6384}6385 6386define <4 x i32>@test_int_x86_avx512_mask_cvt_pd2udq_128(<2 x double> %x0, <4 x i32> %x1, i8 %x2) #0 {6387;6388; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_mask_cvt_pd2udq_128(6389; CHECK-SAME: <2 x double> [[X0:%.*]], <4 x i32> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {6390; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 86391; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 86392; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 86393; CHECK-NEXT: call void @llvm.donothing()6394; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP1]] to i1286395; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 06396; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP2]] to i1286397; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 06398; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6399; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 06400; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]6401; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]6402; CHECK: [[BB6]]:6403; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]6404; CHECK-NEXT: unreachable6405; CHECK: [[BB7]]:6406; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2udq.128(<2 x double> [[X0]], <4 x i32> [[X1]], i8 [[X2]])6407; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 86408; CHECK-NEXT: ret <4 x i32> [[RES]]6409;6410 %res = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2udq.128(<2 x double> %x0, <4 x i32> %x1, i8 %x2)6411 ret <4 x i32> %res6412}6413 6414define <4 x i32>@test_int_x86_avx512_cvt_pd2udq_128_zext(<2 x double> %x0, <4 x i32> %x1) #0 {6415; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_cvt_pd2udq_128_zext(6416; CHECK-SAME: <2 x double> [[X0:%.*]], <4 x i32> [[X1:%.*]]) #[[ATTR0]] {6417; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 86418; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 86419; CHECK-NEXT: call void @llvm.donothing()6420; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP1]] to i1286421; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 06422; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i1286423; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 06424; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6425; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]6426; CHECK: [[BB5]]:6427; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]6428; CHECK-NEXT: unreachable6429; CHECK: [[BB6]]:6430; CHECK-NEXT: [[RES2:%.*]] = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2udq.128(<2 x double> [[X0]], <4 x i32> [[X1]], i8 -1)6431; CHECK-NEXT: [[RES3:%.*]] = shufflevector <4 x i32> [[RES2]], <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>6432; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 86433; CHECK-NEXT: ret <4 x i32> [[RES3]]6434;6435 %res2 = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2udq.128(<2 x double> %x0, <4 x i32> %x1, i8 -1)6436 %res3 = shufflevector <4 x i32> %res2, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>6437 ret <4 x i32> %res36438}6439 6440define <4 x i32>@test_int_x86_avx512_mask_cvt_pd2udq_128_zext(<2 x double> %x0, <4 x i32> %x1, i8 %x2) #0 {6441;6442; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_mask_cvt_pd2udq_128_zext(6443; CHECK-SAME: <2 x double> [[X0:%.*]], <4 x i32> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {6444; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 86445; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 86446; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 86447; CHECK-NEXT: call void @llvm.donothing()6448; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP1]] to i1286449; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 06450; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP2]] to i1286451; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 06452; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6453; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 06454; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]6455; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]6456; CHECK: [[BB6]]:6457; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]6458; CHECK-NEXT: unreachable6459; CHECK: [[BB7]]:6460; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2udq.128(<2 x double> [[X0]], <4 x i32> [[X1]], i8 [[X2]])6461; CHECK-NEXT: [[RES1:%.*]] = shufflevector <4 x i32> [[RES]], <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>6462; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 86463; CHECK-NEXT: ret <4 x i32> [[RES1]]6464;6465 %res = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2udq.128(<2 x double> %x0, <4 x i32> %x1, i8 %x2)6466 %res1 = shufflevector <4 x i32> %res, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>6467 ret <4 x i32> %res16468}6469 6470declare <4 x i32> @llvm.x86.avx512.mask.cvtpd2udq.256(<4 x double>, <4 x i32>, i8)6471 6472define <4 x i32>@test_int_x86_avx512_cvt_pd2udq_256(<4 x double> %x0, <4 x i32> %x1) #0 {6473; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_cvt_pd2udq_256(6474; CHECK-SAME: <4 x double> [[X0:%.*]], <4 x i32> [[X1:%.*]]) #[[ATTR0]] {6475; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 86476; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 86477; CHECK-NEXT: call void @llvm.donothing()6478; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i64> [[TMP1]] to i2566479; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP3]], 06480; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i1286481; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 06482; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6483; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]6484; CHECK: [[BB5]]:6485; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]6486; CHECK-NEXT: unreachable6487; CHECK: [[BB6]]:6488; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2udq.256(<4 x double> [[X0]], <4 x i32> [[X1]], i8 -1)6489; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 86490; CHECK-NEXT: ret <4 x i32> [[RES]]6491;6492 %res = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2udq.256(<4 x double> %x0, <4 x i32> %x1, i8 -1)6493 ret <4 x i32> %res6494}6495 6496define <4 x i32>@test_int_x86_avx512_mask_cvt_pd2udq_256(<4 x double> %x0, <4 x i32> %x1, i8 %x2) #0 {6497;6498; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_mask_cvt_pd2udq_256(6499; CHECK-SAME: <4 x double> [[X0:%.*]], <4 x i32> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {6500; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 86501; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 86502; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 86503; CHECK-NEXT: call void @llvm.donothing()6504; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i64> [[TMP1]] to i2566505; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP4]], 06506; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP2]] to i1286507; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 06508; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6509; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 06510; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]6511; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]6512; CHECK: [[BB6]]:6513; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]6514; CHECK-NEXT: unreachable6515; CHECK: [[BB7]]:6516; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2udq.256(<4 x double> [[X0]], <4 x i32> [[X1]], i8 [[X2]])6517; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 86518; CHECK-NEXT: ret <4 x i32> [[RES]]6519;6520 %res = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2udq.256(<4 x double> %x0, <4 x i32> %x1, i8 %x2)6521 ret <4 x i32> %res6522}6523 6524declare <4 x i32> @llvm.x86.avx512.mask.cvtps2dq.128(<4 x float>, <4 x i32>, i8)6525 6526define <4 x i32>@test_int_x86_avx512_cvt_ps2dq_128(<4 x float> %x0, <4 x i32> %x1) #0 {6527; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_cvt_ps2dq_128(6528; CHECK-SAME: <4 x float> [[X0:%.*]], <4 x i32> [[X1:%.*]]) #[[ATTR0]] {6529; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 86530; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 86531; CHECK-NEXT: call void @llvm.donothing()6532; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP1]] to i1286533; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 06534; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i1286535; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 06536; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6537; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]6538; CHECK: [[BB5]]:6539; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]6540; CHECK-NEXT: unreachable6541; CHECK: [[BB6]]:6542; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx512.mask.cvtps2dq.128(<4 x float> [[X0]], <4 x i32> [[X1]], i8 -1)6543; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 86544; CHECK-NEXT: ret <4 x i32> [[RES]]6545;6546 %res = call <4 x i32> @llvm.x86.avx512.mask.cvtps2dq.128(<4 x float> %x0, <4 x i32> %x1, i8 -1)6547 ret <4 x i32> %res6548}6549 6550define <4 x i32>@test_int_x86_avx512_mask_cvt_ps2dq_128(<4 x float> %x0, <4 x i32> %x1, i8 %x2) #0 {6551;6552; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_mask_cvt_ps2dq_128(6553; CHECK-SAME: <4 x float> [[X0:%.*]], <4 x i32> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {6554; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 86555; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 86556; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 86557; CHECK-NEXT: call void @llvm.donothing()6558; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP1]] to i1286559; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 06560; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP2]] to i1286561; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 06562; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6563; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 06564; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]6565; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]6566; CHECK: [[BB6]]:6567; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]6568; CHECK-NEXT: unreachable6569; CHECK: [[BB7]]:6570; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx512.mask.cvtps2dq.128(<4 x float> [[X0]], <4 x i32> [[X1]], i8 [[X2]])6571; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 86572; CHECK-NEXT: ret <4 x i32> [[RES]]6573;6574 %res = call <4 x i32> @llvm.x86.avx512.mask.cvtps2dq.128(<4 x float> %x0, <4 x i32> %x1, i8 %x2)6575 ret <4 x i32> %res6576}6577 6578declare <8 x i32> @llvm.x86.avx512.mask.cvtps2dq.256(<8 x float>, <8 x i32>, i8)6579 6580define <8 x i32>@test_int_x86_avx512_cvt_ps2dq_256(<8 x float> %x0, <8 x i32> %x1) #0 {6581; CHECK-LABEL: define <8 x i32> @test_int_x86_avx512_cvt_ps2dq_256(6582; CHECK-SAME: <8 x float> [[X0:%.*]], <8 x i32> [[X1:%.*]]) #[[ATTR0]] {6583; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 86584; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 86585; CHECK-NEXT: call void @llvm.donothing()6586; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i32> [[TMP1]] to i2566587; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP3]], 06588; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i32> [[TMP2]] to i2566589; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP4]], 06590; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6591; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]6592; CHECK: [[BB5]]:6593; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]6594; CHECK-NEXT: unreachable6595; CHECK: [[BB6]]:6596; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx512.mask.cvtps2dq.256(<8 x float> [[X0]], <8 x i32> [[X1]], i8 -1)6597; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 86598; CHECK-NEXT: ret <8 x i32> [[RES]]6599;6600 %res = call <8 x i32> @llvm.x86.avx512.mask.cvtps2dq.256(<8 x float> %x0, <8 x i32> %x1, i8 -1)6601 ret <8 x i32> %res6602}6603 6604define <8 x i32>@test_int_x86_avx512_mask_cvt_ps2dq_256(<8 x float> %x0, <8 x i32> %x1, i8 %x2) #0 {6605;6606; CHECK-LABEL: define <8 x i32> @test_int_x86_avx512_mask_cvt_ps2dq_256(6607; CHECK-SAME: <8 x float> [[X0:%.*]], <8 x i32> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {6608; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 86609; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 86610; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 86611; CHECK-NEXT: call void @llvm.donothing()6612; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i32> [[TMP1]] to i2566613; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP4]], 06614; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i32> [[TMP2]] to i2566615; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP5]], 06616; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6617; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 06618; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]6619; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]6620; CHECK: [[BB6]]:6621; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]6622; CHECK-NEXT: unreachable6623; CHECK: [[BB7]]:6624; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx512.mask.cvtps2dq.256(<8 x float> [[X0]], <8 x i32> [[X1]], i8 [[X2]])6625; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 86626; CHECK-NEXT: ret <8 x i32> [[RES]]6627;6628 %res = call <8 x i32> @llvm.x86.avx512.mask.cvtps2dq.256(<8 x float> %x0, <8 x i32> %x1, i8 %x2)6629 ret <8 x i32> %res6630}6631 6632declare <4 x i32> @llvm.x86.avx512.mask.cvtps2udq.128(<4 x float>, <4 x i32>, i8)6633 6634define <4 x i32>@test_int_x86_avx512_cvt_ps2udq_128(<4 x float> %x0, <4 x i32> %x1) #0 {6635; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_cvt_ps2udq_128(6636; CHECK-SAME: <4 x float> [[X0:%.*]], <4 x i32> [[X1:%.*]]) #[[ATTR0]] {6637; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 86638; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 86639; CHECK-NEXT: call void @llvm.donothing()6640; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP1]] to i1286641; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 06642; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i1286643; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 06644; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6645; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]6646; CHECK: [[BB5]]:6647; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]6648; CHECK-NEXT: unreachable6649; CHECK: [[BB6]]:6650; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx512.mask.cvtps2udq.128(<4 x float> [[X0]], <4 x i32> [[X1]], i8 -1)6651; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 86652; CHECK-NEXT: ret <4 x i32> [[RES]]6653;6654 %res = call <4 x i32> @llvm.x86.avx512.mask.cvtps2udq.128(<4 x float> %x0, <4 x i32> %x1, i8 -1)6655 ret <4 x i32> %res6656}6657 6658define <4 x i32>@test_int_x86_avx512_mask_cvt_ps2udq_128(<4 x float> %x0, <4 x i32> %x1, i8 %x2) #0 {6659;6660; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_mask_cvt_ps2udq_128(6661; CHECK-SAME: <4 x float> [[X0:%.*]], <4 x i32> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {6662; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 86663; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 86664; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 86665; CHECK-NEXT: call void @llvm.donothing()6666; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP1]] to i1286667; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 06668; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP2]] to i1286669; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 06670; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6671; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 06672; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]6673; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]6674; CHECK: [[BB6]]:6675; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]6676; CHECK-NEXT: unreachable6677; CHECK: [[BB7]]:6678; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx512.mask.cvtps2udq.128(<4 x float> [[X0]], <4 x i32> [[X1]], i8 [[X2]])6679; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 86680; CHECK-NEXT: ret <4 x i32> [[RES]]6681;6682 %res = call <4 x i32> @llvm.x86.avx512.mask.cvtps2udq.128(<4 x float> %x0, <4 x i32> %x1, i8 %x2)6683 ret <4 x i32> %res6684}6685 6686declare <8 x i32> @llvm.x86.avx512.mask.cvtps2udq.256(<8 x float>, <8 x i32>, i8)6687 6688define <8 x i32>@test_int_x86_avx512_cvt_ps2udq_256(<8 x float> %x0, <8 x i32> %x1) #0 {6689; CHECK-LABEL: define <8 x i32> @test_int_x86_avx512_cvt_ps2udq_256(6690; CHECK-SAME: <8 x float> [[X0:%.*]], <8 x i32> [[X1:%.*]]) #[[ATTR0]] {6691; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 86692; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 86693; CHECK-NEXT: call void @llvm.donothing()6694; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i32> [[TMP1]] to i2566695; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP3]], 06696; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i32> [[TMP2]] to i2566697; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP4]], 06698; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6699; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]6700; CHECK: [[BB5]]:6701; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]6702; CHECK-NEXT: unreachable6703; CHECK: [[BB6]]:6704; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx512.mask.cvtps2udq.256(<8 x float> [[X0]], <8 x i32> [[X1]], i8 -1)6705; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 86706; CHECK-NEXT: ret <8 x i32> [[RES]]6707;6708 %res = call <8 x i32> @llvm.x86.avx512.mask.cvtps2udq.256(<8 x float> %x0, <8 x i32> %x1, i8 -1)6709 ret <8 x i32> %res6710}6711 6712define <8 x i32>@test_int_x86_avx512_mask_cvt_ps2udq_256(<8 x float> %x0, <8 x i32> %x1, i8 %x2) #0 {6713;6714; CHECK-LABEL: define <8 x i32> @test_int_x86_avx512_mask_cvt_ps2udq_256(6715; CHECK-SAME: <8 x float> [[X0:%.*]], <8 x i32> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {6716; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 86717; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 86718; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 86719; CHECK-NEXT: call void @llvm.donothing()6720; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i32> [[TMP1]] to i2566721; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP4]], 06722; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i32> [[TMP2]] to i2566723; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP5]], 06724; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6725; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 06726; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]6727; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]6728; CHECK: [[BB6]]:6729; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]6730; CHECK-NEXT: unreachable6731; CHECK: [[BB7]]:6732; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx512.mask.cvtps2udq.256(<8 x float> [[X0]], <8 x i32> [[X1]], i8 [[X2]])6733; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 86734; CHECK-NEXT: ret <8 x i32> [[RES]]6735;6736 %res = call <8 x i32> @llvm.x86.avx512.mask.cvtps2udq.256(<8 x float> %x0, <8 x i32> %x1, i8 %x2)6737 ret <8 x i32> %res6738}6739 6740declare <4 x i32> @llvm.x86.avx512.mask.cvttpd2dq.128(<2 x double>, <4 x i32>, i8)6741 6742define <4 x i32>@test_int_x86_avx512_ask_cvtt_pd2dq_128(<2 x double> %x0, <4 x i32> %x1) #0 {6743; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_ask_cvtt_pd2dq_128(6744; CHECK-SAME: <2 x double> [[X0:%.*]], <4 x i32> [[X1:%.*]]) #[[ATTR0]] {6745; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 86746; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 86747; CHECK-NEXT: call void @llvm.donothing()6748; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP1]] to i1286749; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 06750; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i1286751; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 06752; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6753; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]6754; CHECK: [[BB5]]:6755; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]6756; CHECK-NEXT: unreachable6757; CHECK: [[BB6]]:6758; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2dq.128(<2 x double> [[X0]], <4 x i32> [[X1]], i8 -1)6759; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 86760; CHECK-NEXT: ret <4 x i32> [[RES]]6761;6762 %res = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2dq.128(<2 x double> %x0, <4 x i32> %x1, i8 -1)6763 ret <4 x i32> %res6764}6765 6766define <4 x i32>@test_int_x86_avx512_mask_cvtt_pd2dq_128(<2 x double> %x0, <4 x i32> %x1, i8 %x2) #0 {6767;6768; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_mask_cvtt_pd2dq_128(6769; CHECK-SAME: <2 x double> [[X0:%.*]], <4 x i32> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {6770; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 86771; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 86772; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 86773; CHECK-NEXT: call void @llvm.donothing()6774; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP1]] to i1286775; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 06776; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP2]] to i1286777; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 06778; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6779; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 06780; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]6781; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]6782; CHECK: [[BB6]]:6783; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]6784; CHECK-NEXT: unreachable6785; CHECK: [[BB7]]:6786; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2dq.128(<2 x double> [[X0]], <4 x i32> [[X1]], i8 [[X2]])6787; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 86788; CHECK-NEXT: ret <4 x i32> [[RES]]6789;6790 %res = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2dq.128(<2 x double> %x0, <4 x i32> %x1, i8 %x2)6791 ret <4 x i32> %res6792}6793 6794define <4 x i32>@test_int_x86_avx512_cvtt_pd2dq_128_zext(<2 x double> %x0, <4 x i32> %x1) #0 {6795; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_cvtt_pd2dq_128_zext(6796; CHECK-SAME: <2 x double> [[X0:%.*]], <4 x i32> [[X1:%.*]]) #[[ATTR0]] {6797; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 86798; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 86799; CHECK-NEXT: call void @llvm.donothing()6800; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP1]] to i1286801; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 06802; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i1286803; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 06804; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6805; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]6806; CHECK: [[BB5]]:6807; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]6808; CHECK-NEXT: unreachable6809; CHECK: [[BB6]]:6810; CHECK-NEXT: [[RES2:%.*]] = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2dq.128(<2 x double> [[X0]], <4 x i32> [[X1]], i8 -1)6811; CHECK-NEXT: [[RES3:%.*]] = shufflevector <4 x i32> [[RES2]], <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>6812; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 86813; CHECK-NEXT: ret <4 x i32> [[RES3]]6814;6815 %res2 = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2dq.128(<2 x double> %x0, <4 x i32> %x1, i8 -1)6816 %res3 = shufflevector <4 x i32> %res2, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>6817 ret <4 x i32> %res36818}6819 6820define <4 x i32>@test_int_x86_avx512_mask_cvtt_pd2dq_128_zext(<2 x double> %x0, <4 x i32> %x1, i8 %x2) #0 {6821;6822; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_mask_cvtt_pd2dq_128_zext(6823; CHECK-SAME: <2 x double> [[X0:%.*]], <4 x i32> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {6824; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 86825; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 86826; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 86827; CHECK-NEXT: call void @llvm.donothing()6828; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP1]] to i1286829; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 06830; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP2]] to i1286831; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 06832; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6833; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 06834; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]6835; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]6836; CHECK: [[BB6]]:6837; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]6838; CHECK-NEXT: unreachable6839; CHECK: [[BB7]]:6840; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2dq.128(<2 x double> [[X0]], <4 x i32> [[X1]], i8 [[X2]])6841; CHECK-NEXT: [[RES1:%.*]] = shufflevector <4 x i32> [[RES]], <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>6842; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 86843; CHECK-NEXT: ret <4 x i32> [[RES1]]6844;6845 %res = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2dq.128(<2 x double> %x0, <4 x i32> %x1, i8 %x2)6846 %res1 = shufflevector <4 x i32> %res, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>6847 ret <4 x i32> %res16848}6849 6850declare <4 x i32> @llvm.x86.avx512.mask.cvttpd2udq.128(<2 x double>, <4 x i32>, i8)6851 6852define <4 x i32>@test_int_x86_avx512_cvtt_pd2udq_128(<2 x double> %x0, <4 x i32> %x1) #0 {6853; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_cvtt_pd2udq_128(6854; CHECK-SAME: <2 x double> [[X0:%.*]], <4 x i32> [[X1:%.*]]) #[[ATTR0]] {6855; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 86856; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 86857; CHECK-NEXT: call void @llvm.donothing()6858; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP1]] to i1286859; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 06860; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i1286861; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 06862; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6863; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]6864; CHECK: [[BB5]]:6865; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]6866; CHECK-NEXT: unreachable6867; CHECK: [[BB6]]:6868; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2udq.128(<2 x double> [[X0]], <4 x i32> [[X1]], i8 -1)6869; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 86870; CHECK-NEXT: ret <4 x i32> [[RES]]6871;6872 %res = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2udq.128(<2 x double> %x0, <4 x i32> %x1, i8 -1)6873 ret <4 x i32> %res6874}6875 6876define <4 x i32>@test_int_x86_avx512_mask_cvtt_pd2udq_128(<2 x double> %x0, <4 x i32> %x1, i8 %x2) #0 {6877;6878; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_mask_cvtt_pd2udq_128(6879; CHECK-SAME: <2 x double> [[X0:%.*]], <4 x i32> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {6880; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 86881; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 86882; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 86883; CHECK-NEXT: call void @llvm.donothing()6884; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP1]] to i1286885; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 06886; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP2]] to i1286887; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 06888; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6889; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 06890; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]6891; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]6892; CHECK: [[BB6]]:6893; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]6894; CHECK-NEXT: unreachable6895; CHECK: [[BB7]]:6896; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2udq.128(<2 x double> [[X0]], <4 x i32> [[X1]], i8 [[X2]])6897; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 86898; CHECK-NEXT: ret <4 x i32> [[RES]]6899;6900 %res = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2udq.128(<2 x double> %x0, <4 x i32> %x1, i8 %x2)6901 ret <4 x i32> %res6902}6903 6904define <4 x i32>@test_int_x86_avx512_cvtt_pd2udq_128_zext(<2 x double> %x0, <4 x i32> %x1) #0 {6905; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_cvtt_pd2udq_128_zext(6906; CHECK-SAME: <2 x double> [[X0:%.*]], <4 x i32> [[X1:%.*]]) #[[ATTR0]] {6907; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 86908; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 86909; CHECK-NEXT: call void @llvm.donothing()6910; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP1]] to i1286911; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 06912; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i1286913; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 06914; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6915; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]6916; CHECK: [[BB5]]:6917; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]6918; CHECK-NEXT: unreachable6919; CHECK: [[BB6]]:6920; CHECK-NEXT: [[RES2:%.*]] = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2udq.128(<2 x double> [[X0]], <4 x i32> [[X1]], i8 -1)6921; CHECK-NEXT: [[RES3:%.*]] = shufflevector <4 x i32> [[RES2]], <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>6922; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 86923; CHECK-NEXT: ret <4 x i32> [[RES3]]6924;6925 %res2 = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2udq.128(<2 x double> %x0, <4 x i32> %x1, i8 -1)6926 %res3 = shufflevector <4 x i32> %res2, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>6927 ret <4 x i32> %res36928}6929 6930define <4 x i32>@test_int_x86_avx512_mask_cvtt_pd2udq_128_zext(<2 x double> %x0, <4 x i32> %x1, i8 %x2) #0 {6931;6932; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_mask_cvtt_pd2udq_128_zext(6933; CHECK-SAME: <2 x double> [[X0:%.*]], <4 x i32> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {6934; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 86935; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 86936; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 86937; CHECK-NEXT: call void @llvm.donothing()6938; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP1]] to i1286939; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 06940; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP2]] to i1286941; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 06942; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6943; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 06944; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]6945; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]6946; CHECK: [[BB6]]:6947; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]6948; CHECK-NEXT: unreachable6949; CHECK: [[BB7]]:6950; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2udq.128(<2 x double> [[X0]], <4 x i32> [[X1]], i8 [[X2]])6951; CHECK-NEXT: [[RES1:%.*]] = shufflevector <4 x i32> [[RES]], <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>6952; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 86953; CHECK-NEXT: ret <4 x i32> [[RES1]]6954;6955 %res = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2udq.128(<2 x double> %x0, <4 x i32> %x1, i8 %x2)6956 %res1 = shufflevector <4 x i32> %res, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>6957 ret <4 x i32> %res16958}6959 6960declare <4 x i32> @llvm.x86.avx512.mask.cvttpd2udq.256(<4 x double>, <4 x i32>, i8)6961 6962define <4 x i32>@test_int_x86_avx512_cvtt_pd2udq_256(<4 x double> %x0, <4 x i32> %x1) #0 {6963; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_cvtt_pd2udq_256(6964; CHECK-SAME: <4 x double> [[X0:%.*]], <4 x i32> [[X1:%.*]]) #[[ATTR0]] {6965; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 86966; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 86967; CHECK-NEXT: call void @llvm.donothing()6968; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i64> [[TMP1]] to i2566969; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP3]], 06970; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i1286971; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 06972; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6973; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]6974; CHECK: [[BB5]]:6975; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]6976; CHECK-NEXT: unreachable6977; CHECK: [[BB6]]:6978; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2udq.256(<4 x double> [[X0]], <4 x i32> [[X1]], i8 -1)6979; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 86980; CHECK-NEXT: ret <4 x i32> [[RES]]6981;6982 %res = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2udq.256(<4 x double> %x0, <4 x i32> %x1, i8 -1)6983 ret <4 x i32> %res6984}6985 6986define <4 x i32>@test_int_x86_avx512_mask_cvtt_pd2udq_256(<4 x double> %x0, <4 x i32> %x1, i8 %x2) #0 {6987;6988; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_mask_cvtt_pd2udq_256(6989; CHECK-SAME: <4 x double> [[X0:%.*]], <4 x i32> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {6990; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 86991; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 86992; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 86993; CHECK-NEXT: call void @llvm.donothing()6994; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i64> [[TMP1]] to i2566995; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP4]], 06996; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP2]] to i1286997; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 06998; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6999; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 07000; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]7001; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]7002; CHECK: [[BB6]]:7003; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]7004; CHECK-NEXT: unreachable7005; CHECK: [[BB7]]:7006; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2udq.256(<4 x double> [[X0]], <4 x i32> [[X1]], i8 [[X2]])7007; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 87008; CHECK-NEXT: ret <4 x i32> [[RES]]7009;7010 %res = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2udq.256(<4 x double> %x0, <4 x i32> %x1, i8 %x2)7011 ret <4 x i32> %res7012}7013 7014declare <4 x i32> @llvm.x86.avx512.mask.cvttps2udq.128(<4 x float>, <4 x i32>, i8)7015 7016define <4 x i32>@test_int_x86_avx512_cvtt_ps2udq_128(<4 x float> %x0, <4 x i32> %x1) #0 {7017; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_cvtt_ps2udq_128(7018; CHECK-SAME: <4 x float> [[X0:%.*]], <4 x i32> [[X1:%.*]]) #[[ATTR0]] {7019; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 87020; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 87021; CHECK-NEXT: call void @llvm.donothing()7022; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP1]] to i1287023; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 07024; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i1287025; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 07026; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]7027; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]7028; CHECK: [[BB5]]:7029; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]7030; CHECK-NEXT: unreachable7031; CHECK: [[BB6]]:7032; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx512.mask.cvttps2udq.128(<4 x float> [[X0]], <4 x i32> [[X1]], i8 -1)7033; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 87034; CHECK-NEXT: ret <4 x i32> [[RES]]7035;7036 %res = call <4 x i32> @llvm.x86.avx512.mask.cvttps2udq.128(<4 x float> %x0, <4 x i32> %x1, i8 -1)7037 ret <4 x i32> %res7038}7039 7040define <4 x i32>@test_int_x86_avx512_mask_cvtt_ps2udq_128(<4 x float> %x0, <4 x i32> %x1, i8 %x2) #0 {7041;7042; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_mask_cvtt_ps2udq_128(7043; CHECK-SAME: <4 x float> [[X0:%.*]], <4 x i32> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {7044; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 87045; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 87046; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 87047; CHECK-NEXT: call void @llvm.donothing()7048; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP1]] to i1287049; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 07050; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP2]] to i1287051; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 07052; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]7053; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 07054; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]7055; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]7056; CHECK: [[BB6]]:7057; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]7058; CHECK-NEXT: unreachable7059; CHECK: [[BB7]]:7060; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx512.mask.cvttps2udq.128(<4 x float> [[X0]], <4 x i32> [[X1]], i8 [[X2]])7061; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 87062; CHECK-NEXT: ret <4 x i32> [[RES]]7063;7064 %res = call <4 x i32> @llvm.x86.avx512.mask.cvttps2udq.128(<4 x float> %x0, <4 x i32> %x1, i8 %x2)7065 ret <4 x i32> %res7066}7067 7068declare <8 x i32> @llvm.x86.avx512.mask.cvttps2udq.256(<8 x float>, <8 x i32>, i8)7069 7070define <8 x i32>@test_int_x86_avx512_cvtt_ps2udq_256(<8 x float> %x0, <8 x i32> %x1) #0 {7071; CHECK-LABEL: define <8 x i32> @test_int_x86_avx512_cvtt_ps2udq_256(7072; CHECK-SAME: <8 x float> [[X0:%.*]], <8 x i32> [[X1:%.*]]) #[[ATTR0]] {7073; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 87074; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 87075; CHECK-NEXT: call void @llvm.donothing()7076; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i32> [[TMP1]] to i2567077; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP3]], 07078; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i32> [[TMP2]] to i2567079; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP4]], 07080; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]7081; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]7082; CHECK: [[BB5]]:7083; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]7084; CHECK-NEXT: unreachable7085; CHECK: [[BB6]]:7086; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx512.mask.cvttps2udq.256(<8 x float> [[X0]], <8 x i32> [[X1]], i8 -1)7087; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 87088; CHECK-NEXT: ret <8 x i32> [[RES]]7089;7090 %res = call <8 x i32> @llvm.x86.avx512.mask.cvttps2udq.256(<8 x float> %x0, <8 x i32> %x1, i8 -1)7091 ret <8 x i32> %res7092}7093 7094define <8 x i32>@test_int_x86_avx512_mask_cvtt_ps2udq_256(<8 x float> %x0, <8 x i32> %x1, i8 %x2) #0 {7095;7096; CHECK-LABEL: define <8 x i32> @test_int_x86_avx512_mask_cvtt_ps2udq_256(7097; CHECK-SAME: <8 x float> [[X0:%.*]], <8 x i32> [[X1:%.*]], i8 [[X2:%.*]]) #[[ATTR0]] {7098; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 87099; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 87100; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 87101; CHECK-NEXT: call void @llvm.donothing()7102; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i32> [[TMP1]] to i2567103; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP4]], 07104; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i32> [[TMP2]] to i2567105; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP5]], 07106; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]7107; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 07108; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]7109; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]7110; CHECK: [[BB6]]:7111; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]7112; CHECK-NEXT: unreachable7113; CHECK: [[BB7]]:7114; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx512.mask.cvttps2udq.256(<8 x float> [[X0]], <8 x i32> [[X1]], i8 [[X2]])7115; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 87116; CHECK-NEXT: ret <8 x i32> [[RES]]7117;7118 %res = call <8 x i32> @llvm.x86.avx512.mask.cvttps2udq.256(<8 x float> %x0, <8 x i32> %x1, i8 %x2)7119 ret <8 x i32> %res7120}7121 7122declare <2 x double> @llvm.x86.avx512.mask.rndscale.pd.128(<2 x double>, i32, <2 x double>, i8)7123 7124define <2 x double>@test_int_x86_avx512_mask_rndscale_pd_128(<2 x double> %x0, <2 x double> %x2, i8 %x3) #0 {7125;7126; CHECK-LABEL: define <2 x double> @test_int_x86_avx512_mask_rndscale_pd_128(7127; CHECK-SAME: <2 x double> [[X0:%.*]], <2 x double> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {7128; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 87129; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 87130; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 87131; CHECK-NEXT: call void @llvm.donothing()7132; CHECK-NEXT: [[TMP4:%.*]] = trunc i8 [[X3]] to i27133; CHECK-NEXT: [[TMP5:%.*]] = bitcast i2 [[TMP4]] to <2 x i1>7134; CHECK-NEXT: [[TMP6:%.*]] = icmp ne <2 x i64> [[TMP1]], zeroinitializer7135; CHECK-NEXT: [[TMP7:%.*]] = sext <2 x i1> [[TMP6]] to <2 x i64>7136; CHECK-NEXT: [[TMP8:%.*]] = select <2 x i1> [[TMP5]], <2 x i64> [[TMP7]], <2 x i64> [[TMP2]]7137; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 07138; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]7139; CHECK: [[BB9]]:7140; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]7141; CHECK-NEXT: unreachable7142; CHECK: [[BB10]]:7143; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx512.mask.rndscale.pd.128(<2 x double> [[X0]], i32 4, <2 x double> [[X2]], i8 [[X3]])7144; CHECK-NEXT: [[TMP11:%.*]] = icmp ne <2 x i64> [[TMP1]], zeroinitializer7145; CHECK-NEXT: [[TMP12:%.*]] = sext <2 x i1> [[TMP11]] to <2 x i64>7146; CHECK-NEXT: [[TMP13:%.*]] = select <2 x i1> splat (i1 true), <2 x i64> [[TMP12]], <2 x i64> [[TMP2]]7147; CHECK-NEXT: [[RES1:%.*]] = call <2 x double> @llvm.x86.avx512.mask.rndscale.pd.128(<2 x double> [[X0]], i32 88, <2 x double> [[X2]], i8 -1)7148; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP8]], [[TMP13]]7149; CHECK-NEXT: [[RES2:%.*]] = fadd <2 x double> [[RES]], [[RES1]]7150; CHECK-NEXT: store <2 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 87151; CHECK-NEXT: ret <2 x double> [[RES2]]7152;7153 %res = call <2 x double> @llvm.x86.avx512.mask.rndscale.pd.128(<2 x double> %x0, i32 4, <2 x double> %x2, i8 %x3)7154 %res1 = call <2 x double> @llvm.x86.avx512.mask.rndscale.pd.128(<2 x double> %x0, i32 88, <2 x double> %x2, i8 -1)7155 %res2 = fadd <2 x double> %res, %res17156 ret <2 x double> %res27157}7158 7159declare <4 x double> @llvm.x86.avx512.mask.rndscale.pd.256(<4 x double>, i32, <4 x double>, i8)7160 7161define <4 x double>@test_int_x86_avx512_mask_rndscale_pd_256(<4 x double> %x0, <4 x double> %x2, i8 %x3) #0 {7162;7163; CHECK-LABEL: define <4 x double> @test_int_x86_avx512_mask_rndscale_pd_256(7164; CHECK-SAME: <4 x double> [[X0:%.*]], <4 x double> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {7165; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 87166; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 87167; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 87168; CHECK-NEXT: call void @llvm.donothing()7169; CHECK-NEXT: [[TMP4:%.*]] = trunc i8 [[X3]] to i47170; CHECK-NEXT: [[TMP5:%.*]] = bitcast i4 [[TMP4]] to <4 x i1>7171; CHECK-NEXT: [[TMP6:%.*]] = icmp ne <4 x i64> [[TMP1]], zeroinitializer7172; CHECK-NEXT: [[TMP7:%.*]] = sext <4 x i1> [[TMP6]] to <4 x i64>7173; CHECK-NEXT: [[TMP8:%.*]] = select <4 x i1> [[TMP5]], <4 x i64> [[TMP7]], <4 x i64> [[TMP2]]7174; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 07175; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]7176; CHECK: [[BB9]]:7177; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]7178; CHECK-NEXT: unreachable7179; CHECK: [[BB10]]:7180; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.x86.avx512.mask.rndscale.pd.256(<4 x double> [[X0]], i32 4, <4 x double> [[X2]], i8 [[X3]])7181; CHECK-NEXT: [[TMP11:%.*]] = icmp ne <4 x i64> [[TMP1]], zeroinitializer7182; CHECK-NEXT: [[TMP12:%.*]] = sext <4 x i1> [[TMP11]] to <4 x i64>7183; CHECK-NEXT: [[TMP13:%.*]] = select <4 x i1> splat (i1 true), <4 x i64> [[TMP12]], <4 x i64> [[TMP2]]7184; CHECK-NEXT: [[RES1:%.*]] = call <4 x double> @llvm.x86.avx512.mask.rndscale.pd.256(<4 x double> [[X0]], i32 88, <4 x double> [[X2]], i8 -1)7185; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i64> [[TMP8]], [[TMP13]]7186; CHECK-NEXT: [[RES2:%.*]] = fadd <4 x double> [[RES]], [[RES1]]7187; CHECK-NEXT: store <4 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 87188; CHECK-NEXT: ret <4 x double> [[RES2]]7189;7190 %res = call <4 x double> @llvm.x86.avx512.mask.rndscale.pd.256(<4 x double> %x0, i32 4, <4 x double> %x2, i8 %x3)7191 %res1 = call <4 x double> @llvm.x86.avx512.mask.rndscale.pd.256(<4 x double> %x0, i32 88, <4 x double> %x2, i8 -1)7192 %res2 = fadd <4 x double> %res, %res17193 ret <4 x double> %res27194}7195 7196declare <4 x float> @llvm.x86.avx512.mask.rndscale.ps.128(<4 x float>, i32, <4 x float>, i8)7197 7198define <4 x float>@test_int_x86_avx512_mask_rndscale_ps_128(<4 x float> %x0, <4 x float> %x2, i8 %x3) #0 {7199;7200; CHECK-LABEL: define <4 x float> @test_int_x86_avx512_mask_rndscale_ps_128(7201; CHECK-SAME: <4 x float> [[X0:%.*]], <4 x float> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {7202; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 87203; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 87204; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 87205; CHECK-NEXT: call void @llvm.donothing()7206; CHECK-NEXT: [[TMP4:%.*]] = trunc i8 [[X3]] to i47207; CHECK-NEXT: [[TMP5:%.*]] = bitcast i4 [[TMP4]] to <4 x i1>7208; CHECK-NEXT: [[TMP6:%.*]] = icmp ne <4 x i32> [[TMP1]], zeroinitializer7209; CHECK-NEXT: [[TMP7:%.*]] = sext <4 x i1> [[TMP6]] to <4 x i32>7210; CHECK-NEXT: [[TMP8:%.*]] = select <4 x i1> [[TMP5]], <4 x i32> [[TMP7]], <4 x i32> [[TMP2]]7211; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 07212; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]7213; CHECK: [[BB9]]:7214; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]7215; CHECK-NEXT: unreachable7216; CHECK: [[BB10]]:7217; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.mask.rndscale.ps.128(<4 x float> [[X0]], i32 88, <4 x float> [[X2]], i8 [[X3]])7218; CHECK-NEXT: [[TMP11:%.*]] = icmp ne <4 x i32> [[TMP1]], zeroinitializer7219; CHECK-NEXT: [[TMP12:%.*]] = sext <4 x i1> [[TMP11]] to <4 x i32>7220; CHECK-NEXT: [[TMP13:%.*]] = select <4 x i1> splat (i1 true), <4 x i32> [[TMP12]], <4 x i32> [[TMP2]]7221; CHECK-NEXT: [[RES1:%.*]] = call <4 x float> @llvm.x86.avx512.mask.rndscale.ps.128(<4 x float> [[X0]], i32 4, <4 x float> [[X2]], i8 -1)7222; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP8]], [[TMP13]]7223; CHECK-NEXT: [[RES2:%.*]] = fadd <4 x float> [[RES]], [[RES1]]7224; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 87225; CHECK-NEXT: ret <4 x float> [[RES2]]7226;7227 %res = call <4 x float> @llvm.x86.avx512.mask.rndscale.ps.128(<4 x float> %x0, i32 88, <4 x float> %x2, i8 %x3)7228 %res1 = call <4 x float> @llvm.x86.avx512.mask.rndscale.ps.128(<4 x float> %x0, i32 4, <4 x float> %x2, i8 -1)7229 %res2 = fadd <4 x float> %res, %res17230 ret <4 x float> %res27231}7232 7233declare <8 x float> @llvm.x86.avx512.mask.rndscale.ps.256(<8 x float>, i32, <8 x float>, i8)7234 7235define <8 x float>@test_int_x86_avx512_mask_rndscale_ps_256(<8 x float> %x0, <8 x float> %x2, i8 %x3) #0 {7236;7237; CHECK-LABEL: define <8 x float> @test_int_x86_avx512_mask_rndscale_ps_256(7238; CHECK-SAME: <8 x float> [[X0:%.*]], <8 x float> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {7239; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 87240; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 87241; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 87242; CHECK-NEXT: call void @llvm.donothing()7243; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8 [[X3]] to <8 x i1>7244; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <8 x i32> [[TMP1]], zeroinitializer7245; CHECK-NEXT: [[TMP6:%.*]] = sext <8 x i1> [[TMP5]] to <8 x i32>7246; CHECK-NEXT: [[TMP7:%.*]] = select <8 x i1> [[TMP4]], <8 x i32> [[TMP6]], <8 x i32> [[TMP2]]7247; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 07248; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]7249; CHECK: [[BB8]]:7250; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]7251; CHECK-NEXT: unreachable7252; CHECK: [[BB9]]:7253; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx512.mask.rndscale.ps.256(<8 x float> [[X0]], i32 5, <8 x float> [[X2]], i8 [[X3]])7254; CHECK-NEXT: [[TMP10:%.*]] = icmp ne <8 x i32> [[TMP1]], zeroinitializer7255; CHECK-NEXT: [[TMP11:%.*]] = sext <8 x i1> [[TMP10]] to <8 x i32>7256; CHECK-NEXT: [[TMP12:%.*]] = select <8 x i1> splat (i1 true), <8 x i32> [[TMP11]], <8 x i32> [[TMP2]]7257; CHECK-NEXT: [[RES1:%.*]] = call <8 x float> @llvm.x86.avx512.mask.rndscale.ps.256(<8 x float> [[X0]], i32 66, <8 x float> [[X2]], i8 -1)7258; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> [[TMP7]], [[TMP12]]7259; CHECK-NEXT: [[RES2:%.*]] = fadd <8 x float> [[RES]], [[RES1]]7260; CHECK-NEXT: store <8 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 87261; CHECK-NEXT: ret <8 x float> [[RES2]]7262;7263 %res = call <8 x float> @llvm.x86.avx512.mask.rndscale.ps.256(<8 x float> %x0, i32 5, <8 x float> %x2, i8 %x3)7264 %res1 = call <8 x float> @llvm.x86.avx512.mask.rndscale.ps.256(<8 x float> %x0, i32 66, <8 x float> %x2, i8 -1)7265 %res2 = fadd <8 x float> %res, %res17266 ret <8 x float> %res27267}7268 7269declare <2 x double> @llvm.x86.avx512.mask.getmant.pd.128(<2 x double>, i32, <2 x double>, i8)7270 7271define <2 x double>@test_int_x86_avx512_mask_getmant_pd_128(<2 x double> %x0, <2 x double> %x2, i8 %x3) #0 {7272;7273; CHECK-LABEL: define <2 x double> @test_int_x86_avx512_mask_getmant_pd_128(7274; CHECK-SAME: <2 x double> [[X0:%.*]], <2 x double> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {7275; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 87276; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 87277; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 87278; CHECK-NEXT: call void @llvm.donothing()7279; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP1]] to i1287280; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 07281; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP2]] to i1287282; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 07283; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]7284; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 07285; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]7286; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]7287; CHECK: [[BB6]]:7288; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]7289; CHECK-NEXT: unreachable7290; CHECK: [[BB7]]:7291; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx512.mask.getmant.pd.128(<2 x double> [[X0]], i32 11, <2 x double> [[X2]], i8 [[X3]])7292; CHECK-NEXT: [[TMP8:%.*]] = bitcast <2 x i64> [[TMP1]] to i1287293; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i128 [[TMP8]], 07294; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i8 [[TMP3]], 07295; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSCMP4]], [[_MSCMP5]]7296; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]7297; CHECK: [[BB9]]:7298; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]7299; CHECK-NEXT: unreachable7300; CHECK: [[BB10]]:7301; CHECK-NEXT: [[RES2:%.*]] = call <2 x double> @llvm.x86.avx512.mask.getmant.pd.128(<2 x double> [[X0]], i32 12, <2 x double> zeroinitializer, i8 [[X3]])7302; CHECK-NEXT: [[TMP11:%.*]] = bitcast <2 x i64> [[TMP1]] to i1287303; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i128 [[TMP11]], 07304; CHECK-NEXT: [[TMP12:%.*]] = bitcast <2 x i64> [[TMP2]] to i1287305; CHECK-NEXT: [[_MSCMP8:%.*]] = icmp ne i128 [[TMP12]], 07306; CHECK-NEXT: [[_MSOR9:%.*]] = or i1 [[_MSCMP7]], [[_MSCMP8]]7307; CHECK-NEXT: br i1 [[_MSOR9]], label %[[BB13:.*]], label %[[BB14:.*]], !prof [[PROF1]]7308; CHECK: [[BB13]]:7309; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]7310; CHECK-NEXT: unreachable7311; CHECK: [[BB14]]:7312; CHECK-NEXT: [[RES1:%.*]] = call <2 x double> @llvm.x86.avx512.mask.getmant.pd.128(<2 x double> [[X0]], i32 13, <2 x double> [[X2]], i8 -1)7313; CHECK-NEXT: [[RES3:%.*]] = fadd <2 x double> [[RES]], [[RES1]]7314; CHECK-NEXT: [[RES4:%.*]] = fadd <2 x double> [[RES2]], [[RES3]]7315; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 87316; CHECK-NEXT: ret <2 x double> [[RES4]]7317;7318 %res = call <2 x double> @llvm.x86.avx512.mask.getmant.pd.128(<2 x double> %x0, i32 11, <2 x double> %x2, i8 %x3)7319 %res2 = call <2 x double> @llvm.x86.avx512.mask.getmant.pd.128(<2 x double> %x0, i32 12, <2 x double> zeroinitializer, i8 %x3)7320 %res1 = call <2 x double> @llvm.x86.avx512.mask.getmant.pd.128(<2 x double> %x0, i32 13, <2 x double> %x2, i8 -1)7321 %res3 = fadd <2 x double> %res, %res17322 %res4 = fadd <2 x double> %res2, %res37323 ret <2 x double> %res47324}7325 7326declare <4 x double> @llvm.x86.avx512.mask.getmant.pd.256(<4 x double>, i32, <4 x double>, i8)7327 7328define <4 x double>@test_int_x86_avx512_mask_getmant_pd_256(<4 x double> %x0, <4 x double> %x2, i8 %x3) #0 {7329;7330; CHECK-LABEL: define <4 x double> @test_int_x86_avx512_mask_getmant_pd_256(7331; CHECK-SAME: <4 x double> [[X0:%.*]], <4 x double> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {7332; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 87333; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 87334; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 87335; CHECK-NEXT: call void @llvm.donothing()7336; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i64> [[TMP1]] to i2567337; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP4]], 07338; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i64> [[TMP2]] to i2567339; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP5]], 07340; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]7341; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 07342; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]7343; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]7344; CHECK: [[BB6]]:7345; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]7346; CHECK-NEXT: unreachable7347; CHECK: [[BB7]]:7348; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.x86.avx512.mask.getmant.pd.256(<4 x double> [[X0]], i32 11, <4 x double> [[X2]], i8 [[X3]])7349; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x i64> [[TMP1]] to i2567350; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i256 [[TMP8]], 07351; CHECK-NEXT: [[TMP9:%.*]] = bitcast <4 x i64> [[TMP2]] to i2567352; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i256 [[TMP9]], 07353; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSCMP4]], [[_MSCMP5]]7354; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB10:.*]], label %[[BB11:.*]], !prof [[PROF1]]7355; CHECK: [[BB10]]:7356; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]7357; CHECK-NEXT: unreachable7358; CHECK: [[BB11]]:7359; CHECK-NEXT: [[RES1:%.*]] = call <4 x double> @llvm.x86.avx512.mask.getmant.pd.256(<4 x double> [[X0]], i32 12, <4 x double> [[X2]], i8 -1)7360; CHECK-NEXT: [[RES2:%.*]] = fadd <4 x double> [[RES]], [[RES1]]7361; CHECK-NEXT: store <4 x i64> zeroinitializer, ptr @__msan_retval_tls, align 87362; CHECK-NEXT: ret <4 x double> [[RES2]]7363;7364 %res = call <4 x double> @llvm.x86.avx512.mask.getmant.pd.256(<4 x double> %x0, i32 11, <4 x double> %x2, i8 %x3)7365 %res1 = call <4 x double> @llvm.x86.avx512.mask.getmant.pd.256(<4 x double> %x0, i32 12, <4 x double> %x2, i8 -1)7366 %res2 = fadd <4 x double> %res, %res17367 ret <4 x double> %res27368}7369 7370declare <4 x float> @llvm.x86.avx512.mask.getmant.ps.128(<4 x float>, i32, <4 x float>, i8)7371 7372define <4 x float>@test_int_x86_avx512_mask_getmant_ps_128(<4 x float> %x0, <4 x float> %x2, i8 %x3) #0 {7373;7374; CHECK-LABEL: define <4 x float> @test_int_x86_avx512_mask_getmant_ps_128(7375; CHECK-SAME: <4 x float> [[X0:%.*]], <4 x float> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {7376; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 87377; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 87378; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 87379; CHECK-NEXT: call void @llvm.donothing()7380; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP1]] to i1287381; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 07382; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP2]] to i1287383; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 07384; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]7385; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 07386; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]7387; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]7388; CHECK: [[BB6]]:7389; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]7390; CHECK-NEXT: unreachable7391; CHECK: [[BB7]]:7392; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.mask.getmant.ps.128(<4 x float> [[X0]], i32 11, <4 x float> [[X2]], i8 [[X3]])7393; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x i32> [[TMP1]] to i1287394; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i128 [[TMP8]], 07395; CHECK-NEXT: [[TMP9:%.*]] = bitcast <4 x i32> [[TMP2]] to i1287396; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i128 [[TMP9]], 07397; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSCMP4]], [[_MSCMP5]]7398; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB10:.*]], label %[[BB11:.*]], !prof [[PROF1]]7399; CHECK: [[BB10]]:7400; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]7401; CHECK-NEXT: unreachable7402; CHECK: [[BB11]]:7403; CHECK-NEXT: [[RES1:%.*]] = call <4 x float> @llvm.x86.avx512.mask.getmant.ps.128(<4 x float> [[X0]], i32 12, <4 x float> [[X2]], i8 -1)7404; CHECK-NEXT: [[RES2:%.*]] = fadd <4 x float> [[RES]], [[RES1]]7405; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 87406; CHECK-NEXT: ret <4 x float> [[RES2]]7407;7408 %res = call <4 x float> @llvm.x86.avx512.mask.getmant.ps.128(<4 x float> %x0, i32 11, <4 x float> %x2, i8 %x3)7409 %res1 = call <4 x float> @llvm.x86.avx512.mask.getmant.ps.128(<4 x float> %x0, i32 12, <4 x float> %x2, i8 -1)7410 %res2 = fadd <4 x float> %res, %res17411 ret <4 x float> %res27412}7413 7414declare <8 x float> @llvm.x86.avx512.mask.getmant.ps.256(<8 x float>, i32, <8 x float>, i8)7415 7416define <8 x float>@test_int_x86_avx512_mask_getmant_ps_256(<8 x float> %x0, <8 x float> %x2, i8 %x3) #0 {7417;7418; CHECK-LABEL: define <8 x float> @test_int_x86_avx512_mask_getmant_ps_256(7419; CHECK-SAME: <8 x float> [[X0:%.*]], <8 x float> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {7420; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 87421; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 87422; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 87423; CHECK-NEXT: call void @llvm.donothing()7424; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i32> [[TMP1]] to i2567425; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP4]], 07426; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i32> [[TMP2]] to i2567427; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP5]], 07428; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]7429; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 07430; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]7431; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]7432; CHECK: [[BB6]]:7433; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]7434; CHECK-NEXT: unreachable7435; CHECK: [[BB7]]:7436; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx512.mask.getmant.ps.256(<8 x float> [[X0]], i32 11, <8 x float> [[X2]], i8 [[X3]])7437; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i32> [[TMP1]] to i2567438; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i256 [[TMP8]], 07439; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i32> [[TMP2]] to i2567440; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i256 [[TMP9]], 07441; CHECK-NEXT: [[_MSOR6:%.*]] = or i1 [[_MSCMP4]], [[_MSCMP5]]7442; CHECK-NEXT: br i1 [[_MSOR6]], label %[[BB10:.*]], label %[[BB11:.*]], !prof [[PROF1]]7443; CHECK: [[BB10]]:7444; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]7445; CHECK-NEXT: unreachable7446; CHECK: [[BB11]]:7447; CHECK-NEXT: [[RES1:%.*]] = call <8 x float> @llvm.x86.avx512.mask.getmant.ps.256(<8 x float> [[X0]], i32 12, <8 x float> [[X2]], i8 -1)7448; CHECK-NEXT: [[RES2:%.*]] = fadd <8 x float> [[RES]], [[RES1]]7449; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 87450; CHECK-NEXT: ret <8 x float> [[RES2]]7451;7452 %res = call <8 x float> @llvm.x86.avx512.mask.getmant.ps.256(<8 x float> %x0, i32 11, <8 x float> %x2, i8 %x3)7453 %res1 = call <8 x float> @llvm.x86.avx512.mask.getmant.ps.256(<8 x float> %x0, i32 12, <8 x float> %x2, i8 -1)7454 %res2 = fadd <8 x float> %res, %res17455 ret <8 x float> %res27456}7457 7458declare <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32>, <4 x i32>, <4 x i32>, i32)7459 7460define <4 x i32>@test_int_x86_avx512_pternlog_d_128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2) #0 {7461; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_pternlog_d_128(7462; CHECK-SAME: <4 x i32> [[X0:%.*]], <4 x i32> [[X1:%.*]], <4 x i32> [[X2:%.*]]) #[[ATTR0]] {7463; CHECK-NEXT: [[TMP7:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 87464; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 87465; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 87466; CHECK-NEXT: call void @llvm.donothing()7467; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP7]] to i1287468; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 07469; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP2]] to i1287470; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 07471; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]7472; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i32> [[TMP3]] to i1287473; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP6]], 07474; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]7475; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]7476; CHECK: [[BB7]]:7477; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]7478; CHECK-NEXT: unreachable7479; CHECK: [[BB8]]:7480; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> [[X0]], <4 x i32> [[X1]], <4 x i32> [[X2]], i32 33)7481; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 87482; CHECK-NEXT: ret <4 x i32> [[TMP1]]7483;7484 %1 = call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i32 33)7485 ret <4 x i32> %17486}7487 7488define <4 x i32>@test_int_x86_avx512_mask_pternlog_d_128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %x4) #0 {7489;7490; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_mask_pternlog_d_128(7491; CHECK-SAME: <4 x i32> [[X0:%.*]], <4 x i32> [[X1:%.*]], <4 x i32> [[X2:%.*]], i8 [[X4:%.*]]) #[[ATTR0]] {7492; CHECK-NEXT: [[TMP8:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 87493; CHECK-NEXT: [[TMP9:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 87494; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 87495; CHECK-NEXT: [[TMP10:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 87496; CHECK-NEXT: call void @llvm.donothing()7497; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i32> [[TMP8]] to i1287498; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP12]], 07499; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i32> [[TMP9]] to i1287500; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP6]], 07501; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]7502; CHECK-NEXT: [[TMP14:%.*]] = bitcast <4 x i32> [[TMP3]] to i1287503; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP14]], 07504; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]7505; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]7506; CHECK: [[BB8]]:7507; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]7508; CHECK-NEXT: unreachable7509; CHECK: [[BB9]]:7510; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> [[X0]], <4 x i32> [[X1]], <4 x i32> [[X2]], i32 33)7511; CHECK-NEXT: [[TMP11:%.*]] = bitcast i8 [[TMP10]] to <8 x i1>7512; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[X4]] to <8 x i1>7513; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP11]], <8 x i1> [[TMP11]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>7514; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> [[TMP2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>7515; CHECK-NEXT: [[TMP13:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i32> zeroinitializer, <4 x i32> [[TMP8]]7516; CHECK-NEXT: [[TMP4:%.*]] = xor <4 x i32> [[TMP1]], [[X0]]7517; CHECK-NEXT: [[TMP5:%.*]] = or <4 x i32> [[TMP4]], zeroinitializer7518; CHECK-NEXT: [[TMP16:%.*]] = or <4 x i32> [[TMP5]], [[TMP8]]7519; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP]], <4 x i32> [[TMP16]], <4 x i32> [[TMP13]]7520; CHECK-NEXT: [[TMP7:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i32> [[TMP1]], <4 x i32> [[X0]]7521; CHECK-NEXT: store <4 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 87522; CHECK-NEXT: ret <4 x i32> [[TMP7]]7523;7524 %1 = call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i32 33)7525 %2 = bitcast i8 %x4 to <8 x i1>7526 %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>7527 %3 = select <4 x i1> %extract, <4 x i32> %1, <4 x i32> %x07528 ret <4 x i32> %37529}7530 7531declare <4 x i32> @llvm.x86.avx512.maskz.pternlog.d.128(<4 x i32>, <4 x i32>, <4 x i32>, i32, i8)7532 7533define <4 x i32>@test_int_x86_avx512_maskz_pternlog_d_128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %x4) #0 {7534;7535; CHECK-LABEL: define <4 x i32> @test_int_x86_avx512_maskz_pternlog_d_128(7536; CHECK-SAME: <4 x i32> [[X0:%.*]], <4 x i32> [[X1:%.*]], <4 x i32> [[X2:%.*]], i8 [[X4:%.*]]) #[[ATTR0]] {7537; CHECK-NEXT: [[TMP8:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 87538; CHECK-NEXT: [[TMP9:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 87539; CHECK-NEXT: [[TMP10:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 87540; CHECK-NEXT: [[TMP12:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 87541; CHECK-NEXT: call void @llvm.donothing()7542; CHECK-NEXT: [[TMP13:%.*]] = bitcast <4 x i32> [[TMP8]] to i1287543; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP13]], 07544; CHECK-NEXT: [[TMP14:%.*]] = bitcast <4 x i32> [[TMP9]] to i1287545; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP14]], 07546; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]7547; CHECK-NEXT: [[TMP15:%.*]] = bitcast <4 x i32> [[TMP10]] to i1287548; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP15]], 07549; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]7550; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]7551; CHECK: [[BB8]]:7552; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]7553; CHECK-NEXT: unreachable7554; CHECK: [[BB9]]:7555; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> [[X0]], <4 x i32> [[X1]], <4 x i32> [[X2]], i32 33)7556; CHECK-NEXT: [[TMP11:%.*]] = bitcast i8 [[TMP12]] to <8 x i1>7557; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[X4]] to <8 x i1>7558; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP11]], <8 x i1> [[TMP11]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>7559; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> [[TMP2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>7560; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i32> zeroinitializer, <4 x i32> zeroinitializer7561; CHECK-NEXT: [[TMP4:%.*]] = xor <4 x i32> [[TMP1]], zeroinitializer7562; CHECK-NEXT: [[TMP5:%.*]] = or <4 x i32> [[TMP4]], zeroinitializer7563; CHECK-NEXT: [[TMP6:%.*]] = or <4 x i32> [[TMP5]], zeroinitializer7564; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP]], <4 x i32> [[TMP6]], <4 x i32> [[TMP3]]7565; CHECK-NEXT: [[TMP7:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i32> [[TMP1]], <4 x i32> zeroinitializer7566; CHECK-NEXT: store <4 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 87567; CHECK-NEXT: ret <4 x i32> [[TMP7]]7568;7569 %1 = call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i32 33)7570 %2 = bitcast i8 %x4 to <8 x i1>7571 %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>7572 %3 = select <4 x i1> %extract, <4 x i32> %1, <4 x i32> zeroinitializer7573 ret <4 x i32> %37574}7575 7576declare <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32>, <8 x i32>, <8 x i32>, i32)7577 7578define <8 x i32>@test_int_x86_avx512_pternlog_d_256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2) #0 {7579; CHECK-LABEL: define <8 x i32> @test_int_x86_avx512_pternlog_d_256(7580; CHECK-SAME: <8 x i32> [[X0:%.*]], <8 x i32> [[X1:%.*]], <8 x i32> [[X2:%.*]]) #[[ATTR0]] {7581; CHECK-NEXT: [[TMP7:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 87582; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 87583; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 87584; CHECK-NEXT: call void @llvm.donothing()7585; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i32> [[TMP7]] to i2567586; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP4]], 07587; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i32> [[TMP2]] to i2567588; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP5]], 07589; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]7590; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i32> [[TMP3]] to i2567591; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i256 [[TMP6]], 07592; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]7593; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]7594; CHECK: [[BB7]]:7595; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]7596; CHECK-NEXT: unreachable7597; CHECK: [[BB8]]:7598; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> [[X0]], <8 x i32> [[X1]], <8 x i32> [[X2]], i32 33)7599; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 87600; CHECK-NEXT: ret <8 x i32> [[TMP1]]7601;7602 %1 = call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i32 33)7603 ret <8 x i32> %17604}7605 7606define <8 x i32>@test_int_x86_avx512_mask_pternlog_d_256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x4) #0 {7607;7608; CHECK-LABEL: define <8 x i32> @test_int_x86_avx512_mask_pternlog_d_256(7609; CHECK-SAME: <8 x i32> [[X0:%.*]], <8 x i32> [[X1:%.*]], <8 x i32> [[X2:%.*]], i8 [[X4:%.*]]) #[[ATTR0]] {7610; CHECK-NEXT: [[TMP8:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 87611; CHECK-NEXT: [[TMP9:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 87612; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 87613; CHECK-NEXT: [[TMP10:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 87614; CHECK-NEXT: call void @llvm.donothing()7615; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x i32> [[TMP8]] to i2567616; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP12]], 07617; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i32> [[TMP9]] to i2567618; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP6]], 07619; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]7620; CHECK-NEXT: [[TMP14:%.*]] = bitcast <8 x i32> [[TMP3]] to i2567621; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i256 [[TMP14]], 07622; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]7623; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]7624; CHECK: [[BB8]]:7625; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]7626; CHECK-NEXT: unreachable7627; CHECK: [[BB9]]:7628; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> [[X0]], <8 x i32> [[X1]], <8 x i32> [[X2]], i32 33)7629; CHECK-NEXT: [[TMP11:%.*]] = bitcast i8 [[TMP10]] to <8 x i1>7630; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[X4]] to <8 x i1>7631; CHECK-NEXT: [[TMP13:%.*]] = select <8 x i1> [[TMP2]], <8 x i32> zeroinitializer, <8 x i32> [[TMP8]]7632; CHECK-NEXT: [[TMP4:%.*]] = xor <8 x i32> [[TMP1]], [[X0]]7633; CHECK-NEXT: [[TMP5:%.*]] = or <8 x i32> [[TMP4]], zeroinitializer7634; CHECK-NEXT: [[TMP16:%.*]] = or <8 x i32> [[TMP5]], [[TMP8]]7635; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP11]], <8 x i32> [[TMP16]], <8 x i32> [[TMP13]]7636; CHECK-NEXT: [[TMP7:%.*]] = select <8 x i1> [[TMP2]], <8 x i32> [[TMP1]], <8 x i32> [[X0]]7637; CHECK-NEXT: store <8 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 87638; CHECK-NEXT: ret <8 x i32> [[TMP7]]7639;7640 %1 = call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i32 33)7641 %2 = bitcast i8 %x4 to <8 x i1>7642 %3 = select <8 x i1> %2, <8 x i32> %1, <8 x i32> %x07643 ret <8 x i32> %37644}7645 7646declare <8 x i32> @llvm.x86.avx512.maskz.pternlog.d.256(<8 x i32>, <8 x i32>, <8 x i32>, i32, i8)7647 7648define <8 x i32>@test_int_x86_avx512_maskz_pternlog_d_256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x4) #0 {7649;7650; CHECK-LABEL: define <8 x i32> @test_int_x86_avx512_maskz_pternlog_d_256(7651; CHECK-SAME: <8 x i32> [[X0:%.*]], <8 x i32> [[X1:%.*]], <8 x i32> [[X2:%.*]], i8 [[X4:%.*]]) #[[ATTR0]] {7652; CHECK-NEXT: [[TMP8:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 87653; CHECK-NEXT: [[TMP9:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 87654; CHECK-NEXT: [[TMP10:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 87655; CHECK-NEXT: [[TMP12:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 87656; CHECK-NEXT: call void @llvm.donothing()7657; CHECK-NEXT: [[TMP13:%.*]] = bitcast <8 x i32> [[TMP8]] to i2567658; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP13]], 07659; CHECK-NEXT: [[TMP14:%.*]] = bitcast <8 x i32> [[TMP9]] to i2567660; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP14]], 07661; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]7662; CHECK-NEXT: [[TMP15:%.*]] = bitcast <8 x i32> [[TMP10]] to i2567663; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i256 [[TMP15]], 07664; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]7665; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]7666; CHECK: [[BB8]]:7667; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]7668; CHECK-NEXT: unreachable7669; CHECK: [[BB9]]:7670; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> [[X0]], <8 x i32> [[X1]], <8 x i32> [[X2]], i32 33)7671; CHECK-NEXT: [[TMP11:%.*]] = bitcast i8 [[TMP12]] to <8 x i1>7672; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[X4]] to <8 x i1>7673; CHECK-NEXT: [[TMP3:%.*]] = select <8 x i1> [[TMP2]], <8 x i32> zeroinitializer, <8 x i32> zeroinitializer7674; CHECK-NEXT: [[TMP4:%.*]] = xor <8 x i32> [[TMP1]], zeroinitializer7675; CHECK-NEXT: [[TMP5:%.*]] = or <8 x i32> [[TMP4]], zeroinitializer7676; CHECK-NEXT: [[TMP6:%.*]] = or <8 x i32> [[TMP5]], zeroinitializer7677; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP11]], <8 x i32> [[TMP6]], <8 x i32> [[TMP3]]7678; CHECK-NEXT: [[TMP7:%.*]] = select <8 x i1> [[TMP2]], <8 x i32> [[TMP1]], <8 x i32> zeroinitializer7679; CHECK-NEXT: store <8 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 87680; CHECK-NEXT: ret <8 x i32> [[TMP7]]7681;7682 %1 = call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i32 33)7683 %2 = bitcast i8 %x4 to <8 x i1>7684 %3 = select <8 x i1> %2, <8 x i32> %1, <8 x i32> zeroinitializer7685 ret <8 x i32> %37686}7687 7688declare <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64>, <2 x i64>, <2 x i64>, i32)7689 7690define <2 x i64>@test_int_x86_avx512_pternlog_q_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2) #0 {7691; CHECK-LABEL: define <2 x i64> @test_int_x86_avx512_pternlog_q_128(7692; CHECK-SAME: <2 x i64> [[X0:%.*]], <2 x i64> [[X1:%.*]], <2 x i64> [[X2:%.*]]) #[[ATTR0]] {7693; CHECK-NEXT: [[TMP7:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 87694; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 87695; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 87696; CHECK-NEXT: call void @llvm.donothing()7697; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP7]] to i1287698; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 07699; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP2]] to i1287700; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP5]], 07701; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]7702; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i64> [[TMP3]] to i1287703; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP6]], 07704; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]7705; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]7706; CHECK: [[BB7]]:7707; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]7708; CHECK-NEXT: unreachable7709; CHECK: [[BB8]]:7710; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[X0]], <2 x i64> [[X1]], <2 x i64> [[X2]], i32 33)7711; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 87712; CHECK-NEXT: ret <2 x i64> [[TMP1]]7713;7714 %1 = call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i32 33)7715 ret <2 x i64> %17716}7717 7718define <2 x i64>@test_int_x86_avx512_mask_pternlog_q_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x4) #0 {7719;7720; CHECK-LABEL: define <2 x i64> @test_int_x86_avx512_mask_pternlog_q_128(7721; CHECK-SAME: <2 x i64> [[X0:%.*]], <2 x i64> [[X1:%.*]], <2 x i64> [[X2:%.*]], i8 [[X4:%.*]]) #[[ATTR0]] {7722; CHECK-NEXT: [[TMP8:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 87723; CHECK-NEXT: [[TMP9:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 87724; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 87725; CHECK-NEXT: [[TMP10:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 87726; CHECK-NEXT: call void @llvm.donothing()7727; CHECK-NEXT: [[TMP12:%.*]] = bitcast <2 x i64> [[TMP8]] to i1287728; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP12]], 07729; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i64> [[TMP9]] to i1287730; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP6]], 07731; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]7732; CHECK-NEXT: [[TMP14:%.*]] = bitcast <2 x i64> [[TMP3]] to i1287733; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP14]], 07734; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]7735; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]7736; CHECK: [[BB8]]:7737; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]7738; CHECK-NEXT: unreachable7739; CHECK: [[BB9]]:7740; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[X0]], <2 x i64> [[X1]], <2 x i64> [[X2]], i32 33)7741; CHECK-NEXT: [[TMP11:%.*]] = bitcast i8 [[TMP10]] to <8 x i1>7742; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[X4]] to <8 x i1>7743; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP11]], <8 x i1> [[TMP11]], <2 x i32> <i32 0, i32 1>7744; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> [[TMP2]], <2 x i32> <i32 0, i32 1>7745; CHECK-NEXT: [[TMP13:%.*]] = select <2 x i1> [[EXTRACT]], <2 x i64> zeroinitializer, <2 x i64> [[TMP8]]7746; CHECK-NEXT: [[TMP4:%.*]] = xor <2 x i64> [[TMP1]], [[X0]]7747; CHECK-NEXT: [[TMP5:%.*]] = or <2 x i64> [[TMP4]], zeroinitializer7748; CHECK-NEXT: [[TMP16:%.*]] = or <2 x i64> [[TMP5]], [[TMP8]]7749; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <2 x i1> [[_MSPROP]], <2 x i64> [[TMP16]], <2 x i64> [[TMP13]]7750; CHECK-NEXT: [[TMP7:%.*]] = select <2 x i1> [[EXTRACT]], <2 x i64> [[TMP1]], <2 x i64> [[X0]]7751; CHECK-NEXT: store <2 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 87752; CHECK-NEXT: ret <2 x i64> [[TMP7]]7753;7754 %1 = call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i32 33)7755 %2 = bitcast i8 %x4 to <8 x i1>7756 %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <2 x i32> <i32 0, i32 1>7757 %3 = select <2 x i1> %extract, <2 x i64> %1, <2 x i64> %x07758 ret <2 x i64> %37759}7760 7761define <2 x i64>@test_int_x86_avx512_maskz_pternlog_q_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x4) #0 {7762;7763; CHECK-LABEL: define <2 x i64> @test_int_x86_avx512_maskz_pternlog_q_128(7764; CHECK-SAME: <2 x i64> [[X0:%.*]], <2 x i64> [[X1:%.*]], <2 x i64> [[X2:%.*]], i8 [[X4:%.*]]) #[[ATTR0]] {7765; CHECK-NEXT: [[TMP8:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 87766; CHECK-NEXT: [[TMP9:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 87767; CHECK-NEXT: [[TMP10:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 87768; CHECK-NEXT: [[TMP12:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 87769; CHECK-NEXT: call void @llvm.donothing()7770; CHECK-NEXT: [[TMP13:%.*]] = bitcast <2 x i64> [[TMP8]] to i1287771; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP13]], 07772; CHECK-NEXT: [[TMP14:%.*]] = bitcast <2 x i64> [[TMP9]] to i1287773; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP14]], 07774; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]7775; CHECK-NEXT: [[TMP15:%.*]] = bitcast <2 x i64> [[TMP10]] to i1287776; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP15]], 07777; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]7778; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]7779; CHECK: [[BB8]]:7780; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]7781; CHECK-NEXT: unreachable7782; CHECK: [[BB9]]:7783; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[X0]], <2 x i64> [[X1]], <2 x i64> [[X2]], i32 33)7784; CHECK-NEXT: [[TMP11:%.*]] = bitcast i8 [[TMP12]] to <8 x i1>7785; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[X4]] to <8 x i1>7786; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP11]], <8 x i1> [[TMP11]], <2 x i32> <i32 0, i32 1>7787; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> [[TMP2]], <2 x i32> <i32 0, i32 1>7788; CHECK-NEXT: [[TMP3:%.*]] = select <2 x i1> [[EXTRACT]], <2 x i64> zeroinitializer, <2 x i64> zeroinitializer7789; CHECK-NEXT: [[TMP4:%.*]] = xor <2 x i64> [[TMP1]], zeroinitializer7790; CHECK-NEXT: [[TMP5:%.*]] = or <2 x i64> [[TMP4]], zeroinitializer7791; CHECK-NEXT: [[TMP6:%.*]] = or <2 x i64> [[TMP5]], zeroinitializer7792; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <2 x i1> [[_MSPROP]], <2 x i64> [[TMP6]], <2 x i64> [[TMP3]]7793; CHECK-NEXT: [[TMP7:%.*]] = select <2 x i1> [[EXTRACT]], <2 x i64> [[TMP1]], <2 x i64> zeroinitializer7794; CHECK-NEXT: store <2 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 87795; CHECK-NEXT: ret <2 x i64> [[TMP7]]7796;7797 %1 = call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i32 33)7798 %2 = bitcast i8 %x4 to <8 x i1>7799 %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <2 x i32> <i32 0, i32 1>7800 %3 = select <2 x i1> %extract, <2 x i64> %1, <2 x i64> zeroinitializer7801 ret <2 x i64> %37802}7803 7804declare <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64>, <4 x i64>, <4 x i64>, i32)7805 7806define <4 x i64>@test_int_x86_avx512_pternlog_q_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2) #0 {7807; CHECK-LABEL: define <4 x i64> @test_int_x86_avx512_pternlog_q_256(7808; CHECK-SAME: <4 x i64> [[X0:%.*]], <4 x i64> [[X1:%.*]], <4 x i64> [[X2:%.*]]) #[[ATTR0]] {7809; CHECK-NEXT: [[TMP7:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 87810; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 87811; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 87812; CHECK-NEXT: call void @llvm.donothing()7813; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i64> [[TMP7]] to i2567814; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP4]], 07815; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i64> [[TMP2]] to i2567816; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP5]], 07817; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]7818; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i64> [[TMP3]] to i2567819; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i256 [[TMP6]], 07820; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]7821; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]7822; CHECK: [[BB7]]:7823; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]7824; CHECK-NEXT: unreachable7825; CHECK: [[BB8]]:7826; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> [[X0]], <4 x i64> [[X1]], <4 x i64> [[X2]], i32 33)7827; CHECK-NEXT: store <4 x i64> zeroinitializer, ptr @__msan_retval_tls, align 87828; CHECK-NEXT: ret <4 x i64> [[TMP1]]7829;7830 %1 = call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i32 33)7831 ret <4 x i64> %17832}7833 7834define <4 x i64>@test_int_x86_avx512_mask_pternlog_q_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x4) #0 {7835;7836; CHECK-LABEL: define <4 x i64> @test_int_x86_avx512_mask_pternlog_q_256(7837; CHECK-SAME: <4 x i64> [[X0:%.*]], <4 x i64> [[X1:%.*]], <4 x i64> [[X2:%.*]], i8 [[X4:%.*]]) #[[ATTR0]] {7838; CHECK-NEXT: [[TMP8:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 87839; CHECK-NEXT: [[TMP9:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 87840; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 87841; CHECK-NEXT: [[TMP10:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 87842; CHECK-NEXT: call void @llvm.donothing()7843; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i64> [[TMP8]] to i2567844; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP12]], 07845; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i64> [[TMP9]] to i2567846; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP6]], 07847; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]7848; CHECK-NEXT: [[TMP14:%.*]] = bitcast <4 x i64> [[TMP3]] to i2567849; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i256 [[TMP14]], 07850; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]7851; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]7852; CHECK: [[BB8]]:7853; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]7854; CHECK-NEXT: unreachable7855; CHECK: [[BB9]]:7856; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> [[X0]], <4 x i64> [[X1]], <4 x i64> [[X2]], i32 33)7857; CHECK-NEXT: [[TMP11:%.*]] = bitcast i8 [[TMP10]] to <8 x i1>7858; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[X4]] to <8 x i1>7859; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP11]], <8 x i1> [[TMP11]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>7860; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> [[TMP2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>7861; CHECK-NEXT: [[TMP13:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i64> zeroinitializer, <4 x i64> [[TMP8]]7862; CHECK-NEXT: [[TMP4:%.*]] = xor <4 x i64> [[TMP1]], [[X0]]7863; CHECK-NEXT: [[TMP5:%.*]] = or <4 x i64> [[TMP4]], zeroinitializer7864; CHECK-NEXT: [[TMP16:%.*]] = or <4 x i64> [[TMP5]], [[TMP8]]7865; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP]], <4 x i64> [[TMP16]], <4 x i64> [[TMP13]]7866; CHECK-NEXT: [[TMP7:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i64> [[TMP1]], <4 x i64> [[X0]]7867; CHECK-NEXT: store <4 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 87868; CHECK-NEXT: ret <4 x i64> [[TMP7]]7869;7870 %1 = call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i32 33)7871 %2 = bitcast i8 %x4 to <8 x i1>7872 %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>7873 %3 = select <4 x i1> %extract, <4 x i64> %1, <4 x i64> %x07874 ret <4 x i64> %37875}7876 7877define <4 x i64>@test_int_x86_avx512_maskz_pternlog_q_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x4) #0 {7878;7879; CHECK-LABEL: define <4 x i64> @test_int_x86_avx512_maskz_pternlog_q_256(7880; CHECK-SAME: <4 x i64> [[X0:%.*]], <4 x i64> [[X1:%.*]], <4 x i64> [[X2:%.*]], i8 [[X4:%.*]]) #[[ATTR0]] {7881; CHECK-NEXT: [[TMP8:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 87882; CHECK-NEXT: [[TMP9:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 87883; CHECK-NEXT: [[TMP10:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 87884; CHECK-NEXT: [[TMP12:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 87885; CHECK-NEXT: call void @llvm.donothing()7886; CHECK-NEXT: [[TMP13:%.*]] = bitcast <4 x i64> [[TMP8]] to i2567887; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP13]], 07888; CHECK-NEXT: [[TMP14:%.*]] = bitcast <4 x i64> [[TMP9]] to i2567889; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP14]], 07890; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]7891; CHECK-NEXT: [[TMP15:%.*]] = bitcast <4 x i64> [[TMP10]] to i2567892; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i256 [[TMP15]], 07893; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]7894; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]7895; CHECK: [[BB8]]:7896; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]7897; CHECK-NEXT: unreachable7898; CHECK: [[BB9]]:7899; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> [[X0]], <4 x i64> [[X1]], <4 x i64> [[X2]], i32 33)7900; CHECK-NEXT: [[TMP11:%.*]] = bitcast i8 [[TMP12]] to <8 x i1>7901; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[X4]] to <8 x i1>7902; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP11]], <8 x i1> [[TMP11]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>7903; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> [[TMP2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>7904; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i64> zeroinitializer, <4 x i64> zeroinitializer7905; CHECK-NEXT: [[TMP4:%.*]] = xor <4 x i64> [[TMP1]], zeroinitializer7906; CHECK-NEXT: [[TMP5:%.*]] = or <4 x i64> [[TMP4]], zeroinitializer7907; CHECK-NEXT: [[TMP6:%.*]] = or <4 x i64> [[TMP5]], zeroinitializer7908; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP]], <4 x i64> [[TMP6]], <4 x i64> [[TMP3]]7909; CHECK-NEXT: [[TMP7:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i64> [[TMP1]], <4 x i64> zeroinitializer7910; CHECK-NEXT: store <4 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 87911; CHECK-NEXT: ret <4 x i64> [[TMP7]]7912;7913 %1 = call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i32 33)7914 %2 = bitcast i8 %x4 to <8 x i1>7915 %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>7916 %3 = select <4 x i1> %extract, <4 x i64> %1, <4 x i64> zeroinitializer7917 ret <4 x i64> %37918}7919 7920define <8 x i16> @test_x86_vcvtps2ph_128(<4 x float> %a0, i8 %mask, <8 x i16> %src) #0 {7921;7922; CHECK-LABEL: define <8 x i16> @test_x86_vcvtps2ph_128(7923; CHECK-SAME: <4 x float> [[A0:%.*]], i8 [[MASK:%.*]], <8 x i16> [[SRC:%.*]]) #[[ATTR0]] {7924; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 87925; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 87926; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 87927; CHECK-NEXT: call void @llvm.donothing()7928; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>7929; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <8 x i32> [[TMP4]], zeroinitializer7930; CHECK-NEXT: [[TMP6:%.*]] = sext <8 x i1> [[TMP5]] to <8 x i16>7931; CHECK-NEXT: [[TMP7:%.*]] = select <8 x i1> bitcast (<1 x i8> splat (i8 15) to <8 x i1>), <8 x i16> [[TMP6]], <8 x i16> zeroinitializer7932; CHECK-NEXT: [[RES1:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.vcvtps2ph.128(<4 x float> [[A0]], i32 2, <8 x i16> zeroinitializer, i8 -1)7933; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>7934; CHECK-NEXT: [[TMP9:%.*]] = trunc i8 [[MASK]] to i47935; CHECK-NEXT: [[TMP10:%.*]] = zext i4 [[TMP9]] to i87936; CHECK-NEXT: [[TMP11:%.*]] = bitcast i8 [[TMP10]] to <8 x i1>7937; CHECK-NEXT: [[TMP12:%.*]] = icmp ne <8 x i32> [[TMP8]], zeroinitializer7938; CHECK-NEXT: [[TMP13:%.*]] = sext <8 x i1> [[TMP12]] to <8 x i16>7939; CHECK-NEXT: [[TMP14:%.*]] = select <8 x i1> [[TMP11]], <8 x i16> [[TMP13]], <8 x i16> zeroinitializer7940; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP2]], 07941; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]7942; CHECK: [[BB8]]:7943; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]7944; CHECK-NEXT: unreachable7945; CHECK: [[BB9]]:7946; CHECK-NEXT: [[RES2:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.vcvtps2ph.128(<4 x float> [[A0]], i32 10, <8 x i16> zeroinitializer, i8 [[MASK]])7947; CHECK-NEXT: [[TMP17:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>7948; CHECK-NEXT: [[TMP18:%.*]] = trunc i8 [[MASK]] to i47949; CHECK-NEXT: [[TMP19:%.*]] = zext i4 [[TMP18]] to i87950; CHECK-NEXT: [[TMP20:%.*]] = bitcast i8 [[TMP19]] to <8 x i1>7951; CHECK-NEXT: [[TMP21:%.*]] = icmp ne <8 x i32> [[TMP17]], zeroinitializer7952; CHECK-NEXT: [[TMP22:%.*]] = sext <8 x i1> [[TMP21]] to <8 x i16>7953; CHECK-NEXT: [[TMP23:%.*]] = select <8 x i1> [[TMP20]], <8 x i16> [[TMP22]], <8 x i16> [[TMP3]]7954; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i8 [[TMP2]], 07955; CHECK-NEXT: br i1 [[_MSCMP6]], label %[[BB12:.*]], label %[[BB13:.*]], !prof [[PROF1]]7956; CHECK: [[BB12]]:7957; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]7958; CHECK-NEXT: unreachable7959; CHECK: [[BB13]]:7960; CHECK-NEXT: [[RES3:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.vcvtps2ph.128(<4 x float> [[A0]], i32 11, <8 x i16> [[SRC]], i8 [[MASK]])7961; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP7]], [[TMP14]]7962; CHECK-NEXT: [[RES0:%.*]] = add <8 x i16> [[RES1]], [[RES2]]7963; CHECK-NEXT: [[_MSPROP1:%.*]] = or <8 x i16> [[TMP23]], [[_MSPROP]]7964; CHECK-NEXT: [[RES:%.*]] = add <8 x i16> [[RES3]], [[RES0]]7965; CHECK-NEXT: store <8 x i16> [[_MSPROP1]], ptr @__msan_retval_tls, align 87966; CHECK-NEXT: ret <8 x i16> [[RES]]7967;7968 %res1 = call <8 x i16> @llvm.x86.avx512.mask.vcvtps2ph.128(<4 x float> %a0, i32 2, <8 x i16> zeroinitializer, i8 -1)7969 %res2 = call <8 x i16> @llvm.x86.avx512.mask.vcvtps2ph.128(<4 x float> %a0, i32 10, <8 x i16> zeroinitializer, i8 %mask)7970 %res3 = call <8 x i16> @llvm.x86.avx512.mask.vcvtps2ph.128(<4 x float> %a0, i32 11, <8 x i16> %src, i8 %mask)7971 %res0 = add <8 x i16> %res1, %res27972 %res = add <8 x i16> %res3, %res07973 ret <8 x i16> %res7974}7975 7976declare <8 x i16> @llvm.x86.avx512.mask.vcvtps2ph.128(<4 x float>, i32, <8 x i16>, i8) nounwind readonly7977 7978define <8 x i16> @test_x86_vcvtps2ph_256(<8 x float> %a0, i8 %mask, <8 x i16> %src) #0 {7979;7980; CHECK-LABEL: define <8 x i16> @test_x86_vcvtps2ph_256(7981; CHECK-SAME: <8 x float> [[A0:%.*]], i8 [[MASK:%.*]], <8 x i16> [[SRC:%.*]]) #[[ATTR0]] {7982; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 87983; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 87984; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 87985; CHECK-NEXT: call void @llvm.donothing()7986; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <8 x i32> [[TMP1]], zeroinitializer7987; CHECK-NEXT: [[TMP6:%.*]] = sext <8 x i1> [[TMP5]] to <8 x i16>7988; CHECK-NEXT: [[TMP7:%.*]] = select <8 x i1> splat (i1 true), <8 x i16> [[TMP6]], <8 x i16> zeroinitializer7989; CHECK-NEXT: [[RES1:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.vcvtps2ph.256(<8 x float> [[A0]], i32 2, <8 x i16> zeroinitializer, i8 -1)7990; CHECK-NEXT: [[TMP9:%.*]] = bitcast i8 [[MASK]] to <8 x i1>7991; CHECK-NEXT: [[TMP10:%.*]] = icmp ne <8 x i32> [[TMP1]], zeroinitializer7992; CHECK-NEXT: [[TMP11:%.*]] = sext <8 x i1> [[TMP10]] to <8 x i16>7993; CHECK-NEXT: [[TMP12:%.*]] = select <8 x i1> [[TMP9]], <8 x i16> [[TMP11]], <8 x i16> zeroinitializer7994; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP2]], 07995; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]7996; CHECK: [[BB6]]:7997; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]7998; CHECK-NEXT: unreachable7999; CHECK: [[BB7]]:8000; CHECK-NEXT: [[RES2:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.vcvtps2ph.256(<8 x float> [[A0]], i32 11, <8 x i16> zeroinitializer, i8 [[MASK]])8001; CHECK-NEXT: [[TMP16:%.*]] = bitcast i8 [[MASK]] to <8 x i1>8002; CHECK-NEXT: [[TMP17:%.*]] = icmp ne <8 x i32> [[TMP1]], zeroinitializer8003; CHECK-NEXT: [[TMP18:%.*]] = sext <8 x i1> [[TMP17]] to <8 x i16>8004; CHECK-NEXT: [[TMP19:%.*]] = select <8 x i1> [[TMP16]], <8 x i16> [[TMP18]], <8 x i16> [[TMP3]]8005; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i8 [[TMP2]], 08006; CHECK-NEXT: br i1 [[_MSCMP6]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]8007; CHECK: [[BB9]]:8008; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]8009; CHECK-NEXT: unreachable8010; CHECK: [[BB10]]:8011; CHECK-NEXT: [[RES3:%.*]] = call <8 x i16> @llvm.x86.avx512.mask.vcvtps2ph.256(<8 x float> [[A0]], i32 12, <8 x i16> [[SRC]], i8 [[MASK]])8012; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP7]], [[TMP12]]8013; CHECK-NEXT: [[RES0:%.*]] = add <8 x i16> [[RES1]], [[RES2]]8014; CHECK-NEXT: [[_MSPROP1:%.*]] = or <8 x i16> [[TMP19]], [[_MSPROP]]8015; CHECK-NEXT: [[RES:%.*]] = add <8 x i16> [[RES3]], [[RES0]]8016; CHECK-NEXT: store <8 x i16> [[_MSPROP1]], ptr @__msan_retval_tls, align 88017; CHECK-NEXT: ret <8 x i16> [[RES]]8018;8019 %res1 = call <8 x i16> @llvm.x86.avx512.mask.vcvtps2ph.256(<8 x float> %a0, i32 2, <8 x i16> zeroinitializer, i8 -1)8020 %res2 = call <8 x i16> @llvm.x86.avx512.mask.vcvtps2ph.256(<8 x float> %a0, i32 11, <8 x i16> zeroinitializer, i8 %mask)8021 %res3 = call <8 x i16> @llvm.x86.avx512.mask.vcvtps2ph.256(<8 x float> %a0, i32 12, <8 x i16> %src, i8 %mask)8022 %res0 = add <8 x i16> %res1, %res28023 %res = add <8 x i16> %res3, %res08024 ret <8 x i16> %res8025}8026 8027declare <8 x i16> @llvm.x86.avx512.mask.vcvtps2ph.256(<8 x float>, i32, <8 x i16>, i8) nounwind readonly8028 8029define <8 x float> @test_rsqrt_ps_256_rr(<8 x float> %a0) #0 {8030; CHECK-LABEL: define <8 x float> @test_rsqrt_ps_256_rr(8031; CHECK-SAME: <8 x float> [[A0:%.*]]) #[[ATTR0]] {8032; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 88033; CHECK-NEXT: call void @llvm.donothing()8034; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <8 x i32> [[TMP1]], zeroinitializer8035; CHECK-NEXT: [[TMP3:%.*]] = sext <8 x i1> [[TMP2]] to <8 x i32>8036; CHECK-NEXT: [[TMP4:%.*]] = select <8 x i1> splat (i1 true), <8 x i32> [[TMP3]], <8 x i32> zeroinitializer8037; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx512.rsqrt14.ps.256(<8 x float> [[A0]], <8 x float> zeroinitializer, i8 -1)8038; CHECK-NEXT: store <8 x i32> [[TMP4]], ptr @__msan_retval_tls, align 88039; CHECK-NEXT: ret <8 x float> [[RES]]8040;8041 %res = call <8 x float> @llvm.x86.avx512.rsqrt14.ps.256(<8 x float> %a0, <8 x float> zeroinitializer, i8 -1)8042 ret <8 x float> %res8043}8044 8045define <8 x float> @test_rsqrt_ps_256_rrkz(<8 x float> %a0, i8 %mask) #0 {8046;8047; CHECK-LABEL: define <8 x float> @test_rsqrt_ps_256_rrkz(8048; CHECK-SAME: <8 x float> [[A0:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {8049; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 88050; CHECK-NEXT: [[TMP7:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 88051; CHECK-NEXT: call void @llvm.donothing()8052; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8 [[MASK]] to <8 x i1>8053; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <8 x i32> [[TMP7]], zeroinitializer8054; CHECK-NEXT: [[TMP5:%.*]] = sext <8 x i1> [[TMP4]] to <8 x i32>8055; CHECK-NEXT: [[TMP6:%.*]] = select <8 x i1> [[TMP3]], <8 x i32> [[TMP5]], <8 x i32> zeroinitializer8056; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i8 [[TMP2]], 08057; CHECK-NEXT: br i1 [[_MSCMP1]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]8058; CHECK: [[BB7]]:8059; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]8060; CHECK-NEXT: unreachable8061; CHECK: [[BB8]]:8062; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx512.rsqrt14.ps.256(<8 x float> [[A0]], <8 x float> zeroinitializer, i8 [[MASK]])8063; CHECK-NEXT: store <8 x i32> [[TMP6]], ptr @__msan_retval_tls, align 88064; CHECK-NEXT: ret <8 x float> [[RES]]8065;8066 %res = call <8 x float> @llvm.x86.avx512.rsqrt14.ps.256(<8 x float> %a0, <8 x float> zeroinitializer, i8 %mask)8067 ret <8 x float> %res8068}8069 8070define <8 x float> @test_rsqrt_ps_256_rrk(<8 x float> %a0, <8 x float> %a1, i8 %mask) #0 {8071;8072; CHECK-LABEL: define <8 x float> @test_rsqrt_ps_256_rrk(8073; CHECK-SAME: <8 x float> [[A0:%.*]], <8 x float> [[A1:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {8074; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 88075; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 88076; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 88077; CHECK-NEXT: call void @llvm.donothing()8078; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8 [[MASK]] to <8 x i1>8079; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <8 x i32> [[TMP1]], zeroinitializer8080; CHECK-NEXT: [[TMP6:%.*]] = sext <8 x i1> [[TMP5]] to <8 x i32>8081; CHECK-NEXT: [[TMP7:%.*]] = select <8 x i1> [[TMP4]], <8 x i32> [[TMP6]], <8 x i32> [[TMP2]]8082; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 08083; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]8084; CHECK: [[BB8]]:8085; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]8086; CHECK-NEXT: unreachable8087; CHECK: [[BB9]]:8088; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx512.rsqrt14.ps.256(<8 x float> [[A0]], <8 x float> [[A1]], i8 [[MASK]])8089; CHECK-NEXT: store <8 x i32> [[TMP7]], ptr @__msan_retval_tls, align 88090; CHECK-NEXT: ret <8 x float> [[RES]]8091;8092 %res = call <8 x float> @llvm.x86.avx512.rsqrt14.ps.256(<8 x float> %a0, <8 x float> %a1, i8 %mask)8093 ret <8 x float> %res8094}8095 8096define <4 x float> @test_rsqrt_ps_128_rr(<4 x float> %a0) #0 {8097; CHECK-LABEL: define <4 x float> @test_rsqrt_ps_128_rr(8098; CHECK-SAME: <4 x float> [[A0:%.*]]) #[[ATTR0]] {8099; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 88100; CHECK-NEXT: call void @llvm.donothing()8101; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <4 x i32> [[TMP1]], zeroinitializer8102; CHECK-NEXT: [[TMP3:%.*]] = sext <4 x i1> [[TMP2]] to <4 x i32>8103; CHECK-NEXT: [[TMP4:%.*]] = select <4 x i1> splat (i1 true), <4 x i32> [[TMP3]], <4 x i32> zeroinitializer8104; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.rsqrt14.ps.128(<4 x float> [[A0]], <4 x float> zeroinitializer, i8 -1)8105; CHECK-NEXT: store <4 x i32> [[TMP4]], ptr @__msan_retval_tls, align 88106; CHECK-NEXT: ret <4 x float> [[RES]]8107;8108 %res = call <4 x float> @llvm.x86.avx512.rsqrt14.ps.128(<4 x float> %a0, <4 x float> zeroinitializer, i8 -1)8109 ret <4 x float> %res8110}8111 8112define <4 x float> @test_rsqrt_ps_128_rrkz(<4 x float> %a0, i8 %mask) #0 {8113;8114; CHECK-LABEL: define <4 x float> @test_rsqrt_ps_128_rrkz(8115; CHECK-SAME: <4 x float> [[A0:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {8116; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 88117; CHECK-NEXT: [[TMP8:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 88118; CHECK-NEXT: call void @llvm.donothing()8119; CHECK-NEXT: [[TMP3:%.*]] = trunc i8 [[MASK]] to i48120; CHECK-NEXT: [[TMP4:%.*]] = bitcast i4 [[TMP3]] to <4 x i1>8121; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <4 x i32> [[TMP8]], zeroinitializer8122; CHECK-NEXT: [[TMP6:%.*]] = sext <4 x i1> [[TMP5]] to <4 x i32>8123; CHECK-NEXT: [[TMP7:%.*]] = select <4 x i1> [[TMP4]], <4 x i32> [[TMP6]], <4 x i32> zeroinitializer8124; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i8 [[TMP2]], 08125; CHECK-NEXT: br i1 [[_MSCMP1]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]8126; CHECK: [[BB8]]:8127; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]8128; CHECK-NEXT: unreachable8129; CHECK: [[BB9]]:8130; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.rsqrt14.ps.128(<4 x float> [[A0]], <4 x float> zeroinitializer, i8 [[MASK]])8131; CHECK-NEXT: store <4 x i32> [[TMP7]], ptr @__msan_retval_tls, align 88132; CHECK-NEXT: ret <4 x float> [[RES]]8133;8134 %res = call <4 x float> @llvm.x86.avx512.rsqrt14.ps.128(<4 x float> %a0, <4 x float> zeroinitializer, i8 %mask)8135 ret <4 x float> %res8136}8137 8138define <4 x float> @test_rsqrt_ps_128_rrk(<4 x float> %a0, <4 x float> %a1, i8 %mask) #0 {8139;8140; CHECK-LABEL: define <4 x float> @test_rsqrt_ps_128_rrk(8141; CHECK-SAME: <4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {8142; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 88143; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 88144; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 88145; CHECK-NEXT: call void @llvm.donothing()8146; CHECK-NEXT: [[TMP4:%.*]] = trunc i8 [[MASK]] to i48147; CHECK-NEXT: [[TMP5:%.*]] = bitcast i4 [[TMP4]] to <4 x i1>8148; CHECK-NEXT: [[TMP6:%.*]] = icmp ne <4 x i32> [[TMP1]], zeroinitializer8149; CHECK-NEXT: [[TMP7:%.*]] = sext <4 x i1> [[TMP6]] to <4 x i32>8150; CHECK-NEXT: [[TMP8:%.*]] = select <4 x i1> [[TMP5]], <4 x i32> [[TMP7]], <4 x i32> [[TMP2]]8151; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 08152; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]8153; CHECK: [[BB9]]:8154; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]8155; CHECK-NEXT: unreachable8156; CHECK: [[BB10]]:8157; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.rsqrt14.ps.128(<4 x float> [[A0]], <4 x float> [[A1]], i8 [[MASK]])8158; CHECK-NEXT: store <4 x i32> [[TMP8]], ptr @__msan_retval_tls, align 88159; CHECK-NEXT: ret <4 x float> [[RES]]8160;8161 %res = call <4 x float> @llvm.x86.avx512.rsqrt14.ps.128(<4 x float> %a0, <4 x float> %a1, i8 %mask)8162 ret <4 x float> %res8163}8164 8165declare <8 x float> @llvm.x86.avx512.rsqrt14.ps.256(<8 x float>, <8 x float>, i8) nounwind readnone8166declare <4 x float> @llvm.x86.avx512.rsqrt14.ps.128(<4 x float>, <4 x float>, i8) nounwind readnone8167 8168define <8 x float> @test_rcp_ps_256_rr(<8 x float> %a0) #0 {8169; CHECK-LABEL: define <8 x float> @test_rcp_ps_256_rr(8170; CHECK-SAME: <8 x float> [[A0:%.*]]) #[[ATTR0]] {8171; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 88172; CHECK-NEXT: call void @llvm.donothing()8173; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <8 x i32> [[TMP1]], zeroinitializer8174; CHECK-NEXT: [[TMP3:%.*]] = sext <8 x i1> [[TMP2]] to <8 x i32>8175; CHECK-NEXT: [[TMP4:%.*]] = select <8 x i1> splat (i1 true), <8 x i32> [[TMP3]], <8 x i32> zeroinitializer8176; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx512.rcp14.ps.256(<8 x float> [[A0]], <8 x float> zeroinitializer, i8 -1)8177; CHECK-NEXT: store <8 x i32> [[TMP4]], ptr @__msan_retval_tls, align 88178; CHECK-NEXT: ret <8 x float> [[RES]]8179;8180 %res = call <8 x float> @llvm.x86.avx512.rcp14.ps.256(<8 x float> %a0, <8 x float> zeroinitializer, i8 -1)8181 ret <8 x float> %res8182}8183 8184define <8 x float> @test_rcp_ps_256_rrkz(<8 x float> %a0, i8 %mask) #0 {8185;8186; CHECK-LABEL: define <8 x float> @test_rcp_ps_256_rrkz(8187; CHECK-SAME: <8 x float> [[A0:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {8188; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 88189; CHECK-NEXT: [[TMP7:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 88190; CHECK-NEXT: call void @llvm.donothing()8191; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8 [[MASK]] to <8 x i1>8192; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <8 x i32> [[TMP7]], zeroinitializer8193; CHECK-NEXT: [[TMP5:%.*]] = sext <8 x i1> [[TMP4]] to <8 x i32>8194; CHECK-NEXT: [[TMP6:%.*]] = select <8 x i1> [[TMP3]], <8 x i32> [[TMP5]], <8 x i32> zeroinitializer8195; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i8 [[TMP2]], 08196; CHECK-NEXT: br i1 [[_MSCMP1]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]8197; CHECK: [[BB7]]:8198; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]8199; CHECK-NEXT: unreachable8200; CHECK: [[BB8]]:8201; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx512.rcp14.ps.256(<8 x float> [[A0]], <8 x float> zeroinitializer, i8 [[MASK]])8202; CHECK-NEXT: store <8 x i32> [[TMP6]], ptr @__msan_retval_tls, align 88203; CHECK-NEXT: ret <8 x float> [[RES]]8204;8205 %res = call <8 x float> @llvm.x86.avx512.rcp14.ps.256(<8 x float> %a0, <8 x float> zeroinitializer, i8 %mask)8206 ret <8 x float> %res8207}8208 8209define <8 x float> @test_rcp_ps_256_rrk(<8 x float> %a0, <8 x float> %a1, i8 %mask) #0 {8210;8211; CHECK-LABEL: define <8 x float> @test_rcp_ps_256_rrk(8212; CHECK-SAME: <8 x float> [[A0:%.*]], <8 x float> [[A1:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {8213; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 88214; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 88215; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 88216; CHECK-NEXT: call void @llvm.donothing()8217; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8 [[MASK]] to <8 x i1>8218; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <8 x i32> [[TMP1]], zeroinitializer8219; CHECK-NEXT: [[TMP6:%.*]] = sext <8 x i1> [[TMP5]] to <8 x i32>8220; CHECK-NEXT: [[TMP7:%.*]] = select <8 x i1> [[TMP4]], <8 x i32> [[TMP6]], <8 x i32> [[TMP2]]8221; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 08222; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]8223; CHECK: [[BB8]]:8224; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]8225; CHECK-NEXT: unreachable8226; CHECK: [[BB9]]:8227; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx512.rcp14.ps.256(<8 x float> [[A0]], <8 x float> [[A1]], i8 [[MASK]])8228; CHECK-NEXT: store <8 x i32> [[TMP7]], ptr @__msan_retval_tls, align 88229; CHECK-NEXT: ret <8 x float> [[RES]]8230;8231 %res = call <8 x float> @llvm.x86.avx512.rcp14.ps.256(<8 x float> %a0, <8 x float> %a1, i8 %mask)8232 ret <8 x float> %res8233}8234 8235define <4 x float> @test_rcp_ps_128_rr(<4 x float> %a0) #0 {8236; CHECK-LABEL: define <4 x float> @test_rcp_ps_128_rr(8237; CHECK-SAME: <4 x float> [[A0:%.*]]) #[[ATTR0]] {8238; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 88239; CHECK-NEXT: call void @llvm.donothing()8240; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <4 x i32> [[TMP1]], zeroinitializer8241; CHECK-NEXT: [[TMP3:%.*]] = sext <4 x i1> [[TMP2]] to <4 x i32>8242; CHECK-NEXT: [[TMP4:%.*]] = select <4 x i1> splat (i1 true), <4 x i32> [[TMP3]], <4 x i32> zeroinitializer8243; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.rcp14.ps.128(<4 x float> [[A0]], <4 x float> zeroinitializer, i8 -1)8244; CHECK-NEXT: store <4 x i32> [[TMP4]], ptr @__msan_retval_tls, align 88245; CHECK-NEXT: ret <4 x float> [[RES]]8246;8247 %res = call <4 x float> @llvm.x86.avx512.rcp14.ps.128(<4 x float> %a0, <4 x float> zeroinitializer, i8 -1)8248 ret <4 x float> %res8249}8250 8251define <4 x float> @test_rcp_ps_128_rrkz(<4 x float> %a0, i8 %mask) #0 {8252;8253; CHECK-LABEL: define <4 x float> @test_rcp_ps_128_rrkz(8254; CHECK-SAME: <4 x float> [[A0:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {8255; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 88256; CHECK-NEXT: [[TMP8:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 88257; CHECK-NEXT: call void @llvm.donothing()8258; CHECK-NEXT: [[TMP3:%.*]] = trunc i8 [[MASK]] to i48259; CHECK-NEXT: [[TMP4:%.*]] = bitcast i4 [[TMP3]] to <4 x i1>8260; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <4 x i32> [[TMP8]], zeroinitializer8261; CHECK-NEXT: [[TMP6:%.*]] = sext <4 x i1> [[TMP5]] to <4 x i32>8262; CHECK-NEXT: [[TMP7:%.*]] = select <4 x i1> [[TMP4]], <4 x i32> [[TMP6]], <4 x i32> zeroinitializer8263; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i8 [[TMP2]], 08264; CHECK-NEXT: br i1 [[_MSCMP1]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]8265; CHECK: [[BB8]]:8266; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]8267; CHECK-NEXT: unreachable8268; CHECK: [[BB9]]:8269; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.rcp14.ps.128(<4 x float> [[A0]], <4 x float> zeroinitializer, i8 [[MASK]])8270; CHECK-NEXT: store <4 x i32> [[TMP7]], ptr @__msan_retval_tls, align 88271; CHECK-NEXT: ret <4 x float> [[RES]]8272;8273 %res = call <4 x float> @llvm.x86.avx512.rcp14.ps.128(<4 x float> %a0, <4 x float> zeroinitializer, i8 %mask)8274 ret <4 x float> %res8275}8276 8277define <4 x float> @test_rcp_ps_128_rrk(<4 x float> %a0, <4 x float> %a1, i8 %mask) #0 {8278;8279; CHECK-LABEL: define <4 x float> @test_rcp_ps_128_rrk(8280; CHECK-SAME: <4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {8281; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 88282; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 88283; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 88284; CHECK-NEXT: call void @llvm.donothing()8285; CHECK-NEXT: [[TMP4:%.*]] = trunc i8 [[MASK]] to i48286; CHECK-NEXT: [[TMP5:%.*]] = bitcast i4 [[TMP4]] to <4 x i1>8287; CHECK-NEXT: [[TMP6:%.*]] = icmp ne <4 x i32> [[TMP1]], zeroinitializer8288; CHECK-NEXT: [[TMP7:%.*]] = sext <4 x i1> [[TMP6]] to <4 x i32>8289; CHECK-NEXT: [[TMP8:%.*]] = select <4 x i1> [[TMP5]], <4 x i32> [[TMP7]], <4 x i32> [[TMP2]]8290; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 08291; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]8292; CHECK: [[BB9]]:8293; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]8294; CHECK-NEXT: unreachable8295; CHECK: [[BB10]]:8296; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.rcp14.ps.128(<4 x float> [[A0]], <4 x float> [[A1]], i8 [[MASK]])8297; CHECK-NEXT: store <4 x i32> [[TMP8]], ptr @__msan_retval_tls, align 88298; CHECK-NEXT: ret <4 x float> [[RES]]8299;8300 %res = call <4 x float> @llvm.x86.avx512.rcp14.ps.128(<4 x float> %a0, <4 x float> %a1, i8 %mask)8301 ret <4 x float> %res8302}8303 8304declare <8 x float> @llvm.x86.avx512.rcp14.ps.256(<8 x float>, <8 x float>, i8) nounwind readnone8305declare <4 x float> @llvm.x86.avx512.rcp14.ps.128(<4 x float>, <4 x float>, i8) nounwind readnone8306 8307define <4 x double> @test_rsqrt_pd_256_rr(<4 x double> %a0) #0 {8308; CHECK-LABEL: define <4 x double> @test_rsqrt_pd_256_rr(8309; CHECK-SAME: <4 x double> [[A0:%.*]]) #[[ATTR0]] {8310; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 88311; CHECK-NEXT: call void @llvm.donothing()8312; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <4 x i64> [[TMP1]], zeroinitializer8313; CHECK-NEXT: [[TMP3:%.*]] = sext <4 x i1> [[TMP2]] to <4 x i64>8314; CHECK-NEXT: [[TMP4:%.*]] = select <4 x i1> splat (i1 true), <4 x i64> [[TMP3]], <4 x i64> zeroinitializer8315; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.x86.avx512.rsqrt14.pd.256(<4 x double> [[A0]], <4 x double> zeroinitializer, i8 -1)8316; CHECK-NEXT: store <4 x i64> [[TMP4]], ptr @__msan_retval_tls, align 88317; CHECK-NEXT: ret <4 x double> [[RES]]8318;8319 %res = call <4 x double> @llvm.x86.avx512.rsqrt14.pd.256(<4 x double> %a0, <4 x double> zeroinitializer, i8 -1)8320 ret <4 x double> %res8321}8322 8323define <4 x double> @test_rsqrt_pd_256_rrkz(<4 x double> %a0, i8 %mask) #0 {8324;8325; CHECK-LABEL: define <4 x double> @test_rsqrt_pd_256_rrkz(8326; CHECK-SAME: <4 x double> [[A0:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {8327; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 88328; CHECK-NEXT: [[TMP8:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 88329; CHECK-NEXT: call void @llvm.donothing()8330; CHECK-NEXT: [[TMP3:%.*]] = trunc i8 [[MASK]] to i48331; CHECK-NEXT: [[TMP4:%.*]] = bitcast i4 [[TMP3]] to <4 x i1>8332; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <4 x i64> [[TMP8]], zeroinitializer8333; CHECK-NEXT: [[TMP6:%.*]] = sext <4 x i1> [[TMP5]] to <4 x i64>8334; CHECK-NEXT: [[TMP7:%.*]] = select <4 x i1> [[TMP4]], <4 x i64> [[TMP6]], <4 x i64> zeroinitializer8335; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i8 [[TMP2]], 08336; CHECK-NEXT: br i1 [[_MSCMP1]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]8337; CHECK: [[BB8]]:8338; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]8339; CHECK-NEXT: unreachable8340; CHECK: [[BB9]]:8341; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.x86.avx512.rsqrt14.pd.256(<4 x double> [[A0]], <4 x double> zeroinitializer, i8 [[MASK]])8342; CHECK-NEXT: store <4 x i64> [[TMP7]], ptr @__msan_retval_tls, align 88343; CHECK-NEXT: ret <4 x double> [[RES]]8344;8345 %res = call <4 x double> @llvm.x86.avx512.rsqrt14.pd.256(<4 x double> %a0, <4 x double> zeroinitializer, i8 %mask)8346 ret <4 x double> %res8347}8348 8349define <4 x double> @test_rsqrt_pd_256_rrk(<4 x double> %a0, <4 x double> %a1, i8 %mask) #0 {8350;8351; CHECK-LABEL: define <4 x double> @test_rsqrt_pd_256_rrk(8352; CHECK-SAME: <4 x double> [[A0:%.*]], <4 x double> [[A1:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {8353; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 88354; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 88355; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 88356; CHECK-NEXT: call void @llvm.donothing()8357; CHECK-NEXT: [[TMP4:%.*]] = trunc i8 [[MASK]] to i48358; CHECK-NEXT: [[TMP5:%.*]] = bitcast i4 [[TMP4]] to <4 x i1>8359; CHECK-NEXT: [[TMP6:%.*]] = icmp ne <4 x i64> [[TMP1]], zeroinitializer8360; CHECK-NEXT: [[TMP7:%.*]] = sext <4 x i1> [[TMP6]] to <4 x i64>8361; CHECK-NEXT: [[TMP8:%.*]] = select <4 x i1> [[TMP5]], <4 x i64> [[TMP7]], <4 x i64> [[TMP2]]8362; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 08363; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]8364; CHECK: [[BB9]]:8365; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]8366; CHECK-NEXT: unreachable8367; CHECK: [[BB10]]:8368; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.x86.avx512.rsqrt14.pd.256(<4 x double> [[A0]], <4 x double> [[A1]], i8 [[MASK]])8369; CHECK-NEXT: store <4 x i64> [[TMP8]], ptr @__msan_retval_tls, align 88370; CHECK-NEXT: ret <4 x double> [[RES]]8371;8372 %res = call <4 x double> @llvm.x86.avx512.rsqrt14.pd.256(<4 x double> %a0, <4 x double> %a1, i8 %mask)8373 ret <4 x double> %res8374}8375 8376define <2 x double> @test_rsqrt_pd_128_rr(<2 x double> %a0) #0 {8377; CHECK-LABEL: define <2 x double> @test_rsqrt_pd_128_rr(8378; CHECK-SAME: <2 x double> [[A0:%.*]]) #[[ATTR0]] {8379; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 88380; CHECK-NEXT: call void @llvm.donothing()8381; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i64> [[TMP1]], zeroinitializer8382; CHECK-NEXT: [[TMP3:%.*]] = sext <2 x i1> [[TMP2]] to <2 x i64>8383; CHECK-NEXT: [[TMP4:%.*]] = select <2 x i1> splat (i1 true), <2 x i64> [[TMP3]], <2 x i64> zeroinitializer8384; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx512.rsqrt14.pd.128(<2 x double> [[A0]], <2 x double> zeroinitializer, i8 -1)8385; CHECK-NEXT: store <2 x i64> [[TMP4]], ptr @__msan_retval_tls, align 88386; CHECK-NEXT: ret <2 x double> [[RES]]8387;8388 %res = call <2 x double> @llvm.x86.avx512.rsqrt14.pd.128(<2 x double> %a0, <2 x double> zeroinitializer, i8 -1)8389 ret <2 x double> %res8390}8391 8392define <2 x double> @test_rsqrt_pd_128_rrkz(<2 x double> %a0, i8 %mask) #0 {8393;8394; CHECK-LABEL: define <2 x double> @test_rsqrt_pd_128_rrkz(8395; CHECK-SAME: <2 x double> [[A0:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {8396; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 88397; CHECK-NEXT: [[TMP8:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 88398; CHECK-NEXT: call void @llvm.donothing()8399; CHECK-NEXT: [[TMP3:%.*]] = trunc i8 [[MASK]] to i28400; CHECK-NEXT: [[TMP4:%.*]] = bitcast i2 [[TMP3]] to <2 x i1>8401; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <2 x i64> [[TMP8]], zeroinitializer8402; CHECK-NEXT: [[TMP6:%.*]] = sext <2 x i1> [[TMP5]] to <2 x i64>8403; CHECK-NEXT: [[TMP7:%.*]] = select <2 x i1> [[TMP4]], <2 x i64> [[TMP6]], <2 x i64> zeroinitializer8404; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i8 [[TMP2]], 08405; CHECK-NEXT: br i1 [[_MSCMP1]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]8406; CHECK: [[BB8]]:8407; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]8408; CHECK-NEXT: unreachable8409; CHECK: [[BB9]]:8410; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx512.rsqrt14.pd.128(<2 x double> [[A0]], <2 x double> zeroinitializer, i8 [[MASK]])8411; CHECK-NEXT: store <2 x i64> [[TMP7]], ptr @__msan_retval_tls, align 88412; CHECK-NEXT: ret <2 x double> [[RES]]8413;8414 %res = call <2 x double> @llvm.x86.avx512.rsqrt14.pd.128(<2 x double> %a0, <2 x double> zeroinitializer, i8 %mask)8415 ret <2 x double> %res8416}8417 8418define <2 x double> @test_rsqrt_pd_128_rrk(<2 x double> %a0, <2 x double> %a1, i8 %mask) #0 {8419;8420; CHECK-LABEL: define <2 x double> @test_rsqrt_pd_128_rrk(8421; CHECK-SAME: <2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {8422; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 88423; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 88424; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 88425; CHECK-NEXT: call void @llvm.donothing()8426; CHECK-NEXT: [[TMP4:%.*]] = trunc i8 [[MASK]] to i28427; CHECK-NEXT: [[TMP5:%.*]] = bitcast i2 [[TMP4]] to <2 x i1>8428; CHECK-NEXT: [[TMP6:%.*]] = icmp ne <2 x i64> [[TMP1]], zeroinitializer8429; CHECK-NEXT: [[TMP7:%.*]] = sext <2 x i1> [[TMP6]] to <2 x i64>8430; CHECK-NEXT: [[TMP8:%.*]] = select <2 x i1> [[TMP5]], <2 x i64> [[TMP7]], <2 x i64> [[TMP2]]8431; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 08432; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]8433; CHECK: [[BB9]]:8434; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]8435; CHECK-NEXT: unreachable8436; CHECK: [[BB10]]:8437; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx512.rsqrt14.pd.128(<2 x double> [[A0]], <2 x double> [[A1]], i8 [[MASK]])8438; CHECK-NEXT: store <2 x i64> [[TMP8]], ptr @__msan_retval_tls, align 88439; CHECK-NEXT: ret <2 x double> [[RES]]8440;8441 %res = call <2 x double> @llvm.x86.avx512.rsqrt14.pd.128(<2 x double> %a0, <2 x double> %a1, i8 %mask)8442 ret <2 x double> %res8443}8444 8445declare <4 x double> @llvm.x86.avx512.rsqrt14.pd.256(<4 x double>, <4 x double>, i8) nounwind readnone8446declare <2 x double> @llvm.x86.avx512.rsqrt14.pd.128(<2 x double>, <2 x double>, i8) nounwind readnone8447 8448define <4 x double> @test_rcp_pd_256_rr(<4 x double> %a0) #0 {8449; CHECK-LABEL: define <4 x double> @test_rcp_pd_256_rr(8450; CHECK-SAME: <4 x double> [[A0:%.*]]) #[[ATTR0]] {8451; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 88452; CHECK-NEXT: call void @llvm.donothing()8453; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <4 x i64> [[TMP1]], zeroinitializer8454; CHECK-NEXT: [[TMP3:%.*]] = sext <4 x i1> [[TMP2]] to <4 x i64>8455; CHECK-NEXT: [[TMP4:%.*]] = select <4 x i1> splat (i1 true), <4 x i64> [[TMP3]], <4 x i64> zeroinitializer8456; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.x86.avx512.rcp14.pd.256(<4 x double> [[A0]], <4 x double> zeroinitializer, i8 -1)8457; CHECK-NEXT: store <4 x i64> [[TMP4]], ptr @__msan_retval_tls, align 88458; CHECK-NEXT: ret <4 x double> [[RES]]8459;8460 %res = call <4 x double> @llvm.x86.avx512.rcp14.pd.256(<4 x double> %a0, <4 x double> zeroinitializer, i8 -1)8461 ret <4 x double> %res8462}8463 8464define <4 x double> @test_rcp_pd_256_rrkz(<4 x double> %a0, i8 %mask) #0 {8465;8466; CHECK-LABEL: define <4 x double> @test_rcp_pd_256_rrkz(8467; CHECK-SAME: <4 x double> [[A0:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {8468; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 88469; CHECK-NEXT: [[TMP8:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 88470; CHECK-NEXT: call void @llvm.donothing()8471; CHECK-NEXT: [[TMP3:%.*]] = trunc i8 [[MASK]] to i48472; CHECK-NEXT: [[TMP4:%.*]] = bitcast i4 [[TMP3]] to <4 x i1>8473; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <4 x i64> [[TMP8]], zeroinitializer8474; CHECK-NEXT: [[TMP6:%.*]] = sext <4 x i1> [[TMP5]] to <4 x i64>8475; CHECK-NEXT: [[TMP7:%.*]] = select <4 x i1> [[TMP4]], <4 x i64> [[TMP6]], <4 x i64> zeroinitializer8476; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i8 [[TMP2]], 08477; CHECK-NEXT: br i1 [[_MSCMP1]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]8478; CHECK: [[BB8]]:8479; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]8480; CHECK-NEXT: unreachable8481; CHECK: [[BB9]]:8482; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.x86.avx512.rcp14.pd.256(<4 x double> [[A0]], <4 x double> zeroinitializer, i8 [[MASK]])8483; CHECK-NEXT: store <4 x i64> [[TMP7]], ptr @__msan_retval_tls, align 88484; CHECK-NEXT: ret <4 x double> [[RES]]8485;8486 %res = call <4 x double> @llvm.x86.avx512.rcp14.pd.256(<4 x double> %a0, <4 x double> zeroinitializer, i8 %mask)8487 ret <4 x double> %res8488}8489 8490define <4 x double> @test_rcp_pd_256_rrk(<4 x double> %a0, <4 x double> %a1, i8 %mask) #0 {8491;8492; CHECK-LABEL: define <4 x double> @test_rcp_pd_256_rrk(8493; CHECK-SAME: <4 x double> [[A0:%.*]], <4 x double> [[A1:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {8494; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 88495; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 88496; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 88497; CHECK-NEXT: call void @llvm.donothing()8498; CHECK-NEXT: [[TMP4:%.*]] = trunc i8 [[MASK]] to i48499; CHECK-NEXT: [[TMP5:%.*]] = bitcast i4 [[TMP4]] to <4 x i1>8500; CHECK-NEXT: [[TMP6:%.*]] = icmp ne <4 x i64> [[TMP1]], zeroinitializer8501; CHECK-NEXT: [[TMP7:%.*]] = sext <4 x i1> [[TMP6]] to <4 x i64>8502; CHECK-NEXT: [[TMP8:%.*]] = select <4 x i1> [[TMP5]], <4 x i64> [[TMP7]], <4 x i64> [[TMP2]]8503; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 08504; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]8505; CHECK: [[BB9]]:8506; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]8507; CHECK-NEXT: unreachable8508; CHECK: [[BB10]]:8509; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.x86.avx512.rcp14.pd.256(<4 x double> [[A0]], <4 x double> [[A1]], i8 [[MASK]])8510; CHECK-NEXT: store <4 x i64> [[TMP8]], ptr @__msan_retval_tls, align 88511; CHECK-NEXT: ret <4 x double> [[RES]]8512;8513 %res = call <4 x double> @llvm.x86.avx512.rcp14.pd.256(<4 x double> %a0, <4 x double> %a1, i8 %mask)8514 ret <4 x double> %res8515}8516 8517define <2 x double> @test_rcp_pd_128_rr(<2 x double> %a0) #0 {8518; CHECK-LABEL: define <2 x double> @test_rcp_pd_128_rr(8519; CHECK-SAME: <2 x double> [[A0:%.*]]) #[[ATTR0]] {8520; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 88521; CHECK-NEXT: call void @llvm.donothing()8522; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i64> [[TMP1]], zeroinitializer8523; CHECK-NEXT: [[TMP3:%.*]] = sext <2 x i1> [[TMP2]] to <2 x i64>8524; CHECK-NEXT: [[TMP4:%.*]] = select <2 x i1> splat (i1 true), <2 x i64> [[TMP3]], <2 x i64> zeroinitializer8525; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx512.rcp14.pd.128(<2 x double> [[A0]], <2 x double> zeroinitializer, i8 -1)8526; CHECK-NEXT: store <2 x i64> [[TMP4]], ptr @__msan_retval_tls, align 88527; CHECK-NEXT: ret <2 x double> [[RES]]8528;8529 %res = call <2 x double> @llvm.x86.avx512.rcp14.pd.128(<2 x double> %a0, <2 x double> zeroinitializer, i8 -1)8530 ret <2 x double> %res8531}8532 8533define <2 x double> @test_rcp_pd_128_rrkz(<2 x double> %a0, i8 %mask) #0 {8534;8535; CHECK-LABEL: define <2 x double> @test_rcp_pd_128_rrkz(8536; CHECK-SAME: <2 x double> [[A0:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {8537; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 88538; CHECK-NEXT: [[TMP8:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 88539; CHECK-NEXT: call void @llvm.donothing()8540; CHECK-NEXT: [[TMP3:%.*]] = trunc i8 [[MASK]] to i28541; CHECK-NEXT: [[TMP4:%.*]] = bitcast i2 [[TMP3]] to <2 x i1>8542; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <2 x i64> [[TMP8]], zeroinitializer8543; CHECK-NEXT: [[TMP6:%.*]] = sext <2 x i1> [[TMP5]] to <2 x i64>8544; CHECK-NEXT: [[TMP7:%.*]] = select <2 x i1> [[TMP4]], <2 x i64> [[TMP6]], <2 x i64> zeroinitializer8545; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i8 [[TMP2]], 08546; CHECK-NEXT: br i1 [[_MSCMP1]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]8547; CHECK: [[BB8]]:8548; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]8549; CHECK-NEXT: unreachable8550; CHECK: [[BB9]]:8551; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx512.rcp14.pd.128(<2 x double> [[A0]], <2 x double> zeroinitializer, i8 [[MASK]])8552; CHECK-NEXT: store <2 x i64> [[TMP7]], ptr @__msan_retval_tls, align 88553; CHECK-NEXT: ret <2 x double> [[RES]]8554;8555 %res = call <2 x double> @llvm.x86.avx512.rcp14.pd.128(<2 x double> %a0, <2 x double> zeroinitializer, i8 %mask)8556 ret <2 x double> %res8557}8558 8559define <2 x double> @test_rcp_pd_128_rrk(<2 x double> %a0, <2 x double> %a1, i8 %mask) #0 {8560;8561; CHECK-LABEL: define <2 x double> @test_rcp_pd_128_rrk(8562; CHECK-SAME: <2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {8563; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 88564; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 88565; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 88566; CHECK-NEXT: call void @llvm.donothing()8567; CHECK-NEXT: [[TMP4:%.*]] = trunc i8 [[MASK]] to i28568; CHECK-NEXT: [[TMP5:%.*]] = bitcast i2 [[TMP4]] to <2 x i1>8569; CHECK-NEXT: [[TMP6:%.*]] = icmp ne <2 x i64> [[TMP1]], zeroinitializer8570; CHECK-NEXT: [[TMP7:%.*]] = sext <2 x i1> [[TMP6]] to <2 x i64>8571; CHECK-NEXT: [[TMP8:%.*]] = select <2 x i1> [[TMP5]], <2 x i64> [[TMP7]], <2 x i64> [[TMP2]]8572; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i8 [[TMP3]], 08573; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]8574; CHECK: [[BB9]]:8575; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]8576; CHECK-NEXT: unreachable8577; CHECK: [[BB10]]:8578; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx512.rcp14.pd.128(<2 x double> [[A0]], <2 x double> [[A1]], i8 [[MASK]])8579; CHECK-NEXT: store <2 x i64> [[TMP8]], ptr @__msan_retval_tls, align 88580; CHECK-NEXT: ret <2 x double> [[RES]]8581;8582 %res = call <2 x double> @llvm.x86.avx512.rcp14.pd.128(<2 x double> %a0, <2 x double> %a1, i8 %mask)8583 ret <2 x double> %res8584}8585 8586declare <4 x double> @llvm.x86.avx512.rcp14.pd.256(<4 x double>, <4 x double>, i8) nounwind readnone8587declare <2 x double> @llvm.x86.avx512.rcp14.pd.128(<2 x double>, <2 x double>, i8) nounwind readnone8588 8589declare <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double>, <4 x i64>)8590 8591define <4 x double>@test_int_x86_avx512_permvar_df_256(<4 x double> %x0, <4 x i64> %x1, <4 x double> %x2) #0 {8592; CHECK-LABEL: define <4 x double> @test_int_x86_avx512_permvar_df_256(8593; CHECK-SAME: <4 x double> [[X0:%.*]], <4 x i64> [[X1:%.*]], <4 x double> [[X2:%.*]]) #[[ATTR0]] {8594; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 88595; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 88596; CHECK-NEXT: call void @llvm.donothing()8597; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i64> [[TMP5]] to i2568598; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP3]], 08599; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i64> [[TMP2]] to i2568600; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP4]], 08601; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]8602; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]8603; CHECK: [[BB5]]:8604; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]8605; CHECK-NEXT: unreachable8606; CHECK: [[BB6]]:8607; CHECK-NEXT: [[TMP1:%.*]] = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> [[X0]], <4 x i64> [[X1]])8608; CHECK-NEXT: store <4 x i64> zeroinitializer, ptr @__msan_retval_tls, align 88609; CHECK-NEXT: ret <4 x double> [[TMP1]]8610;8611 %1 = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> %x0, <4 x i64> %x1)8612 ret <4 x double> %18613}8614 8615define <4 x double>@test_int_x86_avx512_mask_permvar_df_256(<4 x double> %x0, <4 x i64> %x1, <4 x double> %x2, i8 %x3) #0 {8616;8617; CHECK-LABEL: define <4 x double> @test_int_x86_avx512_mask_permvar_df_256(8618; CHECK-SAME: <4 x double> [[X0:%.*]], <4 x i64> [[X1:%.*]], <4 x double> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {8619; CHECK-NEXT: [[TMP8:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 88620; CHECK-NEXT: [[TMP11:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 88621; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 88622; CHECK-NEXT: [[TMP13:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 88623; CHECK-NEXT: call void @llvm.donothing()8624; CHECK-NEXT: [[TMP14:%.*]] = bitcast <4 x i64> [[TMP8]] to i2568625; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP14]], 08626; CHECK-NEXT: [[TMP15:%.*]] = bitcast <4 x i64> [[TMP11]] to i2568627; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP15]], 08628; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]8629; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]8630; CHECK: [[BB7]]:8631; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]8632; CHECK-NEXT: unreachable8633; CHECK: [[BB8]]:8634; CHECK-NEXT: [[TMP1:%.*]] = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> [[X0]], <4 x i64> [[X1]])8635; CHECK-NEXT: [[TMP10:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>8636; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[X3]] to <8 x i1>8637; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP10]], <8 x i1> [[TMP10]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>8638; CHECK-NEXT: [[EXTRACT1:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> [[TMP2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>8639; CHECK-NEXT: [[TMP12:%.*]] = select <4 x i1> [[EXTRACT1]], <4 x i64> zeroinitializer, <4 x i64> [[TMP13]]8640; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x double> [[TMP1]] to <4 x i64>8641; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x double> [[X2]] to <4 x i64>8642; CHECK-NEXT: [[TMP6:%.*]] = xor <4 x i64> [[TMP4]], [[TMP5]]8643; CHECK-NEXT: [[TMP7:%.*]] = or <4 x i64> [[TMP6]], zeroinitializer8644; CHECK-NEXT: [[TMP17:%.*]] = or <4 x i64> [[TMP7]], [[TMP13]]8645; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP]], <4 x i64> [[TMP17]], <4 x i64> [[TMP12]]8646; CHECK-NEXT: [[TMP9:%.*]] = select <4 x i1> [[EXTRACT1]], <4 x double> [[TMP1]], <4 x double> [[X2]]8647; CHECK-NEXT: store <4 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 88648; CHECK-NEXT: ret <4 x double> [[TMP9]]8649;8650 %1 = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> %x0, <4 x i64> %x1)8651 %2 = bitcast i8 %x3 to <8 x i1>8652 %extract1 = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>8653 %3 = select <4 x i1> %extract1, <4 x double> %1, <4 x double> %x28654 ret <4 x double> %38655}8656 8657define <4 x double>@test_int_x86_avx512_maskz_permvar_df_256(<4 x double> %x0, <4 x i64> %x1, i8 %x3) #0 {8658;8659; CHECK-LABEL: define <4 x double> @test_int_x86_avx512_maskz_permvar_df_256(8660; CHECK-SAME: <4 x double> [[X0:%.*]], <4 x i64> [[X1:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {8661; CHECK-NEXT: [[TMP10:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 88662; CHECK-NEXT: [[TMP11:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 88663; CHECK-NEXT: [[TMP12:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 88664; CHECK-NEXT: call void @llvm.donothing()8665; CHECK-NEXT: [[TMP13:%.*]] = bitcast <4 x i64> [[TMP10]] to i2568666; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP13]], 08667; CHECK-NEXT: [[TMP14:%.*]] = bitcast <4 x i64> [[TMP11]] to i2568668; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP14]], 08669; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]8670; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]8671; CHECK: [[BB6]]:8672; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]8673; CHECK-NEXT: unreachable8674; CHECK: [[BB7]]:8675; CHECK-NEXT: [[TMP1:%.*]] = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> [[X0]], <4 x i64> [[X1]])8676; CHECK-NEXT: [[TMP9:%.*]] = bitcast i8 [[TMP12]] to <8 x i1>8677; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[X3]] to <8 x i1>8678; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP9]], <8 x i1> [[TMP9]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>8679; CHECK-NEXT: [[EXTRACT1:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> [[TMP2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>8680; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[EXTRACT1]], <4 x i64> zeroinitializer, <4 x i64> zeroinitializer8681; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x double> [[TMP1]] to <4 x i64>8682; CHECK-NEXT: [[TMP5:%.*]] = xor <4 x i64> [[TMP4]], zeroinitializer8683; CHECK-NEXT: [[TMP6:%.*]] = or <4 x i64> [[TMP5]], zeroinitializer8684; CHECK-NEXT: [[TMP7:%.*]] = or <4 x i64> [[TMP6]], zeroinitializer8685; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP]], <4 x i64> [[TMP7]], <4 x i64> [[TMP3]]8686; CHECK-NEXT: [[TMP8:%.*]] = select <4 x i1> [[EXTRACT1]], <4 x double> [[TMP1]], <4 x double> zeroinitializer8687; CHECK-NEXT: store <4 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 88688; CHECK-NEXT: ret <4 x double> [[TMP8]]8689;8690 %1 = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> %x0, <4 x i64> %x1)8691 %2 = bitcast i8 %x3 to <8 x i1>8692 %extract1 = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>8693 %3 = select <4 x i1> %extract1, <4 x double> %1, <4 x double> zeroinitializer8694 ret <4 x double> %38695}8696 8697declare <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64>, <4 x i64>)8698 8699define <4 x i64>@test_int_x86_avx512_permvar_di_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2) #0 {8700; CHECK-LABEL: define <4 x i64> @test_int_x86_avx512_permvar_di_256(8701; CHECK-SAME: <4 x i64> [[X0:%.*]], <4 x i64> [[X1:%.*]], <4 x i64> [[X2:%.*]]) #[[ATTR0]] {8702; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 88703; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 88704; CHECK-NEXT: call void @llvm.donothing()8705; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i64> [[TMP3]], [[TMP2]]8706; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> [[X0]], <4 x i64> [[X1]])8707; CHECK-NEXT: store <4 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 88708; CHECK-NEXT: ret <4 x i64> [[TMP1]]8709;8710 %1 = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> %x0, <4 x i64> %x1)8711 ret <4 x i64> %18712}8713 8714define <4 x i64>@test_int_x86_avx512_mask_permvar_di_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3) #0 {8715;8716; CHECK-LABEL: define <4 x i64> @test_int_x86_avx512_mask_permvar_di_256(8717; CHECK-SAME: <4 x i64> [[X0:%.*]], <4 x i64> [[X1:%.*]], <4 x i64> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {8718; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 88719; CHECK-NEXT: [[TMP9:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 88720; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 88721; CHECK-NEXT: [[TMP12:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 88722; CHECK-NEXT: call void @llvm.donothing()8723; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i64> [[TMP5]], [[TMP9]]8724; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> [[X0]], <4 x i64> [[X1]])8725; CHECK-NEXT: [[TMP6:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>8726; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[X3]] to <8 x i1>8727; CHECK-NEXT: [[_MSPROP1:%.*]] = shufflevector <8 x i1> [[TMP6]], <8 x i1> [[TMP6]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>8728; CHECK-NEXT: [[EXTRACT1:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> [[TMP2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>8729; CHECK-NEXT: [[TMP8:%.*]] = select <4 x i1> [[EXTRACT1]], <4 x i64> [[_MSPROP]], <4 x i64> [[TMP12]]8730; CHECK-NEXT: [[TMP4:%.*]] = xor <4 x i64> [[TMP1]], [[X2]]8731; CHECK-NEXT: [[TMP10:%.*]] = or <4 x i64> [[TMP4]], [[_MSPROP]]8732; CHECK-NEXT: [[TMP11:%.*]] = or <4 x i64> [[TMP10]], [[TMP12]]8733; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP1]], <4 x i64> [[TMP11]], <4 x i64> [[TMP8]]8734; CHECK-NEXT: [[TMP7:%.*]] = select <4 x i1> [[EXTRACT1]], <4 x i64> [[TMP1]], <4 x i64> [[X2]]8735; CHECK-NEXT: store <4 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 88736; CHECK-NEXT: ret <4 x i64> [[TMP7]]8737;8738 %1 = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> %x0, <4 x i64> %x1)8739 %2 = bitcast i8 %x3 to <8 x i1>8740 %extract1 = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>8741 %3 = select <4 x i1> %extract1, <4 x i64> %1, <4 x i64> %x28742 ret <4 x i64> %38743}8744 8745define <4 x i64>@test_int_x86_avx512_maskz_permvar_di_256(<4 x i64> %x0, <4 x i64> %x1, i8 %x3) #0 {8746;8747; CHECK-LABEL: define <4 x i64> @test_int_x86_avx512_maskz_permvar_di_256(8748; CHECK-SAME: <4 x i64> [[X0:%.*]], <4 x i64> [[X1:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {8749; CHECK-NEXT: [[TMP8:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 88750; CHECK-NEXT: [[TMP9:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 88751; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 88752; CHECK-NEXT: call void @llvm.donothing()8753; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i64> [[TMP8]], [[TMP9]]8754; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> [[X0]], <4 x i64> [[X1]])8755; CHECK-NEXT: [[TMP10:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>8756; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[X3]] to <8 x i1>8757; CHECK-NEXT: [[_MSPROP1:%.*]] = shufflevector <8 x i1> [[TMP10]], <8 x i1> [[TMP10]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>8758; CHECK-NEXT: [[EXTRACT1:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> [[TMP2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>8759; CHECK-NEXT: [[TMP11:%.*]] = select <4 x i1> [[EXTRACT1]], <4 x i64> [[_MSPROP]], <4 x i64> zeroinitializer8760; CHECK-NEXT: [[TMP4:%.*]] = xor <4 x i64> [[TMP1]], zeroinitializer8761; CHECK-NEXT: [[TMP5:%.*]] = or <4 x i64> [[TMP4]], [[_MSPROP]]8762; CHECK-NEXT: [[TMP6:%.*]] = or <4 x i64> [[TMP5]], zeroinitializer8763; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP1]], <4 x i64> [[TMP6]], <4 x i64> [[TMP11]]8764; CHECK-NEXT: [[TMP7:%.*]] = select <4 x i1> [[EXTRACT1]], <4 x i64> [[TMP1]], <4 x i64> zeroinitializer8765; CHECK-NEXT: store <4 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 88766; CHECK-NEXT: ret <4 x i64> [[TMP7]]8767;8768 %1 = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> %x0, <4 x i64> %x1)8769 %2 = bitcast i8 %x3 to <8 x i1>8770 %extract1 = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>8771 %3 = select <4 x i1> %extract1, <4 x i64> %1, <4 x i64> zeroinitializer8772 ret <4 x i64> %38773}8774 8775declare <2 x double> @llvm.x86.avx512.mask.fixupimm.pd.128(<2 x double>, <2 x double>, <2 x i64>, i32, i8)8776 8777define <2 x double>@test_int_x86_avx512_mask_fixupimm_pd_128(<2 x double> %x0, <2 x double> %x1, <2 x i64> %x2, i8 %x4) #0 {8778;8779; CHECK-LABEL: define <2 x double> @test_int_x86_avx512_mask_fixupimm_pd_128(8780; CHECK-SAME: <2 x double> [[X0:%.*]], <2 x double> [[X1:%.*]], <2 x i64> [[X2:%.*]], i8 [[X4:%.*]]) #[[ATTR0]] {8781; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 88782; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 88783; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 88784; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 88785; CHECK-NEXT: call void @llvm.donothing()8786; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP1]] to i1288787; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 08788; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i64> [[TMP2]] to i1288789; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP6]], 08790; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]8791; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i64> [[TMP3]] to i1288792; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 08793; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]8794; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 08795; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]8796; CHECK-NEXT: br i1 [[_MSOR5]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]8797; CHECK: [[BB8]]:8798; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]8799; CHECK-NEXT: unreachable8800; CHECK: [[BB9]]:8801; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx512.mask.fixupimm.pd.128(<2 x double> [[X0]], <2 x double> [[X1]], <2 x i64> [[X2]], i32 5, i8 [[X4]])8802; CHECK-NEXT: [[TMP10:%.*]] = bitcast <2 x i64> [[TMP2]] to i1288803; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i128 [[TMP10]], 08804; CHECK-NEXT: [[TMP11:%.*]] = bitcast <2 x i64> [[TMP3]] to i1288805; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i128 [[TMP11]], 08806; CHECK-NEXT: [[_MSOR8:%.*]] = or i1 [[_MSCMP6]], [[_MSCMP7]]8807; CHECK-NEXT: [[_MSCMP9:%.*]] = icmp ne i8 [[TMP4]], 08808; CHECK-NEXT: [[_MSOR10:%.*]] = or i1 [[_MSOR8]], [[_MSCMP9]]8809; CHECK-NEXT: br i1 [[_MSOR10]], label %[[BB12:.*]], label %[[BB13:.*]], !prof [[PROF1]]8810; CHECK: [[BB12]]:8811; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]8812; CHECK-NEXT: unreachable8813; CHECK: [[BB13]]:8814; CHECK-NEXT: [[RES1:%.*]] = call <2 x double> @llvm.x86.avx512.mask.fixupimm.pd.128(<2 x double> zeroinitializer, <2 x double> [[X1]], <2 x i64> [[X2]], i32 4, i8 [[X4]])8815; CHECK-NEXT: [[TMP14:%.*]] = bitcast <2 x i64> [[TMP1]] to i1288816; CHECK-NEXT: [[_MSCMP11:%.*]] = icmp ne i128 [[TMP14]], 08817; CHECK-NEXT: [[TMP15:%.*]] = bitcast <2 x i64> [[TMP2]] to i1288818; CHECK-NEXT: [[_MSCMP12:%.*]] = icmp ne i128 [[TMP15]], 08819; CHECK-NEXT: [[_MSOR13:%.*]] = or i1 [[_MSCMP11]], [[_MSCMP12]]8820; CHECK-NEXT: [[TMP16:%.*]] = bitcast <2 x i64> [[TMP3]] to i1288821; CHECK-NEXT: [[_MSCMP14:%.*]] = icmp ne i128 [[TMP16]], 08822; CHECK-NEXT: [[_MSOR15:%.*]] = or i1 [[_MSOR13]], [[_MSCMP14]]8823; CHECK-NEXT: br i1 [[_MSOR15]], label %[[BB17:.*]], label %[[BB18:.*]], !prof [[PROF1]]8824; CHECK: [[BB17]]:8825; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]8826; CHECK-NEXT: unreachable8827; CHECK: [[BB18]]:8828; CHECK-NEXT: [[RES2:%.*]] = call <2 x double> @llvm.x86.avx512.mask.fixupimm.pd.128(<2 x double> [[X0]], <2 x double> [[X1]], <2 x i64> [[X2]], i32 3, i8 -1)8829; CHECK-NEXT: [[RES3:%.*]] = fadd <2 x double> [[RES]], [[RES1]]8830; CHECK-NEXT: [[RES4:%.*]] = fadd <2 x double> [[RES3]], [[RES2]]8831; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 88832; CHECK-NEXT: ret <2 x double> [[RES4]]8833;8834 %res = call <2 x double> @llvm.x86.avx512.mask.fixupimm.pd.128(<2 x double> %x0, <2 x double> %x1,<2 x i64> %x2, i32 5, i8 %x4)8835 %res1 = call <2 x double> @llvm.x86.avx512.mask.fixupimm.pd.128(<2 x double> zeroinitializer, <2 x double> %x1, <2 x i64> %x2, i32 4, i8 %x4)8836 %res2 = call <2 x double> @llvm.x86.avx512.mask.fixupimm.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x i64> %x2, i32 3, i8 -1)8837 %res3 = fadd <2 x double> %res, %res18838 %res4 = fadd <2 x double> %res3, %res28839 ret <2 x double> %res48840}8841 8842declare <2 x double> @llvm.x86.avx512.maskz.fixupimm.pd.128(<2 x double>, <2 x double>, <2 x i64>, i32, i8)8843 8844define <2 x double>@test_int_x86_avx512_maskz_fixupimm_pd_128(<2 x double> %x0, <2 x double> %x1, <2 x i64> %x2, i8 %x4) #0 {8845;8846; CHECK-LABEL: define <2 x double> @test_int_x86_avx512_maskz_fixupimm_pd_128(8847; CHECK-SAME: <2 x double> [[X0:%.*]], <2 x double> [[X1:%.*]], <2 x i64> [[X2:%.*]], i8 [[X4:%.*]]) #[[ATTR0]] {8848; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 88849; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 88850; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 88851; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 88852; CHECK-NEXT: call void @llvm.donothing()8853; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP1]] to i1288854; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 08855; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i64> [[TMP2]] to i1288856; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP6]], 08857; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]8858; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i64> [[TMP3]] to i1288859; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 08860; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]8861; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 08862; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]8863; CHECK-NEXT: br i1 [[_MSOR5]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]8864; CHECK: [[BB8]]:8865; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]8866; CHECK-NEXT: unreachable8867; CHECK: [[BB9]]:8868; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx512.maskz.fixupimm.pd.128(<2 x double> [[X0]], <2 x double> [[X1]], <2 x i64> [[X2]], i32 5, i8 [[X4]])8869; CHECK-NEXT: [[TMP10:%.*]] = bitcast <2 x i64> [[TMP1]] to i1288870; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i128 [[TMP10]], 08871; CHECK-NEXT: [[TMP11:%.*]] = bitcast <2 x i64> [[TMP2]] to i1288872; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i128 [[TMP11]], 08873; CHECK-NEXT: [[_MSOR8:%.*]] = or i1 [[_MSCMP6]], [[_MSCMP7]]8874; CHECK-NEXT: [[_MSCMP9:%.*]] = icmp ne i8 [[TMP4]], 08875; CHECK-NEXT: [[_MSOR10:%.*]] = or i1 [[_MSOR8]], [[_MSCMP9]]8876; CHECK-NEXT: br i1 [[_MSOR10]], label %[[BB12:.*]], label %[[BB13:.*]], !prof [[PROF1]]8877; CHECK: [[BB12]]:8878; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]8879; CHECK-NEXT: unreachable8880; CHECK: [[BB13]]:8881; CHECK-NEXT: [[RES1:%.*]] = call <2 x double> @llvm.x86.avx512.maskz.fixupimm.pd.128(<2 x double> [[X0]], <2 x double> [[X1]], <2 x i64> zeroinitializer, i32 3, i8 [[X4]])8882; CHECK-NEXT: [[RES3:%.*]] = fadd <2 x double> [[RES]], [[RES1]]8883; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 88884; CHECK-NEXT: ret <2 x double> [[RES3]]8885;8886 %res = call <2 x double> @llvm.x86.avx512.maskz.fixupimm.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x i64> %x2, i32 5, i8 %x4)8887 %res1 = call <2 x double> @llvm.x86.avx512.maskz.fixupimm.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x i64> zeroinitializer, i32 3, i8 %x4)8888 ;%res2 = call <2 x double> @llvm.x86.avx512.maskz.fixupimm.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x i64> %x2, i32 4, i8 -1)8889 %res3 = fadd <2 x double> %res, %res18890 ;%res4 = fadd <2 x double> %res3, %res28891 ret <2 x double> %res38892}8893 8894declare <4 x double> @llvm.x86.avx512.mask.fixupimm.pd.256(<4 x double>, <4 x double>, <4 x i64>, i32, i8)8895 8896define <4 x double>@test_int_x86_avx512_mask_fixupimm_pd_256(<4 x double> %x0, <4 x double> %x1, <4 x i64> %x2, i8 %x4) #0 {8897;8898; CHECK-LABEL: define <4 x double> @test_int_x86_avx512_mask_fixupimm_pd_256(8899; CHECK-SAME: <4 x double> [[X0:%.*]], <4 x double> [[X1:%.*]], <4 x i64> [[X2:%.*]], i8 [[X4:%.*]]) #[[ATTR0]] {8900; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 88901; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 88902; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 88903; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 88904; CHECK-NEXT: call void @llvm.donothing()8905; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i64> [[TMP1]] to i2568906; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP5]], 08907; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i64> [[TMP2]] to i2568908; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP6]], 08909; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]8910; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i64> [[TMP3]] to i2568911; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i256 [[TMP7]], 08912; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]8913; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 08914; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]8915; CHECK-NEXT: br i1 [[_MSOR5]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]8916; CHECK: [[BB8]]:8917; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]8918; CHECK-NEXT: unreachable8919; CHECK: [[BB9]]:8920; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.x86.avx512.mask.fixupimm.pd.256(<4 x double> [[X0]], <4 x double> [[X1]], <4 x i64> [[X2]], i32 4, i8 [[X4]])8921; CHECK-NEXT: [[TMP10:%.*]] = bitcast <4 x i64> [[TMP2]] to i2568922; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i256 [[TMP10]], 08923; CHECK-NEXT: [[TMP11:%.*]] = bitcast <4 x i64> [[TMP3]] to i2568924; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i256 [[TMP11]], 08925; CHECK-NEXT: [[_MSOR8:%.*]] = or i1 [[_MSCMP6]], [[_MSCMP7]]8926; CHECK-NEXT: [[_MSCMP9:%.*]] = icmp ne i8 [[TMP4]], 08927; CHECK-NEXT: [[_MSOR10:%.*]] = or i1 [[_MSOR8]], [[_MSCMP9]]8928; CHECK-NEXT: br i1 [[_MSOR10]], label %[[BB12:.*]], label %[[BB13:.*]], !prof [[PROF1]]8929; CHECK: [[BB12]]:8930; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]8931; CHECK-NEXT: unreachable8932; CHECK: [[BB13]]:8933; CHECK-NEXT: [[RES1:%.*]] = call <4 x double> @llvm.x86.avx512.mask.fixupimm.pd.256(<4 x double> zeroinitializer, <4 x double> [[X1]], <4 x i64> [[X2]], i32 5, i8 [[X4]])8934; CHECK-NEXT: [[TMP14:%.*]] = bitcast <4 x i64> [[TMP1]] to i2568935; CHECK-NEXT: [[_MSCMP11:%.*]] = icmp ne i256 [[TMP14]], 08936; CHECK-NEXT: [[TMP15:%.*]] = bitcast <4 x i64> [[TMP2]] to i2568937; CHECK-NEXT: [[_MSCMP12:%.*]] = icmp ne i256 [[TMP15]], 08938; CHECK-NEXT: [[_MSOR13:%.*]] = or i1 [[_MSCMP11]], [[_MSCMP12]]8939; CHECK-NEXT: [[TMP16:%.*]] = bitcast <4 x i64> [[TMP3]] to i2568940; CHECK-NEXT: [[_MSCMP14:%.*]] = icmp ne i256 [[TMP16]], 08941; CHECK-NEXT: [[_MSOR15:%.*]] = or i1 [[_MSOR13]], [[_MSCMP14]]8942; CHECK-NEXT: br i1 [[_MSOR15]], label %[[BB17:.*]], label %[[BB18:.*]], !prof [[PROF1]]8943; CHECK: [[BB17]]:8944; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]8945; CHECK-NEXT: unreachable8946; CHECK: [[BB18]]:8947; CHECK-NEXT: [[RES2:%.*]] = call <4 x double> @llvm.x86.avx512.mask.fixupimm.pd.256(<4 x double> [[X0]], <4 x double> [[X1]], <4 x i64> [[X2]], i32 3, i8 -1)8948; CHECK-NEXT: [[RES3:%.*]] = fadd <4 x double> [[RES]], [[RES1]]8949; CHECK-NEXT: [[RES4:%.*]] = fadd <4 x double> [[RES3]], [[RES2]]8950; CHECK-NEXT: store <4 x i64> zeroinitializer, ptr @__msan_retval_tls, align 88951; CHECK-NEXT: ret <4 x double> [[RES4]]8952;8953 %res = call <4 x double> @llvm.x86.avx512.mask.fixupimm.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x i64> %x2, i32 4, i8 %x4)8954 %res1 = call <4 x double> @llvm.x86.avx512.mask.fixupimm.pd.256(<4 x double> zeroinitializer, <4 x double> %x1, <4 x i64> %x2 , i32 5, i8 %x4)8955 %res2 = call <4 x double> @llvm.x86.avx512.mask.fixupimm.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x i64> %x2, i32 3, i8 -1)8956 %res3 = fadd <4 x double> %res, %res18957 %res4 = fadd <4 x double> %res3, %res28958 ret <4 x double> %res48959}8960 8961declare <4 x double> @llvm.x86.avx512.maskz.fixupimm.pd.256(<4 x double>, <4 x double>, <4 x i64>, i32, i8)8962 8963define <4 x double>@test_int_x86_avx512_maskz_fixupimm_pd_256(<4 x double> %x0, <4 x double> %x1, <4 x i64> %x2, i8 %x4) #0 {8964;8965; CHECK-LABEL: define <4 x double> @test_int_x86_avx512_maskz_fixupimm_pd_256(8966; CHECK-SAME: <4 x double> [[X0:%.*]], <4 x double> [[X1:%.*]], <4 x i64> [[X2:%.*]], i8 [[X4:%.*]]) #[[ATTR0]] {8967; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 88968; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 88969; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 88970; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 88971; CHECK-NEXT: call void @llvm.donothing()8972; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i64> [[TMP1]] to i2568973; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP5]], 08974; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i64> [[TMP2]] to i2568975; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP6]], 08976; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]8977; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i64> [[TMP3]] to i2568978; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i256 [[TMP7]], 08979; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]8980; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 08981; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]8982; CHECK-NEXT: br i1 [[_MSOR5]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]8983; CHECK: [[BB8]]:8984; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]8985; CHECK-NEXT: unreachable8986; CHECK: [[BB9]]:8987; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.x86.avx512.maskz.fixupimm.pd.256(<4 x double> [[X0]], <4 x double> [[X1]], <4 x i64> [[X2]], i32 5, i8 [[X4]])8988; CHECK-NEXT: [[TMP10:%.*]] = bitcast <4 x i64> [[TMP1]] to i2568989; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i256 [[TMP10]], 08990; CHECK-NEXT: [[TMP11:%.*]] = bitcast <4 x i64> [[TMP2]] to i2568991; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i256 [[TMP11]], 08992; CHECK-NEXT: [[_MSOR8:%.*]] = or i1 [[_MSCMP6]], [[_MSCMP7]]8993; CHECK-NEXT: [[_MSCMP9:%.*]] = icmp ne i8 [[TMP4]], 08994; CHECK-NEXT: [[_MSOR10:%.*]] = or i1 [[_MSOR8]], [[_MSCMP9]]8995; CHECK-NEXT: br i1 [[_MSOR10]], label %[[BB12:.*]], label %[[BB13:.*]], !prof [[PROF1]]8996; CHECK: [[BB12]]:8997; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]8998; CHECK-NEXT: unreachable8999; CHECK: [[BB13]]:9000; CHECK-NEXT: [[RES1:%.*]] = call <4 x double> @llvm.x86.avx512.maskz.fixupimm.pd.256(<4 x double> [[X0]], <4 x double> [[X1]], <4 x i64> zeroinitializer, i32 4, i8 [[X4]])9001; CHECK-NEXT: [[TMP14:%.*]] = bitcast <4 x i64> [[TMP1]] to i2569002; CHECK-NEXT: [[_MSCMP11:%.*]] = icmp ne i256 [[TMP14]], 09003; CHECK-NEXT: [[TMP15:%.*]] = bitcast <4 x i64> [[TMP2]] to i2569004; CHECK-NEXT: [[_MSCMP12:%.*]] = icmp ne i256 [[TMP15]], 09005; CHECK-NEXT: [[_MSOR13:%.*]] = or i1 [[_MSCMP11]], [[_MSCMP12]]9006; CHECK-NEXT: [[TMP16:%.*]] = bitcast <4 x i64> [[TMP3]] to i2569007; CHECK-NEXT: [[_MSCMP14:%.*]] = icmp ne i256 [[TMP16]], 09008; CHECK-NEXT: [[_MSOR15:%.*]] = or i1 [[_MSOR13]], [[_MSCMP14]]9009; CHECK-NEXT: br i1 [[_MSOR15]], label %[[BB17:.*]], label %[[BB18:.*]], !prof [[PROF1]]9010; CHECK: [[BB17]]:9011; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]9012; CHECK-NEXT: unreachable9013; CHECK: [[BB18]]:9014; CHECK-NEXT: [[RES2:%.*]] = call <4 x double> @llvm.x86.avx512.maskz.fixupimm.pd.256(<4 x double> [[X0]], <4 x double> [[X1]], <4 x i64> [[X2]], i32 3, i8 -1)9015; CHECK-NEXT: [[RES3:%.*]] = fadd <4 x double> [[RES]], [[RES1]]9016; CHECK-NEXT: [[RES4:%.*]] = fadd <4 x double> [[RES3]], [[RES2]]9017; CHECK-NEXT: store <4 x i64> zeroinitializer, ptr @__msan_retval_tls, align 89018; CHECK-NEXT: ret <4 x double> [[RES4]]9019;9020 %res = call <4 x double> @llvm.x86.avx512.maskz.fixupimm.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x i64> %x2, i32 5, i8 %x4)9021 %res1 = call <4 x double> @llvm.x86.avx512.maskz.fixupimm.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x i64> zeroinitializer, i32 4, i8 %x4)9022 %res2 = call <4 x double> @llvm.x86.avx512.maskz.fixupimm.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x i64> %x2, i32 3, i8 -1)9023 %res3 = fadd <4 x double> %res, %res19024 %res4 = fadd <4 x double> %res3, %res29025 ret <4 x double> %res49026}9027 9028declare <4 x float> @llvm.x86.avx512.mask.fixupimm.ps.128(<4 x float>, <4 x float>, <4 x i32>, i32, i8)9029 9030define <4 x float>@test_int_x86_avx512_mask_fixupimm_ps_128(<4 x float> %x0, <4 x float> %x1, <4 x i32> %x2, i8 %x4) #0 {9031;9032; CHECK-LABEL: define <4 x float> @test_int_x86_avx512_mask_fixupimm_ps_128(9033; CHECK-SAME: <4 x float> [[X0:%.*]], <4 x float> [[X1:%.*]], <4 x i32> [[X2:%.*]], i8 [[X4:%.*]]) #[[ATTR0]] {9034; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 89035; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 89036; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 89037; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 89038; CHECK-NEXT: call void @llvm.donothing()9039; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP1]] to i1289040; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 09041; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i32> [[TMP2]] to i1289042; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP6]], 09043; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]9044; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i32> [[TMP3]] to i1289045; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 09046; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]9047; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 09048; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]9049; CHECK-NEXT: br i1 [[_MSOR5]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]9050; CHECK: [[BB8]]:9051; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]9052; CHECK-NEXT: unreachable9053; CHECK: [[BB9]]:9054; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.mask.fixupimm.ps.128(<4 x float> [[X0]], <4 x float> [[X1]], <4 x i32> [[X2]], i32 5, i8 [[X4]])9055; CHECK-NEXT: [[TMP10:%.*]] = bitcast <4 x i32> [[TMP1]] to i1289056; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i128 [[TMP10]], 09057; CHECK-NEXT: [[TMP11:%.*]] = bitcast <4 x i32> [[TMP2]] to i1289058; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i128 [[TMP11]], 09059; CHECK-NEXT: [[_MSOR8:%.*]] = or i1 [[_MSCMP6]], [[_MSCMP7]]9060; CHECK-NEXT: [[_MSCMP9:%.*]] = icmp ne i8 [[TMP4]], 09061; CHECK-NEXT: [[_MSOR10:%.*]] = or i1 [[_MSOR8]], [[_MSCMP9]]9062; CHECK-NEXT: br i1 [[_MSOR10]], label %[[BB12:.*]], label %[[BB13:.*]], !prof [[PROF1]]9063; CHECK: [[BB12]]:9064; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]9065; CHECK-NEXT: unreachable9066; CHECK: [[BB13]]:9067; CHECK-NEXT: [[RES1:%.*]] = call <4 x float> @llvm.x86.avx512.mask.fixupimm.ps.128(<4 x float> [[X0]], <4 x float> [[X1]], <4 x i32> zeroinitializer, i32 6, i8 [[X4]])9068; CHECK-NEXT: [[TMP14:%.*]] = bitcast <4 x i32> [[TMP1]] to i1289069; CHECK-NEXT: [[_MSCMP11:%.*]] = icmp ne i128 [[TMP14]], 09070; CHECK-NEXT: [[TMP15:%.*]] = bitcast <4 x i32> [[TMP2]] to i1289071; CHECK-NEXT: [[_MSCMP12:%.*]] = icmp ne i128 [[TMP15]], 09072; CHECK-NEXT: [[_MSOR13:%.*]] = or i1 [[_MSCMP11]], [[_MSCMP12]]9073; CHECK-NEXT: [[TMP16:%.*]] = bitcast <4 x i32> [[TMP3]] to i1289074; CHECK-NEXT: [[_MSCMP14:%.*]] = icmp ne i128 [[TMP16]], 09075; CHECK-NEXT: [[_MSOR15:%.*]] = or i1 [[_MSOR13]], [[_MSCMP14]]9076; CHECK-NEXT: br i1 [[_MSOR15]], label %[[BB17:.*]], label %[[BB18:.*]], !prof [[PROF1]]9077; CHECK: [[BB17]]:9078; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]9079; CHECK-NEXT: unreachable9080; CHECK: [[BB18]]:9081; CHECK-NEXT: [[RES2:%.*]] = call <4 x float> @llvm.x86.avx512.mask.fixupimm.ps.128(<4 x float> [[X0]], <4 x float> [[X1]], <4 x i32> [[X2]], i32 7, i8 -1)9082; CHECK-NEXT: [[RES3:%.*]] = fadd <4 x float> [[RES]], [[RES1]]9083; CHECK-NEXT: [[RES4:%.*]] = fadd <4 x float> [[RES3]], [[RES2]]9084; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 89085; CHECK-NEXT: ret <4 x float> [[RES4]]9086;9087 %res = call <4 x float> @llvm.x86.avx512.mask.fixupimm.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x i32> %x2, i32 5, i8 %x4)9088 %res1 = call <4 x float> @llvm.x86.avx512.mask.fixupimm.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x i32> zeroinitializer, i32 6, i8 %x4)9089 %res2 = call <4 x float> @llvm.x86.avx512.mask.fixupimm.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x i32> %x2, i32 7, i8 -1)9090 %res3 = fadd <4 x float> %res, %res19091 %res4 = fadd <4 x float> %res3, %res29092 ret <4 x float> %res49093}9094 9095declare <4 x float> @llvm.x86.avx512.maskz.fixupimm.ps.128(<4 x float>, <4 x float>, <4 x i32>, i32, i8)9096 9097define <4 x float>@test_int_x86_avx512_maskz_fixupimm_ps_128(<4 x float> %x0, <4 x float> %x1, <4 x i32> %x2, i8 %x4) #0 {9098;9099; CHECK-LABEL: define <4 x float> @test_int_x86_avx512_maskz_fixupimm_ps_128(9100; CHECK-SAME: <4 x float> [[X0:%.*]], <4 x float> [[X1:%.*]], <4 x i32> [[X2:%.*]], i8 [[X4:%.*]]) #[[ATTR0]] {9101; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 89102; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 89103; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 89104; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 89105; CHECK-NEXT: call void @llvm.donothing()9106; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP1]] to i1289107; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 09108; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i32> [[TMP2]] to i1289109; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP6]], 09110; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]9111; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i32> [[TMP3]] to i1289112; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 09113; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]9114; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 09115; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]9116; CHECK-NEXT: br i1 [[_MSOR5]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]9117; CHECK: [[BB8]]:9118; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]9119; CHECK-NEXT: unreachable9120; CHECK: [[BB9]]:9121; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx512.maskz.fixupimm.ps.128(<4 x float> [[X0]], <4 x float> [[X1]], <4 x i32> [[X2]], i32 5, i8 [[X4]])9122; CHECK-NEXT: [[TMP10:%.*]] = bitcast <4 x i32> [[TMP1]] to i1289123; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i128 [[TMP10]], 09124; CHECK-NEXT: [[TMP11:%.*]] = bitcast <4 x i32> [[TMP2]] to i1289125; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i128 [[TMP11]], 09126; CHECK-NEXT: [[_MSOR8:%.*]] = or i1 [[_MSCMP6]], [[_MSCMP7]]9127; CHECK-NEXT: [[_MSCMP9:%.*]] = icmp ne i8 [[TMP4]], 09128; CHECK-NEXT: [[_MSOR10:%.*]] = or i1 [[_MSOR8]], [[_MSCMP9]]9129; CHECK-NEXT: br i1 [[_MSOR10]], label %[[BB12:.*]], label %[[BB13:.*]], !prof [[PROF1]]9130; CHECK: [[BB12]]:9131; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]9132; CHECK-NEXT: unreachable9133; CHECK: [[BB13]]:9134; CHECK-NEXT: [[RES1:%.*]] = call <4 x float> @llvm.x86.avx512.maskz.fixupimm.ps.128(<4 x float> [[X0]], <4 x float> [[X1]], <4 x i32> zeroinitializer, i32 6, i8 [[X4]])9135; CHECK-NEXT: [[TMP14:%.*]] = bitcast <4 x i32> [[TMP1]] to i1289136; CHECK-NEXT: [[_MSCMP11:%.*]] = icmp ne i128 [[TMP14]], 09137; CHECK-NEXT: [[TMP15:%.*]] = bitcast <4 x i32> [[TMP2]] to i1289138; CHECK-NEXT: [[_MSCMP12:%.*]] = icmp ne i128 [[TMP15]], 09139; CHECK-NEXT: [[_MSOR13:%.*]] = or i1 [[_MSCMP11]], [[_MSCMP12]]9140; CHECK-NEXT: [[TMP16:%.*]] = bitcast <4 x i32> [[TMP3]] to i1289141; CHECK-NEXT: [[_MSCMP14:%.*]] = icmp ne i128 [[TMP16]], 09142; CHECK-NEXT: [[_MSOR15:%.*]] = or i1 [[_MSOR13]], [[_MSCMP14]]9143; CHECK-NEXT: br i1 [[_MSOR15]], label %[[BB17:.*]], label %[[BB18:.*]], !prof [[PROF1]]9144; CHECK: [[BB17]]:9145; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]9146; CHECK-NEXT: unreachable9147; CHECK: [[BB18]]:9148; CHECK-NEXT: [[RES2:%.*]] = call <4 x float> @llvm.x86.avx512.maskz.fixupimm.ps.128(<4 x float> [[X0]], <4 x float> [[X1]], <4 x i32> [[X2]], i32 7, i8 -1)9149; CHECK-NEXT: [[RES3:%.*]] = fadd <4 x float> [[RES]], [[RES1]]9150; CHECK-NEXT: [[RES4:%.*]] = fadd <4 x float> [[RES3]], [[RES2]]9151; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 89152; CHECK-NEXT: ret <4 x float> [[RES4]]9153;9154 %res = call <4 x float> @llvm.x86.avx512.maskz.fixupimm.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x i32> %x2, i32 5, i8 %x4)9155 %res1 = call <4 x float> @llvm.x86.avx512.maskz.fixupimm.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x i32> zeroinitializer, i32 6, i8 %x4)9156 %res2 = call <4 x float> @llvm.x86.avx512.maskz.fixupimm.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x i32> %x2, i32 7, i8 -1)9157 %res3 = fadd <4 x float> %res, %res19158 %res4 = fadd <4 x float> %res3, %res29159 ret <4 x float> %res49160}9161 9162declare <8 x float> @llvm.x86.avx512.mask.fixupimm.ps.256(<8 x float>, <8 x float>, <8 x i32>, i32, i8)9163 9164define <8 x float>@test_int_x86_avx512_mask_fixupimm_ps_256(<8 x float> %x0, <8 x float> %x1, <8 x i32> %x2, i8 %x4) #0 {9165;9166; CHECK-LABEL: define <8 x float> @test_int_x86_avx512_mask_fixupimm_ps_256(9167; CHECK-SAME: <8 x float> [[X0:%.*]], <8 x float> [[X1:%.*]], <8 x i32> [[X2:%.*]], i8 [[X4:%.*]]) #[[ATTR0]] {9168; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 89169; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 89170; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 89171; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 89172; CHECK-NEXT: call void @llvm.donothing()9173; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i32> [[TMP1]] to i2569174; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP5]], 09175; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i32> [[TMP2]] to i2569176; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP6]], 09177; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]9178; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i32> [[TMP3]] to i2569179; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i256 [[TMP7]], 09180; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]9181; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 09182; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]9183; CHECK-NEXT: br i1 [[_MSOR5]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]9184; CHECK: [[BB8]]:9185; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]9186; CHECK-NEXT: unreachable9187; CHECK: [[BB9]]:9188; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx512.mask.fixupimm.ps.256(<8 x float> [[X0]], <8 x float> [[X1]], <8 x i32> [[X2]], i32 5, i8 [[X4]])9189; CHECK-NEXT: [[TMP10:%.*]] = bitcast <8 x i32> [[TMP1]] to i2569190; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i256 [[TMP10]], 09191; CHECK-NEXT: [[TMP11:%.*]] = bitcast <8 x i32> [[TMP2]] to i2569192; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i256 [[TMP11]], 09193; CHECK-NEXT: [[_MSOR8:%.*]] = or i1 [[_MSCMP6]], [[_MSCMP7]]9194; CHECK-NEXT: [[_MSCMP9:%.*]] = icmp ne i8 [[TMP4]], 09195; CHECK-NEXT: [[_MSOR10:%.*]] = or i1 [[_MSOR8]], [[_MSCMP9]]9196; CHECK-NEXT: br i1 [[_MSOR10]], label %[[BB12:.*]], label %[[BB13:.*]], !prof [[PROF1]]9197; CHECK: [[BB12]]:9198; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]9199; CHECK-NEXT: unreachable9200; CHECK: [[BB13]]:9201; CHECK-NEXT: [[RES1:%.*]] = call <8 x float> @llvm.x86.avx512.mask.fixupimm.ps.256(<8 x float> [[X0]], <8 x float> [[X1]], <8 x i32> zeroinitializer, i32 6, i8 [[X4]])9202; CHECK-NEXT: [[TMP14:%.*]] = bitcast <8 x i32> [[TMP1]] to i2569203; CHECK-NEXT: [[_MSCMP11:%.*]] = icmp ne i256 [[TMP14]], 09204; CHECK-NEXT: [[TMP15:%.*]] = bitcast <8 x i32> [[TMP2]] to i2569205; CHECK-NEXT: [[_MSCMP12:%.*]] = icmp ne i256 [[TMP15]], 09206; CHECK-NEXT: [[_MSOR13:%.*]] = or i1 [[_MSCMP11]], [[_MSCMP12]]9207; CHECK-NEXT: [[TMP16:%.*]] = bitcast <8 x i32> [[TMP3]] to i2569208; CHECK-NEXT: [[_MSCMP14:%.*]] = icmp ne i256 [[TMP16]], 09209; CHECK-NEXT: [[_MSOR15:%.*]] = or i1 [[_MSOR13]], [[_MSCMP14]]9210; CHECK-NEXT: br i1 [[_MSOR15]], label %[[BB17:.*]], label %[[BB18:.*]], !prof [[PROF1]]9211; CHECK: [[BB17]]:9212; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]9213; CHECK-NEXT: unreachable9214; CHECK: [[BB18]]:9215; CHECK-NEXT: [[RES2:%.*]] = call <8 x float> @llvm.x86.avx512.mask.fixupimm.ps.256(<8 x float> [[X0]], <8 x float> [[X1]], <8 x i32> [[X2]], i32 7, i8 -1)9216; CHECK-NEXT: [[RES3:%.*]] = fadd <8 x float> [[RES]], [[RES1]]9217; CHECK-NEXT: [[RES4:%.*]] = fadd <8 x float> [[RES3]], [[RES2]]9218; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 89219; CHECK-NEXT: ret <8 x float> [[RES4]]9220;9221 %res = call <8 x float> @llvm.x86.avx512.mask.fixupimm.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x i32> %x2, i32 5, i8 %x4)9222 %res1 = call <8 x float> @llvm.x86.avx512.mask.fixupimm.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x i32> zeroinitializer, i32 6, i8 %x4)9223 %res2 = call <8 x float> @llvm.x86.avx512.mask.fixupimm.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x i32> %x2, i32 7, i8 -1)9224 %res3 = fadd <8 x float> %res, %res19225 %res4 = fadd <8 x float> %res3, %res29226 ret <8 x float> %res49227}9228 9229declare <8 x float> @llvm.x86.avx512.maskz.fixupimm.ps.256(<8 x float>, <8 x float>, <8 x i32>, i32, i8)9230 9231define <8 x float>@test_int_x86_avx512_maskz_fixupimm_ps_256(<8 x float> %x0, <8 x float> %x1, <8 x i32> %x2, i8 %x4) #0 {9232;9233; CHECK-LABEL: define <8 x float> @test_int_x86_avx512_maskz_fixupimm_ps_256(9234; CHECK-SAME: <8 x float> [[X0:%.*]], <8 x float> [[X1:%.*]], <8 x i32> [[X2:%.*]], i8 [[X4:%.*]]) #[[ATTR0]] {9235; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 89236; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 89237; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 89238; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 89239; CHECK-NEXT: call void @llvm.donothing()9240; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i32> [[TMP1]] to i2569241; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP5]], 09242; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i32> [[TMP2]] to i2569243; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP6]], 09244; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]9245; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i32> [[TMP3]] to i2569246; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i256 [[TMP7]], 09247; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]9248; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i8 [[TMP4]], 09249; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]]9250; CHECK-NEXT: br i1 [[_MSOR5]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]9251; CHECK: [[BB8]]:9252; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]9253; CHECK-NEXT: unreachable9254; CHECK: [[BB9]]:9255; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx512.maskz.fixupimm.ps.256(<8 x float> [[X0]], <8 x float> [[X1]], <8 x i32> [[X2]], i32 5, i8 [[X4]])9256; CHECK-NEXT: [[TMP10:%.*]] = bitcast <8 x i32> [[TMP1]] to i2569257; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i256 [[TMP10]], 09258; CHECK-NEXT: [[TMP11:%.*]] = bitcast <8 x i32> [[TMP2]] to i2569259; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i256 [[TMP11]], 09260; CHECK-NEXT: [[_MSOR8:%.*]] = or i1 [[_MSCMP6]], [[_MSCMP7]]9261; CHECK-NEXT: [[_MSCMP9:%.*]] = icmp ne i8 [[TMP4]], 09262; CHECK-NEXT: [[_MSOR10:%.*]] = or i1 [[_MSOR8]], [[_MSCMP9]]9263; CHECK-NEXT: br i1 [[_MSOR10]], label %[[BB12:.*]], label %[[BB13:.*]], !prof [[PROF1]]9264; CHECK: [[BB12]]:9265; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]9266; CHECK-NEXT: unreachable9267; CHECK: [[BB13]]:9268; CHECK-NEXT: [[RES1:%.*]] = call <8 x float> @llvm.x86.avx512.maskz.fixupimm.ps.256(<8 x float> [[X0]], <8 x float> [[X1]], <8 x i32> zeroinitializer, i32 6, i8 [[X4]])9269; CHECK-NEXT: [[TMP14:%.*]] = bitcast <8 x i32> [[TMP1]] to i2569270; CHECK-NEXT: [[_MSCMP11:%.*]] = icmp ne i256 [[TMP14]], 09271; CHECK-NEXT: [[TMP15:%.*]] = bitcast <8 x i32> [[TMP2]] to i2569272; CHECK-NEXT: [[_MSCMP12:%.*]] = icmp ne i256 [[TMP15]], 09273; CHECK-NEXT: [[_MSOR13:%.*]] = or i1 [[_MSCMP11]], [[_MSCMP12]]9274; CHECK-NEXT: [[TMP16:%.*]] = bitcast <8 x i32> [[TMP3]] to i2569275; CHECK-NEXT: [[_MSCMP14:%.*]] = icmp ne i256 [[TMP16]], 09276; CHECK-NEXT: [[_MSOR15:%.*]] = or i1 [[_MSOR13]], [[_MSCMP14]]9277; CHECK-NEXT: br i1 [[_MSOR15]], label %[[BB17:.*]], label %[[BB18:.*]], !prof [[PROF1]]9278; CHECK: [[BB17]]:9279; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]9280; CHECK-NEXT: unreachable9281; CHECK: [[BB18]]:9282; CHECK-NEXT: [[RES2:%.*]] = call <8 x float> @llvm.x86.avx512.maskz.fixupimm.ps.256(<8 x float> [[X0]], <8 x float> [[X1]], <8 x i32> [[X2]], i32 7, i8 -1)9283; CHECK-NEXT: [[RES3:%.*]] = fadd <8 x float> [[RES]], [[RES1]]9284; CHECK-NEXT: [[RES4:%.*]] = fadd <8 x float> [[RES3]], [[RES2]]9285; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 89286; CHECK-NEXT: ret <8 x float> [[RES4]]9287;9288 %res = call <8 x float> @llvm.x86.avx512.maskz.fixupimm.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x i32> %x2, i32 5, i8 %x4)9289 %res1 = call <8 x float> @llvm.x86.avx512.maskz.fixupimm.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x i32> zeroinitializer, i32 6, i8 %x4)9290 %res2 = call <8 x float> @llvm.x86.avx512.maskz.fixupimm.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x i32> %x2, i32 7, i8 -1)9291 %res3 = fadd <8 x float> %res, %res19292 %res4 = fadd <8 x float> %res3, %res29293 ret <8 x float> %res49294}9295 9296define <2 x i64> @test_x86_avx512_psra_q_128(<2 x i64> %a0, <2 x i64> %a1) #0 {9297; CHECK-LABEL: define <2 x i64> @test_x86_avx512_psra_q_128(9298; CHECK-SAME: <2 x i64> [[A0:%.*]], <2 x i64> [[A1:%.*]]) #[[ATTR0]] {9299; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 89300; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 89301; CHECK-NEXT: call void @llvm.donothing()9302; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP2]] to i1289303; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i649304; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 09305; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i1289306; CHECK-NEXT: [[TMP7:%.*]] = bitcast i128 [[TMP6]] to <2 x i64>9307; CHECK-NEXT: [[TMP8:%.*]] = call <2 x i64> @llvm.x86.avx512.psra.q.128(<2 x i64> [[TMP1]], <2 x i64> [[A1]])9308; CHECK-NEXT: [[TMP9:%.*]] = or <2 x i64> [[TMP8]], [[TMP7]]9309; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.avx512.psra.q.128(<2 x i64> [[A0]], <2 x i64> [[A1]])9310; CHECK-NEXT: store <2 x i64> [[TMP9]], ptr @__msan_retval_tls, align 89311; CHECK-NEXT: ret <2 x i64> [[RES]]9312;9313 %res = call <2 x i64> @llvm.x86.avx512.psra.q.128(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1]9314 ret <2 x i64> %res9315}9316define <2 x i64> @test_x86_avx512_mask_psra_q_128(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> %passthru, i8 %mask, i8 %mask2) #0 {9317;9318; CHECK-LABEL: define <2 x i64> @test_x86_avx512_mask_psra_q_128(9319; CHECK-SAME: <2 x i64> [[A0:%.*]], <2 x i64> [[A1:%.*]], <2 x i64> [[PASSTHRU:%.*]], i8 [[MASK:%.*]], i8 [[MASK2:%.*]]) #[[ATTR0]] {9320; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 89321; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 89322; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 89323; CHECK-NEXT: [[TMP16:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 56), align 89324; CHECK-NEXT: [[TMP5:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 89325; CHECK-NEXT: call void @llvm.donothing()9326; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i64> [[TMP2]] to i1289327; CHECK-NEXT: [[TMP7:%.*]] = trunc i128 [[TMP6]] to i649328; CHECK-NEXT: [[TMP8:%.*]] = icmp ne i64 [[TMP7]], 09329; CHECK-NEXT: [[TMP9:%.*]] = sext i1 [[TMP8]] to i1289330; CHECK-NEXT: [[TMP10:%.*]] = bitcast i128 [[TMP9]] to <2 x i64>9331; CHECK-NEXT: [[TMP11:%.*]] = call <2 x i64> @llvm.x86.avx512.psra.q.128(<2 x i64> [[TMP1]], <2 x i64> [[A1]])9332; CHECK-NEXT: [[TMP12:%.*]] = or <2 x i64> [[TMP11]], [[TMP10]]9333; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.avx512.psra.q.128(<2 x i64> [[A0]], <2 x i64> [[A1]])9334; CHECK-NEXT: [[TMP13:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>9335; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i8 [[MASK]] to <8 x i1>9336; CHECK-NEXT: [[TMP14:%.*]] = bitcast i8 [[TMP16]] to <8 x i1>9337; CHECK-NEXT: [[MASK2_CAST:%.*]] = bitcast i8 [[MASK2]] to <8 x i1>9338; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP13]], <8 x i1> [[TMP14]], <2 x i32> <i32 0, i32 1>9339; CHECK-NEXT: [[MASK_EXTRACT:%.*]] = shufflevector <8 x i1> [[MASK_CAST]], <8 x i1> [[MASK2_CAST]], <2 x i32> <i32 0, i32 1>9340; CHECK-NEXT: [[TMP15:%.*]] = select <2 x i1> [[MASK_EXTRACT]], <2 x i64> [[TMP12]], <2 x i64> [[TMP5]]9341; CHECK-NEXT: [[TMP4:%.*]] = xor <2 x i64> [[RES]], [[PASSTHRU]]9342; CHECK-NEXT: [[TMP17:%.*]] = or <2 x i64> [[TMP4]], [[TMP12]]9343; CHECK-NEXT: [[TMP18:%.*]] = or <2 x i64> [[TMP17]], [[TMP5]]9344; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <2 x i1> [[_MSPROP]], <2 x i64> [[TMP18]], <2 x i64> [[TMP15]]9345; CHECK-NEXT: [[RES2:%.*]] = select <2 x i1> [[MASK_EXTRACT]], <2 x i64> [[RES]], <2 x i64> [[PASSTHRU]]9346; CHECK-NEXT: store <2 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 89347; CHECK-NEXT: ret <2 x i64> [[RES2]]9348;9349 %res = call <2 x i64> @llvm.x86.avx512.psra.q.128(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1]9350 %mask.cast = bitcast i8 %mask to <8 x i1>9351 %mask2.cast = bitcast i8 %mask2 to <8 x i1>9352 %mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> %mask2.cast, <2 x i32> <i32 0, i32 1>9353 %res2 = select <2 x i1> %mask.extract, <2 x i64> %res, <2 x i64> %passthru9354 ret <2 x i64> %res29355}9356define <2 x i64> @test_x86_avx512_maskz_psra_q_128(<2 x i64> %a0, <2 x i64> %a1, i8 %mask, i8 %mask2) #0 {9357;9358; CHECK-LABEL: define <2 x i64> @test_x86_avx512_maskz_psra_q_128(9359; CHECK-SAME: <2 x i64> [[A0:%.*]], <2 x i64> [[A1:%.*]], i8 [[MASK:%.*]], i8 [[MASK2:%.*]]) #[[ATTR0]] {9360; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 89361; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 89362; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 89363; CHECK-NEXT: [[TMP15:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 89364; CHECK-NEXT: call void @llvm.donothing()9365; CHECK-NEXT: [[TMP16:%.*]] = bitcast <2 x i64> [[TMP2]] to i1289366; CHECK-NEXT: [[TMP17:%.*]] = trunc i128 [[TMP16]] to i649367; CHECK-NEXT: [[TMP7:%.*]] = icmp ne i64 [[TMP17]], 09368; CHECK-NEXT: [[TMP8:%.*]] = sext i1 [[TMP7]] to i1289369; CHECK-NEXT: [[TMP9:%.*]] = bitcast i128 [[TMP8]] to <2 x i64>9370; CHECK-NEXT: [[TMP10:%.*]] = call <2 x i64> @llvm.x86.avx512.psra.q.128(<2 x i64> [[TMP1]], <2 x i64> [[A1]])9371; CHECK-NEXT: [[TMP11:%.*]] = or <2 x i64> [[TMP10]], [[TMP9]]9372; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.avx512.psra.q.128(<2 x i64> [[A0]], <2 x i64> [[A1]])9373; CHECK-NEXT: [[TMP12:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>9374; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i8 [[MASK]] to <8 x i1>9375; CHECK-NEXT: [[TMP13:%.*]] = bitcast i8 [[TMP15]] to <8 x i1>9376; CHECK-NEXT: [[MASK2_CAST:%.*]] = bitcast i8 [[MASK2]] to <8 x i1>9377; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP12]], <8 x i1> [[TMP13]], <2 x i32> <i32 0, i32 1>9378; CHECK-NEXT: [[MASK_EXTRACT:%.*]] = shufflevector <8 x i1> [[MASK_CAST]], <8 x i1> [[MASK2_CAST]], <2 x i32> <i32 0, i32 1>9379; CHECK-NEXT: [[TMP14:%.*]] = select <2 x i1> [[MASK_EXTRACT]], <2 x i64> [[TMP11]], <2 x i64> zeroinitializer9380; CHECK-NEXT: [[TMP4:%.*]] = xor <2 x i64> [[RES]], zeroinitializer9381; CHECK-NEXT: [[TMP5:%.*]] = or <2 x i64> [[TMP4]], [[TMP11]]9382; CHECK-NEXT: [[TMP6:%.*]] = or <2 x i64> [[TMP5]], zeroinitializer9383; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <2 x i1> [[_MSPROP]], <2 x i64> [[TMP6]], <2 x i64> [[TMP14]]9384; CHECK-NEXT: [[RES2:%.*]] = select <2 x i1> [[MASK_EXTRACT]], <2 x i64> [[RES]], <2 x i64> zeroinitializer9385; CHECK-NEXT: store <2 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 89386; CHECK-NEXT: ret <2 x i64> [[RES2]]9387;9388 %res = call <2 x i64> @llvm.x86.avx512.psra.q.128(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1]9389 %mask.cast = bitcast i8 %mask to <8 x i1>9390 %mask2.cast = bitcast i8 %mask2 to <8 x i1>9391 %mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> %mask2.cast, <2 x i32> <i32 0, i32 1>9392 %res2 = select <2 x i1> %mask.extract, <2 x i64> %res, <2 x i64> zeroinitializer9393 ret <2 x i64> %res29394}9395declare <2 x i64> @llvm.x86.avx512.psra.q.128(<2 x i64>, <2 x i64>) nounwind readnone9396 9397 9398define <4 x i64> @test_x86_avx512_psra_q_256(<4 x i64> %a0, <2 x i64> %a1) #0 {9399; CHECK-LABEL: define <4 x i64> @test_x86_avx512_psra_q_256(9400; CHECK-SAME: <4 x i64> [[A0:%.*]], <2 x i64> [[A1:%.*]]) #[[ATTR0]] {9401; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 89402; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 89403; CHECK-NEXT: call void @llvm.donothing()9404; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP2]] to i1289405; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i649406; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 09407; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i2569408; CHECK-NEXT: [[TMP7:%.*]] = bitcast i256 [[TMP6]] to <4 x i64>9409; CHECK-NEXT: [[TMP8:%.*]] = call <4 x i64> @llvm.x86.avx512.psra.q.256(<4 x i64> [[TMP1]], <2 x i64> [[A1]])9410; CHECK-NEXT: [[TMP9:%.*]] = or <4 x i64> [[TMP8]], [[TMP7]]9411; CHECK-NEXT: [[RES:%.*]] = call <4 x i64> @llvm.x86.avx512.psra.q.256(<4 x i64> [[A0]], <2 x i64> [[A1]])9412; CHECK-NEXT: store <4 x i64> [[TMP9]], ptr @__msan_retval_tls, align 89413; CHECK-NEXT: ret <4 x i64> [[RES]]9414;9415 %res = call <4 x i64> @llvm.x86.avx512.psra.q.256(<4 x i64> %a0, <2 x i64> %a1) ; <<4 x i64>> [#uses=1]9416 ret <4 x i64> %res9417}9418define <4 x i64> @test_x86_avx512_mask_psra_q_256(<4 x i64> %a0, <2 x i64> %a1, <4 x i64> %passthru, i8 %mask, i8 %mask2) #0 {9419;9420; CHECK-LABEL: define <4 x i64> @test_x86_avx512_mask_psra_q_256(9421; CHECK-SAME: <4 x i64> [[A0:%.*]], <2 x i64> [[A1:%.*]], <4 x i64> [[PASSTHRU:%.*]], i8 [[MASK:%.*]], i8 [[MASK2:%.*]]) #[[ATTR0]] {9422; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 89423; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 89424; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 80), align 89425; CHECK-NEXT: [[TMP16:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 88), align 89426; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 89427; CHECK-NEXT: call void @llvm.donothing()9428; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i64> [[TMP2]] to i1289429; CHECK-NEXT: [[TMP7:%.*]] = trunc i128 [[TMP6]] to i649430; CHECK-NEXT: [[TMP8:%.*]] = icmp ne i64 [[TMP7]], 09431; CHECK-NEXT: [[TMP9:%.*]] = sext i1 [[TMP8]] to i2569432; CHECK-NEXT: [[TMP10:%.*]] = bitcast i256 [[TMP9]] to <4 x i64>9433; CHECK-NEXT: [[TMP11:%.*]] = call <4 x i64> @llvm.x86.avx512.psra.q.256(<4 x i64> [[TMP1]], <2 x i64> [[A1]])9434; CHECK-NEXT: [[TMP12:%.*]] = or <4 x i64> [[TMP11]], [[TMP10]]9435; CHECK-NEXT: [[RES:%.*]] = call <4 x i64> @llvm.x86.avx512.psra.q.256(<4 x i64> [[A0]], <2 x i64> [[A1]])9436; CHECK-NEXT: [[TMP13:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>9437; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i8 [[MASK]] to <8 x i1>9438; CHECK-NEXT: [[TMP14:%.*]] = bitcast i8 [[TMP16]] to <8 x i1>9439; CHECK-NEXT: [[MASK2_CAST:%.*]] = bitcast i8 [[MASK2]] to <8 x i1>9440; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP13]], <8 x i1> [[TMP14]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>9441; CHECK-NEXT: [[MASK_EXTRACT:%.*]] = shufflevector <8 x i1> [[MASK_CAST]], <8 x i1> [[MASK2_CAST]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>9442; CHECK-NEXT: [[TMP15:%.*]] = select <4 x i1> [[MASK_EXTRACT]], <4 x i64> [[TMP12]], <4 x i64> [[TMP5]]9443; CHECK-NEXT: [[TMP4:%.*]] = xor <4 x i64> [[RES]], [[PASSTHRU]]9444; CHECK-NEXT: [[TMP17:%.*]] = or <4 x i64> [[TMP4]], [[TMP12]]9445; CHECK-NEXT: [[TMP18:%.*]] = or <4 x i64> [[TMP17]], [[TMP5]]9446; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP]], <4 x i64> [[TMP18]], <4 x i64> [[TMP15]]9447; CHECK-NEXT: [[RES2:%.*]] = select <4 x i1> [[MASK_EXTRACT]], <4 x i64> [[RES]], <4 x i64> [[PASSTHRU]]9448; CHECK-NEXT: store <4 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 89449; CHECK-NEXT: ret <4 x i64> [[RES2]]9450;9451 %res = call <4 x i64> @llvm.x86.avx512.psra.q.256(<4 x i64> %a0, <2 x i64> %a1) ; <<4 x i64>> [#uses=1]9452 %mask.cast = bitcast i8 %mask to <8 x i1>9453 %mask2.cast = bitcast i8 %mask2 to <8 x i1>9454 %mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> %mask2.cast, <4 x i32> <i32 0, i32 1, i32 2, i32 3>9455 %res2 = select <4 x i1> %mask.extract, <4 x i64> %res, <4 x i64> %passthru9456 ret <4 x i64> %res29457}9458define <4 x i64> @test_x86_avx512_maskz_psra_q_256(<4 x i64> %a0, <2 x i64> %a1, <4 x i64> %passthru, i8 %mask, i8 %mask2) #0 {9459;9460; CHECK-LABEL: define <4 x i64> @test_x86_avx512_maskz_psra_q_256(9461; CHECK-SAME: <4 x i64> [[A0:%.*]], <2 x i64> [[A1:%.*]], <4 x i64> [[PASSTHRU:%.*]], i8 [[MASK:%.*]], i8 [[MASK2:%.*]]) #[[ATTR0]] {9462; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 89463; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 89464; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 80), align 89465; CHECK-NEXT: [[TMP15:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 88), align 89466; CHECK-NEXT: call void @llvm.donothing()9467; CHECK-NEXT: [[TMP16:%.*]] = bitcast <2 x i64> [[TMP2]] to i1289468; CHECK-NEXT: [[TMP17:%.*]] = trunc i128 [[TMP16]] to i649469; CHECK-NEXT: [[TMP7:%.*]] = icmp ne i64 [[TMP17]], 09470; CHECK-NEXT: [[TMP8:%.*]] = sext i1 [[TMP7]] to i2569471; CHECK-NEXT: [[TMP9:%.*]] = bitcast i256 [[TMP8]] to <4 x i64>9472; CHECK-NEXT: [[TMP10:%.*]] = call <4 x i64> @llvm.x86.avx512.psra.q.256(<4 x i64> [[TMP1]], <2 x i64> [[A1]])9473; CHECK-NEXT: [[TMP11:%.*]] = or <4 x i64> [[TMP10]], [[TMP9]]9474; CHECK-NEXT: [[RES:%.*]] = call <4 x i64> @llvm.x86.avx512.psra.q.256(<4 x i64> [[A0]], <2 x i64> [[A1]])9475; CHECK-NEXT: [[TMP12:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>9476; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i8 [[MASK]] to <8 x i1>9477; CHECK-NEXT: [[TMP13:%.*]] = bitcast i8 [[TMP15]] to <8 x i1>9478; CHECK-NEXT: [[MASK2_CAST:%.*]] = bitcast i8 [[MASK2]] to <8 x i1>9479; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP12]], <8 x i1> [[TMP13]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>9480; CHECK-NEXT: [[MASK_EXTRACT:%.*]] = shufflevector <8 x i1> [[MASK_CAST]], <8 x i1> [[MASK2_CAST]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>9481; CHECK-NEXT: [[TMP14:%.*]] = select <4 x i1> [[MASK_EXTRACT]], <4 x i64> [[TMP11]], <4 x i64> zeroinitializer9482; CHECK-NEXT: [[TMP4:%.*]] = xor <4 x i64> [[RES]], zeroinitializer9483; CHECK-NEXT: [[TMP5:%.*]] = or <4 x i64> [[TMP4]], [[TMP11]]9484; CHECK-NEXT: [[TMP6:%.*]] = or <4 x i64> [[TMP5]], zeroinitializer9485; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP]], <4 x i64> [[TMP6]], <4 x i64> [[TMP14]]9486; CHECK-NEXT: [[RES2:%.*]] = select <4 x i1> [[MASK_EXTRACT]], <4 x i64> [[RES]], <4 x i64> zeroinitializer9487; CHECK-NEXT: store <4 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 89488; CHECK-NEXT: ret <4 x i64> [[RES2]]9489;9490 %res = call <4 x i64> @llvm.x86.avx512.psra.q.256(<4 x i64> %a0, <2 x i64> %a1) ; <<4 x i64>> [#uses=1]9491 %mask.cast = bitcast i8 %mask to <8 x i1>9492 %mask2.cast = bitcast i8 %mask2 to <8 x i1>9493 %mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> %mask2.cast, <4 x i32> <i32 0, i32 1, i32 2, i32 3>9494 %res2 = select <4 x i1> %mask.extract, <4 x i64> %res, <4 x i64> zeroinitializer9495 ret <4 x i64> %res29496}9497declare <4 x i64> @llvm.x86.avx512.psra.q.256(<4 x i64>, <2 x i64>) nounwind readnone9498 9499 9500define <2 x i64> @test_x86_avx512_psrai_q_128(<2 x i64> %a0) #0 {9501; CHECK-LABEL: define <2 x i64> @test_x86_avx512_psrai_q_128(9502; CHECK-SAME: <2 x i64> [[A0:%.*]]) #[[ATTR0]] {9503; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 89504; CHECK-NEXT: call void @llvm.donothing()9505; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i64> @llvm.x86.avx512.psrai.q.128(<2 x i64> [[TMP3]], i32 7)9506; CHECK-NEXT: [[TMP2:%.*]] = or <2 x i64> [[TMP1]], zeroinitializer9507; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.avx512.psrai.q.128(<2 x i64> [[A0]], i32 7)9508; CHECK-NEXT: store <2 x i64> [[TMP2]], ptr @__msan_retval_tls, align 89509; CHECK-NEXT: ret <2 x i64> [[RES]]9510;9511 %res = call <2 x i64> @llvm.x86.avx512.psrai.q.128(<2 x i64> %a0, i32 7) ; <<2 x i64>> [#uses=1]9512 ret <2 x i64> %res9513}9514define <2 x i64> @test_x86_avx512_mask_psrai_q_128(<2 x i64> %a0, <2 x i64> %passthru, i8 %mask, i8 %mask2) #0 {9515;9516; CHECK-LABEL: define <2 x i64> @test_x86_avx512_mask_psrai_q_128(9517; CHECK-SAME: <2 x i64> [[A0:%.*]], <2 x i64> [[PASSTHRU:%.*]], i8 [[MASK:%.*]], i8 [[MASK2:%.*]]) #[[ATTR0]] {9518; CHECK-NEXT: [[TMP5:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 89519; CHECK-NEXT: [[TMP6:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 89520; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 89521; CHECK-NEXT: [[TMP10:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 89522; CHECK-NEXT: call void @llvm.donothing()9523; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i64> @llvm.x86.avx512.psrai.q.128(<2 x i64> [[TMP5]], i32 7)9524; CHECK-NEXT: [[TMP2:%.*]] = or <2 x i64> [[TMP1]], zeroinitializer9525; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.avx512.psrai.q.128(<2 x i64> [[A0]], i32 7)9526; CHECK-NEXT: [[TMP7:%.*]] = bitcast i8 [[TMP6]] to <8 x i1>9527; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i8 [[MASK]] to <8 x i1>9528; CHECK-NEXT: [[TMP8:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>9529; CHECK-NEXT: [[MASK2_CAST:%.*]] = bitcast i8 [[MASK2]] to <8 x i1>9530; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP7]], <8 x i1> [[TMP8]], <2 x i32> <i32 0, i32 1>9531; CHECK-NEXT: [[MASK_EXTRACT:%.*]] = shufflevector <8 x i1> [[MASK_CAST]], <8 x i1> [[MASK2_CAST]], <2 x i32> <i32 0, i32 1>9532; CHECK-NEXT: [[TMP9:%.*]] = select <2 x i1> [[MASK_EXTRACT]], <2 x i64> [[TMP2]], <2 x i64> [[TMP10]]9533; CHECK-NEXT: [[TMP4:%.*]] = xor <2 x i64> [[RES]], [[PASSTHRU]]9534; CHECK-NEXT: [[TMP11:%.*]] = or <2 x i64> [[TMP4]], [[TMP2]]9535; CHECK-NEXT: [[TMP12:%.*]] = or <2 x i64> [[TMP11]], [[TMP10]]9536; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <2 x i1> [[_MSPROP]], <2 x i64> [[TMP12]], <2 x i64> [[TMP9]]9537; CHECK-NEXT: [[RES2:%.*]] = select <2 x i1> [[MASK_EXTRACT]], <2 x i64> [[RES]], <2 x i64> [[PASSTHRU]]9538; CHECK-NEXT: store <2 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 89539; CHECK-NEXT: ret <2 x i64> [[RES2]]9540;9541 %res = call <2 x i64> @llvm.x86.avx512.psrai.q.128(<2 x i64> %a0, i32 7) ; <<2 x i64>> [#uses=1]9542 %mask.cast = bitcast i8 %mask to <8 x i1>9543 %mask2.cast = bitcast i8 %mask2 to <8 x i1>9544 %mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> %mask2.cast, <2 x i32> <i32 0, i32 1>9545 %res2 = select <2 x i1> %mask.extract, <2 x i64> %res, <2 x i64> %passthru9546 ret <2 x i64> %res29547}9548define <2 x i64> @test_x86_avx512_maskz_psrai_q_128(<2 x i64> %a0, i8 %mask, i8 %mask2) #0 {9549;9550; CHECK-LABEL: define <2 x i64> @test_x86_avx512_maskz_psrai_q_128(9551; CHECK-SAME: <2 x i64> [[A0:%.*]], i8 [[MASK:%.*]], i8 [[MASK2:%.*]]) #[[ATTR0]] {9552; CHECK-NEXT: [[TMP9:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 89553; CHECK-NEXT: [[TMP10:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 89554; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 89555; CHECK-NEXT: call void @llvm.donothing()9556; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i64> @llvm.x86.avx512.psrai.q.128(<2 x i64> [[TMP9]], i32 7)9557; CHECK-NEXT: [[TMP2:%.*]] = or <2 x i64> [[TMP1]], zeroinitializer9558; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.avx512.psrai.q.128(<2 x i64> [[A0]], i32 7)9559; CHECK-NEXT: [[TMP11:%.*]] = bitcast i8 [[TMP10]] to <8 x i1>9560; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i8 [[MASK]] to <8 x i1>9561; CHECK-NEXT: [[TMP7:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>9562; CHECK-NEXT: [[MASK2_CAST:%.*]] = bitcast i8 [[MASK2]] to <8 x i1>9563; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP11]], <8 x i1> [[TMP7]], <2 x i32> <i32 0, i32 1>9564; CHECK-NEXT: [[MASK_EXTRACT:%.*]] = shufflevector <8 x i1> [[MASK_CAST]], <8 x i1> [[MASK2_CAST]], <2 x i32> <i32 0, i32 1>9565; CHECK-NEXT: [[TMP8:%.*]] = select <2 x i1> [[MASK_EXTRACT]], <2 x i64> [[TMP2]], <2 x i64> zeroinitializer9566; CHECK-NEXT: [[TMP4:%.*]] = xor <2 x i64> [[RES]], zeroinitializer9567; CHECK-NEXT: [[TMP5:%.*]] = or <2 x i64> [[TMP4]], [[TMP2]]9568; CHECK-NEXT: [[TMP6:%.*]] = or <2 x i64> [[TMP5]], zeroinitializer9569; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <2 x i1> [[_MSPROP]], <2 x i64> [[TMP6]], <2 x i64> [[TMP8]]9570; CHECK-NEXT: [[RES2:%.*]] = select <2 x i1> [[MASK_EXTRACT]], <2 x i64> [[RES]], <2 x i64> zeroinitializer9571; CHECK-NEXT: store <2 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 89572; CHECK-NEXT: ret <2 x i64> [[RES2]]9573;9574 %res = call <2 x i64> @llvm.x86.avx512.psrai.q.128(<2 x i64> %a0, i32 7) ; <<2 x i64>> [#uses=1]9575 %mask.cast = bitcast i8 %mask to <8 x i1>9576 %mask2.cast = bitcast i8 %mask2 to <8 x i1>9577 %mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> %mask2.cast, <2 x i32> <i32 0, i32 1>9578 %res2 = select <2 x i1> %mask.extract, <2 x i64> %res, <2 x i64> zeroinitializer9579 ret <2 x i64> %res29580}9581declare <2 x i64> @llvm.x86.avx512.psrai.q.128(<2 x i64>, i32) nounwind readnone9582 9583 9584define <4 x i64> @test_x86_avx512_psrai_q_256(<4 x i64> %a0) #0 {9585; CHECK-LABEL: define <4 x i64> @test_x86_avx512_psrai_q_256(9586; CHECK-SAME: <4 x i64> [[A0:%.*]]) #[[ATTR0]] {9587; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 89588; CHECK-NEXT: call void @llvm.donothing()9589; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i64> @llvm.x86.avx512.psrai.q.256(<4 x i64> [[TMP3]], i32 7)9590; CHECK-NEXT: [[TMP2:%.*]] = or <4 x i64> [[TMP1]], zeroinitializer9591; CHECK-NEXT: [[RES:%.*]] = call <4 x i64> @llvm.x86.avx512.psrai.q.256(<4 x i64> [[A0]], i32 7)9592; CHECK-NEXT: store <4 x i64> [[TMP2]], ptr @__msan_retval_tls, align 89593; CHECK-NEXT: ret <4 x i64> [[RES]]9594;9595 %res = call <4 x i64> @llvm.x86.avx512.psrai.q.256(<4 x i64> %a0, i32 7) ; <<4 x i64>> [#uses=1]9596 ret <4 x i64> %res9597}9598define <4 x i64> @test_x86_avx512_mask_psrai_q_256(<4 x i64> %a0, <4 x i64> %passthru, i8 %mask, i8 %mask2) #0 {9599;9600; CHECK-LABEL: define <4 x i64> @test_x86_avx512_mask_psrai_q_256(9601; CHECK-SAME: <4 x i64> [[A0:%.*]], <4 x i64> [[PASSTHRU:%.*]], i8 [[MASK:%.*]], i8 [[MASK2:%.*]]) #[[ATTR0]] {9602; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 89603; CHECK-NEXT: [[TMP6:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 89604; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 72), align 89605; CHECK-NEXT: [[TMP10:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 89606; CHECK-NEXT: call void @llvm.donothing()9607; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i64> @llvm.x86.avx512.psrai.q.256(<4 x i64> [[TMP5]], i32 7)9608; CHECK-NEXT: [[TMP2:%.*]] = or <4 x i64> [[TMP1]], zeroinitializer9609; CHECK-NEXT: [[RES:%.*]] = call <4 x i64> @llvm.x86.avx512.psrai.q.256(<4 x i64> [[A0]], i32 7)9610; CHECK-NEXT: [[TMP7:%.*]] = bitcast i8 [[TMP6]] to <8 x i1>9611; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i8 [[MASK]] to <8 x i1>9612; CHECK-NEXT: [[TMP8:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>9613; CHECK-NEXT: [[MASK2_CAST:%.*]] = bitcast i8 [[MASK2]] to <8 x i1>9614; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP7]], <8 x i1> [[TMP8]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>9615; CHECK-NEXT: [[MASK_EXTRACT:%.*]] = shufflevector <8 x i1> [[MASK_CAST]], <8 x i1> [[MASK2_CAST]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>9616; CHECK-NEXT: [[TMP9:%.*]] = select <4 x i1> [[MASK_EXTRACT]], <4 x i64> [[TMP2]], <4 x i64> [[TMP10]]9617; CHECK-NEXT: [[TMP4:%.*]] = xor <4 x i64> [[RES]], [[PASSTHRU]]9618; CHECK-NEXT: [[TMP11:%.*]] = or <4 x i64> [[TMP4]], [[TMP2]]9619; CHECK-NEXT: [[TMP12:%.*]] = or <4 x i64> [[TMP11]], [[TMP10]]9620; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP]], <4 x i64> [[TMP12]], <4 x i64> [[TMP9]]9621; CHECK-NEXT: [[RES2:%.*]] = select <4 x i1> [[MASK_EXTRACT]], <4 x i64> [[RES]], <4 x i64> [[PASSTHRU]]9622; CHECK-NEXT: store <4 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 89623; CHECK-NEXT: ret <4 x i64> [[RES2]]9624;9625 %res = call <4 x i64> @llvm.x86.avx512.psrai.q.256(<4 x i64> %a0, i32 7) ; <<4 x i64>> [#uses=1]9626 %mask.cast = bitcast i8 %mask to <8 x i1>9627 %mask2.cast = bitcast i8 %mask2 to <8 x i1>9628 %mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> %mask2.cast, <4 x i32> <i32 0, i32 1, i32 2, i32 3>9629 %res2 = select <4 x i1> %mask.extract, <4 x i64> %res, <4 x i64> %passthru9630 ret <4 x i64> %res29631}9632define <4 x i64> @test_x86_avx512_maskz_psrai_q_256(<4 x i64> %a0, i8 %mask, i8 %mask2) #0 {9633;9634; CHECK-LABEL: define <4 x i64> @test_x86_avx512_maskz_psrai_q_256(9635; CHECK-SAME: <4 x i64> [[A0:%.*]], i8 [[MASK:%.*]], i8 [[MASK2:%.*]]) #[[ATTR0]] {9636; CHECK-NEXT: [[TMP9:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 89637; CHECK-NEXT: [[TMP10:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 89638; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 89639; CHECK-NEXT: call void @llvm.donothing()9640; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i64> @llvm.x86.avx512.psrai.q.256(<4 x i64> [[TMP9]], i32 7)9641; CHECK-NEXT: [[TMP2:%.*]] = or <4 x i64> [[TMP1]], zeroinitializer9642; CHECK-NEXT: [[RES:%.*]] = call <4 x i64> @llvm.x86.avx512.psrai.q.256(<4 x i64> [[A0]], i32 7)9643; CHECK-NEXT: [[TMP11:%.*]] = bitcast i8 [[TMP10]] to <8 x i1>9644; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i8 [[MASK]] to <8 x i1>9645; CHECK-NEXT: [[TMP7:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>9646; CHECK-NEXT: [[MASK2_CAST:%.*]] = bitcast i8 [[MASK2]] to <8 x i1>9647; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP11]], <8 x i1> [[TMP7]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>9648; CHECK-NEXT: [[MASK_EXTRACT:%.*]] = shufflevector <8 x i1> [[MASK_CAST]], <8 x i1> [[MASK2_CAST]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>9649; CHECK-NEXT: [[TMP8:%.*]] = select <4 x i1> [[MASK_EXTRACT]], <4 x i64> [[TMP2]], <4 x i64> zeroinitializer9650; CHECK-NEXT: [[TMP4:%.*]] = xor <4 x i64> [[RES]], zeroinitializer9651; CHECK-NEXT: [[TMP5:%.*]] = or <4 x i64> [[TMP4]], [[TMP2]]9652; CHECK-NEXT: [[TMP6:%.*]] = or <4 x i64> [[TMP5]], zeroinitializer9653; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP]], <4 x i64> [[TMP6]], <4 x i64> [[TMP8]]9654; CHECK-NEXT: [[RES2:%.*]] = select <4 x i1> [[MASK_EXTRACT]], <4 x i64> [[RES]], <4 x i64> zeroinitializer9655; CHECK-NEXT: store <4 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 89656; CHECK-NEXT: ret <4 x i64> [[RES2]]9657;9658 %res = call <4 x i64> @llvm.x86.avx512.psrai.q.256(<4 x i64> %a0, i32 7) ; <<4 x i64>> [#uses=1]9659 %mask.cast = bitcast i8 %mask to <8 x i1>9660 %mask2.cast = bitcast i8 %mask2 to <8 x i1>9661 %mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> %mask2.cast, <4 x i32> <i32 0, i32 1, i32 2, i32 3>9662 %res2 = select <4 x i1> %mask.extract, <4 x i64> %res, <4 x i64> zeroinitializer9663 ret <4 x i64> %res29664}9665declare <4 x i64> @llvm.x86.avx512.psrai.q.256(<4 x i64>, i32) nounwind readnone9666 9667define <2 x i64> @test_x86_avx512_psrav_q_128(<2 x i64> %a0, <2 x i64> %a1) #0 {9668; CHECK-LABEL: define <2 x i64> @test_x86_avx512_psrav_q_128(9669; CHECK-SAME: <2 x i64> [[A0:%.*]], <2 x i64> [[A1:%.*]]) #[[ATTR0]] {9670; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 89671; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 89672; CHECK-NEXT: call void @llvm.donothing()9673; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <2 x i64> [[TMP2]], zeroinitializer9674; CHECK-NEXT: [[TMP4:%.*]] = sext <2 x i1> [[TMP3]] to <2 x i64>9675; CHECK-NEXT: [[TMP5:%.*]] = call <2 x i64> @llvm.x86.avx512.psrav.q.128(<2 x i64> [[TMP1]], <2 x i64> [[A1]])9676; CHECK-NEXT: [[TMP6:%.*]] = or <2 x i64> [[TMP5]], [[TMP4]]9677; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.avx512.psrav.q.128(<2 x i64> [[A0]], <2 x i64> [[A1]])9678; CHECK-NEXT: store <2 x i64> [[TMP6]], ptr @__msan_retval_tls, align 89679; CHECK-NEXT: ret <2 x i64> [[RES]]9680;9681 %res = call <2 x i64> @llvm.x86.avx512.psrav.q.128(<2 x i64> %a0, <2 x i64> %a1)9682 ret <2 x i64> %res9683}9684 9685define <2 x i64> @test_x86_avx512_mask_psrav_q_128(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> %a2, i8 %mask, i8 %mask2) #0 {9686;9687; CHECK-LABEL: define <2 x i64> @test_x86_avx512_mask_psrav_q_128(9688; CHECK-SAME: <2 x i64> [[A0:%.*]], <2 x i64> [[A1:%.*]], <2 x i64> [[A2:%.*]], i8 [[MASK:%.*]], i8 [[MASK2:%.*]]) #[[ATTR0]] {9689; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 89690; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 89691; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 89692; CHECK-NEXT: [[TMP13:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 56), align 89693; CHECK-NEXT: [[TMP5:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 89694; CHECK-NEXT: call void @llvm.donothing()9695; CHECK-NEXT: [[TMP6:%.*]] = icmp ne <2 x i64> [[TMP2]], zeroinitializer9696; CHECK-NEXT: [[TMP7:%.*]] = sext <2 x i1> [[TMP6]] to <2 x i64>9697; CHECK-NEXT: [[TMP8:%.*]] = call <2 x i64> @llvm.x86.avx512.psrav.q.128(<2 x i64> [[TMP1]], <2 x i64> [[A1]])9698; CHECK-NEXT: [[TMP9:%.*]] = or <2 x i64> [[TMP8]], [[TMP7]]9699; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.avx512.psrav.q.128(<2 x i64> [[A0]], <2 x i64> [[A1]])9700; CHECK-NEXT: [[TMP10:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>9701; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i8 [[MASK]] to <8 x i1>9702; CHECK-NEXT: [[TMP11:%.*]] = bitcast i8 [[TMP13]] to <8 x i1>9703; CHECK-NEXT: [[MASK2_CAST:%.*]] = bitcast i8 [[MASK2]] to <8 x i1>9704; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP10]], <8 x i1> [[TMP11]], <2 x i32> <i32 0, i32 1>9705; CHECK-NEXT: [[MASK_EXTRACT:%.*]] = shufflevector <8 x i1> [[MASK_CAST]], <8 x i1> [[MASK2_CAST]], <2 x i32> <i32 0, i32 1>9706; CHECK-NEXT: [[TMP12:%.*]] = select <2 x i1> [[MASK_EXTRACT]], <2 x i64> [[TMP9]], <2 x i64> [[TMP5]]9707; CHECK-NEXT: [[TMP4:%.*]] = xor <2 x i64> [[RES]], [[A2]]9708; CHECK-NEXT: [[TMP14:%.*]] = or <2 x i64> [[TMP4]], [[TMP9]]9709; CHECK-NEXT: [[TMP15:%.*]] = or <2 x i64> [[TMP14]], [[TMP5]]9710; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <2 x i1> [[_MSPROP]], <2 x i64> [[TMP15]], <2 x i64> [[TMP12]]9711; CHECK-NEXT: [[RES2:%.*]] = select <2 x i1> [[MASK_EXTRACT]], <2 x i64> [[RES]], <2 x i64> [[A2]]9712; CHECK-NEXT: store <2 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 89713; CHECK-NEXT: ret <2 x i64> [[RES2]]9714;9715 %res = call <2 x i64> @llvm.x86.avx512.psrav.q.128(<2 x i64> %a0, <2 x i64> %a1)9716 %mask.cast = bitcast i8 %mask to <8 x i1>9717 %mask2.cast = bitcast i8 %mask2 to <8 x i1>9718 %mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> %mask2.cast, <2 x i32> <i32 0, i32 1>9719 %res2 = select <2 x i1> %mask.extract, <2 x i64> %res, <2 x i64> %a29720 ret <2 x i64> %res29721}9722 9723define <2 x i64> @test_x86_avx512_maskz_psrav_q_128(<2 x i64> %a0, <2 x i64> %a1, i8 %mask, i8 %mask2) #0 {9724;9725; CHECK-LABEL: define <2 x i64> @test_x86_avx512_maskz_psrav_q_128(9726; CHECK-SAME: <2 x i64> [[A0:%.*]], <2 x i64> [[A1:%.*]], i8 [[MASK:%.*]], i8 [[MASK2:%.*]]) #[[ATTR0]] {9727; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 89728; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 89729; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 89730; CHECK-NEXT: [[TMP12:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 89731; CHECK-NEXT: call void @llvm.donothing()9732; CHECK-NEXT: [[TMP13:%.*]] = icmp ne <2 x i64> [[TMP2]], zeroinitializer9733; CHECK-NEXT: [[TMP14:%.*]] = sext <2 x i1> [[TMP13]] to <2 x i64>9734; CHECK-NEXT: [[TMP7:%.*]] = call <2 x i64> @llvm.x86.avx512.psrav.q.128(<2 x i64> [[TMP1]], <2 x i64> [[A1]])9735; CHECK-NEXT: [[TMP8:%.*]] = or <2 x i64> [[TMP7]], [[TMP14]]9736; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.avx512.psrav.q.128(<2 x i64> [[A0]], <2 x i64> [[A1]])9737; CHECK-NEXT: [[TMP9:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>9738; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i8 [[MASK]] to <8 x i1>9739; CHECK-NEXT: [[TMP10:%.*]] = bitcast i8 [[TMP12]] to <8 x i1>9740; CHECK-NEXT: [[MASK2_CAST:%.*]] = bitcast i8 [[MASK2]] to <8 x i1>9741; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP9]], <8 x i1> [[TMP10]], <2 x i32> <i32 0, i32 1>9742; CHECK-NEXT: [[MASK_EXTRACT:%.*]] = shufflevector <8 x i1> [[MASK_CAST]], <8 x i1> [[MASK2_CAST]], <2 x i32> <i32 0, i32 1>9743; CHECK-NEXT: [[TMP11:%.*]] = select <2 x i1> [[MASK_EXTRACT]], <2 x i64> [[TMP8]], <2 x i64> zeroinitializer9744; CHECK-NEXT: [[TMP4:%.*]] = xor <2 x i64> [[RES]], zeroinitializer9745; CHECK-NEXT: [[TMP5:%.*]] = or <2 x i64> [[TMP4]], [[TMP8]]9746; CHECK-NEXT: [[TMP6:%.*]] = or <2 x i64> [[TMP5]], zeroinitializer9747; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <2 x i1> [[_MSPROP]], <2 x i64> [[TMP6]], <2 x i64> [[TMP11]]9748; CHECK-NEXT: [[RES2:%.*]] = select <2 x i1> [[MASK_EXTRACT]], <2 x i64> [[RES]], <2 x i64> zeroinitializer9749; CHECK-NEXT: store <2 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 89750; CHECK-NEXT: ret <2 x i64> [[RES2]]9751;9752 %res = call <2 x i64> @llvm.x86.avx512.psrav.q.128(<2 x i64> %a0, <2 x i64> %a1)9753 %mask.cast = bitcast i8 %mask to <8 x i1>9754 %mask2.cast = bitcast i8 %mask2 to <8 x i1>9755 %mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> %mask2.cast, <2 x i32> <i32 0, i32 1>9756 %res2 = select <2 x i1> %mask.extract, <2 x i64> %res, <2 x i64> zeroinitializer9757 ret <2 x i64> %res29758}9759 9760declare <2 x i64> @llvm.x86.avx512.psrav.q.128(<2 x i64>, <2 x i64>) nounwind readnone9761 9762define <4 x i64> @test_x86_avx512_psrav_q_256(<4 x i64> %a0, <4 x i64> %a1) #0 {9763; CHECK-LABEL: define <4 x i64> @test_x86_avx512_psrav_q_256(9764; CHECK-SAME: <4 x i64> [[A0:%.*]], <4 x i64> [[A1:%.*]]) #[[ATTR0]] {9765; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 89766; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 89767; CHECK-NEXT: call void @llvm.donothing()9768; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <4 x i64> [[TMP2]], zeroinitializer9769; CHECK-NEXT: [[TMP4:%.*]] = sext <4 x i1> [[TMP3]] to <4 x i64>9770; CHECK-NEXT: [[TMP5:%.*]] = call <4 x i64> @llvm.x86.avx512.psrav.q.256(<4 x i64> [[TMP1]], <4 x i64> [[A1]])9771; CHECK-NEXT: [[TMP6:%.*]] = or <4 x i64> [[TMP5]], [[TMP4]]9772; CHECK-NEXT: [[RES:%.*]] = call <4 x i64> @llvm.x86.avx512.psrav.q.256(<4 x i64> [[A0]], <4 x i64> [[A1]])9773; CHECK-NEXT: store <4 x i64> [[TMP6]], ptr @__msan_retval_tls, align 89774; CHECK-NEXT: ret <4 x i64> [[RES]]9775;9776 %res = call <4 x i64> @llvm.x86.avx512.psrav.q.256(<4 x i64> %a0, <4 x i64> %a1)9777 ret <4 x i64> %res9778}9779 9780define <4 x i64> @test_x86_avx512_mask_psrav_q_256(<4 x i64> %a0, <4 x i64> %a1, <4 x i64> %a2, i8 %mask, i8 %mask2) #0 {9781;9782; CHECK-LABEL: define <4 x i64> @test_x86_avx512_mask_psrav_q_256(9783; CHECK-SAME: <4 x i64> [[A0:%.*]], <4 x i64> [[A1:%.*]], <4 x i64> [[A2:%.*]], i8 [[MASK:%.*]], i8 [[MASK2:%.*]]) #[[ATTR0]] {9784; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 89785; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 89786; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 89787; CHECK-NEXT: [[TMP13:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 104), align 89788; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 89789; CHECK-NEXT: call void @llvm.donothing()9790; CHECK-NEXT: [[TMP6:%.*]] = icmp ne <4 x i64> [[TMP2]], zeroinitializer9791; CHECK-NEXT: [[TMP7:%.*]] = sext <4 x i1> [[TMP6]] to <4 x i64>9792; CHECK-NEXT: [[TMP8:%.*]] = call <4 x i64> @llvm.x86.avx512.psrav.q.256(<4 x i64> [[TMP1]], <4 x i64> [[A1]])9793; CHECK-NEXT: [[TMP9:%.*]] = or <4 x i64> [[TMP8]], [[TMP7]]9794; CHECK-NEXT: [[RES:%.*]] = call <4 x i64> @llvm.x86.avx512.psrav.q.256(<4 x i64> [[A0]], <4 x i64> [[A1]])9795; CHECK-NEXT: [[TMP10:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>9796; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i8 [[MASK]] to <8 x i1>9797; CHECK-NEXT: [[TMP11:%.*]] = bitcast i8 [[TMP13]] to <8 x i1>9798; CHECK-NEXT: [[MASK2_CAST:%.*]] = bitcast i8 [[MASK2]] to <8 x i1>9799; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP10]], <8 x i1> [[TMP11]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>9800; CHECK-NEXT: [[MASK_EXTRACT:%.*]] = shufflevector <8 x i1> [[MASK_CAST]], <8 x i1> [[MASK2_CAST]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>9801; CHECK-NEXT: [[TMP12:%.*]] = select <4 x i1> [[MASK_EXTRACT]], <4 x i64> [[TMP9]], <4 x i64> [[TMP5]]9802; CHECK-NEXT: [[TMP4:%.*]] = xor <4 x i64> [[RES]], [[A2]]9803; CHECK-NEXT: [[TMP14:%.*]] = or <4 x i64> [[TMP4]], [[TMP9]]9804; CHECK-NEXT: [[TMP15:%.*]] = or <4 x i64> [[TMP14]], [[TMP5]]9805; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP]], <4 x i64> [[TMP15]], <4 x i64> [[TMP12]]9806; CHECK-NEXT: [[RES2:%.*]] = select <4 x i1> [[MASK_EXTRACT]], <4 x i64> [[RES]], <4 x i64> [[A2]]9807; CHECK-NEXT: store <4 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 89808; CHECK-NEXT: ret <4 x i64> [[RES2]]9809;9810 %res = call <4 x i64> @llvm.x86.avx512.psrav.q.256(<4 x i64> %a0, <4 x i64> %a1)9811 %mask.cast = bitcast i8 %mask to <8 x i1>9812 %mask2.cast = bitcast i8 %mask2 to <8 x i1>9813 %mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> %mask2.cast , <4 x i32> <i32 0, i32 1, i32 2, i32 3>9814 %res2 = select <4 x i1> %mask.extract, <4 x i64> %res, <4 x i64> %a29815 ret <4 x i64> %res29816}9817 9818define <4 x i64> @test_x86_avx512_maskz_psrav_q_256(<4 x i64> %a0, <4 x i64> %a1, i8 %mask, i8 %mask2) #0 {9819;9820; CHECK-LABEL: define <4 x i64> @test_x86_avx512_maskz_psrav_q_256(9821; CHECK-SAME: <4 x i64> [[A0:%.*]], <4 x i64> [[A1:%.*]], i8 [[MASK:%.*]], i8 [[MASK2:%.*]]) #[[ATTR0]] {9822; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 89823; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 89824; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 89825; CHECK-NEXT: [[TMP12:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 72), align 89826; CHECK-NEXT: call void @llvm.donothing()9827; CHECK-NEXT: [[TMP13:%.*]] = icmp ne <4 x i64> [[TMP2]], zeroinitializer9828; CHECK-NEXT: [[TMP14:%.*]] = sext <4 x i1> [[TMP13]] to <4 x i64>9829; CHECK-NEXT: [[TMP7:%.*]] = call <4 x i64> @llvm.x86.avx512.psrav.q.256(<4 x i64> [[TMP1]], <4 x i64> [[A1]])9830; CHECK-NEXT: [[TMP8:%.*]] = or <4 x i64> [[TMP7]], [[TMP14]]9831; CHECK-NEXT: [[RES:%.*]] = call <4 x i64> @llvm.x86.avx512.psrav.q.256(<4 x i64> [[A0]], <4 x i64> [[A1]])9832; CHECK-NEXT: [[TMP9:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>9833; CHECK-NEXT: [[MASK_CAST:%.*]] = bitcast i8 [[MASK]] to <8 x i1>9834; CHECK-NEXT: [[TMP10:%.*]] = bitcast i8 [[TMP12]] to <8 x i1>9835; CHECK-NEXT: [[MASK2_CAST:%.*]] = bitcast i8 [[MASK2]] to <8 x i1>9836; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP9]], <8 x i1> [[TMP10]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>9837; CHECK-NEXT: [[MASK_EXTRACT:%.*]] = shufflevector <8 x i1> [[MASK_CAST]], <8 x i1> [[MASK2_CAST]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>9838; CHECK-NEXT: [[TMP11:%.*]] = select <4 x i1> [[MASK_EXTRACT]], <4 x i64> [[TMP8]], <4 x i64> zeroinitializer9839; CHECK-NEXT: [[TMP4:%.*]] = xor <4 x i64> [[RES]], zeroinitializer9840; CHECK-NEXT: [[TMP5:%.*]] = or <4 x i64> [[TMP4]], [[TMP8]]9841; CHECK-NEXT: [[TMP6:%.*]] = or <4 x i64> [[TMP5]], zeroinitializer9842; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP]], <4 x i64> [[TMP6]], <4 x i64> [[TMP11]]9843; CHECK-NEXT: [[RES2:%.*]] = select <4 x i1> [[MASK_EXTRACT]], <4 x i64> [[RES]], <4 x i64> zeroinitializer9844; CHECK-NEXT: store <4 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 89845; CHECK-NEXT: ret <4 x i64> [[RES2]]9846;9847 %res = call <4 x i64> @llvm.x86.avx512.psrav.q.256(<4 x i64> %a0, <4 x i64> %a1)9848 %mask.cast = bitcast i8 %mask to <8 x i1>9849 %mask2.cast = bitcast i8 %mask2 to <8 x i1>9850 %mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> %mask2.cast , <4 x i32> <i32 0, i32 1, i32 2, i32 3>9851 %res2 = select <4 x i1> %mask.extract, <4 x i64> %res, <4 x i64> zeroinitializer9852 ret <4 x i64> %res29853}9854 9855declare <4 x i64> @llvm.x86.avx512.psrav.q.256(<4 x i64>, <4 x i64>) nounwind readnone9856 9857define <8 x float> @test_vfmadd256_ps(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2) #0 {9858; CHECK-LABEL: define <8 x float> @test_vfmadd256_ps(9859; CHECK-SAME: <8 x float> [[A0:%.*]], <8 x float> [[A1:%.*]], <8 x float> [[A2:%.*]]) #[[ATTR0]] {9860; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 89861; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 89862; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 89863; CHECK-NEXT: call void @llvm.donothing()9864; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> [[TMP4]], [[TMP2]]9865; CHECK-NEXT: [[_MSPROP1:%.*]] = or <8 x i32> [[_MSPROP]], [[TMP3]]9866; CHECK-NEXT: [[TMP1:%.*]] = call <8 x float> @llvm.fma.v8f32(<8 x float> [[A0]], <8 x float> [[A1]], <8 x float> [[A2]])9867; CHECK-NEXT: store <8 x i32> [[_MSPROP1]], ptr @__msan_retval_tls, align 89868; CHECK-NEXT: ret <8 x float> [[TMP1]]9869;9870 %1 = call <8 x float> @llvm.fma.v8f32(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2)9871 ret <8 x float> %19872}9873 9874define <8 x float> @test_mask_vfmadd256_ps(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2, i8 %mask) #0 {9875;9876; CHECK-LABEL: define <8 x float> @test_mask_vfmadd256_ps(9877; CHECK-SAME: <8 x float> [[A0:%.*]], <8 x float> [[A1:%.*]], <8 x float> [[A2:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {9878; CHECK-NEXT: [[TMP7:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 89879; CHECK-NEXT: [[TMP10:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 89880; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 89881; CHECK-NEXT: [[TMP11:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 89882; CHECK-NEXT: call void @llvm.donothing()9883; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> [[TMP7]], [[TMP10]]9884; CHECK-NEXT: [[_MSPROP1:%.*]] = or <8 x i32> [[_MSPROP]], [[TMP3]]9885; CHECK-NEXT: [[TMP1:%.*]] = call <8 x float> @llvm.fma.v8f32(<8 x float> [[A0]], <8 x float> [[A1]], <8 x float> [[A2]])9886; CHECK-NEXT: [[TMP14:%.*]] = bitcast i8 [[TMP11]] to <8 x i1>9887; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[MASK]] to <8 x i1>9888; CHECK-NEXT: [[TMP8:%.*]] = select <8 x i1> [[TMP2]], <8 x i32> [[_MSPROP1]], <8 x i32> [[TMP7]]9889; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x float> [[TMP1]] to <8 x i32>9890; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x float> [[A0]] to <8 x i32>9891; CHECK-NEXT: [[TMP6:%.*]] = xor <8 x i32> [[TMP4]], [[TMP5]]9892; CHECK-NEXT: [[TMP12:%.*]] = or <8 x i32> [[TMP6]], [[_MSPROP1]]9893; CHECK-NEXT: [[TMP13:%.*]] = or <8 x i32> [[TMP12]], [[TMP7]]9894; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP14]], <8 x i32> [[TMP13]], <8 x i32> [[TMP8]]9895; CHECK-NEXT: [[TMP9:%.*]] = select <8 x i1> [[TMP2]], <8 x float> [[TMP1]], <8 x float> [[A0]]9896; CHECK-NEXT: store <8 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 89897; CHECK-NEXT: ret <8 x float> [[TMP9]]9898;9899 %1 = call <8 x float> @llvm.fma.v8f32(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2)9900 %2 = bitcast i8 %mask to <8 x i1>9901 %3 = select <8 x i1> %2, <8 x float> %1, <8 x float> %a09902 ret <8 x float> %39903}9904 9905define <4 x float> @test_vfmadd128_ps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) #0 {9906; CHECK-LABEL: define <4 x float> @test_vfmadd128_ps(9907; CHECK-SAME: <4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], <4 x float> [[A2:%.*]]) #[[ATTR0]] {9908; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 89909; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 89910; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 89911; CHECK-NEXT: call void @llvm.donothing()9912; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP4]], [[TMP2]]9913; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i32> [[_MSPROP]], [[TMP3]]9914; CHECK-NEXT: [[TMP1:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[A0]], <4 x float> [[A1]], <4 x float> [[A2]])9915; CHECK-NEXT: store <4 x i32> [[_MSPROP1]], ptr @__msan_retval_tls, align 89916; CHECK-NEXT: ret <4 x float> [[TMP1]]9917;9918 %1 = call <4 x float> @llvm.fma.v4f32(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2)9919 ret <4 x float> %19920}9921 9922define <4 x float> @test_mask_vfmadd128_ps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) #0 {9923;9924; CHECK-LABEL: define <4 x float> @test_mask_vfmadd128_ps(9925; CHECK-SAME: <4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], <4 x float> [[A2:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {9926; CHECK-NEXT: [[TMP7:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 89927; CHECK-NEXT: [[TMP10:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 89928; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 89929; CHECK-NEXT: [[TMP11:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 89930; CHECK-NEXT: call void @llvm.donothing()9931; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP7]], [[TMP10]]9932; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i32> [[_MSPROP]], [[TMP3]]9933; CHECK-NEXT: [[TMP1:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[A0]], <4 x float> [[A1]], <4 x float> [[A2]])9934; CHECK-NEXT: [[TMP14:%.*]] = bitcast i8 [[TMP11]] to <8 x i1>9935; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[MASK]] to <8 x i1>9936; CHECK-NEXT: [[_MSPROP2:%.*]] = shufflevector <8 x i1> [[TMP14]], <8 x i1> [[TMP14]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>9937; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> [[TMP2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>9938; CHECK-NEXT: [[TMP8:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i32> [[_MSPROP1]], <4 x i32> [[TMP7]]9939; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x float> [[TMP1]] to <4 x i32>9940; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x float> [[A0]] to <4 x i32>9941; CHECK-NEXT: [[TMP6:%.*]] = xor <4 x i32> [[TMP4]], [[TMP5]]9942; CHECK-NEXT: [[TMP12:%.*]] = or <4 x i32> [[TMP6]], [[_MSPROP1]]9943; CHECK-NEXT: [[TMP13:%.*]] = or <4 x i32> [[TMP12]], [[TMP7]]9944; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP2]], <4 x i32> [[TMP13]], <4 x i32> [[TMP8]]9945; CHECK-NEXT: [[TMP9:%.*]] = select <4 x i1> [[EXTRACT]], <4 x float> [[TMP1]], <4 x float> [[A0]]9946; CHECK-NEXT: store <4 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 89947; CHECK-NEXT: ret <4 x float> [[TMP9]]9948;9949 %1 = call <4 x float> @llvm.fma.v4f32(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2)9950 %2 = bitcast i8 %mask to <8 x i1>9951 %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>9952 %3 = select <4 x i1> %extract, <4 x float> %1, <4 x float> %a09953 ret <4 x float> %39954}9955 9956define <4 x double> @test_fmadd256_pd(<4 x double> %a, <4 x double> %b, <4 x double> %c) #0 {9957; CHECK-LABEL: define <4 x double> @test_fmadd256_pd(9958; CHECK-SAME: <4 x double> [[A:%.*]], <4 x double> [[B:%.*]], <4 x double> [[C:%.*]]) #[[ATTR0]] {9959; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 89960; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 89961; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 89962; CHECK-NEXT: call void @llvm.donothing()9963; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i64> [[TMP4]], [[TMP2]]9964; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i64> [[_MSPROP]], [[TMP3]]9965; CHECK-NEXT: [[TMP1:%.*]] = call <4 x double> @llvm.fma.v4f64(<4 x double> [[A]], <4 x double> [[B]], <4 x double> [[C]])9966; CHECK-NEXT: store <4 x i64> [[_MSPROP1]], ptr @__msan_retval_tls, align 89967; CHECK-NEXT: ret <4 x double> [[TMP1]]9968;9969 %1 = call <4 x double> @llvm.fma.v4f64(<4 x double> %a, <4 x double> %b, <4 x double> %c)9970 ret <4 x double> %19971}9972 9973define <4 x double> @test_mask_fmadd256_pd(<4 x double> %a, <4 x double> %b, <4 x double> %c, i8 %mask) #0 {9974;9975; CHECK-LABEL: define <4 x double> @test_mask_fmadd256_pd(9976; CHECK-SAME: <4 x double> [[A:%.*]], <4 x double> [[B:%.*]], <4 x double> [[C:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {9977; CHECK-NEXT: [[TMP7:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 89978; CHECK-NEXT: [[TMP10:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 89979; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 89980; CHECK-NEXT: [[TMP11:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 89981; CHECK-NEXT: call void @llvm.donothing()9982; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i64> [[TMP7]], [[TMP10]]9983; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i64> [[_MSPROP]], [[TMP3]]9984; CHECK-NEXT: [[TMP1:%.*]] = call <4 x double> @llvm.fma.v4f64(<4 x double> [[A]], <4 x double> [[B]], <4 x double> [[C]])9985; CHECK-NEXT: [[TMP14:%.*]] = bitcast i8 [[TMP11]] to <8 x i1>9986; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[MASK]] to <8 x i1>9987; CHECK-NEXT: [[_MSPROP2:%.*]] = shufflevector <8 x i1> [[TMP14]], <8 x i1> [[TMP14]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>9988; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> [[TMP2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>9989; CHECK-NEXT: [[TMP8:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i64> [[_MSPROP1]], <4 x i64> [[TMP7]]9990; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x double> [[TMP1]] to <4 x i64>9991; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x double> [[A]] to <4 x i64>9992; CHECK-NEXT: [[TMP6:%.*]] = xor <4 x i64> [[TMP4]], [[TMP5]]9993; CHECK-NEXT: [[TMP12:%.*]] = or <4 x i64> [[TMP6]], [[_MSPROP1]]9994; CHECK-NEXT: [[TMP13:%.*]] = or <4 x i64> [[TMP12]], [[TMP7]]9995; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP2]], <4 x i64> [[TMP13]], <4 x i64> [[TMP8]]9996; CHECK-NEXT: [[TMP9:%.*]] = select <4 x i1> [[EXTRACT]], <4 x double> [[TMP1]], <4 x double> [[A]]9997; CHECK-NEXT: store <4 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 89998; CHECK-NEXT: ret <4 x double> [[TMP9]]9999;10000 %1 = call <4 x double> @llvm.fma.v4f64(<4 x double> %a, <4 x double> %b, <4 x double> %c)10001 %2 = bitcast i8 %mask to <8 x i1>10002 %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>10003 %3 = select <4 x i1> %extract, <4 x double> %1, <4 x double> %a10004 ret <4 x double> %310005}10006 10007define <2 x double> @test_fmadd128_pd(<2 x double> %a, <2 x double> %b, <2 x double> %c) #0 {10008; CHECK-LABEL: define <2 x double> @test_fmadd128_pd(10009; CHECK-SAME: <2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> [[C:%.*]]) #[[ATTR0]] {10010; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 810011; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 810012; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 810013; CHECK-NEXT: call void @llvm.donothing()10014; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP4]], [[TMP2]]10015; CHECK-NEXT: [[_MSPROP1:%.*]] = or <2 x i64> [[_MSPROP]], [[TMP3]]10016; CHECK-NEXT: [[TMP1:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> [[A]], <2 x double> [[B]], <2 x double> [[C]])10017; CHECK-NEXT: store <2 x i64> [[_MSPROP1]], ptr @__msan_retval_tls, align 810018; CHECK-NEXT: ret <2 x double> [[TMP1]]10019;10020 %1 = call <2 x double> @llvm.fma.v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c)10021 ret <2 x double> %110022}10023 10024define <2 x double> @test_mask_fmadd128_pd(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) #0 {10025;10026; CHECK-LABEL: define <2 x double> @test_mask_fmadd128_pd(10027; CHECK-SAME: <2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> [[C:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {10028; CHECK-NEXT: [[TMP7:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 810029; CHECK-NEXT: [[TMP10:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 810030; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 810031; CHECK-NEXT: [[TMP11:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 810032; CHECK-NEXT: call void @llvm.donothing()10033; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP7]], [[TMP10]]10034; CHECK-NEXT: [[_MSPROP1:%.*]] = or <2 x i64> [[_MSPROP]], [[TMP3]]10035; CHECK-NEXT: [[TMP1:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> [[A]], <2 x double> [[B]], <2 x double> [[C]])10036; CHECK-NEXT: [[TMP14:%.*]] = bitcast i8 [[TMP11]] to <8 x i1>10037; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[MASK]] to <8 x i1>10038; CHECK-NEXT: [[_MSPROP2:%.*]] = shufflevector <8 x i1> [[TMP14]], <8 x i1> [[TMP14]], <2 x i32> <i32 0, i32 1>10039; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> [[TMP2]], <2 x i32> <i32 0, i32 1>10040; CHECK-NEXT: [[TMP8:%.*]] = select <2 x i1> [[EXTRACT]], <2 x i64> [[_MSPROP1]], <2 x i64> [[TMP7]]10041; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x double> [[TMP1]] to <2 x i64>10042; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x double> [[A]] to <2 x i64>10043; CHECK-NEXT: [[TMP6:%.*]] = xor <2 x i64> [[TMP4]], [[TMP5]]10044; CHECK-NEXT: [[TMP12:%.*]] = or <2 x i64> [[TMP6]], [[_MSPROP1]]10045; CHECK-NEXT: [[TMP13:%.*]] = or <2 x i64> [[TMP12]], [[TMP7]]10046; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <2 x i1> [[_MSPROP2]], <2 x i64> [[TMP13]], <2 x i64> [[TMP8]]10047; CHECK-NEXT: [[TMP9:%.*]] = select <2 x i1> [[EXTRACT]], <2 x double> [[TMP1]], <2 x double> [[A]]10048; CHECK-NEXT: store <2 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 810049; CHECK-NEXT: ret <2 x double> [[TMP9]]10050;10051 %1 = call <2 x double> @llvm.fma.v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c)10052 %2 = bitcast i8 %mask to <8 x i1>10053 %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <2 x i32> <i32 0, i32 1>10054 %3 = select <2 x i1> %extract, <2 x double> %1, <2 x double> %a10055 ret <2 x double> %310056}10057 10058define <2 x double>@test_int_x86_avx512_mask3_vfmadd_pd_128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) #0 {10059;10060; CHECK-LABEL: define <2 x double> @test_int_x86_avx512_mask3_vfmadd_pd_128(10061; CHECK-SAME: <2 x double> [[X0:%.*]], <2 x double> [[X1:%.*]], <2 x double> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {10062; CHECK-NEXT: [[TMP7:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 810063; CHECK-NEXT: [[TMP10:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 810064; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 810065; CHECK-NEXT: [[TMP11:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 810066; CHECK-NEXT: call void @llvm.donothing()10067; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP7]], [[TMP10]]10068; CHECK-NEXT: [[_MSPROP1:%.*]] = or <2 x i64> [[_MSPROP]], [[TMP3]]10069; CHECK-NEXT: [[TMP1:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> [[X0]], <2 x double> [[X1]], <2 x double> [[X2]])10070; CHECK-NEXT: [[TMP14:%.*]] = bitcast i8 [[TMP11]] to <8 x i1>10071; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[X3]] to <8 x i1>10072; CHECK-NEXT: [[_MSPROP2:%.*]] = shufflevector <8 x i1> [[TMP14]], <8 x i1> [[TMP14]], <2 x i32> <i32 0, i32 1>10073; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> [[TMP2]], <2 x i32> <i32 0, i32 1>10074; CHECK-NEXT: [[TMP8:%.*]] = select <2 x i1> [[EXTRACT]], <2 x i64> [[_MSPROP1]], <2 x i64> [[TMP3]]10075; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x double> [[TMP1]] to <2 x i64>10076; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x double> [[X2]] to <2 x i64>10077; CHECK-NEXT: [[TMP6:%.*]] = xor <2 x i64> [[TMP4]], [[TMP5]]10078; CHECK-NEXT: [[TMP12:%.*]] = or <2 x i64> [[TMP6]], [[_MSPROP1]]10079; CHECK-NEXT: [[TMP13:%.*]] = or <2 x i64> [[TMP12]], [[TMP3]]10080; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <2 x i1> [[_MSPROP2]], <2 x i64> [[TMP13]], <2 x i64> [[TMP8]]10081; CHECK-NEXT: [[TMP9:%.*]] = select <2 x i1> [[EXTRACT]], <2 x double> [[TMP1]], <2 x double> [[X2]]10082; CHECK-NEXT: store <2 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 810083; CHECK-NEXT: ret <2 x double> [[TMP9]]10084;10085 %1 = call <2 x double> @llvm.fma.v2f64(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2)10086 %2 = bitcast i8 %x3 to <8 x i1>10087 %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <2 x i32> <i32 0, i32 1>10088 %3 = select <2 x i1> %extract, <2 x double> %1, <2 x double> %x210089 ret <2 x double> %310090}10091 10092define <2 x double>@test_int_x86_avx512_maskz_vfmadd_pd_128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) #0 {10093;10094; CHECK-LABEL: define <2 x double> @test_int_x86_avx512_maskz_vfmadd_pd_128(10095; CHECK-SAME: <2 x double> [[X0:%.*]], <2 x double> [[X1:%.*]], <2 x double> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {10096; CHECK-NEXT: [[TMP9:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 810097; CHECK-NEXT: [[TMP10:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 810098; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 810099; CHECK-NEXT: [[TMP11:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 810100; CHECK-NEXT: call void @llvm.donothing()10101; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP9]], [[TMP10]]10102; CHECK-NEXT: [[_MSPROP1:%.*]] = or <2 x i64> [[_MSPROP]], [[TMP3]]10103; CHECK-NEXT: [[TMP1:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> [[X0]], <2 x double> [[X1]], <2 x double> [[X2]])10104; CHECK-NEXT: [[TMP12:%.*]] = bitcast i8 [[TMP11]] to <8 x i1>10105; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[X3]] to <8 x i1>10106; CHECK-NEXT: [[_MSPROP2:%.*]] = shufflevector <8 x i1> [[TMP12]], <8 x i1> [[TMP12]], <2 x i32> <i32 0, i32 1>10107; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> [[TMP2]], <2 x i32> <i32 0, i32 1>10108; CHECK-NEXT: [[TMP13:%.*]] = select <2 x i1> [[EXTRACT]], <2 x i64> [[_MSPROP1]], <2 x i64> zeroinitializer10109; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x double> [[TMP1]] to <2 x i64>10110; CHECK-NEXT: [[TMP5:%.*]] = xor <2 x i64> [[TMP4]], zeroinitializer10111; CHECK-NEXT: [[TMP6:%.*]] = or <2 x i64> [[TMP5]], [[_MSPROP1]]10112; CHECK-NEXT: [[TMP7:%.*]] = or <2 x i64> [[TMP6]], zeroinitializer10113; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <2 x i1> [[_MSPROP2]], <2 x i64> [[TMP7]], <2 x i64> [[TMP13]]10114; CHECK-NEXT: [[TMP8:%.*]] = select <2 x i1> [[EXTRACT]], <2 x double> [[TMP1]], <2 x double> zeroinitializer10115; CHECK-NEXT: store <2 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 810116; CHECK-NEXT: ret <2 x double> [[TMP8]]10117;10118 %1 = call <2 x double> @llvm.fma.v2f64(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2)10119 %2 = bitcast i8 %x3 to <8 x i1>10120 %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <2 x i32> <i32 0, i32 1>10121 %3 = select <2 x i1> %extract, <2 x double> %1, <2 x double> zeroinitializer10122 ret <2 x double> %310123}10124 10125define <4 x double>@test_int_x86_avx512_mask3_vfmadd_pd_256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) #0 {10126;10127; CHECK-LABEL: define <4 x double> @test_int_x86_avx512_mask3_vfmadd_pd_256(10128; CHECK-SAME: <4 x double> [[X0:%.*]], <4 x double> [[X1:%.*]], <4 x double> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {10129; CHECK-NEXT: [[TMP7:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 810130; CHECK-NEXT: [[TMP10:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 810131; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 810132; CHECK-NEXT: [[TMP11:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 810133; CHECK-NEXT: call void @llvm.donothing()10134; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i64> [[TMP7]], [[TMP10]]10135; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i64> [[_MSPROP]], [[TMP3]]10136; CHECK-NEXT: [[TMP1:%.*]] = call <4 x double> @llvm.fma.v4f64(<4 x double> [[X0]], <4 x double> [[X1]], <4 x double> [[X2]])10137; CHECK-NEXT: [[TMP14:%.*]] = bitcast i8 [[TMP11]] to <8 x i1>10138; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[X3]] to <8 x i1>10139; CHECK-NEXT: [[_MSPROP2:%.*]] = shufflevector <8 x i1> [[TMP14]], <8 x i1> [[TMP14]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>10140; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> [[TMP2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>10141; CHECK-NEXT: [[TMP8:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i64> [[_MSPROP1]], <4 x i64> [[TMP3]]10142; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x double> [[TMP1]] to <4 x i64>10143; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x double> [[X2]] to <4 x i64>10144; CHECK-NEXT: [[TMP6:%.*]] = xor <4 x i64> [[TMP4]], [[TMP5]]10145; CHECK-NEXT: [[TMP12:%.*]] = or <4 x i64> [[TMP6]], [[_MSPROP1]]10146; CHECK-NEXT: [[TMP13:%.*]] = or <4 x i64> [[TMP12]], [[TMP3]]10147; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP2]], <4 x i64> [[TMP13]], <4 x i64> [[TMP8]]10148; CHECK-NEXT: [[TMP9:%.*]] = select <4 x i1> [[EXTRACT]], <4 x double> [[TMP1]], <4 x double> [[X2]]10149; CHECK-NEXT: store <4 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 810150; CHECK-NEXT: ret <4 x double> [[TMP9]]10151;10152 %1 = call <4 x double> @llvm.fma.v4f64(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2)10153 %2 = bitcast i8 %x3 to <8 x i1>10154 %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>10155 %3 = select <4 x i1> %extract, <4 x double> %1, <4 x double> %x210156 ret <4 x double> %310157}10158 10159define <4 x double>@test_int_x86_avx512_maskz_vfmadd_pd_256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) #0 {10160;10161; CHECK-LABEL: define <4 x double> @test_int_x86_avx512_maskz_vfmadd_pd_256(10162; CHECK-SAME: <4 x double> [[X0:%.*]], <4 x double> [[X1:%.*]], <4 x double> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {10163; CHECK-NEXT: [[TMP9:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 810164; CHECK-NEXT: [[TMP10:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 810165; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 810166; CHECK-NEXT: [[TMP11:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 810167; CHECK-NEXT: call void @llvm.donothing()10168; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i64> [[TMP9]], [[TMP10]]10169; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i64> [[_MSPROP]], [[TMP3]]10170; CHECK-NEXT: [[TMP1:%.*]] = call <4 x double> @llvm.fma.v4f64(<4 x double> [[X0]], <4 x double> [[X1]], <4 x double> [[X2]])10171; CHECK-NEXT: [[TMP12:%.*]] = bitcast i8 [[TMP11]] to <8 x i1>10172; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[X3]] to <8 x i1>10173; CHECK-NEXT: [[_MSPROP2:%.*]] = shufflevector <8 x i1> [[TMP12]], <8 x i1> [[TMP12]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>10174; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> [[TMP2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>10175; CHECK-NEXT: [[TMP13:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i64> [[_MSPROP1]], <4 x i64> zeroinitializer10176; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x double> [[TMP1]] to <4 x i64>10177; CHECK-NEXT: [[TMP5:%.*]] = xor <4 x i64> [[TMP4]], zeroinitializer10178; CHECK-NEXT: [[TMP6:%.*]] = or <4 x i64> [[TMP5]], [[_MSPROP1]]10179; CHECK-NEXT: [[TMP7:%.*]] = or <4 x i64> [[TMP6]], zeroinitializer10180; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP2]], <4 x i64> [[TMP7]], <4 x i64> [[TMP13]]10181; CHECK-NEXT: [[TMP8:%.*]] = select <4 x i1> [[EXTRACT]], <4 x double> [[TMP1]], <4 x double> zeroinitializer10182; CHECK-NEXT: store <4 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 810183; CHECK-NEXT: ret <4 x double> [[TMP8]]10184;10185 %1 = call <4 x double> @llvm.fma.v4f64(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2)10186 %2 = bitcast i8 %x3 to <8 x i1>10187 %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>10188 %3 = select <4 x i1> %extract, <4 x double> %1, <4 x double> zeroinitializer10189 ret <4 x double> %310190}10191 10192define <4 x float>@test_int_x86_avx512_mask3_vfmadd_ps_128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) #0 {10193;10194; CHECK-LABEL: define <4 x float> @test_int_x86_avx512_mask3_vfmadd_ps_128(10195; CHECK-SAME: <4 x float> [[X0:%.*]], <4 x float> [[X1:%.*]], <4 x float> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {10196; CHECK-NEXT: [[TMP7:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 810197; CHECK-NEXT: [[TMP10:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 810198; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 810199; CHECK-NEXT: [[TMP11:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 810200; CHECK-NEXT: call void @llvm.donothing()10201; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP7]], [[TMP10]]10202; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i32> [[_MSPROP]], [[TMP3]]10203; CHECK-NEXT: [[TMP1:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[X0]], <4 x float> [[X1]], <4 x float> [[X2]])10204; CHECK-NEXT: [[TMP14:%.*]] = bitcast i8 [[TMP11]] to <8 x i1>10205; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[X3]] to <8 x i1>10206; CHECK-NEXT: [[_MSPROP2:%.*]] = shufflevector <8 x i1> [[TMP14]], <8 x i1> [[TMP14]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>10207; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> [[TMP2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>10208; CHECK-NEXT: [[TMP8:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i32> [[_MSPROP1]], <4 x i32> [[TMP3]]10209; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x float> [[TMP1]] to <4 x i32>10210; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x float> [[X2]] to <4 x i32>10211; CHECK-NEXT: [[TMP6:%.*]] = xor <4 x i32> [[TMP4]], [[TMP5]]10212; CHECK-NEXT: [[TMP12:%.*]] = or <4 x i32> [[TMP6]], [[_MSPROP1]]10213; CHECK-NEXT: [[TMP13:%.*]] = or <4 x i32> [[TMP12]], [[TMP3]]10214; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP2]], <4 x i32> [[TMP13]], <4 x i32> [[TMP8]]10215; CHECK-NEXT: [[TMP9:%.*]] = select <4 x i1> [[EXTRACT]], <4 x float> [[TMP1]], <4 x float> [[X2]]10216; CHECK-NEXT: store <4 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 810217; CHECK-NEXT: ret <4 x float> [[TMP9]]10218;10219 %1 = call <4 x float> @llvm.fma.v4f32(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2)10220 %2 = bitcast i8 %x3 to <8 x i1>10221 %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>10222 %3 = select <4 x i1> %extract, <4 x float> %1, <4 x float> %x210223 ret <4 x float> %310224}10225 10226define <4 x float>@test_int_x86_avx512_maskz_vfmadd_ps_128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) #0 {10227;10228; CHECK-LABEL: define <4 x float> @test_int_x86_avx512_maskz_vfmadd_ps_128(10229; CHECK-SAME: <4 x float> [[X0:%.*]], <4 x float> [[X1:%.*]], <4 x float> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {10230; CHECK-NEXT: [[TMP9:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 810231; CHECK-NEXT: [[TMP10:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 810232; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 810233; CHECK-NEXT: [[TMP11:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 810234; CHECK-NEXT: call void @llvm.donothing()10235; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP9]], [[TMP10]]10236; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i32> [[_MSPROP]], [[TMP3]]10237; CHECK-NEXT: [[TMP1:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[X0]], <4 x float> [[X1]], <4 x float> [[X2]])10238; CHECK-NEXT: [[TMP12:%.*]] = bitcast i8 [[TMP11]] to <8 x i1>10239; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[X3]] to <8 x i1>10240; CHECK-NEXT: [[_MSPROP2:%.*]] = shufflevector <8 x i1> [[TMP12]], <8 x i1> [[TMP12]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>10241; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> [[TMP2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>10242; CHECK-NEXT: [[TMP13:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i32> [[_MSPROP1]], <4 x i32> zeroinitializer10243; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x float> [[TMP1]] to <4 x i32>10244; CHECK-NEXT: [[TMP5:%.*]] = xor <4 x i32> [[TMP4]], zeroinitializer10245; CHECK-NEXT: [[TMP6:%.*]] = or <4 x i32> [[TMP5]], [[_MSPROP1]]10246; CHECK-NEXT: [[TMP7:%.*]] = or <4 x i32> [[TMP6]], zeroinitializer10247; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP2]], <4 x i32> [[TMP7]], <4 x i32> [[TMP13]]10248; CHECK-NEXT: [[TMP8:%.*]] = select <4 x i1> [[EXTRACT]], <4 x float> [[TMP1]], <4 x float> zeroinitializer10249; CHECK-NEXT: store <4 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 810250; CHECK-NEXT: ret <4 x float> [[TMP8]]10251;10252 %1 = call <4 x float> @llvm.fma.v4f32(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2)10253 %2 = bitcast i8 %x3 to <8 x i1>10254 %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>10255 %3 = select <4 x i1> %extract, <4 x float> %1, <4 x float> zeroinitializer10256 ret <4 x float> %310257}10258 10259define <8 x float>@test_int_x86_avx512_mask3_vfmadd_ps_256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) #0 {10260;10261; CHECK-LABEL: define <8 x float> @test_int_x86_avx512_mask3_vfmadd_ps_256(10262; CHECK-SAME: <8 x float> [[X0:%.*]], <8 x float> [[X1:%.*]], <8 x float> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {10263; CHECK-NEXT: [[TMP7:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 810264; CHECK-NEXT: [[TMP10:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 810265; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 810266; CHECK-NEXT: [[TMP11:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 810267; CHECK-NEXT: call void @llvm.donothing()10268; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> [[TMP7]], [[TMP10]]10269; CHECK-NEXT: [[_MSPROP1:%.*]] = or <8 x i32> [[_MSPROP]], [[TMP3]]10270; CHECK-NEXT: [[TMP1:%.*]] = call <8 x float> @llvm.fma.v8f32(<8 x float> [[X0]], <8 x float> [[X1]], <8 x float> [[X2]])10271; CHECK-NEXT: [[TMP14:%.*]] = bitcast i8 [[TMP11]] to <8 x i1>10272; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[X3]] to <8 x i1>10273; CHECK-NEXT: [[TMP8:%.*]] = select <8 x i1> [[TMP2]], <8 x i32> [[_MSPROP1]], <8 x i32> [[TMP3]]10274; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x float> [[TMP1]] to <8 x i32>10275; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x float> [[X2]] to <8 x i32>10276; CHECK-NEXT: [[TMP6:%.*]] = xor <8 x i32> [[TMP4]], [[TMP5]]10277; CHECK-NEXT: [[TMP12:%.*]] = or <8 x i32> [[TMP6]], [[_MSPROP1]]10278; CHECK-NEXT: [[TMP13:%.*]] = or <8 x i32> [[TMP12]], [[TMP3]]10279; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP14]], <8 x i32> [[TMP13]], <8 x i32> [[TMP8]]10280; CHECK-NEXT: [[TMP9:%.*]] = select <8 x i1> [[TMP2]], <8 x float> [[TMP1]], <8 x float> [[X2]]10281; CHECK-NEXT: store <8 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 810282; CHECK-NEXT: ret <8 x float> [[TMP9]]10283;10284 %1 = call <8 x float> @llvm.fma.v8f32(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2)10285 %2 = bitcast i8 %x3 to <8 x i1>10286 %3 = select <8 x i1> %2, <8 x float> %1, <8 x float> %x210287 ret <8 x float> %310288}10289 10290define <8 x float>@test_int_x86_avx512_maskz_vfmadd_ps_256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) #0 {10291;10292; CHECK-LABEL: define <8 x float> @test_int_x86_avx512_maskz_vfmadd_ps_256(10293; CHECK-SAME: <8 x float> [[X0:%.*]], <8 x float> [[X1:%.*]], <8 x float> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {10294; CHECK-NEXT: [[TMP9:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 810295; CHECK-NEXT: [[TMP10:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 810296; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 810297; CHECK-NEXT: [[TMP11:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 810298; CHECK-NEXT: call void @llvm.donothing()10299; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> [[TMP9]], [[TMP10]]10300; CHECK-NEXT: [[_MSPROP1:%.*]] = or <8 x i32> [[_MSPROP]], [[TMP3]]10301; CHECK-NEXT: [[TMP1:%.*]] = call <8 x float> @llvm.fma.v8f32(<8 x float> [[X0]], <8 x float> [[X1]], <8 x float> [[X2]])10302; CHECK-NEXT: [[TMP12:%.*]] = bitcast i8 [[TMP11]] to <8 x i1>10303; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[X3]] to <8 x i1>10304; CHECK-NEXT: [[TMP13:%.*]] = select <8 x i1> [[TMP2]], <8 x i32> [[_MSPROP1]], <8 x i32> zeroinitializer10305; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x float> [[TMP1]] to <8 x i32>10306; CHECK-NEXT: [[TMP5:%.*]] = xor <8 x i32> [[TMP4]], zeroinitializer10307; CHECK-NEXT: [[TMP6:%.*]] = or <8 x i32> [[TMP5]], [[_MSPROP1]]10308; CHECK-NEXT: [[TMP7:%.*]] = or <8 x i32> [[TMP6]], zeroinitializer10309; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP12]], <8 x i32> [[TMP7]], <8 x i32> [[TMP13]]10310; CHECK-NEXT: [[TMP8:%.*]] = select <8 x i1> [[TMP2]], <8 x float> [[TMP1]], <8 x float> zeroinitializer10311; CHECK-NEXT: store <8 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 810312; CHECK-NEXT: ret <8 x float> [[TMP8]]10313;10314 %1 = call <8 x float> @llvm.fma.v8f32(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2)10315 %2 = bitcast i8 %x3 to <8 x i1>10316 %3 = select <8 x i1> %2, <8 x float> %1, <8 x float> zeroinitializer10317 ret <8 x float> %310318}10319 10320define <2 x double>@test_int_x86_avx512_mask3_vfmsub_pd_128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) #0 {10321;10322; CHECK-LABEL: define <2 x double> @test_int_x86_avx512_mask3_vfmsub_pd_128(10323; CHECK-SAME: <2 x double> [[X0:%.*]], <2 x double> [[X1:%.*]], <2 x double> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {10324; CHECK-NEXT: [[TMP8:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 810325; CHECK-NEXT: [[TMP11:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 810326; CHECK-NEXT: [[TMP12:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 810327; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 810328; CHECK-NEXT: call void @llvm.donothing()10329; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> zeroinitializer, [[TMP8]]10330; CHECK-NEXT: [[TMP1:%.*]] = fsub <2 x double> splat (double -0.000000e+00), [[X2]]10331; CHECK-NEXT: [[_MSPROP1:%.*]] = or <2 x i64> [[TMP11]], [[TMP12]]10332; CHECK-NEXT: [[_MSPROP2:%.*]] = or <2 x i64> [[_MSPROP1]], [[_MSPROP]]10333; CHECK-NEXT: [[TMP2:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> [[X0]], <2 x double> [[X1]], <2 x double> [[TMP1]])10334; CHECK-NEXT: [[TMP15:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>10335; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8 [[X3]] to <8 x i1>10336; CHECK-NEXT: [[_MSPROP3:%.*]] = shufflevector <8 x i1> [[TMP15]], <8 x i1> [[TMP15]], <2 x i32> <i32 0, i32 1>10337; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP3]], <8 x i1> [[TMP3]], <2 x i32> <i32 0, i32 1>10338; CHECK-NEXT: [[TMP9:%.*]] = select <2 x i1> [[EXTRACT]], <2 x i64> [[_MSPROP2]], <2 x i64> [[TMP8]]10339; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x double> [[TMP2]] to <2 x i64>10340; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x double> [[X2]] to <2 x i64>10341; CHECK-NEXT: [[TMP7:%.*]] = xor <2 x i64> [[TMP5]], [[TMP6]]10342; CHECK-NEXT: [[TMP13:%.*]] = or <2 x i64> [[TMP7]], [[_MSPROP2]]10343; CHECK-NEXT: [[TMP14:%.*]] = or <2 x i64> [[TMP13]], [[TMP8]]10344; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <2 x i1> [[_MSPROP3]], <2 x i64> [[TMP14]], <2 x i64> [[TMP9]]10345; CHECK-NEXT: [[TMP10:%.*]] = select <2 x i1> [[EXTRACT]], <2 x double> [[TMP2]], <2 x double> [[X2]]10346; CHECK-NEXT: store <2 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 810347; CHECK-NEXT: ret <2 x double> [[TMP10]]10348;10349 %1 = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %x210350 %2 = call <2 x double> @llvm.fma.v2f64(<2 x double> %x0, <2 x double> %x1, <2 x double> %1)10351 %3 = bitcast i8 %x3 to <8 x i1>10352 %extract = shufflevector <8 x i1> %3, <8 x i1> %3, <2 x i32> <i32 0, i32 1>10353 %4 = select <2 x i1> %extract, <2 x double> %2, <2 x double> %x210354 ret <2 x double> %410355}10356 10357define <4 x double>@test_int_x86_avx512_mask3_vfmsub_pd_256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) #0 {10358;10359; CHECK-LABEL: define <4 x double> @test_int_x86_avx512_mask3_vfmsub_pd_256(10360; CHECK-SAME: <4 x double> [[X0:%.*]], <4 x double> [[X1:%.*]], <4 x double> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {10361; CHECK-NEXT: [[TMP8:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 810362; CHECK-NEXT: [[TMP11:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 810363; CHECK-NEXT: [[TMP12:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 810364; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 810365; CHECK-NEXT: call void @llvm.donothing()10366; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i64> zeroinitializer, [[TMP8]]10367; CHECK-NEXT: [[TMP1:%.*]] = fsub <4 x double> splat (double -0.000000e+00), [[X2]]10368; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i64> [[TMP11]], [[TMP12]]10369; CHECK-NEXT: [[_MSPROP2:%.*]] = or <4 x i64> [[_MSPROP1]], [[_MSPROP]]10370; CHECK-NEXT: [[TMP2:%.*]] = call <4 x double> @llvm.fma.v4f64(<4 x double> [[X0]], <4 x double> [[X1]], <4 x double> [[TMP1]])10371; CHECK-NEXT: [[TMP15:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>10372; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8 [[X3]] to <8 x i1>10373; CHECK-NEXT: [[_MSPROP3:%.*]] = shufflevector <8 x i1> [[TMP15]], <8 x i1> [[TMP15]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>10374; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP3]], <8 x i1> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>10375; CHECK-NEXT: [[TMP9:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i64> [[_MSPROP2]], <4 x i64> [[TMP8]]10376; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x double> [[TMP2]] to <4 x i64>10377; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x double> [[X2]] to <4 x i64>10378; CHECK-NEXT: [[TMP7:%.*]] = xor <4 x i64> [[TMP5]], [[TMP6]]10379; CHECK-NEXT: [[TMP13:%.*]] = or <4 x i64> [[TMP7]], [[_MSPROP2]]10380; CHECK-NEXT: [[TMP14:%.*]] = or <4 x i64> [[TMP13]], [[TMP8]]10381; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP3]], <4 x i64> [[TMP14]], <4 x i64> [[TMP9]]10382; CHECK-NEXT: [[TMP10:%.*]] = select <4 x i1> [[EXTRACT]], <4 x double> [[TMP2]], <4 x double> [[X2]]10383; CHECK-NEXT: store <4 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 810384; CHECK-NEXT: ret <4 x double> [[TMP10]]10385;10386 %1 = fsub <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %x210387 %2 = call <4 x double> @llvm.fma.v4f64(<4 x double> %x0, <4 x double> %x1, <4 x double> %1)10388 %3 = bitcast i8 %x3 to <8 x i1>10389 %extract = shufflevector <8 x i1> %3, <8 x i1> %3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>10390 %4 = select <4 x i1> %extract, <4 x double> %2, <4 x double> %x210391 ret <4 x double> %410392}10393 10394define <4 x float>@test_int_x86_avx512_mask3_vfmsub_ps_128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) #0 {10395;10396; CHECK-LABEL: define <4 x float> @test_int_x86_avx512_mask3_vfmsub_ps_128(10397; CHECK-SAME: <4 x float> [[X0:%.*]], <4 x float> [[X1:%.*]], <4 x float> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {10398; CHECK-NEXT: [[TMP8:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 810399; CHECK-NEXT: [[TMP11:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 810400; CHECK-NEXT: [[TMP12:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 810401; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 810402; CHECK-NEXT: call void @llvm.donothing()10403; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> zeroinitializer, [[TMP8]]10404; CHECK-NEXT: [[TMP1:%.*]] = fsub <4 x float> splat (float -0.000000e+00), [[X2]]10405; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i32> [[TMP11]], [[TMP12]]10406; CHECK-NEXT: [[_MSPROP2:%.*]] = or <4 x i32> [[_MSPROP1]], [[_MSPROP]]10407; CHECK-NEXT: [[TMP2:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[X0]], <4 x float> [[X1]], <4 x float> [[TMP1]])10408; CHECK-NEXT: [[TMP15:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>10409; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8 [[X3]] to <8 x i1>10410; CHECK-NEXT: [[_MSPROP3:%.*]] = shufflevector <8 x i1> [[TMP15]], <8 x i1> [[TMP15]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>10411; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP3]], <8 x i1> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>10412; CHECK-NEXT: [[TMP9:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i32> [[_MSPROP2]], <4 x i32> [[TMP8]]10413; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x float> [[TMP2]] to <4 x i32>10414; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x float> [[X2]] to <4 x i32>10415; CHECK-NEXT: [[TMP7:%.*]] = xor <4 x i32> [[TMP5]], [[TMP6]]10416; CHECK-NEXT: [[TMP13:%.*]] = or <4 x i32> [[TMP7]], [[_MSPROP2]]10417; CHECK-NEXT: [[TMP14:%.*]] = or <4 x i32> [[TMP13]], [[TMP8]]10418; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP3]], <4 x i32> [[TMP14]], <4 x i32> [[TMP9]]10419; CHECK-NEXT: [[TMP10:%.*]] = select <4 x i1> [[EXTRACT]], <4 x float> [[TMP2]], <4 x float> [[X2]]10420; CHECK-NEXT: store <4 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 810421; CHECK-NEXT: ret <4 x float> [[TMP10]]10422;10423 %1 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %x210424 %2 = call <4 x float> @llvm.fma.v4f32(<4 x float> %x0, <4 x float> %x1, <4 x float> %1)10425 %3 = bitcast i8 %x3 to <8 x i1>10426 %extract = shufflevector <8 x i1> %3, <8 x i1> %3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>10427 %4 = select <4 x i1> %extract, <4 x float> %2, <4 x float> %x210428 ret <4 x float> %410429}10430 10431define <8 x float>@test_int_x86_avx512_mask3_vfmsub_ps_256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) #0 {10432;10433; CHECK-LABEL: define <8 x float> @test_int_x86_avx512_mask3_vfmsub_ps_256(10434; CHECK-SAME: <8 x float> [[X0:%.*]], <8 x float> [[X1:%.*]], <8 x float> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {10435; CHECK-NEXT: [[TMP8:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 810436; CHECK-NEXT: [[TMP11:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 810437; CHECK-NEXT: [[TMP12:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 810438; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 810439; CHECK-NEXT: call void @llvm.donothing()10440; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> zeroinitializer, [[TMP8]]10441; CHECK-NEXT: [[TMP1:%.*]] = fsub <8 x float> splat (float -0.000000e+00), [[X2]]10442; CHECK-NEXT: [[_MSPROP1:%.*]] = or <8 x i32> [[TMP11]], [[TMP12]]10443; CHECK-NEXT: [[_MSPROP2:%.*]] = or <8 x i32> [[_MSPROP1]], [[_MSPROP]]10444; CHECK-NEXT: [[TMP2:%.*]] = call <8 x float> @llvm.fma.v8f32(<8 x float> [[X0]], <8 x float> [[X1]], <8 x float> [[TMP1]])10445; CHECK-NEXT: [[TMP15:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>10446; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8 [[X3]] to <8 x i1>10447; CHECK-NEXT: [[TMP9:%.*]] = select <8 x i1> [[TMP3]], <8 x i32> [[_MSPROP2]], <8 x i32> [[TMP8]]10448; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x float> [[TMP2]] to <8 x i32>10449; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x float> [[X2]] to <8 x i32>10450; CHECK-NEXT: [[TMP7:%.*]] = xor <8 x i32> [[TMP5]], [[TMP6]]10451; CHECK-NEXT: [[TMP13:%.*]] = or <8 x i32> [[TMP7]], [[_MSPROP2]]10452; CHECK-NEXT: [[TMP14:%.*]] = or <8 x i32> [[TMP13]], [[TMP8]]10453; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP15]], <8 x i32> [[TMP14]], <8 x i32> [[TMP9]]10454; CHECK-NEXT: [[TMP10:%.*]] = select <8 x i1> [[TMP3]], <8 x float> [[TMP2]], <8 x float> [[X2]]10455; CHECK-NEXT: store <8 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 810456; CHECK-NEXT: ret <8 x float> [[TMP10]]10457;10458 %1 = fsub <8 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %x210459 %2 = call <8 x float> @llvm.fma.v8f32(<8 x float> %x0, <8 x float> %x1, <8 x float> %1)10460 %3 = bitcast i8 %x3 to <8 x i1>10461 %4 = select <8 x i1> %3, <8 x float> %2, <8 x float> %x210462 ret <8 x float> %410463}10464 10465define <8 x float> @test_vfnmadd256_ps(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2) #0 {10466; CHECK-LABEL: define <8 x float> @test_vfnmadd256_ps(10467; CHECK-SAME: <8 x float> [[A0:%.*]], <8 x float> [[A1:%.*]], <8 x float> [[A2:%.*]]) #[[ATTR0]] {10468; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 810469; CHECK-NEXT: [[TMP5:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 810470; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 810471; CHECK-NEXT: call void @llvm.donothing()10472; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> zeroinitializer, [[TMP4]]10473; CHECK-NEXT: [[TMP1:%.*]] = fsub <8 x float> splat (float -0.000000e+00), [[A1]]10474; CHECK-NEXT: [[_MSPROP1:%.*]] = or <8 x i32> [[TMP5]], [[_MSPROP]]10475; CHECK-NEXT: [[_MSPROP2:%.*]] = or <8 x i32> [[_MSPROP1]], [[TMP3]]10476; CHECK-NEXT: [[TMP2:%.*]] = call <8 x float> @llvm.fma.v8f32(<8 x float> [[A0]], <8 x float> [[TMP1]], <8 x float> [[A2]])10477; CHECK-NEXT: store <8 x i32> [[_MSPROP2]], ptr @__msan_retval_tls, align 810478; CHECK-NEXT: ret <8 x float> [[TMP2]]10479;10480 %1 = fsub <8 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %a110481 %2 = call <8 x float> @llvm.fma.v8f32(<8 x float> %a0, <8 x float> %1, <8 x float> %a2)10482 ret <8 x float> %210483}10484 10485define <8 x float> @test_mask_vfnmadd256_ps(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2, i8 %mask) #0 {10486;10487; CHECK-LABEL: define <8 x float> @test_mask_vfnmadd256_ps(10488; CHECK-SAME: <8 x float> [[A0:%.*]], <8 x float> [[A1:%.*]], <8 x float> [[A2:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {10489; CHECK-NEXT: [[TMP8:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 810490; CHECK-NEXT: [[TMP11:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 810491; CHECK-NEXT: [[TMP12:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 810492; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 810493; CHECK-NEXT: call void @llvm.donothing()10494; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> zeroinitializer, [[TMP8]]10495; CHECK-NEXT: [[TMP1:%.*]] = fsub <8 x float> splat (float -0.000000e+00), [[A1]]10496; CHECK-NEXT: [[_MSPROP1:%.*]] = or <8 x i32> [[TMP11]], [[_MSPROP]]10497; CHECK-NEXT: [[_MSPROP2:%.*]] = or <8 x i32> [[_MSPROP1]], [[TMP12]]10498; CHECK-NEXT: [[TMP2:%.*]] = call <8 x float> @llvm.fma.v8f32(<8 x float> [[A0]], <8 x float> [[TMP1]], <8 x float> [[A2]])10499; CHECK-NEXT: [[TMP15:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>10500; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8 [[MASK]] to <8 x i1>10501; CHECK-NEXT: [[TMP9:%.*]] = select <8 x i1> [[TMP3]], <8 x i32> [[_MSPROP2]], <8 x i32> [[TMP11]]10502; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x float> [[TMP2]] to <8 x i32>10503; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x float> [[A0]] to <8 x i32>10504; CHECK-NEXT: [[TMP7:%.*]] = xor <8 x i32> [[TMP5]], [[TMP6]]10505; CHECK-NEXT: [[TMP13:%.*]] = or <8 x i32> [[TMP7]], [[_MSPROP2]]10506; CHECK-NEXT: [[TMP14:%.*]] = or <8 x i32> [[TMP13]], [[TMP11]]10507; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP15]], <8 x i32> [[TMP14]], <8 x i32> [[TMP9]]10508; CHECK-NEXT: [[TMP10:%.*]] = select <8 x i1> [[TMP3]], <8 x float> [[TMP2]], <8 x float> [[A0]]10509; CHECK-NEXT: store <8 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 810510; CHECK-NEXT: ret <8 x float> [[TMP10]]10511;10512 %1 = fsub <8 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %a110513 %2 = call <8 x float> @llvm.fma.v8f32(<8 x float> %a0, <8 x float> %1, <8 x float> %a2)10514 %3 = bitcast i8 %mask to <8 x i1>10515 %4 = select <8 x i1> %3, <8 x float> %2, <8 x float> %a010516 ret <8 x float> %410517}10518 10519define <4 x float> @test_vfnmadd128_ps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) #0 {10520; CHECK-LABEL: define <4 x float> @test_vfnmadd128_ps(10521; CHECK-SAME: <4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], <4 x float> [[A2:%.*]]) #[[ATTR0]] {10522; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 810523; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 810524; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 810525; CHECK-NEXT: call void @llvm.donothing()10526; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> zeroinitializer, [[TMP4]]10527; CHECK-NEXT: [[TMP1:%.*]] = fsub <4 x float> splat (float -0.000000e+00), [[A1]]10528; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i32> [[TMP5]], [[_MSPROP]]10529; CHECK-NEXT: [[_MSPROP2:%.*]] = or <4 x i32> [[_MSPROP1]], [[TMP3]]10530; CHECK-NEXT: [[TMP2:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[A0]], <4 x float> [[TMP1]], <4 x float> [[A2]])10531; CHECK-NEXT: store <4 x i32> [[_MSPROP2]], ptr @__msan_retval_tls, align 810532; CHECK-NEXT: ret <4 x float> [[TMP2]]10533;10534 %1 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %a110535 %2 = call <4 x float> @llvm.fma.v4f32(<4 x float> %a0, <4 x float> %1, <4 x float> %a2)10536 ret <4 x float> %210537}10538 10539define <4 x float> @test_mask_vfnmadd128_ps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) #0 {10540;10541; CHECK-LABEL: define <4 x float> @test_mask_vfnmadd128_ps(10542; CHECK-SAME: <4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], <4 x float> [[A2:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {10543; CHECK-NEXT: [[TMP8:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 810544; CHECK-NEXT: [[TMP11:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 810545; CHECK-NEXT: [[TMP12:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 810546; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 810547; CHECK-NEXT: call void @llvm.donothing()10548; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> zeroinitializer, [[TMP8]]10549; CHECK-NEXT: [[TMP1:%.*]] = fsub <4 x float> splat (float -0.000000e+00), [[A1]]10550; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i32> [[TMP11]], [[_MSPROP]]10551; CHECK-NEXT: [[_MSPROP2:%.*]] = or <4 x i32> [[_MSPROP1]], [[TMP12]]10552; CHECK-NEXT: [[TMP2:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[A0]], <4 x float> [[TMP1]], <4 x float> [[A2]])10553; CHECK-NEXT: [[TMP15:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>10554; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8 [[MASK]] to <8 x i1>10555; CHECK-NEXT: [[_MSPROP3:%.*]] = shufflevector <8 x i1> [[TMP15]], <8 x i1> [[TMP15]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>10556; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP3]], <8 x i1> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>10557; CHECK-NEXT: [[TMP9:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i32> [[_MSPROP2]], <4 x i32> [[TMP11]]10558; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x float> [[TMP2]] to <4 x i32>10559; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x float> [[A0]] to <4 x i32>10560; CHECK-NEXT: [[TMP7:%.*]] = xor <4 x i32> [[TMP5]], [[TMP6]]10561; CHECK-NEXT: [[TMP13:%.*]] = or <4 x i32> [[TMP7]], [[_MSPROP2]]10562; CHECK-NEXT: [[TMP14:%.*]] = or <4 x i32> [[TMP13]], [[TMP11]]10563; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP3]], <4 x i32> [[TMP14]], <4 x i32> [[TMP9]]10564; CHECK-NEXT: [[TMP10:%.*]] = select <4 x i1> [[EXTRACT]], <4 x float> [[TMP2]], <4 x float> [[A0]]10565; CHECK-NEXT: store <4 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 810566; CHECK-NEXT: ret <4 x float> [[TMP10]]10567;10568 %1 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %a110569 %2 = call <4 x float> @llvm.fma.v4f32(<4 x float> %a0, <4 x float> %1, <4 x float> %a2)10570 %3 = bitcast i8 %mask to <8 x i1>10571 %extract = shufflevector <8 x i1> %3, <8 x i1> %3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>10572 %4 = select <4 x i1> %extract, <4 x float> %2, <4 x float> %a010573 ret <4 x float> %410574}10575 10576define <4 x double> @test_vfnmadd256_pd(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2) #0 {10577; CHECK-LABEL: define <4 x double> @test_vfnmadd256_pd(10578; CHECK-SAME: <4 x double> [[A0:%.*]], <4 x double> [[A1:%.*]], <4 x double> [[A2:%.*]]) #[[ATTR0]] {10579; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 810580; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 810581; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 810582; CHECK-NEXT: call void @llvm.donothing()10583; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i64> zeroinitializer, [[TMP4]]10584; CHECK-NEXT: [[TMP1:%.*]] = fsub <4 x double> splat (double -0.000000e+00), [[A1]]10585; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i64> [[TMP5]], [[_MSPROP]]10586; CHECK-NEXT: [[_MSPROP2:%.*]] = or <4 x i64> [[_MSPROP1]], [[TMP3]]10587; CHECK-NEXT: [[TMP2:%.*]] = call <4 x double> @llvm.fma.v4f64(<4 x double> [[A0]], <4 x double> [[TMP1]], <4 x double> [[A2]])10588; CHECK-NEXT: store <4 x i64> [[_MSPROP2]], ptr @__msan_retval_tls, align 810589; CHECK-NEXT: ret <4 x double> [[TMP2]]10590;10591 %1 = fsub <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %a110592 %2 = call <4 x double> @llvm.fma.v4f64(<4 x double> %a0, <4 x double> %1, <4 x double> %a2)10593 ret <4 x double> %210594}10595 10596define <4 x double> @test_mask_vfnmadd256_pd(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2, i8 %mask) #0 {10597;10598; CHECK-LABEL: define <4 x double> @test_mask_vfnmadd256_pd(10599; CHECK-SAME: <4 x double> [[A0:%.*]], <4 x double> [[A1:%.*]], <4 x double> [[A2:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {10600; CHECK-NEXT: [[TMP8:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 810601; CHECK-NEXT: [[TMP11:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 810602; CHECK-NEXT: [[TMP12:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 810603; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 810604; CHECK-NEXT: call void @llvm.donothing()10605; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i64> zeroinitializer, [[TMP8]]10606; CHECK-NEXT: [[TMP1:%.*]] = fsub <4 x double> splat (double -0.000000e+00), [[A1]]10607; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i64> [[TMP11]], [[_MSPROP]]10608; CHECK-NEXT: [[_MSPROP2:%.*]] = or <4 x i64> [[_MSPROP1]], [[TMP12]]10609; CHECK-NEXT: [[TMP2:%.*]] = call <4 x double> @llvm.fma.v4f64(<4 x double> [[A0]], <4 x double> [[TMP1]], <4 x double> [[A2]])10610; CHECK-NEXT: [[TMP15:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>10611; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8 [[MASK]] to <8 x i1>10612; CHECK-NEXT: [[_MSPROP3:%.*]] = shufflevector <8 x i1> [[TMP15]], <8 x i1> [[TMP15]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>10613; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP3]], <8 x i1> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>10614; CHECK-NEXT: [[TMP9:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i64> [[_MSPROP2]], <4 x i64> [[TMP11]]10615; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x double> [[TMP2]] to <4 x i64>10616; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x double> [[A0]] to <4 x i64>10617; CHECK-NEXT: [[TMP7:%.*]] = xor <4 x i64> [[TMP5]], [[TMP6]]10618; CHECK-NEXT: [[TMP13:%.*]] = or <4 x i64> [[TMP7]], [[_MSPROP2]]10619; CHECK-NEXT: [[TMP14:%.*]] = or <4 x i64> [[TMP13]], [[TMP11]]10620; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP3]], <4 x i64> [[TMP14]], <4 x i64> [[TMP9]]10621; CHECK-NEXT: [[TMP10:%.*]] = select <4 x i1> [[EXTRACT]], <4 x double> [[TMP2]], <4 x double> [[A0]]10622; CHECK-NEXT: store <4 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 810623; CHECK-NEXT: ret <4 x double> [[TMP10]]10624;10625 %1 = fsub <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %a110626 %2 = call <4 x double> @llvm.fma.v4f64(<4 x double> %a0, <4 x double> %1, <4 x double> %a2)10627 %3 = bitcast i8 %mask to <8 x i1>10628 %extract = shufflevector <8 x i1> %3, <8 x i1> %3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>10629 %4 = select <4 x i1> %extract, <4 x double> %2, <4 x double> %a010630 ret <4 x double> %410631}10632 10633define <2 x double> @test_vfnmadd128_pd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) #0 {10634; CHECK-LABEL: define <2 x double> @test_vfnmadd128_pd(10635; CHECK-SAME: <2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]], <2 x double> [[A2:%.*]]) #[[ATTR0]] {10636; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 810637; CHECK-NEXT: [[TMP5:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 810638; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 810639; CHECK-NEXT: call void @llvm.donothing()10640; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> zeroinitializer, [[TMP4]]10641; CHECK-NEXT: [[TMP1:%.*]] = fsub <2 x double> splat (double -0.000000e+00), [[A1]]10642; CHECK-NEXT: [[_MSPROP1:%.*]] = or <2 x i64> [[TMP5]], [[_MSPROP]]10643; CHECK-NEXT: [[_MSPROP2:%.*]] = or <2 x i64> [[_MSPROP1]], [[TMP3]]10644; CHECK-NEXT: [[TMP2:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> [[A0]], <2 x double> [[TMP1]], <2 x double> [[A2]])10645; CHECK-NEXT: store <2 x i64> [[_MSPROP2]], ptr @__msan_retval_tls, align 810646; CHECK-NEXT: ret <2 x double> [[TMP2]]10647;10648 %1 = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %a110649 %2 = call <2 x double> @llvm.fma.v2f64(<2 x double> %a0, <2 x double> %1, <2 x double> %a2)10650 ret <2 x double> %210651}10652 10653define <2 x double> @test_mask_vfnmadd128_pd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) #0 {10654;10655; CHECK-LABEL: define <2 x double> @test_mask_vfnmadd128_pd(10656; CHECK-SAME: <2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]], <2 x double> [[A2:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {10657; CHECK-NEXT: [[TMP8:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 810658; CHECK-NEXT: [[TMP11:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 810659; CHECK-NEXT: [[TMP12:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 810660; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 810661; CHECK-NEXT: call void @llvm.donothing()10662; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> zeroinitializer, [[TMP8]]10663; CHECK-NEXT: [[TMP1:%.*]] = fsub <2 x double> splat (double -0.000000e+00), [[A1]]10664; CHECK-NEXT: [[_MSPROP1:%.*]] = or <2 x i64> [[TMP11]], [[_MSPROP]]10665; CHECK-NEXT: [[_MSPROP2:%.*]] = or <2 x i64> [[_MSPROP1]], [[TMP12]]10666; CHECK-NEXT: [[TMP2:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> [[A0]], <2 x double> [[TMP1]], <2 x double> [[A2]])10667; CHECK-NEXT: [[TMP15:%.*]] = bitcast i8 [[TMP4]] to <8 x i1>10668; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8 [[MASK]] to <8 x i1>10669; CHECK-NEXT: [[_MSPROP3:%.*]] = shufflevector <8 x i1> [[TMP15]], <8 x i1> [[TMP15]], <2 x i32> <i32 0, i32 1>10670; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP3]], <8 x i1> [[TMP3]], <2 x i32> <i32 0, i32 1>10671; CHECK-NEXT: [[TMP9:%.*]] = select <2 x i1> [[EXTRACT]], <2 x i64> [[_MSPROP2]], <2 x i64> [[TMP11]]10672; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x double> [[TMP2]] to <2 x i64>10673; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x double> [[A0]] to <2 x i64>10674; CHECK-NEXT: [[TMP7:%.*]] = xor <2 x i64> [[TMP5]], [[TMP6]]10675; CHECK-NEXT: [[TMP13:%.*]] = or <2 x i64> [[TMP7]], [[_MSPROP2]]10676; CHECK-NEXT: [[TMP14:%.*]] = or <2 x i64> [[TMP13]], [[TMP11]]10677; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <2 x i1> [[_MSPROP3]], <2 x i64> [[TMP14]], <2 x i64> [[TMP9]]10678; CHECK-NEXT: [[TMP10:%.*]] = select <2 x i1> [[EXTRACT]], <2 x double> [[TMP2]], <2 x double> [[A0]]10679; CHECK-NEXT: store <2 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 810680; CHECK-NEXT: ret <2 x double> [[TMP10]]10681;10682 %1 = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %a110683 %2 = call <2 x double> @llvm.fma.v2f64(<2 x double> %a0, <2 x double> %1, <2 x double> %a2)10684 %3 = bitcast i8 %mask to <8 x i1>10685 %extract = shufflevector <8 x i1> %3, <8 x i1> %3, <2 x i32> <i32 0, i32 1>10686 %4 = select <2 x i1> %extract, <2 x double> %2, <2 x double> %a010687 ret <2 x double> %410688}10689 10690define <8 x float> @test_vfnmsub256_ps(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2) #0 {10691; CHECK-LABEL: define <8 x float> @test_vfnmsub256_ps(10692; CHECK-SAME: <8 x float> [[A0:%.*]], <8 x float> [[A1:%.*]], <8 x float> [[A2:%.*]]) #[[ATTR0]] {10693; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 810694; CHECK-NEXT: [[TMP5:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 810695; CHECK-NEXT: [[TMP6:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 810696; CHECK-NEXT: call void @llvm.donothing()10697; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> zeroinitializer, [[TMP4]]10698; CHECK-NEXT: [[TMP1:%.*]] = fsub <8 x float> splat (float -0.000000e+00), [[A1]]10699; CHECK-NEXT: [[_MSPROP1:%.*]] = or <8 x i32> zeroinitializer, [[TMP5]]10700; CHECK-NEXT: [[TMP2:%.*]] = fsub <8 x float> splat (float -0.000000e+00), [[A2]]10701; CHECK-NEXT: [[_MSPROP2:%.*]] = or <8 x i32> [[TMP6]], [[_MSPROP]]10702; CHECK-NEXT: [[_MSPROP3:%.*]] = or <8 x i32> [[_MSPROP2]], [[_MSPROP1]]10703; CHECK-NEXT: [[TMP3:%.*]] = call <8 x float> @llvm.fma.v8f32(<8 x float> [[A0]], <8 x float> [[TMP1]], <8 x float> [[TMP2]])10704; CHECK-NEXT: store <8 x i32> [[_MSPROP3]], ptr @__msan_retval_tls, align 810705; CHECK-NEXT: ret <8 x float> [[TMP3]]10706;10707 %1 = fsub <8 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %a110708 %2 = fsub <8 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %a210709 %3 = call <8 x float> @llvm.fma.v8f32(<8 x float> %a0, <8 x float> %1, <8 x float> %2)10710 ret <8 x float> %310711}10712 10713define <8 x float> @test_mask_vfnmsub256_ps(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2, i8 %mask) #0 {10714;10715; CHECK-LABEL: define <8 x float> @test_mask_vfnmsub256_ps(10716; CHECK-SAME: <8 x float> [[A0:%.*]], <8 x float> [[A1:%.*]], <8 x float> [[A2:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {10717; CHECK-NEXT: [[TMP5:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 810718; CHECK-NEXT: [[TMP9:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 810719; CHECK-NEXT: [[TMP12:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 810720; CHECK-NEXT: [[TMP13:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 810721; CHECK-NEXT: call void @llvm.donothing()10722; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> zeroinitializer, [[TMP5]]10723; CHECK-NEXT: [[TMP1:%.*]] = fsub <8 x float> splat (float -0.000000e+00), [[A1]]10724; CHECK-NEXT: [[_MSPROP1:%.*]] = or <8 x i32> zeroinitializer, [[TMP9]]10725; CHECK-NEXT: [[TMP2:%.*]] = fsub <8 x float> splat (float -0.000000e+00), [[A2]]10726; CHECK-NEXT: [[_MSPROP2:%.*]] = or <8 x i32> [[TMP12]], [[_MSPROP]]10727; CHECK-NEXT: [[_MSPROP3:%.*]] = or <8 x i32> [[_MSPROP2]], [[_MSPROP1]]10728; CHECK-NEXT: [[TMP3:%.*]] = call <8 x float> @llvm.fma.v8f32(<8 x float> [[A0]], <8 x float> [[TMP1]], <8 x float> [[TMP2]])10729; CHECK-NEXT: [[TMP16:%.*]] = bitcast i8 [[TMP13]] to <8 x i1>10730; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8 [[MASK]] to <8 x i1>10731; CHECK-NEXT: [[TMP10:%.*]] = select <8 x i1> [[TMP4]], <8 x i32> [[_MSPROP3]], <8 x i32> [[TMP12]]10732; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x float> [[TMP3]] to <8 x i32>10733; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x float> [[A0]] to <8 x i32>10734; CHECK-NEXT: [[TMP8:%.*]] = xor <8 x i32> [[TMP6]], [[TMP7]]10735; CHECK-NEXT: [[TMP14:%.*]] = or <8 x i32> [[TMP8]], [[_MSPROP3]]10736; CHECK-NEXT: [[TMP15:%.*]] = or <8 x i32> [[TMP14]], [[TMP12]]10737; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP16]], <8 x i32> [[TMP15]], <8 x i32> [[TMP10]]10738; CHECK-NEXT: [[TMP11:%.*]] = select <8 x i1> [[TMP4]], <8 x float> [[TMP3]], <8 x float> [[A0]]10739; CHECK-NEXT: store <8 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 810740; CHECK-NEXT: ret <8 x float> [[TMP11]]10741;10742 %1 = fsub <8 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %a110743 %2 = fsub <8 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %a210744 %3 = call <8 x float> @llvm.fma.v8f32(<8 x float> %a0, <8 x float> %1, <8 x float> %2)10745 %4 = bitcast i8 %mask to <8 x i1>10746 %5 = select <8 x i1> %4, <8 x float> %3, <8 x float> %a010747 ret <8 x float> %510748}10749 10750define <4 x float> @test_vfnmsub128_ps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) #0 {10751; CHECK-LABEL: define <4 x float> @test_vfnmsub128_ps(10752; CHECK-SAME: <4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], <4 x float> [[A2:%.*]]) #[[ATTR0]] {10753; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 810754; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 810755; CHECK-NEXT: [[TMP6:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 810756; CHECK-NEXT: call void @llvm.donothing()10757; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> zeroinitializer, [[TMP4]]10758; CHECK-NEXT: [[TMP1:%.*]] = fsub <4 x float> splat (float -0.000000e+00), [[A1]]10759; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i32> zeroinitializer, [[TMP5]]10760; CHECK-NEXT: [[TMP2:%.*]] = fsub <4 x float> splat (float -0.000000e+00), [[A2]]10761; CHECK-NEXT: [[_MSPROP2:%.*]] = or <4 x i32> [[TMP6]], [[_MSPROP]]10762; CHECK-NEXT: [[_MSPROP3:%.*]] = or <4 x i32> [[_MSPROP2]], [[_MSPROP1]]10763; CHECK-NEXT: [[TMP3:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[A0]], <4 x float> [[TMP1]], <4 x float> [[TMP2]])10764; CHECK-NEXT: store <4 x i32> [[_MSPROP3]], ptr @__msan_retval_tls, align 810765; CHECK-NEXT: ret <4 x float> [[TMP3]]10766;10767 %1 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %a110768 %2 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %a210769 %3 = call <4 x float> @llvm.fma.v4f32(<4 x float> %a0, <4 x float> %1, <4 x float> %2)10770 ret <4 x float> %310771}10772 10773define <4 x float> @test_mask_vfnmsub128_ps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) #0 {10774;10775; CHECK-LABEL: define <4 x float> @test_mask_vfnmsub128_ps(10776; CHECK-SAME: <4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], <4 x float> [[A2:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {10777; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 810778; CHECK-NEXT: [[TMP9:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 810779; CHECK-NEXT: [[TMP12:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 810780; CHECK-NEXT: [[TMP13:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 810781; CHECK-NEXT: call void @llvm.donothing()10782; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> zeroinitializer, [[TMP5]]10783; CHECK-NEXT: [[TMP1:%.*]] = fsub <4 x float> splat (float -0.000000e+00), [[A1]]10784; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i32> zeroinitializer, [[TMP9]]10785; CHECK-NEXT: [[TMP2:%.*]] = fsub <4 x float> splat (float -0.000000e+00), [[A2]]10786; CHECK-NEXT: [[_MSPROP2:%.*]] = or <4 x i32> [[TMP12]], [[_MSPROP]]10787; CHECK-NEXT: [[_MSPROP3:%.*]] = or <4 x i32> [[_MSPROP2]], [[_MSPROP1]]10788; CHECK-NEXT: [[TMP3:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[A0]], <4 x float> [[TMP1]], <4 x float> [[TMP2]])10789; CHECK-NEXT: [[TMP16:%.*]] = bitcast i8 [[TMP13]] to <8 x i1>10790; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8 [[MASK]] to <8 x i1>10791; CHECK-NEXT: [[_MSPROP4:%.*]] = shufflevector <8 x i1> [[TMP16]], <8 x i1> [[TMP16]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>10792; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP4]], <8 x i1> [[TMP4]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>10793; CHECK-NEXT: [[TMP10:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i32> [[_MSPROP3]], <4 x i32> [[TMP12]]10794; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x float> [[TMP3]] to <4 x i32>10795; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x float> [[A0]] to <4 x i32>10796; CHECK-NEXT: [[TMP8:%.*]] = xor <4 x i32> [[TMP6]], [[TMP7]]10797; CHECK-NEXT: [[TMP14:%.*]] = or <4 x i32> [[TMP8]], [[_MSPROP3]]10798; CHECK-NEXT: [[TMP15:%.*]] = or <4 x i32> [[TMP14]], [[TMP12]]10799; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP4]], <4 x i32> [[TMP15]], <4 x i32> [[TMP10]]10800; CHECK-NEXT: [[TMP11:%.*]] = select <4 x i1> [[EXTRACT]], <4 x float> [[TMP3]], <4 x float> [[A0]]10801; CHECK-NEXT: store <4 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 810802; CHECK-NEXT: ret <4 x float> [[TMP11]]10803;10804 %1 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %a110805 %2 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %a210806 %3 = call <4 x float> @llvm.fma.v4f32(<4 x float> %a0, <4 x float> %1, <4 x float> %2)10807 %4 = bitcast i8 %mask to <8 x i1>10808 %extract = shufflevector <8 x i1> %4, <8 x i1> %4, <4 x i32> <i32 0, i32 1, i32 2, i32 3>10809 %5 = select <4 x i1> %extract, <4 x float> %3, <4 x float> %a010810 ret <4 x float> %510811}10812 10813define <4 x double> @test_vfnmsub256_pd(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2) #0 {10814; CHECK-LABEL: define <4 x double> @test_vfnmsub256_pd(10815; CHECK-SAME: <4 x double> [[A0:%.*]], <4 x double> [[A1:%.*]], <4 x double> [[A2:%.*]]) #[[ATTR0]] {10816; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 810817; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 810818; CHECK-NEXT: [[TMP6:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 810819; CHECK-NEXT: call void @llvm.donothing()10820; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i64> zeroinitializer, [[TMP4]]10821; CHECK-NEXT: [[TMP1:%.*]] = fsub <4 x double> splat (double -0.000000e+00), [[A1]]10822; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i64> zeroinitializer, [[TMP5]]10823; CHECK-NEXT: [[TMP2:%.*]] = fsub <4 x double> splat (double -0.000000e+00), [[A2]]10824; CHECK-NEXT: [[_MSPROP2:%.*]] = or <4 x i64> [[TMP6]], [[_MSPROP]]10825; CHECK-NEXT: [[_MSPROP3:%.*]] = or <4 x i64> [[_MSPROP2]], [[_MSPROP1]]10826; CHECK-NEXT: [[TMP3:%.*]] = call <4 x double> @llvm.fma.v4f64(<4 x double> [[A0]], <4 x double> [[TMP1]], <4 x double> [[TMP2]])10827; CHECK-NEXT: store <4 x i64> [[_MSPROP3]], ptr @__msan_retval_tls, align 810828; CHECK-NEXT: ret <4 x double> [[TMP3]]10829;10830 %1 = fsub <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %a110831 %2 = fsub <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %a210832 %3 = call <4 x double> @llvm.fma.v4f64(<4 x double> %a0, <4 x double> %1, <4 x double> %2)10833 ret <4 x double> %310834}10835 10836define <4 x double> @test_mask_vfnmsub256_pd(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2, i8 %mask) #0 {10837;10838; CHECK-LABEL: define <4 x double> @test_mask_vfnmsub256_pd(10839; CHECK-SAME: <4 x double> [[A0:%.*]], <4 x double> [[A1:%.*]], <4 x double> [[A2:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {10840; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 810841; CHECK-NEXT: [[TMP9:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 810842; CHECK-NEXT: [[TMP12:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 810843; CHECK-NEXT: [[TMP13:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 810844; CHECK-NEXT: call void @llvm.donothing()10845; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i64> zeroinitializer, [[TMP5]]10846; CHECK-NEXT: [[TMP1:%.*]] = fsub <4 x double> splat (double -0.000000e+00), [[A1]]10847; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i64> zeroinitializer, [[TMP9]]10848; CHECK-NEXT: [[TMP2:%.*]] = fsub <4 x double> splat (double -0.000000e+00), [[A2]]10849; CHECK-NEXT: [[_MSPROP2:%.*]] = or <4 x i64> [[TMP12]], [[_MSPROP]]10850; CHECK-NEXT: [[_MSPROP3:%.*]] = or <4 x i64> [[_MSPROP2]], [[_MSPROP1]]10851; CHECK-NEXT: [[TMP3:%.*]] = call <4 x double> @llvm.fma.v4f64(<4 x double> [[A0]], <4 x double> [[TMP1]], <4 x double> [[TMP2]])10852; CHECK-NEXT: [[TMP16:%.*]] = bitcast i8 [[TMP13]] to <8 x i1>10853; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8 [[MASK]] to <8 x i1>10854; CHECK-NEXT: [[_MSPROP4:%.*]] = shufflevector <8 x i1> [[TMP16]], <8 x i1> [[TMP16]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>10855; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP4]], <8 x i1> [[TMP4]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>10856; CHECK-NEXT: [[TMP10:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i64> [[_MSPROP3]], <4 x i64> [[TMP12]]10857; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x double> [[TMP3]] to <4 x i64>10858; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x double> [[A0]] to <4 x i64>10859; CHECK-NEXT: [[TMP8:%.*]] = xor <4 x i64> [[TMP6]], [[TMP7]]10860; CHECK-NEXT: [[TMP14:%.*]] = or <4 x i64> [[TMP8]], [[_MSPROP3]]10861; CHECK-NEXT: [[TMP15:%.*]] = or <4 x i64> [[TMP14]], [[TMP12]]10862; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP4]], <4 x i64> [[TMP15]], <4 x i64> [[TMP10]]10863; CHECK-NEXT: [[TMP11:%.*]] = select <4 x i1> [[EXTRACT]], <4 x double> [[TMP3]], <4 x double> [[A0]]10864; CHECK-NEXT: store <4 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 810865; CHECK-NEXT: ret <4 x double> [[TMP11]]10866;10867 %1 = fsub <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %a110868 %2 = fsub <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %a210869 %3 = call <4 x double> @llvm.fma.v4f64(<4 x double> %a0, <4 x double> %1, <4 x double> %2)10870 %4 = bitcast i8 %mask to <8 x i1>10871 %extract = shufflevector <8 x i1> %4, <8 x i1> %4, <4 x i32> <i32 0, i32 1, i32 2, i32 3>10872 %5 = select <4 x i1> %extract, <4 x double> %3, <4 x double> %a010873 ret <4 x double> %510874}10875 10876define <2 x double> @test_vfnmsub128_pd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) #0 {10877; CHECK-LABEL: define <2 x double> @test_vfnmsub128_pd(10878; CHECK-SAME: <2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]], <2 x double> [[A2:%.*]]) #[[ATTR0]] {10879; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 810880; CHECK-NEXT: [[TMP5:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 810881; CHECK-NEXT: [[TMP6:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 810882; CHECK-NEXT: call void @llvm.donothing()10883; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> zeroinitializer, [[TMP4]]10884; CHECK-NEXT: [[TMP1:%.*]] = fsub <2 x double> splat (double -0.000000e+00), [[A1]]10885; CHECK-NEXT: [[_MSPROP1:%.*]] = or <2 x i64> zeroinitializer, [[TMP5]]10886; CHECK-NEXT: [[TMP2:%.*]] = fsub <2 x double> splat (double -0.000000e+00), [[A2]]10887; CHECK-NEXT: [[_MSPROP2:%.*]] = or <2 x i64> [[TMP6]], [[_MSPROP]]10888; CHECK-NEXT: [[_MSPROP3:%.*]] = or <2 x i64> [[_MSPROP2]], [[_MSPROP1]]10889; CHECK-NEXT: [[TMP3:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> [[A0]], <2 x double> [[TMP1]], <2 x double> [[TMP2]])10890; CHECK-NEXT: store <2 x i64> [[_MSPROP3]], ptr @__msan_retval_tls, align 810891; CHECK-NEXT: ret <2 x double> [[TMP3]]10892;10893 %1 = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %a110894 %2 = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %a210895 %3 = call <2 x double> @llvm.fma.v2f64(<2 x double> %a0, <2 x double> %1, <2 x double> %2)10896 ret <2 x double> %310897}10898 10899define <2 x double> @test_mask_vfnmsub128_pd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) #0 {10900;10901; CHECK-LABEL: define <2 x double> @test_mask_vfnmsub128_pd(10902; CHECK-SAME: <2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]], <2 x double> [[A2:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {10903; CHECK-NEXT: [[TMP5:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 810904; CHECK-NEXT: [[TMP9:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 810905; CHECK-NEXT: [[TMP12:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 810906; CHECK-NEXT: [[TMP13:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 810907; CHECK-NEXT: call void @llvm.donothing()10908; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> zeroinitializer, [[TMP5]]10909; CHECK-NEXT: [[TMP1:%.*]] = fsub <2 x double> splat (double -0.000000e+00), [[A1]]10910; CHECK-NEXT: [[_MSPROP1:%.*]] = or <2 x i64> zeroinitializer, [[TMP9]]10911; CHECK-NEXT: [[TMP2:%.*]] = fsub <2 x double> splat (double -0.000000e+00), [[A2]]10912; CHECK-NEXT: [[_MSPROP2:%.*]] = or <2 x i64> [[TMP12]], [[_MSPROP]]10913; CHECK-NEXT: [[_MSPROP3:%.*]] = or <2 x i64> [[_MSPROP2]], [[_MSPROP1]]10914; CHECK-NEXT: [[TMP3:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> [[A0]], <2 x double> [[TMP1]], <2 x double> [[TMP2]])10915; CHECK-NEXT: [[TMP16:%.*]] = bitcast i8 [[TMP13]] to <8 x i1>10916; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8 [[MASK]] to <8 x i1>10917; CHECK-NEXT: [[_MSPROP4:%.*]] = shufflevector <8 x i1> [[TMP16]], <8 x i1> [[TMP16]], <2 x i32> <i32 0, i32 1>10918; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP4]], <8 x i1> [[TMP4]], <2 x i32> <i32 0, i32 1>10919; CHECK-NEXT: [[TMP10:%.*]] = select <2 x i1> [[EXTRACT]], <2 x i64> [[_MSPROP3]], <2 x i64> [[TMP12]]10920; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x double> [[TMP3]] to <2 x i64>10921; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x double> [[A0]] to <2 x i64>10922; CHECK-NEXT: [[TMP8:%.*]] = xor <2 x i64> [[TMP6]], [[TMP7]]10923; CHECK-NEXT: [[TMP14:%.*]] = or <2 x i64> [[TMP8]], [[_MSPROP3]]10924; CHECK-NEXT: [[TMP15:%.*]] = or <2 x i64> [[TMP14]], [[TMP12]]10925; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <2 x i1> [[_MSPROP4]], <2 x i64> [[TMP15]], <2 x i64> [[TMP10]]10926; CHECK-NEXT: [[TMP11:%.*]] = select <2 x i1> [[EXTRACT]], <2 x double> [[TMP3]], <2 x double> [[A0]]10927; CHECK-NEXT: store <2 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 810928; CHECK-NEXT: ret <2 x double> [[TMP11]]10929;10930 %1 = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %a110931 %2 = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %a210932 %3 = call <2 x double> @llvm.fma.v2f64(<2 x double> %a0, <2 x double> %1, <2 x double> %2)10933 %4 = bitcast i8 %mask to <8 x i1>10934 %extract = shufflevector <8 x i1> %4, <8 x i1> %4, <2 x i32> <i32 0, i32 1>10935 %5 = select <2 x i1> %extract, <2 x double> %3, <2 x double> %a010936 ret <2 x double> %510937}10938 10939define <2 x double>@test_int_x86_avx512_mask3_vfnmsub_pd_128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) #0 {10940;10941; CHECK-LABEL: define <2 x double> @test_int_x86_avx512_mask3_vfnmsub_pd_128(10942; CHECK-SAME: <2 x double> [[X0:%.*]], <2 x double> [[X1:%.*]], <2 x double> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {10943; CHECK-NEXT: [[TMP5:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 810944; CHECK-NEXT: [[TMP9:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 810945; CHECK-NEXT: [[TMP12:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 810946; CHECK-NEXT: [[TMP13:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 810947; CHECK-NEXT: call void @llvm.donothing()10948; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> zeroinitializer, [[TMP5]]10949; CHECK-NEXT: [[TMP1:%.*]] = fsub <2 x double> splat (double -0.000000e+00), [[X0]]10950; CHECK-NEXT: [[_MSPROP1:%.*]] = or <2 x i64> zeroinitializer, [[TMP9]]10951; CHECK-NEXT: [[TMP2:%.*]] = fsub <2 x double> splat (double -0.000000e+00), [[X2]]10952; CHECK-NEXT: [[_MSPROP2:%.*]] = or <2 x i64> [[_MSPROP]], [[TMP12]]10953; CHECK-NEXT: [[_MSPROP3:%.*]] = or <2 x i64> [[_MSPROP2]], [[_MSPROP1]]10954; CHECK-NEXT: [[TMP3:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> [[TMP1]], <2 x double> [[X1]], <2 x double> [[TMP2]])10955; CHECK-NEXT: [[TMP16:%.*]] = bitcast i8 [[TMP13]] to <8 x i1>10956; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8 [[X3]] to <8 x i1>10957; CHECK-NEXT: [[_MSPROP4:%.*]] = shufflevector <8 x i1> [[TMP16]], <8 x i1> [[TMP16]], <2 x i32> <i32 0, i32 1>10958; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP4]], <8 x i1> [[TMP4]], <2 x i32> <i32 0, i32 1>10959; CHECK-NEXT: [[TMP10:%.*]] = select <2 x i1> [[EXTRACT]], <2 x i64> [[_MSPROP3]], <2 x i64> [[TMP9]]10960; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x double> [[TMP3]] to <2 x i64>10961; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x double> [[X2]] to <2 x i64>10962; CHECK-NEXT: [[TMP8:%.*]] = xor <2 x i64> [[TMP6]], [[TMP7]]10963; CHECK-NEXT: [[TMP14:%.*]] = or <2 x i64> [[TMP8]], [[_MSPROP3]]10964; CHECK-NEXT: [[TMP15:%.*]] = or <2 x i64> [[TMP14]], [[TMP9]]10965; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <2 x i1> [[_MSPROP4]], <2 x i64> [[TMP15]], <2 x i64> [[TMP10]]10966; CHECK-NEXT: [[TMP11:%.*]] = select <2 x i1> [[EXTRACT]], <2 x double> [[TMP3]], <2 x double> [[X2]]10967; CHECK-NEXT: store <2 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 810968; CHECK-NEXT: ret <2 x double> [[TMP11]]10969;10970 %1 = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %x010971 %2 = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %x210972 %3 = call <2 x double> @llvm.fma.v2f64(<2 x double> %1, <2 x double> %x1, <2 x double> %2)10973 %4 = bitcast i8 %x3 to <8 x i1>10974 %extract = shufflevector <8 x i1> %4, <8 x i1> %4, <2 x i32> <i32 0, i32 1>10975 %5 = select <2 x i1> %extract, <2 x double> %3, <2 x double> %x210976 ret <2 x double> %510977}10978 10979define <4 x double>@test_int_x86_avx512_mask3_vfnmsub_pd_256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) #0 {10980;10981; CHECK-LABEL: define <4 x double> @test_int_x86_avx512_mask3_vfnmsub_pd_256(10982; CHECK-SAME: <4 x double> [[X0:%.*]], <4 x double> [[X1:%.*]], <4 x double> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {10983; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 810984; CHECK-NEXT: [[TMP9:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 810985; CHECK-NEXT: [[TMP12:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 810986; CHECK-NEXT: [[TMP13:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 810987; CHECK-NEXT: call void @llvm.donothing()10988; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i64> zeroinitializer, [[TMP5]]10989; CHECK-NEXT: [[TMP1:%.*]] = fsub <4 x double> splat (double -0.000000e+00), [[X0]]10990; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i64> zeroinitializer, [[TMP9]]10991; CHECK-NEXT: [[TMP2:%.*]] = fsub <4 x double> splat (double -0.000000e+00), [[X2]]10992; CHECK-NEXT: [[_MSPROP2:%.*]] = or <4 x i64> [[_MSPROP]], [[TMP12]]10993; CHECK-NEXT: [[_MSPROP3:%.*]] = or <4 x i64> [[_MSPROP2]], [[_MSPROP1]]10994; CHECK-NEXT: [[TMP3:%.*]] = call <4 x double> @llvm.fma.v4f64(<4 x double> [[TMP1]], <4 x double> [[X1]], <4 x double> [[TMP2]])10995; CHECK-NEXT: [[TMP16:%.*]] = bitcast i8 [[TMP13]] to <8 x i1>10996; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8 [[X3]] to <8 x i1>10997; CHECK-NEXT: [[_MSPROP4:%.*]] = shufflevector <8 x i1> [[TMP16]], <8 x i1> [[TMP16]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>10998; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP4]], <8 x i1> [[TMP4]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>10999; CHECK-NEXT: [[TMP10:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i64> [[_MSPROP3]], <4 x i64> [[TMP9]]11000; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x double> [[TMP3]] to <4 x i64>11001; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x double> [[X2]] to <4 x i64>11002; CHECK-NEXT: [[TMP8:%.*]] = xor <4 x i64> [[TMP6]], [[TMP7]]11003; CHECK-NEXT: [[TMP14:%.*]] = or <4 x i64> [[TMP8]], [[_MSPROP3]]11004; CHECK-NEXT: [[TMP15:%.*]] = or <4 x i64> [[TMP14]], [[TMP9]]11005; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP4]], <4 x i64> [[TMP15]], <4 x i64> [[TMP10]]11006; CHECK-NEXT: [[TMP11:%.*]] = select <4 x i1> [[EXTRACT]], <4 x double> [[TMP3]], <4 x double> [[X2]]11007; CHECK-NEXT: store <4 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 811008; CHECK-NEXT: ret <4 x double> [[TMP11]]11009;11010 %1 = fsub <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %x011011 %2 = fsub <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %x211012 %3 = call <4 x double> @llvm.fma.v4f64(<4 x double> %1, <4 x double> %x1, <4 x double> %2)11013 %4 = bitcast i8 %x3 to <8 x i1>11014 %extract = shufflevector <8 x i1> %4, <8 x i1> %4, <4 x i32> <i32 0, i32 1, i32 2, i32 3>11015 %5 = select <4 x i1> %extract, <4 x double> %3, <4 x double> %x211016 ret <4 x double> %511017}11018 11019define <4 x float>@test_int_x86_avx512_mask3_vfnmsub_ps_128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) #0 {11020;11021; CHECK-LABEL: define <4 x float> @test_int_x86_avx512_mask3_vfnmsub_ps_128(11022; CHECK-SAME: <4 x float> [[X0:%.*]], <4 x float> [[X1:%.*]], <4 x float> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {11023; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 811024; CHECK-NEXT: [[TMP9:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 811025; CHECK-NEXT: [[TMP12:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 811026; CHECK-NEXT: [[TMP13:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 811027; CHECK-NEXT: call void @llvm.donothing()11028; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> zeroinitializer, [[TMP5]]11029; CHECK-NEXT: [[TMP1:%.*]] = fsub <4 x float> splat (float -0.000000e+00), [[X0]]11030; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i32> zeroinitializer, [[TMP9]]11031; CHECK-NEXT: [[TMP2:%.*]] = fsub <4 x float> splat (float -0.000000e+00), [[X2]]11032; CHECK-NEXT: [[_MSPROP2:%.*]] = or <4 x i32> [[_MSPROP]], [[TMP12]]11033; CHECK-NEXT: [[_MSPROP3:%.*]] = or <4 x i32> [[_MSPROP2]], [[_MSPROP1]]11034; CHECK-NEXT: [[TMP3:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[TMP1]], <4 x float> [[X1]], <4 x float> [[TMP2]])11035; CHECK-NEXT: [[TMP16:%.*]] = bitcast i8 [[TMP13]] to <8 x i1>11036; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8 [[X3]] to <8 x i1>11037; CHECK-NEXT: [[_MSPROP4:%.*]] = shufflevector <8 x i1> [[TMP16]], <8 x i1> [[TMP16]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>11038; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP4]], <8 x i1> [[TMP4]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>11039; CHECK-NEXT: [[TMP10:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i32> [[_MSPROP3]], <4 x i32> [[TMP9]]11040; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x float> [[TMP3]] to <4 x i32>11041; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x float> [[X2]] to <4 x i32>11042; CHECK-NEXT: [[TMP8:%.*]] = xor <4 x i32> [[TMP6]], [[TMP7]]11043; CHECK-NEXT: [[TMP14:%.*]] = or <4 x i32> [[TMP8]], [[_MSPROP3]]11044; CHECK-NEXT: [[TMP15:%.*]] = or <4 x i32> [[TMP14]], [[TMP9]]11045; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP4]], <4 x i32> [[TMP15]], <4 x i32> [[TMP10]]11046; CHECK-NEXT: [[TMP11:%.*]] = select <4 x i1> [[EXTRACT]], <4 x float> [[TMP3]], <4 x float> [[X2]]11047; CHECK-NEXT: store <4 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 811048; CHECK-NEXT: ret <4 x float> [[TMP11]]11049;11050 %1 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %x011051 %2 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %x211052 %3 = call <4 x float> @llvm.fma.v4f32(<4 x float> %1, <4 x float> %x1, <4 x float> %2)11053 %4 = bitcast i8 %x3 to <8 x i1>11054 %extract = shufflevector <8 x i1> %4, <8 x i1> %4, <4 x i32> <i32 0, i32 1, i32 2, i32 3>11055 %5 = select <4 x i1> %extract, <4 x float> %3, <4 x float> %x211056 ret <4 x float> %511057}11058 11059define <8 x float>@test_int_x86_avx512_mask3_vfnmsub_ps_256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) #0 {11060;11061; CHECK-LABEL: define <8 x float> @test_int_x86_avx512_mask3_vfnmsub_ps_256(11062; CHECK-SAME: <8 x float> [[X0:%.*]], <8 x float> [[X1:%.*]], <8 x float> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {11063; CHECK-NEXT: [[TMP5:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 811064; CHECK-NEXT: [[TMP9:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 811065; CHECK-NEXT: [[TMP12:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 811066; CHECK-NEXT: [[TMP13:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 811067; CHECK-NEXT: call void @llvm.donothing()11068; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> zeroinitializer, [[TMP5]]11069; CHECK-NEXT: [[TMP1:%.*]] = fsub <8 x float> splat (float -0.000000e+00), [[X0]]11070; CHECK-NEXT: [[_MSPROP1:%.*]] = or <8 x i32> zeroinitializer, [[TMP9]]11071; CHECK-NEXT: [[TMP2:%.*]] = fsub <8 x float> splat (float -0.000000e+00), [[X2]]11072; CHECK-NEXT: [[_MSPROP2:%.*]] = or <8 x i32> [[_MSPROP]], [[TMP12]]11073; CHECK-NEXT: [[_MSPROP3:%.*]] = or <8 x i32> [[_MSPROP2]], [[_MSPROP1]]11074; CHECK-NEXT: [[TMP3:%.*]] = call <8 x float> @llvm.fma.v8f32(<8 x float> [[TMP1]], <8 x float> [[X1]], <8 x float> [[TMP2]])11075; CHECK-NEXT: [[TMP16:%.*]] = bitcast i8 [[TMP13]] to <8 x i1>11076; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8 [[X3]] to <8 x i1>11077; CHECK-NEXT: [[TMP10:%.*]] = select <8 x i1> [[TMP4]], <8 x i32> [[_MSPROP3]], <8 x i32> [[TMP9]]11078; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x float> [[TMP3]] to <8 x i32>11079; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x float> [[X2]] to <8 x i32>11080; CHECK-NEXT: [[TMP8:%.*]] = xor <8 x i32> [[TMP6]], [[TMP7]]11081; CHECK-NEXT: [[TMP14:%.*]] = or <8 x i32> [[TMP8]], [[_MSPROP3]]11082; CHECK-NEXT: [[TMP15:%.*]] = or <8 x i32> [[TMP14]], [[TMP9]]11083; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP16]], <8 x i32> [[TMP15]], <8 x i32> [[TMP10]]11084; CHECK-NEXT: [[TMP11:%.*]] = select <8 x i1> [[TMP4]], <8 x float> [[TMP3]], <8 x float> [[X2]]11085; CHECK-NEXT: store <8 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 811086; CHECK-NEXT: ret <8 x float> [[TMP11]]11087;11088 %1 = fsub <8 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %x011089 %2 = fsub <8 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %x211090 %3 = call <8 x float> @llvm.fma.v8f32(<8 x float> %1, <8 x float> %x1, <8 x float> %2)11091 %4 = bitcast i8 %x3 to <8 x i1>11092 %5 = select <8 x i1> %4, <8 x float> %3, <8 x float> %x211093 ret <8 x float> %511094}11095 11096define <8 x float> @test_fmaddsub256_ps(<8 x float> %a, <8 x float> %b, <8 x float> %c) #0 {11097; CHECK-LABEL: define <8 x float> @test_fmaddsub256_ps(11098; CHECK-SAME: <8 x float> [[A:%.*]], <8 x float> [[B:%.*]], <8 x float> [[C:%.*]]) #[[ATTR0]] {11099; CHECK-NEXT: [[TMP5:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 811100; CHECK-NEXT: [[TMP6:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 811101; CHECK-NEXT: [[TMP7:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 811102; CHECK-NEXT: call void @llvm.donothing()11103; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> [[TMP5]], [[TMP6]]11104; CHECK-NEXT: [[_MSPROP1:%.*]] = or <8 x i32> [[_MSPROP]], [[TMP7]]11105; CHECK-NEXT: [[TMP1:%.*]] = call <8 x float> @llvm.fma.v8f32(<8 x float> [[A]], <8 x float> [[B]], <8 x float> [[C]])11106; CHECK-NEXT: [[_MSPROP2:%.*]] = or <8 x i32> zeroinitializer, [[TMP7]]11107; CHECK-NEXT: [[TMP2:%.*]] = fsub <8 x float> splat (float -0.000000e+00), [[C]]11108; CHECK-NEXT: [[_MSPROP3:%.*]] = or <8 x i32> [[TMP5]], [[TMP6]]11109; CHECK-NEXT: [[_MSPROP4:%.*]] = or <8 x i32> [[_MSPROP3]], [[_MSPROP2]]11110; CHECK-NEXT: [[TMP3:%.*]] = call <8 x float> @llvm.fma.v8f32(<8 x float> [[A]], <8 x float> [[B]], <8 x float> [[TMP2]])11111; CHECK-NEXT: [[_MSPROP5:%.*]] = shufflevector <8 x i32> [[_MSPROP4]], <8 x i32> [[_MSPROP1]], <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>11112; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <8 x float> [[TMP3]], <8 x float> [[TMP1]], <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>11113; CHECK-NEXT: store <8 x i32> [[_MSPROP5]], ptr @__msan_retval_tls, align 811114; CHECK-NEXT: ret <8 x float> [[TMP4]]11115;11116 %1 = call <8 x float> @llvm.fma.v8f32(<8 x float> %a, <8 x float> %b, <8 x float> %c)11117 %2 = fsub <8 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %c11118 %3 = call <8 x float> @llvm.fma.v8f32(<8 x float> %a, <8 x float> %b, <8 x float> %2)11119 %4 = shufflevector <8 x float> %3, <8 x float> %1, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>11120 ret <8 x float> %411121}11122 11123define <8 x float> @test_mask_fmaddsub256_ps(<8 x float> %a, <8 x float> %b, <8 x float> %c, i8 %mask) #0 {11124;11125; CHECK-LABEL: define <8 x float> @test_mask_fmaddsub256_ps(11126; CHECK-SAME: <8 x float> [[A:%.*]], <8 x float> [[B:%.*]], <8 x float> [[C:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {11127; CHECK-NEXT: [[TMP6:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 811128; CHECK-NEXT: [[TMP10:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 811129; CHECK-NEXT: [[TMP13:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 811130; CHECK-NEXT: [[TMP14:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 811131; CHECK-NEXT: call void @llvm.donothing()11132; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> [[TMP6]], [[TMP10]]11133; CHECK-NEXT: [[_MSPROP1:%.*]] = or <8 x i32> [[_MSPROP]], [[TMP13]]11134; CHECK-NEXT: [[TMP1:%.*]] = call <8 x float> @llvm.fma.v8f32(<8 x float> [[A]], <8 x float> [[B]], <8 x float> [[C]])11135; CHECK-NEXT: [[_MSPROP2:%.*]] = or <8 x i32> zeroinitializer, [[TMP13]]11136; CHECK-NEXT: [[TMP2:%.*]] = fsub <8 x float> splat (float -0.000000e+00), [[C]]11137; CHECK-NEXT: [[_MSPROP3:%.*]] = or <8 x i32> [[TMP6]], [[TMP10]]11138; CHECK-NEXT: [[_MSPROP4:%.*]] = or <8 x i32> [[_MSPROP3]], [[_MSPROP2]]11139; CHECK-NEXT: [[TMP3:%.*]] = call <8 x float> @llvm.fma.v8f32(<8 x float> [[A]], <8 x float> [[B]], <8 x float> [[TMP2]])11140; CHECK-NEXT: [[_MSPROP5:%.*]] = shufflevector <8 x i32> [[_MSPROP4]], <8 x i32> [[_MSPROP1]], <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>11141; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <8 x float> [[TMP3]], <8 x float> [[TMP1]], <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>11142; CHECK-NEXT: [[TMP17:%.*]] = bitcast i8 [[TMP14]] to <8 x i1>11143; CHECK-NEXT: [[TMP5:%.*]] = bitcast i8 [[MASK]] to <8 x i1>11144; CHECK-NEXT: [[TMP11:%.*]] = select <8 x i1> [[TMP5]], <8 x i32> [[_MSPROP5]], <8 x i32> [[TMP6]]11145; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x float> [[TMP4]] to <8 x i32>11146; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x float> [[A]] to <8 x i32>11147; CHECK-NEXT: [[TMP9:%.*]] = xor <8 x i32> [[TMP7]], [[TMP8]]11148; CHECK-NEXT: [[TMP15:%.*]] = or <8 x i32> [[TMP9]], [[_MSPROP5]]11149; CHECK-NEXT: [[TMP16:%.*]] = or <8 x i32> [[TMP15]], [[TMP6]]11150; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP17]], <8 x i32> [[TMP16]], <8 x i32> [[TMP11]]11151; CHECK-NEXT: [[TMP12:%.*]] = select <8 x i1> [[TMP5]], <8 x float> [[TMP4]], <8 x float> [[A]]11152; CHECK-NEXT: store <8 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 811153; CHECK-NEXT: ret <8 x float> [[TMP12]]11154;11155 %1 = call <8 x float> @llvm.fma.v8f32(<8 x float> %a, <8 x float> %b, <8 x float> %c)11156 %2 = fsub <8 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %c11157 %3 = call <8 x float> @llvm.fma.v8f32(<8 x float> %a, <8 x float> %b, <8 x float> %2)11158 %4 = shufflevector <8 x float> %3, <8 x float> %1, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>11159 %5 = bitcast i8 %mask to <8 x i1>11160 %6 = select <8 x i1> %5, <8 x float> %4, <8 x float> %a11161 ret <8 x float> %611162}11163 11164define <4 x float> @test_fmaddsub128_ps(<4 x float> %a, <4 x float> %b, <4 x float> %c) #0 {11165; CHECK-LABEL: define <4 x float> @test_fmaddsub128_ps(11166; CHECK-SAME: <4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> [[C:%.*]]) #[[ATTR0]] {11167; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 811168; CHECK-NEXT: [[TMP6:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 811169; CHECK-NEXT: [[TMP7:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 811170; CHECK-NEXT: call void @llvm.donothing()11171; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP5]], [[TMP6]]11172; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i32> [[_MSPROP]], [[TMP7]]11173; CHECK-NEXT: [[TMP1:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[A]], <4 x float> [[B]], <4 x float> [[C]])11174; CHECK-NEXT: [[_MSPROP2:%.*]] = or <4 x i32> zeroinitializer, [[TMP7]]11175; CHECK-NEXT: [[TMP2:%.*]] = fsub <4 x float> splat (float -0.000000e+00), [[C]]11176; CHECK-NEXT: [[_MSPROP3:%.*]] = or <4 x i32> [[TMP5]], [[TMP6]]11177; CHECK-NEXT: [[_MSPROP4:%.*]] = or <4 x i32> [[_MSPROP3]], [[_MSPROP2]]11178; CHECK-NEXT: [[TMP3:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[A]], <4 x float> [[B]], <4 x float> [[TMP2]])11179; CHECK-NEXT: [[_MSPROP5:%.*]] = shufflevector <4 x i32> [[_MSPROP4]], <4 x i32> [[_MSPROP1]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>11180; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x float> [[TMP3]], <4 x float> [[TMP1]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>11181; CHECK-NEXT: store <4 x i32> [[_MSPROP5]], ptr @__msan_retval_tls, align 811182; CHECK-NEXT: ret <4 x float> [[TMP4]]11183;11184 %1 = call <4 x float> @llvm.fma.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c)11185 %2 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %c11186 %3 = call <4 x float> @llvm.fma.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %2)11187 %4 = shufflevector <4 x float> %3, <4 x float> %1, <4 x i32> <i32 0, i32 5, i32 2, i32 7>11188 ret <4 x float> %411189}11190 11191define <4 x float> @test_mask_fmaddsub128_ps(<4 x float> %a, <4 x float> %b, <4 x float> %c, i8 %mask) #0 {11192;11193; CHECK-LABEL: define <4 x float> @test_mask_fmaddsub128_ps(11194; CHECK-SAME: <4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> [[C:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {11195; CHECK-NEXT: [[TMP6:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 811196; CHECK-NEXT: [[TMP10:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 811197; CHECK-NEXT: [[TMP13:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 811198; CHECK-NEXT: [[TMP14:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 811199; CHECK-NEXT: call void @llvm.donothing()11200; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP6]], [[TMP10]]11201; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i32> [[_MSPROP]], [[TMP13]]11202; CHECK-NEXT: [[TMP1:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[A]], <4 x float> [[B]], <4 x float> [[C]])11203; CHECK-NEXT: [[_MSPROP2:%.*]] = or <4 x i32> zeroinitializer, [[TMP13]]11204; CHECK-NEXT: [[TMP2:%.*]] = fsub <4 x float> splat (float -0.000000e+00), [[C]]11205; CHECK-NEXT: [[_MSPROP3:%.*]] = or <4 x i32> [[TMP6]], [[TMP10]]11206; CHECK-NEXT: [[_MSPROP4:%.*]] = or <4 x i32> [[_MSPROP3]], [[_MSPROP2]]11207; CHECK-NEXT: [[TMP3:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[A]], <4 x float> [[B]], <4 x float> [[TMP2]])11208; CHECK-NEXT: [[_MSPROP5:%.*]] = shufflevector <4 x i32> [[_MSPROP4]], <4 x i32> [[_MSPROP1]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>11209; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x float> [[TMP3]], <4 x float> [[TMP1]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>11210; CHECK-NEXT: [[TMP17:%.*]] = bitcast i8 [[TMP14]] to <8 x i1>11211; CHECK-NEXT: [[TMP5:%.*]] = bitcast i8 [[MASK]] to <8 x i1>11212; CHECK-NEXT: [[_MSPROP6:%.*]] = shufflevector <8 x i1> [[TMP17]], <8 x i1> [[TMP17]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>11213; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP5]], <8 x i1> [[TMP5]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>11214; CHECK-NEXT: [[TMP11:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i32> [[_MSPROP5]], <4 x i32> [[TMP6]]11215; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x float> [[TMP4]] to <4 x i32>11216; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>11217; CHECK-NEXT: [[TMP9:%.*]] = xor <4 x i32> [[TMP7]], [[TMP8]]11218; CHECK-NEXT: [[TMP15:%.*]] = or <4 x i32> [[TMP9]], [[_MSPROP5]]11219; CHECK-NEXT: [[TMP16:%.*]] = or <4 x i32> [[TMP15]], [[TMP6]]11220; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP6]], <4 x i32> [[TMP16]], <4 x i32> [[TMP11]]11221; CHECK-NEXT: [[TMP12:%.*]] = select <4 x i1> [[EXTRACT]], <4 x float> [[TMP4]], <4 x float> [[A]]11222; CHECK-NEXT: store <4 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 811223; CHECK-NEXT: ret <4 x float> [[TMP12]]11224;11225 %1 = call <4 x float> @llvm.fma.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c)11226 %2 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %c11227 %3 = call <4 x float> @llvm.fma.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %2)11228 %4 = shufflevector <4 x float> %3, <4 x float> %1, <4 x i32> <i32 0, i32 5, i32 2, i32 7>11229 %5 = bitcast i8 %mask to <8 x i1>11230 %extract = shufflevector <8 x i1> %5, <8 x i1> %5, <4 x i32> <i32 0, i32 1, i32 2, i32 3>11231 %6 = select <4 x i1> %extract, <4 x float> %4, <4 x float> %a11232 ret <4 x float> %611233}11234 11235define <4 x double> @test_vfmaddsub256_pd(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2) #0 {11236; CHECK-LABEL: define <4 x double> @test_vfmaddsub256_pd(11237; CHECK-SAME: <4 x double> [[A0:%.*]], <4 x double> [[A1:%.*]], <4 x double> [[A2:%.*]]) #[[ATTR0]] {11238; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 811239; CHECK-NEXT: [[TMP6:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 811240; CHECK-NEXT: [[TMP7:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 811241; CHECK-NEXT: call void @llvm.donothing()11242; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i64> [[TMP5]], [[TMP6]]11243; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i64> [[_MSPROP]], [[TMP7]]11244; CHECK-NEXT: [[TMP1:%.*]] = call <4 x double> @llvm.fma.v4f64(<4 x double> [[A0]], <4 x double> [[A1]], <4 x double> [[A2]])11245; CHECK-NEXT: [[_MSPROP2:%.*]] = or <4 x i64> zeroinitializer, [[TMP7]]11246; CHECK-NEXT: [[TMP2:%.*]] = fsub <4 x double> splat (double -0.000000e+00), [[A2]]11247; CHECK-NEXT: [[_MSPROP3:%.*]] = or <4 x i64> [[TMP5]], [[TMP6]]11248; CHECK-NEXT: [[_MSPROP4:%.*]] = or <4 x i64> [[_MSPROP3]], [[_MSPROP2]]11249; CHECK-NEXT: [[TMP3:%.*]] = call <4 x double> @llvm.fma.v4f64(<4 x double> [[A0]], <4 x double> [[A1]], <4 x double> [[TMP2]])11250; CHECK-NEXT: [[_MSPROP5:%.*]] = shufflevector <4 x i64> [[_MSPROP4]], <4 x i64> [[_MSPROP1]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>11251; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x double> [[TMP3]], <4 x double> [[TMP1]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>11252; CHECK-NEXT: store <4 x i64> [[_MSPROP5]], ptr @__msan_retval_tls, align 811253; CHECK-NEXT: ret <4 x double> [[TMP4]]11254;11255 %1 = call <4 x double> @llvm.fma.v4f64(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2)11256 %2 = fsub <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %a211257 %3 = call <4 x double> @llvm.fma.v4f64(<4 x double> %a0, <4 x double> %a1, <4 x double> %2)11258 %4 = shufflevector <4 x double> %3, <4 x double> %1, <4 x i32> <i32 0, i32 5, i32 2, i32 7>11259 ret <4 x double> %411260}11261 11262define <4 x double> @test_mask_vfmaddsub256_pd(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2, i8 %mask) #0 {11263;11264; CHECK-LABEL: define <4 x double> @test_mask_vfmaddsub256_pd(11265; CHECK-SAME: <4 x double> [[A0:%.*]], <4 x double> [[A1:%.*]], <4 x double> [[A2:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {11266; CHECK-NEXT: [[TMP6:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 811267; CHECK-NEXT: [[TMP10:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 811268; CHECK-NEXT: [[TMP13:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 811269; CHECK-NEXT: [[TMP14:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 811270; CHECK-NEXT: call void @llvm.donothing()11271; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i64> [[TMP6]], [[TMP10]]11272; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i64> [[_MSPROP]], [[TMP13]]11273; CHECK-NEXT: [[TMP1:%.*]] = call <4 x double> @llvm.fma.v4f64(<4 x double> [[A0]], <4 x double> [[A1]], <4 x double> [[A2]])11274; CHECK-NEXT: [[_MSPROP2:%.*]] = or <4 x i64> zeroinitializer, [[TMP13]]11275; CHECK-NEXT: [[TMP2:%.*]] = fsub <4 x double> splat (double -0.000000e+00), [[A2]]11276; CHECK-NEXT: [[_MSPROP3:%.*]] = or <4 x i64> [[TMP6]], [[TMP10]]11277; CHECK-NEXT: [[_MSPROP4:%.*]] = or <4 x i64> [[_MSPROP3]], [[_MSPROP2]]11278; CHECK-NEXT: [[TMP3:%.*]] = call <4 x double> @llvm.fma.v4f64(<4 x double> [[A0]], <4 x double> [[A1]], <4 x double> [[TMP2]])11279; CHECK-NEXT: [[_MSPROP5:%.*]] = shufflevector <4 x i64> [[_MSPROP4]], <4 x i64> [[_MSPROP1]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>11280; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x double> [[TMP3]], <4 x double> [[TMP1]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>11281; CHECK-NEXT: [[TMP17:%.*]] = bitcast i8 [[TMP14]] to <8 x i1>11282; CHECK-NEXT: [[TMP5:%.*]] = bitcast i8 [[MASK]] to <8 x i1>11283; CHECK-NEXT: [[_MSPROP6:%.*]] = shufflevector <8 x i1> [[TMP17]], <8 x i1> [[TMP17]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>11284; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP5]], <8 x i1> [[TMP5]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>11285; CHECK-NEXT: [[TMP11:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i64> [[_MSPROP5]], <4 x i64> [[TMP6]]11286; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x double> [[TMP4]] to <4 x i64>11287; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x double> [[A0]] to <4 x i64>11288; CHECK-NEXT: [[TMP9:%.*]] = xor <4 x i64> [[TMP7]], [[TMP8]]11289; CHECK-NEXT: [[TMP15:%.*]] = or <4 x i64> [[TMP9]], [[_MSPROP5]]11290; CHECK-NEXT: [[TMP16:%.*]] = or <4 x i64> [[TMP15]], [[TMP6]]11291; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP6]], <4 x i64> [[TMP16]], <4 x i64> [[TMP11]]11292; CHECK-NEXT: [[TMP12:%.*]] = select <4 x i1> [[EXTRACT]], <4 x double> [[TMP4]], <4 x double> [[A0]]11293; CHECK-NEXT: store <4 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 811294; CHECK-NEXT: ret <4 x double> [[TMP12]]11295;11296 %1 = call <4 x double> @llvm.fma.v4f64(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2)11297 %2 = fsub <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %a211298 %3 = call <4 x double> @llvm.fma.v4f64(<4 x double> %a0, <4 x double> %a1, <4 x double> %2)11299 %4 = shufflevector <4 x double> %3, <4 x double> %1, <4 x i32> <i32 0, i32 5, i32 2, i32 7>11300 %5 = bitcast i8 %mask to <8 x i1>11301 %extract = shufflevector <8 x i1> %5, <8 x i1> %5, <4 x i32> <i32 0, i32 1, i32 2, i32 3>11302 %6 = select <4 x i1> %extract, <4 x double> %4, <4 x double> %a011303 ret <4 x double> %611304}11305 11306define <2 x double> @test_vfmaddsub128_pd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) #0 {11307; CHECK-LABEL: define <2 x double> @test_vfmaddsub128_pd(11308; CHECK-SAME: <2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]], <2 x double> [[A2:%.*]]) #[[ATTR0]] {11309; CHECK-NEXT: [[TMP5:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 811310; CHECK-NEXT: [[TMP6:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 811311; CHECK-NEXT: [[TMP7:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 811312; CHECK-NEXT: call void @llvm.donothing()11313; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP5]], [[TMP6]]11314; CHECK-NEXT: [[_MSPROP1:%.*]] = or <2 x i64> [[_MSPROP]], [[TMP7]]11315; CHECK-NEXT: [[TMP1:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> [[A0]], <2 x double> [[A1]], <2 x double> [[A2]])11316; CHECK-NEXT: [[_MSPROP2:%.*]] = or <2 x i64> zeroinitializer, [[TMP7]]11317; CHECK-NEXT: [[TMP2:%.*]] = fsub <2 x double> splat (double -0.000000e+00), [[A2]]11318; CHECK-NEXT: [[_MSPROP3:%.*]] = or <2 x i64> [[TMP5]], [[TMP6]]11319; CHECK-NEXT: [[_MSPROP4:%.*]] = or <2 x i64> [[_MSPROP3]], [[_MSPROP2]]11320; CHECK-NEXT: [[TMP3:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> [[A0]], <2 x double> [[A1]], <2 x double> [[TMP2]])11321; CHECK-NEXT: [[_MSPROP5:%.*]] = shufflevector <2 x i64> [[_MSPROP4]], <2 x i64> [[_MSPROP1]], <2 x i32> <i32 0, i32 3>11322; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> [[TMP1]], <2 x i32> <i32 0, i32 3>11323; CHECK-NEXT: store <2 x i64> [[_MSPROP5]], ptr @__msan_retval_tls, align 811324; CHECK-NEXT: ret <2 x double> [[TMP4]]11325;11326 %1 = call <2 x double> @llvm.fma.v2f64(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2)11327 %2 = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %a211328 %3 = call <2 x double> @llvm.fma.v2f64(<2 x double> %a0, <2 x double> %a1, <2 x double> %2)11329 %4 = shufflevector <2 x double> %3, <2 x double> %1, <2 x i32> <i32 0, i32 3>11330 ret <2 x double> %411331}11332 11333define <2 x double> @test_mask_vfmaddsub128_pd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) #0 {11334;11335; CHECK-LABEL: define <2 x double> @test_mask_vfmaddsub128_pd(11336; CHECK-SAME: <2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]], <2 x double> [[A2:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {11337; CHECK-NEXT: [[TMP6:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 811338; CHECK-NEXT: [[TMP10:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 811339; CHECK-NEXT: [[TMP13:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 811340; CHECK-NEXT: [[TMP14:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 811341; CHECK-NEXT: call void @llvm.donothing()11342; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP6]], [[TMP10]]11343; CHECK-NEXT: [[_MSPROP1:%.*]] = or <2 x i64> [[_MSPROP]], [[TMP13]]11344; CHECK-NEXT: [[TMP1:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> [[A0]], <2 x double> [[A1]], <2 x double> [[A2]])11345; CHECK-NEXT: [[_MSPROP2:%.*]] = or <2 x i64> zeroinitializer, [[TMP13]]11346; CHECK-NEXT: [[TMP2:%.*]] = fsub <2 x double> splat (double -0.000000e+00), [[A2]]11347; CHECK-NEXT: [[_MSPROP3:%.*]] = or <2 x i64> [[TMP6]], [[TMP10]]11348; CHECK-NEXT: [[_MSPROP4:%.*]] = or <2 x i64> [[_MSPROP3]], [[_MSPROP2]]11349; CHECK-NEXT: [[TMP3:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> [[A0]], <2 x double> [[A1]], <2 x double> [[TMP2]])11350; CHECK-NEXT: [[_MSPROP5:%.*]] = shufflevector <2 x i64> [[_MSPROP4]], <2 x i64> [[_MSPROP1]], <2 x i32> <i32 0, i32 3>11351; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> [[TMP1]], <2 x i32> <i32 0, i32 3>11352; CHECK-NEXT: [[TMP17:%.*]] = bitcast i8 [[TMP14]] to <8 x i1>11353; CHECK-NEXT: [[TMP5:%.*]] = bitcast i8 [[MASK]] to <8 x i1>11354; CHECK-NEXT: [[_MSPROP6:%.*]] = shufflevector <8 x i1> [[TMP17]], <8 x i1> [[TMP17]], <2 x i32> <i32 0, i32 1>11355; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP5]], <8 x i1> [[TMP5]], <2 x i32> <i32 0, i32 1>11356; CHECK-NEXT: [[TMP11:%.*]] = select <2 x i1> [[EXTRACT]], <2 x i64> [[_MSPROP5]], <2 x i64> [[TMP6]]11357; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x double> [[TMP4]] to <2 x i64>11358; CHECK-NEXT: [[TMP8:%.*]] = bitcast <2 x double> [[A0]] to <2 x i64>11359; CHECK-NEXT: [[TMP9:%.*]] = xor <2 x i64> [[TMP7]], [[TMP8]]11360; CHECK-NEXT: [[TMP15:%.*]] = or <2 x i64> [[TMP9]], [[_MSPROP5]]11361; CHECK-NEXT: [[TMP16:%.*]] = or <2 x i64> [[TMP15]], [[TMP6]]11362; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <2 x i1> [[_MSPROP6]], <2 x i64> [[TMP16]], <2 x i64> [[TMP11]]11363; CHECK-NEXT: [[TMP12:%.*]] = select <2 x i1> [[EXTRACT]], <2 x double> [[TMP4]], <2 x double> [[A0]]11364; CHECK-NEXT: store <2 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 811365; CHECK-NEXT: ret <2 x double> [[TMP12]]11366;11367 %1 = call <2 x double> @llvm.fma.v2f64(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2)11368 %2 = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %a211369 %3 = call <2 x double> @llvm.fma.v2f64(<2 x double> %a0, <2 x double> %a1, <2 x double> %2)11370 %4 = shufflevector <2 x double> %3, <2 x double> %1, <2 x i32> <i32 0, i32 3>11371 %5 = bitcast i8 %mask to <8 x i1>11372 %extract = shufflevector <8 x i1> %5, <8 x i1> %5, <2 x i32> <i32 0, i32 1>11373 %6 = select <2 x i1> %extract, <2 x double> %4, <2 x double> %a011374 ret <2 x double> %611375}11376 11377define <2 x double>@test_int_x86_avx512_mask3_vfmaddsub_pd_128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) #0 {11378;11379; CHECK-LABEL: define <2 x double> @test_int_x86_avx512_mask3_vfmaddsub_pd_128(11380; CHECK-SAME: <2 x double> [[X0:%.*]], <2 x double> [[X1:%.*]], <2 x double> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {11381; CHECK-NEXT: [[TMP6:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 811382; CHECK-NEXT: [[TMP10:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 811383; CHECK-NEXT: [[TMP13:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 811384; CHECK-NEXT: [[TMP14:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 811385; CHECK-NEXT: call void @llvm.donothing()11386; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP6]], [[TMP10]]11387; CHECK-NEXT: [[_MSPROP1:%.*]] = or <2 x i64> [[_MSPROP]], [[TMP13]]11388; CHECK-NEXT: [[TMP1:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> [[X0]], <2 x double> [[X1]], <2 x double> [[X2]])11389; CHECK-NEXT: [[_MSPROP2:%.*]] = or <2 x i64> zeroinitializer, [[TMP13]]11390; CHECK-NEXT: [[TMP2:%.*]] = fsub <2 x double> splat (double -0.000000e+00), [[X2]]11391; CHECK-NEXT: [[_MSPROP3:%.*]] = or <2 x i64> [[TMP6]], [[TMP10]]11392; CHECK-NEXT: [[_MSPROP4:%.*]] = or <2 x i64> [[_MSPROP3]], [[_MSPROP2]]11393; CHECK-NEXT: [[TMP3:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> [[X0]], <2 x double> [[X1]], <2 x double> [[TMP2]])11394; CHECK-NEXT: [[_MSPROP5:%.*]] = shufflevector <2 x i64> [[_MSPROP4]], <2 x i64> [[_MSPROP1]], <2 x i32> <i32 0, i32 3>11395; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> [[TMP1]], <2 x i32> <i32 0, i32 3>11396; CHECK-NEXT: [[TMP17:%.*]] = bitcast i8 [[TMP14]] to <8 x i1>11397; CHECK-NEXT: [[TMP5:%.*]] = bitcast i8 [[X3]] to <8 x i1>11398; CHECK-NEXT: [[_MSPROP6:%.*]] = shufflevector <8 x i1> [[TMP17]], <8 x i1> [[TMP17]], <2 x i32> <i32 0, i32 1>11399; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP5]], <8 x i1> [[TMP5]], <2 x i32> <i32 0, i32 1>11400; CHECK-NEXT: [[TMP11:%.*]] = select <2 x i1> [[EXTRACT]], <2 x i64> [[_MSPROP5]], <2 x i64> [[TMP13]]11401; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x double> [[TMP4]] to <2 x i64>11402; CHECK-NEXT: [[TMP8:%.*]] = bitcast <2 x double> [[X2]] to <2 x i64>11403; CHECK-NEXT: [[TMP9:%.*]] = xor <2 x i64> [[TMP7]], [[TMP8]]11404; CHECK-NEXT: [[TMP15:%.*]] = or <2 x i64> [[TMP9]], [[_MSPROP5]]11405; CHECK-NEXT: [[TMP16:%.*]] = or <2 x i64> [[TMP15]], [[TMP13]]11406; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <2 x i1> [[_MSPROP6]], <2 x i64> [[TMP16]], <2 x i64> [[TMP11]]11407; CHECK-NEXT: [[TMP12:%.*]] = select <2 x i1> [[EXTRACT]], <2 x double> [[TMP4]], <2 x double> [[X2]]11408; CHECK-NEXT: store <2 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 811409; CHECK-NEXT: ret <2 x double> [[TMP12]]11410;11411 %1 = call <2 x double> @llvm.fma.v2f64(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2)11412 %2 = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %x211413 %3 = call <2 x double> @llvm.fma.v2f64(<2 x double> %x0, <2 x double> %x1, <2 x double> %2)11414 %4 = shufflevector <2 x double> %3, <2 x double> %1, <2 x i32> <i32 0, i32 3>11415 %5 = bitcast i8 %x3 to <8 x i1>11416 %extract = shufflevector <8 x i1> %5, <8 x i1> %5, <2 x i32> <i32 0, i32 1>11417 %6 = select <2 x i1> %extract, <2 x double> %4, <2 x double> %x211418 ret <2 x double> %611419}11420 11421define <2 x double>@test_int_x86_avx512_maskz_vfmaddsub_pd_128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) #0 {11422;11423; CHECK-LABEL: define <2 x double> @test_int_x86_avx512_maskz_vfmaddsub_pd_128(11424; CHECK-SAME: <2 x double> [[X0:%.*]], <2 x double> [[X1:%.*]], <2 x double> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {11425; CHECK-NEXT: [[TMP6:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 811426; CHECK-NEXT: [[TMP12:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 811427; CHECK-NEXT: [[TMP13:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 811428; CHECK-NEXT: [[TMP14:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 811429; CHECK-NEXT: call void @llvm.donothing()11430; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP6]], [[TMP12]]11431; CHECK-NEXT: [[_MSPROP1:%.*]] = or <2 x i64> [[_MSPROP]], [[TMP13]]11432; CHECK-NEXT: [[TMP1:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> [[X0]], <2 x double> [[X1]], <2 x double> [[X2]])11433; CHECK-NEXT: [[_MSPROP2:%.*]] = or <2 x i64> zeroinitializer, [[TMP13]]11434; CHECK-NEXT: [[TMP2:%.*]] = fsub <2 x double> splat (double -0.000000e+00), [[X2]]11435; CHECK-NEXT: [[_MSPROP3:%.*]] = or <2 x i64> [[TMP6]], [[TMP12]]11436; CHECK-NEXT: [[_MSPROP4:%.*]] = or <2 x i64> [[_MSPROP3]], [[_MSPROP2]]11437; CHECK-NEXT: [[TMP3:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> [[X0]], <2 x double> [[X1]], <2 x double> [[TMP2]])11438; CHECK-NEXT: [[_MSPROP5:%.*]] = shufflevector <2 x i64> [[_MSPROP4]], <2 x i64> [[_MSPROP1]], <2 x i32> <i32 0, i32 3>11439; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> [[TMP1]], <2 x i32> <i32 0, i32 3>11440; CHECK-NEXT: [[TMP15:%.*]] = bitcast i8 [[TMP14]] to <8 x i1>11441; CHECK-NEXT: [[TMP5:%.*]] = bitcast i8 [[X3]] to <8 x i1>11442; CHECK-NEXT: [[_MSPROP6:%.*]] = shufflevector <8 x i1> [[TMP15]], <8 x i1> [[TMP15]], <2 x i32> <i32 0, i32 1>11443; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP5]], <8 x i1> [[TMP5]], <2 x i32> <i32 0, i32 1>11444; CHECK-NEXT: [[TMP16:%.*]] = select <2 x i1> [[EXTRACT]], <2 x i64> [[_MSPROP5]], <2 x i64> zeroinitializer11445; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x double> [[TMP4]] to <2 x i64>11446; CHECK-NEXT: [[TMP8:%.*]] = xor <2 x i64> [[TMP7]], zeroinitializer11447; CHECK-NEXT: [[TMP9:%.*]] = or <2 x i64> [[TMP8]], [[_MSPROP5]]11448; CHECK-NEXT: [[TMP10:%.*]] = or <2 x i64> [[TMP9]], zeroinitializer11449; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <2 x i1> [[_MSPROP6]], <2 x i64> [[TMP10]], <2 x i64> [[TMP16]]11450; CHECK-NEXT: [[TMP11:%.*]] = select <2 x i1> [[EXTRACT]], <2 x double> [[TMP4]], <2 x double> zeroinitializer11451; CHECK-NEXT: store <2 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 811452; CHECK-NEXT: ret <2 x double> [[TMP11]]11453;11454 %1 = call <2 x double> @llvm.fma.v2f64(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2)11455 %2 = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %x211456 %3 = call <2 x double> @llvm.fma.v2f64(<2 x double> %x0, <2 x double> %x1, <2 x double> %2)11457 %4 = shufflevector <2 x double> %3, <2 x double> %1, <2 x i32> <i32 0, i32 3>11458 %5 = bitcast i8 %x3 to <8 x i1>11459 %extract = shufflevector <8 x i1> %5, <8 x i1> %5, <2 x i32> <i32 0, i32 1>11460 %6 = select <2 x i1> %extract, <2 x double> %4, <2 x double> zeroinitializer11461 ret <2 x double> %611462}11463 11464define <4 x double>@test_int_x86_avx512_mask3_vfmaddsub_pd_256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) #0 {11465;11466; CHECK-LABEL: define <4 x double> @test_int_x86_avx512_mask3_vfmaddsub_pd_256(11467; CHECK-SAME: <4 x double> [[X0:%.*]], <4 x double> [[X1:%.*]], <4 x double> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {11468; CHECK-NEXT: [[TMP6:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 811469; CHECK-NEXT: [[TMP10:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 811470; CHECK-NEXT: [[TMP13:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 811471; CHECK-NEXT: [[TMP14:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 811472; CHECK-NEXT: call void @llvm.donothing()11473; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i64> [[TMP6]], [[TMP10]]11474; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i64> [[_MSPROP]], [[TMP13]]11475; CHECK-NEXT: [[TMP1:%.*]] = call <4 x double> @llvm.fma.v4f64(<4 x double> [[X0]], <4 x double> [[X1]], <4 x double> [[X2]])11476; CHECK-NEXT: [[_MSPROP2:%.*]] = or <4 x i64> zeroinitializer, [[TMP13]]11477; CHECK-NEXT: [[TMP2:%.*]] = fsub <4 x double> splat (double -0.000000e+00), [[X2]]11478; CHECK-NEXT: [[_MSPROP3:%.*]] = or <4 x i64> [[TMP6]], [[TMP10]]11479; CHECK-NEXT: [[_MSPROP4:%.*]] = or <4 x i64> [[_MSPROP3]], [[_MSPROP2]]11480; CHECK-NEXT: [[TMP3:%.*]] = call <4 x double> @llvm.fma.v4f64(<4 x double> [[X0]], <4 x double> [[X1]], <4 x double> [[TMP2]])11481; CHECK-NEXT: [[_MSPROP5:%.*]] = shufflevector <4 x i64> [[_MSPROP4]], <4 x i64> [[_MSPROP1]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>11482; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x double> [[TMP3]], <4 x double> [[TMP1]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>11483; CHECK-NEXT: [[TMP17:%.*]] = bitcast i8 [[TMP14]] to <8 x i1>11484; CHECK-NEXT: [[TMP5:%.*]] = bitcast i8 [[X3]] to <8 x i1>11485; CHECK-NEXT: [[_MSPROP6:%.*]] = shufflevector <8 x i1> [[TMP17]], <8 x i1> [[TMP17]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>11486; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP5]], <8 x i1> [[TMP5]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>11487; CHECK-NEXT: [[TMP11:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i64> [[_MSPROP5]], <4 x i64> [[TMP13]]11488; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x double> [[TMP4]] to <4 x i64>11489; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x double> [[X2]] to <4 x i64>11490; CHECK-NEXT: [[TMP9:%.*]] = xor <4 x i64> [[TMP7]], [[TMP8]]11491; CHECK-NEXT: [[TMP15:%.*]] = or <4 x i64> [[TMP9]], [[_MSPROP5]]11492; CHECK-NEXT: [[TMP16:%.*]] = or <4 x i64> [[TMP15]], [[TMP13]]11493; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP6]], <4 x i64> [[TMP16]], <4 x i64> [[TMP11]]11494; CHECK-NEXT: [[TMP12:%.*]] = select <4 x i1> [[EXTRACT]], <4 x double> [[TMP4]], <4 x double> [[X2]]11495; CHECK-NEXT: store <4 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 811496; CHECK-NEXT: ret <4 x double> [[TMP12]]11497;11498 %1 = call <4 x double> @llvm.fma.v4f64(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2)11499 %2 = fsub <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %x211500 %3 = call <4 x double> @llvm.fma.v4f64(<4 x double> %x0, <4 x double> %x1, <4 x double> %2)11501 %4 = shufflevector <4 x double> %3, <4 x double> %1, <4 x i32> <i32 0, i32 5, i32 2, i32 7>11502 %5 = bitcast i8 %x3 to <8 x i1>11503 %extract = shufflevector <8 x i1> %5, <8 x i1> %5, <4 x i32> <i32 0, i32 1, i32 2, i32 3>11504 %6 = select <4 x i1> %extract, <4 x double> %4, <4 x double> %x211505 ret <4 x double> %611506}11507 11508define <4 x double>@test_int_x86_avx512_maskz_vfmaddsub_pd_256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) #0 {11509;11510; CHECK-LABEL: define <4 x double> @test_int_x86_avx512_maskz_vfmaddsub_pd_256(11511; CHECK-SAME: <4 x double> [[X0:%.*]], <4 x double> [[X1:%.*]], <4 x double> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {11512; CHECK-NEXT: [[TMP6:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 811513; CHECK-NEXT: [[TMP12:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 811514; CHECK-NEXT: [[TMP13:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 811515; CHECK-NEXT: [[TMP14:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 811516; CHECK-NEXT: call void @llvm.donothing()11517; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i64> [[TMP6]], [[TMP12]]11518; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i64> [[_MSPROP]], [[TMP13]]11519; CHECK-NEXT: [[TMP1:%.*]] = call <4 x double> @llvm.fma.v4f64(<4 x double> [[X0]], <4 x double> [[X1]], <4 x double> [[X2]])11520; CHECK-NEXT: [[_MSPROP2:%.*]] = or <4 x i64> zeroinitializer, [[TMP13]]11521; CHECK-NEXT: [[TMP2:%.*]] = fsub <4 x double> splat (double -0.000000e+00), [[X2]]11522; CHECK-NEXT: [[_MSPROP3:%.*]] = or <4 x i64> [[TMP6]], [[TMP12]]11523; CHECK-NEXT: [[_MSPROP4:%.*]] = or <4 x i64> [[_MSPROP3]], [[_MSPROP2]]11524; CHECK-NEXT: [[TMP3:%.*]] = call <4 x double> @llvm.fma.v4f64(<4 x double> [[X0]], <4 x double> [[X1]], <4 x double> [[TMP2]])11525; CHECK-NEXT: [[_MSPROP5:%.*]] = shufflevector <4 x i64> [[_MSPROP4]], <4 x i64> [[_MSPROP1]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>11526; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x double> [[TMP3]], <4 x double> [[TMP1]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>11527; CHECK-NEXT: [[TMP15:%.*]] = bitcast i8 [[TMP14]] to <8 x i1>11528; CHECK-NEXT: [[TMP5:%.*]] = bitcast i8 [[X3]] to <8 x i1>11529; CHECK-NEXT: [[_MSPROP6:%.*]] = shufflevector <8 x i1> [[TMP15]], <8 x i1> [[TMP15]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>11530; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP5]], <8 x i1> [[TMP5]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>11531; CHECK-NEXT: [[TMP16:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i64> [[_MSPROP5]], <4 x i64> zeroinitializer11532; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x double> [[TMP4]] to <4 x i64>11533; CHECK-NEXT: [[TMP8:%.*]] = xor <4 x i64> [[TMP7]], zeroinitializer11534; CHECK-NEXT: [[TMP9:%.*]] = or <4 x i64> [[TMP8]], [[_MSPROP5]]11535; CHECK-NEXT: [[TMP10:%.*]] = or <4 x i64> [[TMP9]], zeroinitializer11536; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP6]], <4 x i64> [[TMP10]], <4 x i64> [[TMP16]]11537; CHECK-NEXT: [[TMP11:%.*]] = select <4 x i1> [[EXTRACT]], <4 x double> [[TMP4]], <4 x double> zeroinitializer11538; CHECK-NEXT: store <4 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 811539; CHECK-NEXT: ret <4 x double> [[TMP11]]11540;11541 %1 = call <4 x double> @llvm.fma.v4f64(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2)11542 %2 = fsub <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %x211543 %3 = call <4 x double> @llvm.fma.v4f64(<4 x double> %x0, <4 x double> %x1, <4 x double> %2)11544 %4 = shufflevector <4 x double> %3, <4 x double> %1, <4 x i32> <i32 0, i32 5, i32 2, i32 7>11545 %5 = bitcast i8 %x3 to <8 x i1>11546 %extract = shufflevector <8 x i1> %5, <8 x i1> %5, <4 x i32> <i32 0, i32 1, i32 2, i32 3>11547 %6 = select <4 x i1> %extract, <4 x double> %4, <4 x double> zeroinitializer11548 ret <4 x double> %611549}11550 11551define <4 x float>@test_int_x86_avx512_mask3_vfmaddsub_ps_128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) #0 {11552;11553; CHECK-LABEL: define <4 x float> @test_int_x86_avx512_mask3_vfmaddsub_ps_128(11554; CHECK-SAME: <4 x float> [[X0:%.*]], <4 x float> [[X1:%.*]], <4 x float> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {11555; CHECK-NEXT: [[TMP6:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 811556; CHECK-NEXT: [[TMP10:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 811557; CHECK-NEXT: [[TMP13:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 811558; CHECK-NEXT: [[TMP14:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 811559; CHECK-NEXT: call void @llvm.donothing()11560; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP6]], [[TMP10]]11561; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i32> [[_MSPROP]], [[TMP13]]11562; CHECK-NEXT: [[TMP1:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[X0]], <4 x float> [[X1]], <4 x float> [[X2]])11563; CHECK-NEXT: [[_MSPROP2:%.*]] = or <4 x i32> zeroinitializer, [[TMP13]]11564; CHECK-NEXT: [[TMP2:%.*]] = fsub <4 x float> splat (float -0.000000e+00), [[X2]]11565; CHECK-NEXT: [[_MSPROP3:%.*]] = or <4 x i32> [[TMP6]], [[TMP10]]11566; CHECK-NEXT: [[_MSPROP4:%.*]] = or <4 x i32> [[_MSPROP3]], [[_MSPROP2]]11567; CHECK-NEXT: [[TMP3:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[X0]], <4 x float> [[X1]], <4 x float> [[TMP2]])11568; CHECK-NEXT: [[_MSPROP5:%.*]] = shufflevector <4 x i32> [[_MSPROP4]], <4 x i32> [[_MSPROP1]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>11569; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x float> [[TMP3]], <4 x float> [[TMP1]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>11570; CHECK-NEXT: [[TMP17:%.*]] = bitcast i8 [[TMP14]] to <8 x i1>11571; CHECK-NEXT: [[TMP5:%.*]] = bitcast i8 [[X3]] to <8 x i1>11572; CHECK-NEXT: [[_MSPROP6:%.*]] = shufflevector <8 x i1> [[TMP17]], <8 x i1> [[TMP17]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>11573; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP5]], <8 x i1> [[TMP5]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>11574; CHECK-NEXT: [[TMP11:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i32> [[_MSPROP5]], <4 x i32> [[TMP13]]11575; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x float> [[TMP4]] to <4 x i32>11576; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x float> [[X2]] to <4 x i32>11577; CHECK-NEXT: [[TMP9:%.*]] = xor <4 x i32> [[TMP7]], [[TMP8]]11578; CHECK-NEXT: [[TMP15:%.*]] = or <4 x i32> [[TMP9]], [[_MSPROP5]]11579; CHECK-NEXT: [[TMP16:%.*]] = or <4 x i32> [[TMP15]], [[TMP13]]11580; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP6]], <4 x i32> [[TMP16]], <4 x i32> [[TMP11]]11581; CHECK-NEXT: [[TMP12:%.*]] = select <4 x i1> [[EXTRACT]], <4 x float> [[TMP4]], <4 x float> [[X2]]11582; CHECK-NEXT: store <4 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 811583; CHECK-NEXT: ret <4 x float> [[TMP12]]11584;11585 %1 = call <4 x float> @llvm.fma.v4f32(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2)11586 %2 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %x211587 %3 = call <4 x float> @llvm.fma.v4f32(<4 x float> %x0, <4 x float> %x1, <4 x float> %2)11588 %4 = shufflevector <4 x float> %3, <4 x float> %1, <4 x i32> <i32 0, i32 5, i32 2, i32 7>11589 %5 = bitcast i8 %x3 to <8 x i1>11590 %extract = shufflevector <8 x i1> %5, <8 x i1> %5, <4 x i32> <i32 0, i32 1, i32 2, i32 3>11591 %6 = select <4 x i1> %extract, <4 x float> %4, <4 x float> %x211592 ret <4 x float> %611593}11594 11595define <4 x float>@test_int_x86_avx512_maskz_vfmaddsub_ps_128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) #0 {11596;11597; CHECK-LABEL: define <4 x float> @test_int_x86_avx512_maskz_vfmaddsub_ps_128(11598; CHECK-SAME: <4 x float> [[X0:%.*]], <4 x float> [[X1:%.*]], <4 x float> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {11599; CHECK-NEXT: [[TMP6:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 811600; CHECK-NEXT: [[TMP12:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 811601; CHECK-NEXT: [[TMP13:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 811602; CHECK-NEXT: [[TMP14:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 811603; CHECK-NEXT: call void @llvm.donothing()11604; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP6]], [[TMP12]]11605; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i32> [[_MSPROP]], [[TMP13]]11606; CHECK-NEXT: [[TMP1:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[X0]], <4 x float> [[X1]], <4 x float> [[X2]])11607; CHECK-NEXT: [[_MSPROP2:%.*]] = or <4 x i32> zeroinitializer, [[TMP13]]11608; CHECK-NEXT: [[TMP2:%.*]] = fsub <4 x float> splat (float -0.000000e+00), [[X2]]11609; CHECK-NEXT: [[_MSPROP3:%.*]] = or <4 x i32> [[TMP6]], [[TMP12]]11610; CHECK-NEXT: [[_MSPROP4:%.*]] = or <4 x i32> [[_MSPROP3]], [[_MSPROP2]]11611; CHECK-NEXT: [[TMP3:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[X0]], <4 x float> [[X1]], <4 x float> [[TMP2]])11612; CHECK-NEXT: [[_MSPROP5:%.*]] = shufflevector <4 x i32> [[_MSPROP4]], <4 x i32> [[_MSPROP1]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>11613; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x float> [[TMP3]], <4 x float> [[TMP1]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>11614; CHECK-NEXT: [[TMP15:%.*]] = bitcast i8 [[TMP14]] to <8 x i1>11615; CHECK-NEXT: [[TMP5:%.*]] = bitcast i8 [[X3]] to <8 x i1>11616; CHECK-NEXT: [[_MSPROP6:%.*]] = shufflevector <8 x i1> [[TMP15]], <8 x i1> [[TMP15]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>11617; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP5]], <8 x i1> [[TMP5]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>11618; CHECK-NEXT: [[TMP16:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i32> [[_MSPROP5]], <4 x i32> zeroinitializer11619; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x float> [[TMP4]] to <4 x i32>11620; CHECK-NEXT: [[TMP8:%.*]] = xor <4 x i32> [[TMP7]], zeroinitializer11621; CHECK-NEXT: [[TMP9:%.*]] = or <4 x i32> [[TMP8]], [[_MSPROP5]]11622; CHECK-NEXT: [[TMP10:%.*]] = or <4 x i32> [[TMP9]], zeroinitializer11623; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP6]], <4 x i32> [[TMP10]], <4 x i32> [[TMP16]]11624; CHECK-NEXT: [[TMP11:%.*]] = select <4 x i1> [[EXTRACT]], <4 x float> [[TMP4]], <4 x float> zeroinitializer11625; CHECK-NEXT: store <4 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 811626; CHECK-NEXT: ret <4 x float> [[TMP11]]11627;11628 %1 = call <4 x float> @llvm.fma.v4f32(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2)11629 %2 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %x211630 %3 = call <4 x float> @llvm.fma.v4f32(<4 x float> %x0, <4 x float> %x1, <4 x float> %2)11631 %4 = shufflevector <4 x float> %3, <4 x float> %1, <4 x i32> <i32 0, i32 5, i32 2, i32 7>11632 %5 = bitcast i8 %x3 to <8 x i1>11633 %extract = shufflevector <8 x i1> %5, <8 x i1> %5, <4 x i32> <i32 0, i32 1, i32 2, i32 3>11634 %6 = select <4 x i1> %extract, <4 x float> %4, <4 x float> zeroinitializer11635 ret <4 x float> %611636}11637 11638define <8 x float>@test_int_x86_avx512_mask3_vfmaddsub_ps_256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) #0 {11639;11640; CHECK-LABEL: define <8 x float> @test_int_x86_avx512_mask3_vfmaddsub_ps_256(11641; CHECK-SAME: <8 x float> [[X0:%.*]], <8 x float> [[X1:%.*]], <8 x float> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {11642; CHECK-NEXT: [[TMP6:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 811643; CHECK-NEXT: [[TMP10:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 811644; CHECK-NEXT: [[TMP13:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 811645; CHECK-NEXT: [[TMP14:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 811646; CHECK-NEXT: call void @llvm.donothing()11647; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> [[TMP6]], [[TMP10]]11648; CHECK-NEXT: [[_MSPROP1:%.*]] = or <8 x i32> [[_MSPROP]], [[TMP13]]11649; CHECK-NEXT: [[TMP1:%.*]] = call <8 x float> @llvm.fma.v8f32(<8 x float> [[X0]], <8 x float> [[X1]], <8 x float> [[X2]])11650; CHECK-NEXT: [[_MSPROP2:%.*]] = or <8 x i32> zeroinitializer, [[TMP13]]11651; CHECK-NEXT: [[TMP2:%.*]] = fsub <8 x float> splat (float -0.000000e+00), [[X2]]11652; CHECK-NEXT: [[_MSPROP3:%.*]] = or <8 x i32> [[TMP6]], [[TMP10]]11653; CHECK-NEXT: [[_MSPROP4:%.*]] = or <8 x i32> [[_MSPROP3]], [[_MSPROP2]]11654; CHECK-NEXT: [[TMP3:%.*]] = call <8 x float> @llvm.fma.v8f32(<8 x float> [[X0]], <8 x float> [[X1]], <8 x float> [[TMP2]])11655; CHECK-NEXT: [[_MSPROP5:%.*]] = shufflevector <8 x i32> [[_MSPROP4]], <8 x i32> [[_MSPROP1]], <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>11656; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <8 x float> [[TMP3]], <8 x float> [[TMP1]], <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>11657; CHECK-NEXT: [[TMP17:%.*]] = bitcast i8 [[TMP14]] to <8 x i1>11658; CHECK-NEXT: [[TMP5:%.*]] = bitcast i8 [[X3]] to <8 x i1>11659; CHECK-NEXT: [[TMP11:%.*]] = select <8 x i1> [[TMP5]], <8 x i32> [[_MSPROP5]], <8 x i32> [[TMP13]]11660; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x float> [[TMP4]] to <8 x i32>11661; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x float> [[X2]] to <8 x i32>11662; CHECK-NEXT: [[TMP9:%.*]] = xor <8 x i32> [[TMP7]], [[TMP8]]11663; CHECK-NEXT: [[TMP15:%.*]] = or <8 x i32> [[TMP9]], [[_MSPROP5]]11664; CHECK-NEXT: [[TMP16:%.*]] = or <8 x i32> [[TMP15]], [[TMP13]]11665; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP17]], <8 x i32> [[TMP16]], <8 x i32> [[TMP11]]11666; CHECK-NEXT: [[TMP12:%.*]] = select <8 x i1> [[TMP5]], <8 x float> [[TMP4]], <8 x float> [[X2]]11667; CHECK-NEXT: store <8 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 811668; CHECK-NEXT: ret <8 x float> [[TMP12]]11669;11670 %1 = call <8 x float> @llvm.fma.v8f32(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2)11671 %2 = fsub <8 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %x211672 %3 = call <8 x float> @llvm.fma.v8f32(<8 x float> %x0, <8 x float> %x1, <8 x float> %2)11673 %4 = shufflevector <8 x float> %3, <8 x float> %1, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>11674 %5 = bitcast i8 %x3 to <8 x i1>11675 %6 = select <8 x i1> %5, <8 x float> %4, <8 x float> %x211676 ret <8 x float> %611677}11678 11679define <8 x float>@test_int_x86_avx512_maskz_vfmaddsub_ps_256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) #0 {11680;11681; CHECK-LABEL: define <8 x float> @test_int_x86_avx512_maskz_vfmaddsub_ps_256(11682; CHECK-SAME: <8 x float> [[X0:%.*]], <8 x float> [[X1:%.*]], <8 x float> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {11683; CHECK-NEXT: [[TMP6:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 811684; CHECK-NEXT: [[TMP12:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 811685; CHECK-NEXT: [[TMP13:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 811686; CHECK-NEXT: [[TMP14:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 811687; CHECK-NEXT: call void @llvm.donothing()11688; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> [[TMP6]], [[TMP12]]11689; CHECK-NEXT: [[_MSPROP1:%.*]] = or <8 x i32> [[_MSPROP]], [[TMP13]]11690; CHECK-NEXT: [[TMP1:%.*]] = call <8 x float> @llvm.fma.v8f32(<8 x float> [[X0]], <8 x float> [[X1]], <8 x float> [[X2]])11691; CHECK-NEXT: [[_MSPROP2:%.*]] = or <8 x i32> zeroinitializer, [[TMP13]]11692; CHECK-NEXT: [[TMP2:%.*]] = fsub <8 x float> splat (float -0.000000e+00), [[X2]]11693; CHECK-NEXT: [[_MSPROP3:%.*]] = or <8 x i32> [[TMP6]], [[TMP12]]11694; CHECK-NEXT: [[_MSPROP4:%.*]] = or <8 x i32> [[_MSPROP3]], [[_MSPROP2]]11695; CHECK-NEXT: [[TMP3:%.*]] = call <8 x float> @llvm.fma.v8f32(<8 x float> [[X0]], <8 x float> [[X1]], <8 x float> [[TMP2]])11696; CHECK-NEXT: [[_MSPROP5:%.*]] = shufflevector <8 x i32> [[_MSPROP4]], <8 x i32> [[_MSPROP1]], <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>11697; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <8 x float> [[TMP3]], <8 x float> [[TMP1]], <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>11698; CHECK-NEXT: [[TMP15:%.*]] = bitcast i8 [[TMP14]] to <8 x i1>11699; CHECK-NEXT: [[TMP5:%.*]] = bitcast i8 [[X3]] to <8 x i1>11700; CHECK-NEXT: [[TMP16:%.*]] = select <8 x i1> [[TMP5]], <8 x i32> [[_MSPROP5]], <8 x i32> zeroinitializer11701; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x float> [[TMP4]] to <8 x i32>11702; CHECK-NEXT: [[TMP8:%.*]] = xor <8 x i32> [[TMP7]], zeroinitializer11703; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i32> [[TMP8]], [[_MSPROP5]]11704; CHECK-NEXT: [[TMP10:%.*]] = or <8 x i32> [[TMP9]], zeroinitializer11705; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP15]], <8 x i32> [[TMP10]], <8 x i32> [[TMP16]]11706; CHECK-NEXT: [[TMP11:%.*]] = select <8 x i1> [[TMP5]], <8 x float> [[TMP4]], <8 x float> zeroinitializer11707; CHECK-NEXT: store <8 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 811708; CHECK-NEXT: ret <8 x float> [[TMP11]]11709;11710 %1 = call <8 x float> @llvm.fma.v8f32(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2)11711 %2 = fsub <8 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %x211712 %3 = call <8 x float> @llvm.fma.v8f32(<8 x float> %x0, <8 x float> %x1, <8 x float> %2)11713 %4 = shufflevector <8 x float> %3, <8 x float> %1, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>11714 %5 = bitcast i8 %x3 to <8 x i1>11715 %6 = select <8 x i1> %5, <8 x float> %4, <8 x float> zeroinitializer11716 ret <8 x float> %611717}11718 11719define <2 x double>@test_int_x86_avx512_mask3_vfmsubadd_pd_128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) #0 {11720;11721; CHECK-LABEL: define <2 x double> @test_int_x86_avx512_mask3_vfmsubadd_pd_128(11722; CHECK-SAME: <2 x double> [[X0:%.*]], <2 x double> [[X1:%.*]], <2 x double> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {11723; CHECK-NEXT: [[TMP6:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 811724; CHECK-NEXT: [[TMP10:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 811725; CHECK-NEXT: [[TMP13:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 811726; CHECK-NEXT: [[TMP14:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 811727; CHECK-NEXT: call void @llvm.donothing()11728; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP6]], [[TMP10]]11729; CHECK-NEXT: [[_MSPROP1:%.*]] = or <2 x i64> [[_MSPROP]], [[TMP13]]11730; CHECK-NEXT: [[TMP1:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> [[X0]], <2 x double> [[X1]], <2 x double> [[X2]])11731; CHECK-NEXT: [[_MSPROP2:%.*]] = or <2 x i64> zeroinitializer, [[TMP13]]11732; CHECK-NEXT: [[TMP2:%.*]] = fsub <2 x double> splat (double -0.000000e+00), [[X2]]11733; CHECK-NEXT: [[_MSPROP3:%.*]] = or <2 x i64> [[TMP6]], [[TMP10]]11734; CHECK-NEXT: [[_MSPROP4:%.*]] = or <2 x i64> [[_MSPROP3]], [[_MSPROP2]]11735; CHECK-NEXT: [[TMP3:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> [[X0]], <2 x double> [[X1]], <2 x double> [[TMP2]])11736; CHECK-NEXT: [[_MSPROP5:%.*]] = shufflevector <2 x i64> [[_MSPROP1]], <2 x i64> [[_MSPROP4]], <2 x i32> <i32 0, i32 3>11737; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x double> [[TMP1]], <2 x double> [[TMP3]], <2 x i32> <i32 0, i32 3>11738; CHECK-NEXT: [[TMP17:%.*]] = bitcast i8 [[TMP14]] to <8 x i1>11739; CHECK-NEXT: [[TMP5:%.*]] = bitcast i8 [[X3]] to <8 x i1>11740; CHECK-NEXT: [[_MSPROP6:%.*]] = shufflevector <8 x i1> [[TMP17]], <8 x i1> [[TMP17]], <2 x i32> <i32 0, i32 1>11741; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP5]], <8 x i1> [[TMP5]], <2 x i32> <i32 0, i32 1>11742; CHECK-NEXT: [[TMP11:%.*]] = select <2 x i1> [[EXTRACT]], <2 x i64> [[_MSPROP5]], <2 x i64> [[TMP13]]11743; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x double> [[TMP4]] to <2 x i64>11744; CHECK-NEXT: [[TMP8:%.*]] = bitcast <2 x double> [[X2]] to <2 x i64>11745; CHECK-NEXT: [[TMP9:%.*]] = xor <2 x i64> [[TMP7]], [[TMP8]]11746; CHECK-NEXT: [[TMP15:%.*]] = or <2 x i64> [[TMP9]], [[_MSPROP5]]11747; CHECK-NEXT: [[TMP16:%.*]] = or <2 x i64> [[TMP15]], [[TMP13]]11748; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <2 x i1> [[_MSPROP6]], <2 x i64> [[TMP16]], <2 x i64> [[TMP11]]11749; CHECK-NEXT: [[TMP12:%.*]] = select <2 x i1> [[EXTRACT]], <2 x double> [[TMP4]], <2 x double> [[X2]]11750; CHECK-NEXT: store <2 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 811751; CHECK-NEXT: ret <2 x double> [[TMP12]]11752;11753 %1 = call <2 x double> @llvm.fma.v2f64(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2)11754 %2 = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %x211755 %3 = call <2 x double> @llvm.fma.v2f64(<2 x double> %x0, <2 x double> %x1, <2 x double> %2)11756 %4 = shufflevector <2 x double> %1, <2 x double> %3, <2 x i32> <i32 0, i32 3>11757 %5 = bitcast i8 %x3 to <8 x i1>11758 %extract = shufflevector <8 x i1> %5, <8 x i1> %5, <2 x i32> <i32 0, i32 1>11759 %6 = select <2 x i1> %extract, <2 x double> %4, <2 x double> %x211760 ret <2 x double> %611761}11762 11763define <4 x double>@test_int_x86_avx512_mask3_vfmsubadd_pd_256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) #0 {11764;11765; CHECK-LABEL: define <4 x double> @test_int_x86_avx512_mask3_vfmsubadd_pd_256(11766; CHECK-SAME: <4 x double> [[X0:%.*]], <4 x double> [[X1:%.*]], <4 x double> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {11767; CHECK-NEXT: [[TMP6:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 811768; CHECK-NEXT: [[TMP10:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 811769; CHECK-NEXT: [[TMP13:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 811770; CHECK-NEXT: [[TMP14:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 811771; CHECK-NEXT: call void @llvm.donothing()11772; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i64> [[TMP6]], [[TMP10]]11773; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i64> [[_MSPROP]], [[TMP13]]11774; CHECK-NEXT: [[TMP1:%.*]] = call <4 x double> @llvm.fma.v4f64(<4 x double> [[X0]], <4 x double> [[X1]], <4 x double> [[X2]])11775; CHECK-NEXT: [[_MSPROP2:%.*]] = or <4 x i64> zeroinitializer, [[TMP13]]11776; CHECK-NEXT: [[TMP2:%.*]] = fsub <4 x double> splat (double -0.000000e+00), [[X2]]11777; CHECK-NEXT: [[_MSPROP3:%.*]] = or <4 x i64> [[TMP6]], [[TMP10]]11778; CHECK-NEXT: [[_MSPROP4:%.*]] = or <4 x i64> [[_MSPROP3]], [[_MSPROP2]]11779; CHECK-NEXT: [[TMP3:%.*]] = call <4 x double> @llvm.fma.v4f64(<4 x double> [[X0]], <4 x double> [[X1]], <4 x double> [[TMP2]])11780; CHECK-NEXT: [[_MSPROP5:%.*]] = shufflevector <4 x i64> [[_MSPROP1]], <4 x i64> [[_MSPROP4]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>11781; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x double> [[TMP1]], <4 x double> [[TMP3]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>11782; CHECK-NEXT: [[TMP17:%.*]] = bitcast i8 [[TMP14]] to <8 x i1>11783; CHECK-NEXT: [[TMP5:%.*]] = bitcast i8 [[X3]] to <8 x i1>11784; CHECK-NEXT: [[_MSPROP6:%.*]] = shufflevector <8 x i1> [[TMP17]], <8 x i1> [[TMP17]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>11785; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP5]], <8 x i1> [[TMP5]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>11786; CHECK-NEXT: [[TMP11:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i64> [[_MSPROP5]], <4 x i64> [[TMP13]]11787; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x double> [[TMP4]] to <4 x i64>11788; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x double> [[X2]] to <4 x i64>11789; CHECK-NEXT: [[TMP9:%.*]] = xor <4 x i64> [[TMP7]], [[TMP8]]11790; CHECK-NEXT: [[TMP15:%.*]] = or <4 x i64> [[TMP9]], [[_MSPROP5]]11791; CHECK-NEXT: [[TMP16:%.*]] = or <4 x i64> [[TMP15]], [[TMP13]]11792; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP6]], <4 x i64> [[TMP16]], <4 x i64> [[TMP11]]11793; CHECK-NEXT: [[TMP12:%.*]] = select <4 x i1> [[EXTRACT]], <4 x double> [[TMP4]], <4 x double> [[X2]]11794; CHECK-NEXT: store <4 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 811795; CHECK-NEXT: ret <4 x double> [[TMP12]]11796;11797 %1 = call <4 x double> @llvm.fma.v4f64(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2)11798 %2 = fsub <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %x211799 %3 = call <4 x double> @llvm.fma.v4f64(<4 x double> %x0, <4 x double> %x1, <4 x double> %2)11800 %4 = shufflevector <4 x double> %1, <4 x double> %3, <4 x i32> <i32 0, i32 5, i32 2, i32 7>11801 %5 = bitcast i8 %x3 to <8 x i1>11802 %extract = shufflevector <8 x i1> %5, <8 x i1> %5, <4 x i32> <i32 0, i32 1, i32 2, i32 3>11803 %6 = select <4 x i1> %extract, <4 x double> %4, <4 x double> %x211804 ret <4 x double> %611805}11806 11807define <4 x float>@test_int_x86_avx512_mask3_vfmsubadd_ps_128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) #0 {11808;11809; CHECK-LABEL: define <4 x float> @test_int_x86_avx512_mask3_vfmsubadd_ps_128(11810; CHECK-SAME: <4 x float> [[X0:%.*]], <4 x float> [[X1:%.*]], <4 x float> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {11811; CHECK-NEXT: [[TMP6:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 811812; CHECK-NEXT: [[TMP10:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 811813; CHECK-NEXT: [[TMP13:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 811814; CHECK-NEXT: [[TMP14:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 811815; CHECK-NEXT: call void @llvm.donothing()11816; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP6]], [[TMP10]]11817; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i32> [[_MSPROP]], [[TMP13]]11818; CHECK-NEXT: [[TMP1:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[X0]], <4 x float> [[X1]], <4 x float> [[X2]])11819; CHECK-NEXT: [[_MSPROP2:%.*]] = or <4 x i32> zeroinitializer, [[TMP13]]11820; CHECK-NEXT: [[TMP2:%.*]] = fsub <4 x float> splat (float -0.000000e+00), [[X2]]11821; CHECK-NEXT: [[_MSPROP3:%.*]] = or <4 x i32> [[TMP6]], [[TMP10]]11822; CHECK-NEXT: [[_MSPROP4:%.*]] = or <4 x i32> [[_MSPROP3]], [[_MSPROP2]]11823; CHECK-NEXT: [[TMP3:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[X0]], <4 x float> [[X1]], <4 x float> [[TMP2]])11824; CHECK-NEXT: [[_MSPROP5:%.*]] = shufflevector <4 x i32> [[_MSPROP1]], <4 x i32> [[_MSPROP4]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>11825; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> [[TMP3]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>11826; CHECK-NEXT: [[TMP17:%.*]] = bitcast i8 [[TMP14]] to <8 x i1>11827; CHECK-NEXT: [[TMP5:%.*]] = bitcast i8 [[X3]] to <8 x i1>11828; CHECK-NEXT: [[_MSPROP6:%.*]] = shufflevector <8 x i1> [[TMP17]], <8 x i1> [[TMP17]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>11829; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP5]], <8 x i1> [[TMP5]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>11830; CHECK-NEXT: [[TMP11:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i32> [[_MSPROP5]], <4 x i32> [[TMP13]]11831; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x float> [[TMP4]] to <4 x i32>11832; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x float> [[X2]] to <4 x i32>11833; CHECK-NEXT: [[TMP9:%.*]] = xor <4 x i32> [[TMP7]], [[TMP8]]11834; CHECK-NEXT: [[TMP15:%.*]] = or <4 x i32> [[TMP9]], [[_MSPROP5]]11835; CHECK-NEXT: [[TMP16:%.*]] = or <4 x i32> [[TMP15]], [[TMP13]]11836; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP6]], <4 x i32> [[TMP16]], <4 x i32> [[TMP11]]11837; CHECK-NEXT: [[TMP12:%.*]] = select <4 x i1> [[EXTRACT]], <4 x float> [[TMP4]], <4 x float> [[X2]]11838; CHECK-NEXT: store <4 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 811839; CHECK-NEXT: ret <4 x float> [[TMP12]]11840;11841 %1 = call <4 x float> @llvm.fma.v4f32(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2)11842 %2 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %x211843 %3 = call <4 x float> @llvm.fma.v4f32(<4 x float> %x0, <4 x float> %x1, <4 x float> %2)11844 %4 = shufflevector <4 x float> %1, <4 x float> %3, <4 x i32> <i32 0, i32 5, i32 2, i32 7>11845 %5 = bitcast i8 %x3 to <8 x i1>11846 %extract = shufflevector <8 x i1> %5, <8 x i1> %5, <4 x i32> <i32 0, i32 1, i32 2, i32 3>11847 %6 = select <4 x i1> %extract, <4 x float> %4, <4 x float> %x211848 ret <4 x float> %611849}11850 11851define <8 x float>@test_int_x86_avx512_mask3_vfmsubadd_ps_256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) #0 {11852;11853; CHECK-LABEL: define <8 x float> @test_int_x86_avx512_mask3_vfmsubadd_ps_256(11854; CHECK-SAME: <8 x float> [[X0:%.*]], <8 x float> [[X1:%.*]], <8 x float> [[X2:%.*]], i8 [[X3:%.*]]) #[[ATTR0]] {11855; CHECK-NEXT: [[TMP6:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 811856; CHECK-NEXT: [[TMP10:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 811857; CHECK-NEXT: [[TMP13:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 811858; CHECK-NEXT: [[TMP14:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 811859; CHECK-NEXT: call void @llvm.donothing()11860; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> [[TMP6]], [[TMP10]]11861; CHECK-NEXT: [[_MSPROP1:%.*]] = or <8 x i32> [[_MSPROP]], [[TMP13]]11862; CHECK-NEXT: [[TMP1:%.*]] = call <8 x float> @llvm.fma.v8f32(<8 x float> [[X0]], <8 x float> [[X1]], <8 x float> [[X2]])11863; CHECK-NEXT: [[_MSPROP2:%.*]] = or <8 x i32> zeroinitializer, [[TMP13]]11864; CHECK-NEXT: [[TMP2:%.*]] = fsub <8 x float> splat (float -0.000000e+00), [[X2]]11865; CHECK-NEXT: [[_MSPROP3:%.*]] = or <8 x i32> [[TMP6]], [[TMP10]]11866; CHECK-NEXT: [[_MSPROP4:%.*]] = or <8 x i32> [[_MSPROP3]], [[_MSPROP2]]11867; CHECK-NEXT: [[TMP3:%.*]] = call <8 x float> @llvm.fma.v8f32(<8 x float> [[X0]], <8 x float> [[X1]], <8 x float> [[TMP2]])11868; CHECK-NEXT: [[_MSPROP5:%.*]] = shufflevector <8 x i32> [[_MSPROP1]], <8 x i32> [[_MSPROP4]], <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>11869; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <8 x float> [[TMP1]], <8 x float> [[TMP3]], <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>11870; CHECK-NEXT: [[TMP17:%.*]] = bitcast i8 [[TMP14]] to <8 x i1>11871; CHECK-NEXT: [[TMP5:%.*]] = bitcast i8 [[X3]] to <8 x i1>11872; CHECK-NEXT: [[TMP11:%.*]] = select <8 x i1> [[TMP5]], <8 x i32> [[_MSPROP5]], <8 x i32> [[TMP13]]11873; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x float> [[TMP4]] to <8 x i32>11874; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x float> [[X2]] to <8 x i32>11875; CHECK-NEXT: [[TMP9:%.*]] = xor <8 x i32> [[TMP7]], [[TMP8]]11876; CHECK-NEXT: [[TMP15:%.*]] = or <8 x i32> [[TMP9]], [[_MSPROP5]]11877; CHECK-NEXT: [[TMP16:%.*]] = or <8 x i32> [[TMP15]], [[TMP13]]11878; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP17]], <8 x i32> [[TMP16]], <8 x i32> [[TMP11]]11879; CHECK-NEXT: [[TMP12:%.*]] = select <8 x i1> [[TMP5]], <8 x float> [[TMP4]], <8 x float> [[X2]]11880; CHECK-NEXT: store <8 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 811881; CHECK-NEXT: ret <8 x float> [[TMP12]]11882;11883 %1 = call <8 x float> @llvm.fma.v8f32(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2)11884 %2 = fsub <8 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %x211885 %3 = call <8 x float> @llvm.fma.v8f32(<8 x float> %x0, <8 x float> %x1, <8 x float> %2)11886 %4 = shufflevector <8 x float> %1, <8 x float> %3, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>11887 %5 = bitcast i8 %x3 to <8 x i1>11888 %6 = select <8 x i1> %5, <8 x float> %4, <8 x float> %x211889 ret <8 x float> %611890}11891 11892define <4 x float> @test_mask_vfmadd128_ps_rmk(<4 x float> %a0, <4 x float> %a1, ptr %ptr_a2, i8 %mask) #0 {11893;11894; CHECK-LABEL: define <4 x float> @test_mask_vfmadd128_ps_rmk(11895; CHECK-SAME: <4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], ptr [[PTR_A2:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {11896; CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 811897; CHECK-NEXT: [[TMP12:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 811898; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 811899; CHECK-NEXT: [[TMP14:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 811900; CHECK-NEXT: call void @llvm.donothing()11901; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP10]], 011902; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]11903; CHECK: [[BB5]]:11904; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]11905; CHECK-NEXT: unreachable11906; CHECK: [[BB6]]:11907; CHECK-NEXT: [[A2:%.*]] = load <4 x float>, ptr [[PTR_A2]], align 1611908; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[PTR_A2]] to i6411909; CHECK-NEXT: [[TMP8:%.*]] = xor i64 [[TMP7]], 8796093022208011910; CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP8]] to ptr11911; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP15]], align 1611912; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP12]], [[TMP3]]11913; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i32> [[_MSPROP]], [[_MSLD]]11914; CHECK-NEXT: [[TMP1:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[A0]], <4 x float> [[A1]], <4 x float> [[A2]])11915; CHECK-NEXT: [[TMP11:%.*]] = bitcast i8 [[TMP14]] to <8 x i1>11916; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[MASK]] to <8 x i1>11917; CHECK-NEXT: [[_MSPROP2:%.*]] = shufflevector <8 x i1> [[TMP11]], <8 x i1> [[TMP11]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>11918; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> [[TMP2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>11919; CHECK-NEXT: [[TMP13:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i32> [[_MSPROP1]], <4 x i32> [[TMP12]]11920; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x float> [[TMP1]] to <4 x i32>11921; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x float> [[A0]] to <4 x i32>11922; CHECK-NEXT: [[TMP6:%.*]] = xor <4 x i32> [[TMP4]], [[TMP5]]11923; CHECK-NEXT: [[TMP17:%.*]] = or <4 x i32> [[TMP6]], [[_MSPROP1]]11924; CHECK-NEXT: [[TMP18:%.*]] = or <4 x i32> [[TMP17]], [[TMP12]]11925; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP2]], <4 x i32> [[TMP18]], <4 x i32> [[TMP13]]11926; CHECK-NEXT: [[TMP9:%.*]] = select <4 x i1> [[EXTRACT]], <4 x float> [[TMP1]], <4 x float> [[A0]]11927; CHECK-NEXT: store <4 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 811928; CHECK-NEXT: ret <4 x float> [[TMP9]]11929;11930 %a2 = load <4 x float>, ptr %ptr_a211931 %1 = call <4 x float> @llvm.fma.v4f32(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2)11932 %2 = bitcast i8 %mask to <8 x i1>11933 %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>11934 %3 = select <4 x i1> %extract, <4 x float> %1, <4 x float> %a011935 ret <4 x float> %311936}11937 11938define <4 x float> @test_mask_vfmadd128_ps_rmka(<4 x float> %a0, <4 x float> %a1, ptr %ptr_a2, i8 %mask) #0 {11939;11940; CHECK-LABEL: define <4 x float> @test_mask_vfmadd128_ps_rmka(11941; CHECK-SAME: <4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], ptr [[PTR_A2:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {11942; CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 811943; CHECK-NEXT: [[TMP12:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 811944; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 811945; CHECK-NEXT: [[TMP14:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 811946; CHECK-NEXT: call void @llvm.donothing()11947; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP10]], 011948; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]11949; CHECK: [[BB5]]:11950; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]11951; CHECK-NEXT: unreachable11952; CHECK: [[BB6]]:11953; CHECK-NEXT: [[A2:%.*]] = load <4 x float>, ptr [[PTR_A2]], align 811954; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[PTR_A2]] to i6411955; CHECK-NEXT: [[TMP8:%.*]] = xor i64 [[TMP7]], 8796093022208011956; CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP8]] to ptr11957; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP15]], align 811958; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP12]], [[TMP3]]11959; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i32> [[_MSPROP]], [[_MSLD]]11960; CHECK-NEXT: [[TMP1:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[A0]], <4 x float> [[A1]], <4 x float> [[A2]])11961; CHECK-NEXT: [[TMP11:%.*]] = bitcast i8 [[TMP14]] to <8 x i1>11962; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[MASK]] to <8 x i1>11963; CHECK-NEXT: [[_MSPROP2:%.*]] = shufflevector <8 x i1> [[TMP11]], <8 x i1> [[TMP11]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>11964; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> [[TMP2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>11965; CHECK-NEXT: [[TMP13:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i32> [[_MSPROP1]], <4 x i32> [[TMP12]]11966; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x float> [[TMP1]] to <4 x i32>11967; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x float> [[A0]] to <4 x i32>11968; CHECK-NEXT: [[TMP6:%.*]] = xor <4 x i32> [[TMP4]], [[TMP5]]11969; CHECK-NEXT: [[TMP17:%.*]] = or <4 x i32> [[TMP6]], [[_MSPROP1]]11970; CHECK-NEXT: [[TMP18:%.*]] = or <4 x i32> [[TMP17]], [[TMP12]]11971; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP2]], <4 x i32> [[TMP18]], <4 x i32> [[TMP13]]11972; CHECK-NEXT: [[TMP9:%.*]] = select <4 x i1> [[EXTRACT]], <4 x float> [[TMP1]], <4 x float> [[A0]]11973; CHECK-NEXT: store <4 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 811974; CHECK-NEXT: ret <4 x float> [[TMP9]]11975;11976 %a2 = load <4 x float>, ptr %ptr_a2, align 811977 %1 = call <4 x float> @llvm.fma.v4f32(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2)11978 %2 = bitcast i8 %mask to <8 x i1>11979 %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>11980 %3 = select <4 x i1> %extract, <4 x float> %1, <4 x float> %a011981 ret <4 x float> %311982}11983 11984define <4 x float> @test_mask_vfmadd128_ps_rmkz(<4 x float> %a0, <4 x float> %a1, ptr %ptr_a2) #0 {11985;11986; CHECK-LABEL: define <4 x float> @test_mask_vfmadd128_ps_rmkz(11987; CHECK-SAME: <4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], ptr [[PTR_A2:%.*]]) #[[ATTR0]] {11988; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 811989; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 811990; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 811991; CHECK-NEXT: call void @llvm.donothing()11992; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP4]], 011993; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]11994; CHECK: [[BB4]]:11995; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]11996; CHECK-NEXT: unreachable11997; CHECK: [[BB5]]:11998; CHECK-NEXT: [[A2:%.*]] = load <4 x float>, ptr [[PTR_A2]], align 1611999; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[PTR_A2]] to i6412000; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 8796093022208012001; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr12002; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP8]], align 1612003; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP2]], [[TMP3]]12004; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i32> [[_MSPROP]], [[_MSLD]]12005; CHECK-NEXT: [[TMP1:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[A0]], <4 x float> [[A1]], <4 x float> [[A2]])12006; CHECK-NEXT: store <4 x i32> [[_MSPROP1]], ptr @__msan_retval_tls, align 812007; CHECK-NEXT: ret <4 x float> [[TMP1]]12008;12009 %a2 = load <4 x float>, ptr %ptr_a212010 %1 = call <4 x float> @llvm.fma.v4f32(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2)12011 ret <4 x float> %112012}12013 12014define <4 x float> @test_mask_vfmadd128_ps_rmkza(<4 x float> %a0, <4 x float> %a1, ptr %ptr_a2) #0 {12015;12016; CHECK-LABEL: define <4 x float> @test_mask_vfmadd128_ps_rmkza(12017; CHECK-SAME: <4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], ptr [[PTR_A2:%.*]]) #[[ATTR0]] {12018; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 812019; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 812020; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 812021; CHECK-NEXT: call void @llvm.donothing()12022; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP4]], 012023; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]12024; CHECK: [[BB4]]:12025; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]12026; CHECK-NEXT: unreachable12027; CHECK: [[BB5]]:12028; CHECK-NEXT: [[A2:%.*]] = load <4 x float>, ptr [[PTR_A2]], align 412029; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[PTR_A2]] to i6412030; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 8796093022208012031; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr12032; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP8]], align 412033; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP2]], [[TMP3]]12034; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i32> [[_MSPROP]], [[_MSLD]]12035; CHECK-NEXT: [[TMP1:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[A0]], <4 x float> [[A1]], <4 x float> [[A2]])12036; CHECK-NEXT: store <4 x i32> [[_MSPROP1]], ptr @__msan_retval_tls, align 812037; CHECK-NEXT: ret <4 x float> [[TMP1]]12038;12039 %a2 = load <4 x float>, ptr %ptr_a2, align 412040 %1 = call <4 x float> @llvm.fma.v4f32(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2)12041 ret <4 x float> %112042}12043 12044define <4 x float> @test_mask_vfmadd128_ps_rmb(<4 x float> %a0, <4 x float> %a1, ptr %ptr_a2, i8 %mask) #0 {12045;12046; CHECK-LABEL: define <4 x float> @test_mask_vfmadd128_ps_rmb(12047; CHECK-SAME: <4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], ptr [[PTR_A2:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {12048; CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 812049; CHECK-NEXT: [[TMP12:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 812050; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 812051; CHECK-NEXT: [[TMP14:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 812052; CHECK-NEXT: call void @llvm.donothing()12053; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP10]], 012054; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]12055; CHECK: [[BB5]]:12056; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]12057; CHECK-NEXT: unreachable12058; CHECK: [[BB6]]:12059; CHECK-NEXT: [[Q:%.*]] = load float, ptr [[PTR_A2]], align 412060; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[PTR_A2]] to i6412061; CHECK-NEXT: [[TMP8:%.*]] = xor i64 [[TMP7]], 8796093022208012062; CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP8]] to ptr12063; CHECK-NEXT: [[_MSLD:%.*]] = load i32, ptr [[TMP15]], align 412064; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <4 x i32> splat (i32 -1), i32 [[_MSLD]], i32 012065; CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x float> poison, float [[Q]], i32 012066; CHECK-NEXT: [[_MSPROP1:%.*]] = insertelement <4 x i32> [[_MSPROP]], i32 [[_MSLD]], i32 112067; CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], float [[Q]], i32 112068; CHECK-NEXT: [[_MSPROP2:%.*]] = insertelement <4 x i32> [[_MSPROP1]], i32 [[_MSLD]], i32 212069; CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <4 x float> [[VECINIT2_I]], float [[Q]], i32 212070; CHECK-NEXT: [[_MSPROP3:%.*]] = insertelement <4 x i32> [[_MSPROP2]], i32 [[_MSLD]], i32 312071; CHECK-NEXT: [[VECINIT6_I:%.*]] = insertelement <4 x float> [[VECINIT4_I]], float [[Q]], i32 312072; CHECK-NEXT: [[_MSPROP4:%.*]] = or <4 x i32> [[TMP12]], [[TMP3]]12073; CHECK-NEXT: [[_MSPROP5:%.*]] = or <4 x i32> [[_MSPROP4]], [[_MSPROP3]]12074; CHECK-NEXT: [[TMP1:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[A0]], <4 x float> [[A1]], <4 x float> [[VECINIT6_I]])12075; CHECK-NEXT: [[TMP11:%.*]] = bitcast i8 [[TMP14]] to <8 x i1>12076; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[MASK]] to <8 x i1>12077; CHECK-NEXT: [[_MSPROP6:%.*]] = shufflevector <8 x i1> [[TMP11]], <8 x i1> [[TMP11]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>12078; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> [[TMP2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>12079; CHECK-NEXT: [[TMP13:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i32> [[_MSPROP5]], <4 x i32> [[TMP12]]12080; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x float> [[TMP1]] to <4 x i32>12081; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x float> [[A0]] to <4 x i32>12082; CHECK-NEXT: [[TMP6:%.*]] = xor <4 x i32> [[TMP4]], [[TMP5]]12083; CHECK-NEXT: [[TMP17:%.*]] = or <4 x i32> [[TMP6]], [[_MSPROP5]]12084; CHECK-NEXT: [[TMP18:%.*]] = or <4 x i32> [[TMP17]], [[TMP12]]12085; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP6]], <4 x i32> [[TMP18]], <4 x i32> [[TMP13]]12086; CHECK-NEXT: [[TMP9:%.*]] = select <4 x i1> [[EXTRACT]], <4 x float> [[TMP1]], <4 x float> [[A0]]12087; CHECK-NEXT: store <4 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 812088; CHECK-NEXT: ret <4 x float> [[TMP9]]12089;12090 %q = load float, ptr %ptr_a212091 %vecinit.i = insertelement <4 x float> poison, float %q, i32 012092 %vecinit2.i = insertelement <4 x float> %vecinit.i, float %q, i32 112093 %vecinit4.i = insertelement <4 x float> %vecinit2.i, float %q, i32 212094 %vecinit6.i = insertelement <4 x float> %vecinit4.i, float %q, i32 312095 %1 = call <4 x float> @llvm.fma.v4f32(<4 x float> %a0, <4 x float> %a1, <4 x float> %vecinit6.i)12096 %2 = bitcast i8 %mask to <8 x i1>12097 %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>12098 %3 = select <4 x i1> %extract, <4 x float> %1, <4 x float> %a012099 ret <4 x float> %312100}12101 12102define <4 x float> @test_mask_vfmadd128_ps_rmba(<4 x float> %a0, <4 x float> %a1, ptr %ptr_a2, i8 %mask) #0 {12103;12104; CHECK-LABEL: define <4 x float> @test_mask_vfmadd128_ps_rmba(12105; CHECK-SAME: <4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], ptr [[PTR_A2:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {12106; CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 812107; CHECK-NEXT: [[TMP12:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 812108; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 812109; CHECK-NEXT: [[TMP14:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 812110; CHECK-NEXT: call void @llvm.donothing()12111; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP10]], 012112; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]12113; CHECK: [[BB5]]:12114; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]12115; CHECK-NEXT: unreachable12116; CHECK: [[BB6]]:12117; CHECK-NEXT: [[Q:%.*]] = load float, ptr [[PTR_A2]], align 412118; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[PTR_A2]] to i6412119; CHECK-NEXT: [[TMP8:%.*]] = xor i64 [[TMP7]], 8796093022208012120; CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP8]] to ptr12121; CHECK-NEXT: [[_MSLD:%.*]] = load i32, ptr [[TMP15]], align 412122; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <4 x i32> splat (i32 -1), i32 [[_MSLD]], i32 012123; CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x float> poison, float [[Q]], i32 012124; CHECK-NEXT: [[_MSPROP1:%.*]] = insertelement <4 x i32> [[_MSPROP]], i32 [[_MSLD]], i32 112125; CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], float [[Q]], i32 112126; CHECK-NEXT: [[_MSPROP2:%.*]] = insertelement <4 x i32> [[_MSPROP1]], i32 [[_MSLD]], i32 212127; CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <4 x float> [[VECINIT2_I]], float [[Q]], i32 212128; CHECK-NEXT: [[_MSPROP3:%.*]] = insertelement <4 x i32> [[_MSPROP2]], i32 [[_MSLD]], i32 312129; CHECK-NEXT: [[VECINIT6_I:%.*]] = insertelement <4 x float> [[VECINIT4_I]], float [[Q]], i32 312130; CHECK-NEXT: [[_MSPROP4:%.*]] = or <4 x i32> [[TMP12]], [[TMP3]]12131; CHECK-NEXT: [[_MSPROP5:%.*]] = or <4 x i32> [[_MSPROP4]], [[_MSPROP3]]12132; CHECK-NEXT: [[TMP1:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[A0]], <4 x float> [[A1]], <4 x float> [[VECINIT6_I]])12133; CHECK-NEXT: [[TMP11:%.*]] = bitcast i8 [[TMP14]] to <8 x i1>12134; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[MASK]] to <8 x i1>12135; CHECK-NEXT: [[_MSPROP6:%.*]] = shufflevector <8 x i1> [[TMP11]], <8 x i1> [[TMP11]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>12136; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> [[TMP2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>12137; CHECK-NEXT: [[TMP13:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i32> [[_MSPROP5]], <4 x i32> [[TMP12]]12138; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x float> [[TMP1]] to <4 x i32>12139; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x float> [[A0]] to <4 x i32>12140; CHECK-NEXT: [[TMP6:%.*]] = xor <4 x i32> [[TMP4]], [[TMP5]]12141; CHECK-NEXT: [[TMP17:%.*]] = or <4 x i32> [[TMP6]], [[_MSPROP5]]12142; CHECK-NEXT: [[TMP18:%.*]] = or <4 x i32> [[TMP17]], [[TMP12]]12143; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP6]], <4 x i32> [[TMP18]], <4 x i32> [[TMP13]]12144; CHECK-NEXT: [[TMP9:%.*]] = select <4 x i1> [[EXTRACT]], <4 x float> [[TMP1]], <4 x float> [[A0]]12145; CHECK-NEXT: store <4 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 812146; CHECK-NEXT: ret <4 x float> [[TMP9]]12147;12148 %q = load float, ptr %ptr_a2, align 412149 %vecinit.i = insertelement <4 x float> poison, float %q, i32 012150 %vecinit2.i = insertelement <4 x float> %vecinit.i, float %q, i32 112151 %vecinit4.i = insertelement <4 x float> %vecinit2.i, float %q, i32 212152 %vecinit6.i = insertelement <4 x float> %vecinit4.i, float %q, i32 312153 %1 = call <4 x float> @llvm.fma.v4f32(<4 x float> %a0, <4 x float> %a1, <4 x float> %vecinit6.i)12154 %2 = bitcast i8 %mask to <8 x i1>12155 %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>12156 %3 = select <4 x i1> %extract, <4 x float> %1, <4 x float> %a012157 ret <4 x float> %312158}12159 12160define <4 x float> @test_mask_vfmadd128_ps_rmbz(<4 x float> %a0, <4 x float> %a1, ptr %ptr_a2) #0 {12161;12162; CHECK-LABEL: define <4 x float> @test_mask_vfmadd128_ps_rmbz(12163; CHECK-SAME: <4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], ptr [[PTR_A2:%.*]]) #[[ATTR0]] {12164; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 812165; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 812166; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 812167; CHECK-NEXT: call void @llvm.donothing()12168; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP4]], 012169; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]12170; CHECK: [[BB4]]:12171; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]12172; CHECK-NEXT: unreachable12173; CHECK: [[BB5]]:12174; CHECK-NEXT: [[Q:%.*]] = load float, ptr [[PTR_A2]], align 412175; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[PTR_A2]] to i6412176; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 8796093022208012177; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr12178; CHECK-NEXT: [[_MSLD:%.*]] = load i32, ptr [[TMP8]], align 412179; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <4 x i32> splat (i32 -1), i32 [[_MSLD]], i32 012180; CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x float> poison, float [[Q]], i32 012181; CHECK-NEXT: [[_MSPROP1:%.*]] = insertelement <4 x i32> [[_MSPROP]], i32 [[_MSLD]], i32 112182; CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], float [[Q]], i32 112183; CHECK-NEXT: [[_MSPROP2:%.*]] = insertelement <4 x i32> [[_MSPROP1]], i32 [[_MSLD]], i32 212184; CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <4 x float> [[VECINIT2_I]], float [[Q]], i32 212185; CHECK-NEXT: [[_MSPROP3:%.*]] = insertelement <4 x i32> [[_MSPROP2]], i32 [[_MSLD]], i32 312186; CHECK-NEXT: [[VECINIT6_I:%.*]] = insertelement <4 x float> [[VECINIT4_I]], float [[Q]], i32 312187; CHECK-NEXT: [[_MSPROP4:%.*]] = or <4 x i32> [[TMP2]], [[TMP3]]12188; CHECK-NEXT: [[_MSPROP5:%.*]] = or <4 x i32> [[_MSPROP4]], [[_MSPROP3]]12189; CHECK-NEXT: [[TMP1:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[A0]], <4 x float> [[A1]], <4 x float> [[VECINIT6_I]])12190; CHECK-NEXT: store <4 x i32> [[_MSPROP5]], ptr @__msan_retval_tls, align 812191; CHECK-NEXT: ret <4 x float> [[TMP1]]12192;12193 %q = load float, ptr %ptr_a212194 %vecinit.i = insertelement <4 x float> poison, float %q, i32 012195 %vecinit2.i = insertelement <4 x float> %vecinit.i, float %q, i32 112196 %vecinit4.i = insertelement <4 x float> %vecinit2.i, float %q, i32 212197 %vecinit6.i = insertelement <4 x float> %vecinit4.i, float %q, i32 312198 %1 = call <4 x float> @llvm.fma.v4f32(<4 x float> %a0, <4 x float> %a1, <4 x float> %vecinit6.i)12199 ret <4 x float> %112200}12201 12202define <4 x float> @test_mask_vfmadd128_ps_rmbza(<4 x float> %a0, <4 x float> %a1, ptr %ptr_a2) #0 {12203;12204; CHECK-LABEL: define <4 x float> @test_mask_vfmadd128_ps_rmbza(12205; CHECK-SAME: <4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], ptr [[PTR_A2:%.*]]) #[[ATTR0]] {12206; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 812207; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 812208; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 812209; CHECK-NEXT: call void @llvm.donothing()12210; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP4]], 012211; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]12212; CHECK: [[BB4]]:12213; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]12214; CHECK-NEXT: unreachable12215; CHECK: [[BB5]]:12216; CHECK-NEXT: [[Q:%.*]] = load float, ptr [[PTR_A2]], align 412217; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[PTR_A2]] to i6412218; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 8796093022208012219; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr12220; CHECK-NEXT: [[_MSLD:%.*]] = load i32, ptr [[TMP8]], align 412221; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <4 x i32> splat (i32 -1), i32 [[_MSLD]], i32 012222; CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x float> poison, float [[Q]], i32 012223; CHECK-NEXT: [[_MSPROP1:%.*]] = insertelement <4 x i32> [[_MSPROP]], i32 [[_MSLD]], i32 112224; CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], float [[Q]], i32 112225; CHECK-NEXT: [[_MSPROP2:%.*]] = insertelement <4 x i32> [[_MSPROP1]], i32 [[_MSLD]], i32 212226; CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <4 x float> [[VECINIT2_I]], float [[Q]], i32 212227; CHECK-NEXT: [[_MSPROP3:%.*]] = insertelement <4 x i32> [[_MSPROP2]], i32 [[_MSLD]], i32 312228; CHECK-NEXT: [[VECINIT6_I:%.*]] = insertelement <4 x float> [[VECINIT4_I]], float [[Q]], i32 312229; CHECK-NEXT: [[_MSPROP4:%.*]] = or <4 x i32> [[TMP2]], [[TMP3]]12230; CHECK-NEXT: [[_MSPROP5:%.*]] = or <4 x i32> [[_MSPROP4]], [[_MSPROP3]]12231; CHECK-NEXT: [[TMP1:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[A0]], <4 x float> [[A1]], <4 x float> [[VECINIT6_I]])12232; CHECK-NEXT: store <4 x i32> [[_MSPROP5]], ptr @__msan_retval_tls, align 812233; CHECK-NEXT: ret <4 x float> [[TMP1]]12234;12235 %q = load float, ptr %ptr_a2, align 412236 %vecinit.i = insertelement <4 x float> poison, float %q, i32 012237 %vecinit2.i = insertelement <4 x float> %vecinit.i, float %q, i32 112238 %vecinit4.i = insertelement <4 x float> %vecinit2.i, float %q, i32 212239 %vecinit6.i = insertelement <4 x float> %vecinit4.i, float %q, i32 312240 %1 = call <4 x float> @llvm.fma.v4f32(<4 x float> %a0, <4 x float> %a1, <4 x float> %vecinit6.i)12241 ret <4 x float> %112242}12243 12244define <2 x double> @test_mask_vfmadd128_pd_rmk(<2 x double> %a0, <2 x double> %a1, ptr %ptr_a2, i8 %mask) #0 {12245;12246; CHECK-LABEL: define <2 x double> @test_mask_vfmadd128_pd_rmk(12247; CHECK-SAME: <2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]], ptr [[PTR_A2:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {12248; CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 812249; CHECK-NEXT: [[TMP12:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 812250; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 812251; CHECK-NEXT: [[TMP14:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 812252; CHECK-NEXT: call void @llvm.donothing()12253; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP10]], 012254; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]12255; CHECK: [[BB5]]:12256; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]12257; CHECK-NEXT: unreachable12258; CHECK: [[BB6]]:12259; CHECK-NEXT: [[A2:%.*]] = load <2 x double>, ptr [[PTR_A2]], align 1612260; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[PTR_A2]] to i6412261; CHECK-NEXT: [[TMP8:%.*]] = xor i64 [[TMP7]], 8796093022208012262; CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP8]] to ptr12263; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP15]], align 1612264; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP12]], [[TMP3]]12265; CHECK-NEXT: [[_MSPROP1:%.*]] = or <2 x i64> [[_MSPROP]], [[_MSLD]]12266; CHECK-NEXT: [[TMP1:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> [[A0]], <2 x double> [[A1]], <2 x double> [[A2]])12267; CHECK-NEXT: [[TMP11:%.*]] = bitcast i8 [[TMP14]] to <8 x i1>12268; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[MASK]] to <8 x i1>12269; CHECK-NEXT: [[_MSPROP2:%.*]] = shufflevector <8 x i1> [[TMP11]], <8 x i1> [[TMP11]], <2 x i32> <i32 0, i32 1>12270; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> [[TMP2]], <2 x i32> <i32 0, i32 1>12271; CHECK-NEXT: [[TMP13:%.*]] = select <2 x i1> [[EXTRACT]], <2 x i64> [[_MSPROP1]], <2 x i64> [[TMP12]]12272; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x double> [[TMP1]] to <2 x i64>12273; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x double> [[A0]] to <2 x i64>12274; CHECK-NEXT: [[TMP6:%.*]] = xor <2 x i64> [[TMP4]], [[TMP5]]12275; CHECK-NEXT: [[TMP17:%.*]] = or <2 x i64> [[TMP6]], [[_MSPROP1]]12276; CHECK-NEXT: [[TMP18:%.*]] = or <2 x i64> [[TMP17]], [[TMP12]]12277; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <2 x i1> [[_MSPROP2]], <2 x i64> [[TMP18]], <2 x i64> [[TMP13]]12278; CHECK-NEXT: [[TMP9:%.*]] = select <2 x i1> [[EXTRACT]], <2 x double> [[TMP1]], <2 x double> [[A0]]12279; CHECK-NEXT: store <2 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 812280; CHECK-NEXT: ret <2 x double> [[TMP9]]12281;12282 %a2 = load <2 x double>, ptr %ptr_a212283 %1 = call <2 x double> @llvm.fma.v2f64(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2)12284 %2 = bitcast i8 %mask to <8 x i1>12285 %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <2 x i32> <i32 0, i32 1>12286 %3 = select <2 x i1> %extract, <2 x double> %1, <2 x double> %a012287 ret <2 x double> %312288}12289 12290define <2 x double> @test_mask_vfmadd128_pd_rmkz(<2 x double> %a0, <2 x double> %a1, ptr %ptr_a2) #0 {12291;12292; CHECK-LABEL: define <2 x double> @test_mask_vfmadd128_pd_rmkz(12293; CHECK-SAME: <2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]], ptr [[PTR_A2:%.*]]) #[[ATTR0]] {12294; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 812295; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 812296; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 812297; CHECK-NEXT: call void @llvm.donothing()12298; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP4]], 012299; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]12300; CHECK: [[BB4]]:12301; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]12302; CHECK-NEXT: unreachable12303; CHECK: [[BB5]]:12304; CHECK-NEXT: [[A2:%.*]] = load <2 x double>, ptr [[PTR_A2]], align 1612305; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[PTR_A2]] to i6412306; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 8796093022208012307; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr12308; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP8]], align 1612309; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP2]], [[TMP3]]12310; CHECK-NEXT: [[_MSPROP1:%.*]] = or <2 x i64> [[_MSPROP]], [[_MSLD]]12311; CHECK-NEXT: [[TMP1:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> [[A0]], <2 x double> [[A1]], <2 x double> [[A2]])12312; CHECK-NEXT: store <2 x i64> [[_MSPROP1]], ptr @__msan_retval_tls, align 812313; CHECK-NEXT: ret <2 x double> [[TMP1]]12314;12315 %a2 = load <2 x double>, ptr %ptr_a212316 %1 = call <2 x double> @llvm.fma.v2f64(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2)12317 ret <2 x double> %112318}12319 12320define <4 x double> @test_mask_vfmadd256_pd_rmk(<4 x double> %a0, <4 x double> %a1, ptr %ptr_a2, i8 %mask) #0 {12321;12322; CHECK-LABEL: define <4 x double> @test_mask_vfmadd256_pd_rmk(12323; CHECK-SAME: <4 x double> [[A0:%.*]], <4 x double> [[A1:%.*]], ptr [[PTR_A2:%.*]], i8 [[MASK:%.*]]) #[[ATTR0]] {12324; CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 812325; CHECK-NEXT: [[TMP12:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 812326; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 812327; CHECK-NEXT: [[TMP14:%.*]] = load i8, ptr getelementptr (i8, ptr @__msan_param_tls, i64 72), align 812328; CHECK-NEXT: call void @llvm.donothing()12329; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP10]], 012330; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]12331; CHECK: [[BB5]]:12332; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]12333; CHECK-NEXT: unreachable12334; CHECK: [[BB6]]:12335; CHECK-NEXT: [[A2:%.*]] = load <4 x double>, ptr [[PTR_A2]], align 3212336; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[PTR_A2]] to i6412337; CHECK-NEXT: [[TMP8:%.*]] = xor i64 [[TMP7]], 8796093022208012338; CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP8]] to ptr12339; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i64>, ptr [[TMP15]], align 3212340; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i64> [[TMP12]], [[TMP3]]12341; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i64> [[_MSPROP]], [[_MSLD]]12342; CHECK-NEXT: [[TMP1:%.*]] = call <4 x double> @llvm.fma.v4f64(<4 x double> [[A0]], <4 x double> [[A1]], <4 x double> [[A2]])12343; CHECK-NEXT: [[TMP11:%.*]] = bitcast i8 [[TMP14]] to <8 x i1>12344; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[MASK]] to <8 x i1>12345; CHECK-NEXT: [[_MSPROP2:%.*]] = shufflevector <8 x i1> [[TMP11]], <8 x i1> [[TMP11]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>12346; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> [[TMP2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>12347; CHECK-NEXT: [[TMP13:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i64> [[_MSPROP1]], <4 x i64> [[TMP12]]12348; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x double> [[TMP1]] to <4 x i64>12349; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x double> [[A0]] to <4 x i64>12350; CHECK-NEXT: [[TMP6:%.*]] = xor <4 x i64> [[TMP4]], [[TMP5]]12351; CHECK-NEXT: [[TMP17:%.*]] = or <4 x i64> [[TMP6]], [[_MSPROP1]]12352; CHECK-NEXT: [[TMP18:%.*]] = or <4 x i64> [[TMP17]], [[TMP12]]12353; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP2]], <4 x i64> [[TMP18]], <4 x i64> [[TMP13]]12354; CHECK-NEXT: [[TMP9:%.*]] = select <4 x i1> [[EXTRACT]], <4 x double> [[TMP1]], <4 x double> [[A0]]12355; CHECK-NEXT: store <4 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 812356; CHECK-NEXT: ret <4 x double> [[TMP9]]12357;12358 %a2 = load <4 x double>, ptr %ptr_a212359 %1 = call <4 x double> @llvm.fma.v4f64(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2)12360 %2 = bitcast i8 %mask to <8 x i1>12361 %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>12362 %3 = select <4 x i1> %extract, <4 x double> %1, <4 x double> %a012363 ret <4 x double> %312364}12365 12366define <4 x double> @test_mask_vfmadd256_pd_rmkz(<4 x double> %a0, <4 x double> %a1, ptr %ptr_a2) #0 {12367;12368; CHECK-LABEL: define <4 x double> @test_mask_vfmadd256_pd_rmkz(12369; CHECK-SAME: <4 x double> [[A0:%.*]], <4 x double> [[A1:%.*]], ptr [[PTR_A2:%.*]]) #[[ATTR0]] {12370; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 812371; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 812372; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 812373; CHECK-NEXT: call void @llvm.donothing()12374; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP4]], 012375; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]12376; CHECK: [[BB4]]:12377; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]12378; CHECK-NEXT: unreachable12379; CHECK: [[BB5]]:12380; CHECK-NEXT: [[A2:%.*]] = load <4 x double>, ptr [[PTR_A2]], align 3212381; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[PTR_A2]] to i6412382; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 8796093022208012383; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr12384; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i64>, ptr [[TMP8]], align 3212385; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i64> [[TMP2]], [[TMP3]]12386; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i64> [[_MSPROP]], [[_MSLD]]12387; CHECK-NEXT: [[TMP1:%.*]] = call <4 x double> @llvm.fma.v4f64(<4 x double> [[A0]], <4 x double> [[A1]], <4 x double> [[A2]])12388; CHECK-NEXT: store <4 x i64> [[_MSPROP1]], ptr @__msan_retval_tls, align 812389; CHECK-NEXT: ret <4 x double> [[TMP1]]12390;12391 %a2 = load <4 x double>, ptr %ptr_a212392 %1 = call <4 x double> @llvm.fma.v4f64(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2)12393 ret <4 x double> %112394}12395 12396define <8 x i32> @combine_vpermi2d_vpermps(<16 x i32> noundef %a) #0 {12397;12398; CHECK-LABEL: define <8 x i32> @combine_vpermi2d_vpermps(12399; CHECK-SAME: <16 x i32> noundef [[A:%.*]]) #[[ATTR0]] {12400; CHECK-NEXT: [[TMP5:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 812401; CHECK-NEXT: call void @llvm.donothing()12402; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <16 x i32> [[TMP5]], <16 x i32> splat (i32 -1), <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>12403; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[A]], <16 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>12404; CHECK-NEXT: [[_MSPROP1:%.*]] = shufflevector <16 x i32> [[TMP5]], <16 x i32> splat (i32 -1), <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>12405; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <16 x i32> [[A]], <16 x i32> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>12406; CHECK-NEXT: [[TMP4:%.*]] = call <8 x i32> @llvm.x86.avx512.vpermi2var.d.256(<8 x i32> [[_MSPROP]], <8 x i32> <i32 14, i32 13, i32 6, i32 3, i32 5, i32 15, i32 0, i32 1>, <8 x i32> [[_MSPROP1]])12407; CHECK-NEXT: [[TMP3:%.*]] = tail call <8 x i32> @llvm.x86.avx512.vpermi2var.d.256(<8 x i32> [[TMP1]], <8 x i32> <i32 14, i32 13, i32 6, i32 3, i32 5, i32 15, i32 0, i32 1>, <8 x i32> [[TMP2]])12408; CHECK-NEXT: store <8 x i32> [[TMP4]], ptr @__msan_retval_tls, align 812409; CHECK-NEXT: ret <8 x i32> [[TMP3]]12410;12411 %1 = shufflevector <16 x i32> %a, <16 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>12412 %2 = shufflevector <16 x i32> %a, <16 x i32> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>12413 %3 = tail call <8 x i32> @llvm.x86.avx512.vpermi2var.d.256(<8 x i32> %1, <8 x i32> <i32 14, i32 13, i32 6, i32 3, i32 5, i32 15, i32 0, i32 1>, <8 x i32> %2)12414 ret <8 x i32> %312415}12416 12417declare <8 x float> @llvm.fma.v8f32(<8 x float>, <8 x float>, <8 x float>)12418declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>)12419declare <4 x double> @llvm.fma.v4f64(<4 x double>, <4 x double>, <4 x double>)12420declare <2 x double> @llvm.fma.v2f64(<2 x double>, <2 x double>, <2 x double>)12421declare <2 x double> @llvm.x86.avx512.mask.compress.v2f64(<2 x double>, <2 x double>, <2 x i1>)12422declare <4 x float> @llvm.x86.avx512.mask.compress.v4f32(<4 x float>, <4 x float>, <4 x i1>)12423declare <2 x i64> @llvm.x86.avx512.mask.compress.v2i64(<2 x i64>, <2 x i64>, <2 x i1>)12424declare <4 x i32> @llvm.x86.avx512.mask.compress.v4i32(<4 x i32>, <4 x i32>, <4 x i1>)12425declare <2 x double> @llvm.x86.avx512.mask.expand.v2f64(<2 x double>, <2 x double>, <2 x i1>)12426declare <4 x float> @llvm.x86.avx512.mask.expand.v4f32(<4 x float>, <4 x float>, <4 x i1>)12427declare <2 x i64> @llvm.x86.avx512.mask.expand.v2i64(<2 x i64>, <2 x i64>, <2 x i1>)12428declare <4 x i32> @llvm.x86.avx512.mask.expand.v4i32(<4 x i32>, <4 x i32>, <4 x i1>)12429declare <4 x double> @llvm.x86.avx512.mask.compress.v4f64(<4 x double>, <4 x double>, <4 x i1>)12430declare <8 x float> @llvm.x86.avx512.mask.compress.v8f32(<8 x float>, <8 x float>, <8 x i1>)12431declare <4 x i64> @llvm.x86.avx512.mask.compress.v4i64(<4 x i64>, <4 x i64>, <4 x i1>)12432declare <8 x i32> @llvm.x86.avx512.mask.compress.v8i32(<8 x i32>, <8 x i32>, <8 x i1>)12433declare <4 x double> @llvm.x86.avx512.mask.expand.v4f64(<4 x double>, <4 x double>, <4 x i1>)12434declare <8 x float> @llvm.x86.avx512.mask.expand.v8f32(<8 x float>, <8 x float>, <8 x i1>)12435declare <4 x i64> @llvm.x86.avx512.mask.expand.v4i64(<4 x i64>, <4 x i64>, <4 x i1>)12436declare <8 x i32> @llvm.x86.avx512.mask.expand.v8i32(<8 x i32>, <8 x i32>, <8 x i1>)12437 12438attributes #0 = { sanitize_memory }12439;.12440; CHECK: [[PROF1]] = !{!"branch_weights", i32 1, i32 1048575}12441;.12442