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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt < %s -passes=msan -S | FileCheck %s3;4; Forked from llvm/test/CodeGen/X86/f16c-intrinsics-upgrade.ll5;6; Handled by reduction to fpext:7; - llvm.x86.vcvtph2ps.{128,256}8 9target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"10target triple = "x86_64-unknown-linux-gnu"11 12define <4 x float> @test_x86_vcvtph2ps_128(<8 x i16> %a0) #0 {13; CHECK-LABEL: define <4 x float> @test_x86_vcvtph2ps_128(14; CHECK-SAME: <8 x i16> [[A0:%.*]]) #[[ATTR0:[0-9]+]] {15; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 816; CHECK-NEXT: call void @llvm.donothing()17; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> [[TMP1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>18; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i16> [[A0]], <8 x i16> [[A0]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>19; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to <4 x half>20; CHECK-NEXT: [[TMP4:%.*]] = zext <4 x i16> [[_MSPROP]] to <4 x i32>21; CHECK-NEXT: [[CVTPH2PS:%.*]] = fpext <4 x half> [[TMP3]] to <4 x float>22; CHECK-NEXT: store <4 x i32> [[TMP4]], ptr @__msan_retval_tls, align 823; CHECK-NEXT: ret <4 x float> [[CVTPH2PS]]24;25 %res = call <4 x float> @llvm.x86.vcvtph2ps.128(<8 x i16> %a0) ; <<4 x float>> [#uses=1]26 ret <4 x float> %res27}28declare <4 x float> @llvm.x86.vcvtph2ps.128(<8 x i16>) nounwind readonly29 30define <4 x float> @test_x86_vcvtph2ps_128_m(ptr nocapture %a) #0 {31; CHECK-LABEL: define <4 x float> @test_x86_vcvtph2ps_128_m(32; CHECK-SAME: ptr captures(none) [[A:%.*]]) #[[ATTR0]] {33; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 834; CHECK-NEXT: call void @llvm.donothing()35; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 036; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB2:.*]], label %[[BB3:.*]], !prof [[PROF1:![0-9]+]]37; CHECK: [[BB2]]:38; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4:[0-9]+]]39; CHECK-NEXT: unreachable40; CHECK: [[BB3]]:41; CHECK-NEXT: [[LOAD:%.*]] = load <8 x i16>, ptr [[A]], align 1642; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i6443; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 8796093022208044; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr45; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP6]], align 1646; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i16> [[_MSLD]], <8 x i16> [[_MSLD]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>47; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <8 x i16> [[LOAD]], <8 x i16> [[LOAD]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>48; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x i16> [[TMP7]] to <4 x half>49; CHECK-NEXT: [[TMP9:%.*]] = zext <4 x i16> [[_MSPROP]] to <4 x i32>50; CHECK-NEXT: [[CVTPH2PS:%.*]] = fpext <4 x half> [[TMP8]] to <4 x float>51; CHECK-NEXT: store <4 x i32> [[TMP9]], ptr @__msan_retval_tls, align 852; CHECK-NEXT: ret <4 x float> [[CVTPH2PS]]53;54 %load = load <8 x i16>, ptr %a55 %res = call <4 x float> @llvm.x86.vcvtph2ps.128(<8 x i16> %load) ; <<4 x float>> [#uses=1]56 ret <4 x float> %res57}58 59define <8 x float> @test_x86_vcvtph2ps_256(<8 x i16> %a0) #0 {60; CHECK-LABEL: define <8 x float> @test_x86_vcvtph2ps_256(61; CHECK-SAME: <8 x i16> [[A0:%.*]]) #[[ATTR0]] {62; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 863; CHECK-NEXT: call void @llvm.donothing()64; CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i16> [[A0]] to <8 x half>65; CHECK-NEXT: [[TMP3:%.*]] = zext <8 x i16> [[TMP1]] to <8 x i32>66; CHECK-NEXT: [[CVTPH2PS:%.*]] = fpext <8 x half> [[TMP2]] to <8 x float>67; CHECK-NEXT: store <8 x i32> [[TMP3]], ptr @__msan_retval_tls, align 868; CHECK-NEXT: ret <8 x float> [[CVTPH2PS]]69;70 %res = call <8 x float> @llvm.x86.vcvtph2ps.256(<8 x i16> %a0) ; <<8 x float>> [#uses=1]71 ret <8 x float> %res72}73declare <8 x float> @llvm.x86.vcvtph2ps.256(<8 x i16>) nounwind readonly74 75define <8 x float> @test_x86_vcvtph2ps_256_m(ptr nocapture %a) nounwind #0 {76; CHECK-LABEL: define <8 x float> @test_x86_vcvtph2ps_256_m(77; CHECK-SAME: ptr captures(none) [[A:%.*]]) #[[ATTR1:[0-9]+]] {78; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 879; CHECK-NEXT: call void @llvm.donothing()80; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 081; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB2:.*]], label %[[BB3:.*]], !prof [[PROF1]]82; CHECK: [[BB2]]:83; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]84; CHECK-NEXT: unreachable85; CHECK: [[BB3]]:86; CHECK-NEXT: [[LOAD:%.*]] = load <8 x i16>, ptr [[A]], align 1687; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i6488; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 8796093022208089; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr90; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP6]], align 1691; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i16> [[LOAD]] to <8 x half>92; CHECK-NEXT: [[TMP8:%.*]] = zext <8 x i16> [[_MSLD]] to <8 x i32>93; CHECK-NEXT: [[CVTPH2PS:%.*]] = fpext <8 x half> [[TMP7]] to <8 x float>94; CHECK-NEXT: store <8 x i32> [[TMP8]], ptr @__msan_retval_tls, align 895; CHECK-NEXT: ret <8 x float> [[CVTPH2PS]]96;97 %load = load <8 x i16>, ptr %a98 %res = tail call <8 x float> @llvm.x86.vcvtph2ps.256(<8 x i16> %load)99 ret <8 x float> %res100}101 102define <4 x float> @test_x86_vcvtph2ps_128_scalar(ptr %ptr) #0 {103; CHECK-LABEL: define <4 x float> @test_x86_vcvtph2ps_128_scalar(104; CHECK-SAME: ptr [[PTR:%.*]]) #[[ATTR0]] {105; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8106; CHECK-NEXT: call void @llvm.donothing()107; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0108; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB2:.*]], label %[[BB3:.*]], !prof [[PROF1]]109; CHECK: [[BB2]]:110; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]111; CHECK-NEXT: unreachable112; CHECK: [[BB3]]:113; CHECK-NEXT: [[LOAD:%.*]] = load i64, ptr [[PTR]], align 8114; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[PTR]] to i64115; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 87960930222080116; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr117; CHECK-NEXT: [[_MSLD:%.*]] = load i64, ptr [[TMP6]], align 8118; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <2 x i64> splat (i64 -1), i64 [[_MSLD]], i32 0119; CHECK-NEXT: [[INS1:%.*]] = insertelement <2 x i64> poison, i64 [[LOAD]], i32 0120; CHECK-NEXT: [[_MSPROP1:%.*]] = insertelement <2 x i64> [[_MSPROP]], i64 0, i32 1121; CHECK-NEXT: [[INS2:%.*]] = insertelement <2 x i64> [[INS1]], i64 0, i32 1122; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i64> [[_MSPROP1]] to <8 x i16>123; CHECK-NEXT: [[BC:%.*]] = bitcast <2 x i64> [[INS2]] to <8 x i16>124; CHECK-NEXT: [[_MSPROP2:%.*]] = shufflevector <8 x i16> [[TMP7]], <8 x i16> [[TMP7]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>125; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <8 x i16> [[BC]], <8 x i16> [[BC]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>126; CHECK-NEXT: [[TMP9:%.*]] = bitcast <4 x i16> [[TMP8]] to <4 x half>127; CHECK-NEXT: [[TMP10:%.*]] = zext <4 x i16> [[_MSPROP2]] to <4 x i32>128; CHECK-NEXT: [[CVTPH2PS:%.*]] = fpext <4 x half> [[TMP9]] to <4 x float>129; CHECK-NEXT: store <4 x i32> [[TMP10]], ptr @__msan_retval_tls, align 8130; CHECK-NEXT: ret <4 x float> [[CVTPH2PS]]131;132 %load = load i64, ptr %ptr133 %ins1 = insertelement <2 x i64> poison, i64 %load, i32 0134 %ins2 = insertelement <2 x i64> %ins1, i64 0, i32 1135 %bc = bitcast <2 x i64> %ins2 to <8 x i16>136 %res = tail call <4 x float> @llvm.x86.vcvtph2ps.128(<8 x i16> %bc) #2137 ret <4 x float> %res138}139 140define <4 x float> @test_x86_vcvtph2ps_128_scalar2(ptr %ptr) #0 {141; CHECK-LABEL: define <4 x float> @test_x86_vcvtph2ps_128_scalar2(142; CHECK-SAME: ptr [[PTR:%.*]]) #[[ATTR0]] {143; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8144; CHECK-NEXT: call void @llvm.donothing()145; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0146; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB2:.*]], label %[[BB3:.*]], !prof [[PROF1]]147; CHECK: [[BB2]]:148; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]149; CHECK-NEXT: unreachable150; CHECK: [[BB3]]:151; CHECK-NEXT: [[LOAD:%.*]] = load i64, ptr [[PTR]], align 8152; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[PTR]] to i64153; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 87960930222080154; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr155; CHECK-NEXT: [[_MSLD:%.*]] = load i64, ptr [[TMP6]], align 8156; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <2 x i64> splat (i64 -1), i64 [[_MSLD]], i32 0157; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i64> poison, i64 [[LOAD]], i32 0158; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i64> [[_MSPROP]] to <8 x i16>159; CHECK-NEXT: [[BC:%.*]] = bitcast <2 x i64> [[INS]] to <8 x i16>160; CHECK-NEXT: [[_MSPROP1:%.*]] = shufflevector <8 x i16> [[TMP7]], <8 x i16> [[TMP7]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>161; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <8 x i16> [[BC]], <8 x i16> [[BC]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>162; CHECK-NEXT: [[TMP9:%.*]] = bitcast <4 x i16> [[TMP8]] to <4 x half>163; CHECK-NEXT: [[TMP10:%.*]] = zext <4 x i16> [[_MSPROP1]] to <4 x i32>164; CHECK-NEXT: [[CVTPH2PS:%.*]] = fpext <4 x half> [[TMP9]] to <4 x float>165; CHECK-NEXT: store <4 x i32> [[TMP10]], ptr @__msan_retval_tls, align 8166; CHECK-NEXT: ret <4 x float> [[CVTPH2PS]]167;168 %load = load i64, ptr %ptr169 %ins = insertelement <2 x i64> poison, i64 %load, i32 0170 %bc = bitcast <2 x i64> %ins to <8 x i16>171 %res = tail call <4 x float> @llvm.x86.vcvtph2ps.128(<8 x i16> %bc)172 ret <4 x float> %res173}174 175attributes #0 = { sanitize_memory }176