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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt < %s -passes=msan -S | FileCheck %s3;4; Forked from llvm/test/CodeGen/X86/f16c-intrinsics.ll5;6; Handled by handleSSEVectorConvertIntrinsicByProp:7; - llvm.x86.vcvtps2ph.128/2568 9target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"10target triple = "x86_64-unknown-linux-gnu"11 12define <8 x i16> @test_x86_vcvtps2ph_128(<4 x float> %a0) #0 {13; CHECK-LABEL: define <8 x i16> @test_x86_vcvtps2ph_128(14; CHECK-SAME: <4 x float> [[A0:%.*]]) #[[ATTR0:[0-9]+]] {15; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 816; CHECK-NEXT: call void @llvm.donothing()17; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <4 x i32> [[TMP1]], zeroinitializer18; CHECK-NEXT: [[TMP3:%.*]] = sext <4 x i1> [[TMP2]] to <4 x i16>19; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <4 x i16> [[TMP3]], <4 x i16> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>20; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float> [[A0]], i32 0)21; CHECK-NEXT: store <8 x i16> [[TMP11]], ptr @__msan_retval_tls, align 822; CHECK-NEXT: ret <8 x i16> [[RES]]23;24 %res = call <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float> %a0, i32 0) ; <<8 x i16>> [#uses=1]25 ret <8 x i16> %res26}27declare <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float>, i32) nounwind readonly28 29define <8 x i16> @test_x86_vcvtps2ph_256(<8 x float> %a0) #0 {30; CHECK-LABEL: define <8 x i16> @test_x86_vcvtps2ph_256(31; CHECK-SAME: <8 x float> [[A0:%.*]]) #[[ATTR0]] {32; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 833; CHECK-NEXT: call void @llvm.donothing()34; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <8 x i32> [[TMP1]], zeroinitializer35; CHECK-NEXT: [[TMP3:%.*]] = sext <8 x i1> [[TMP2]] to <8 x i16>36; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float> [[A0]], i32 0)37; CHECK-NEXT: store <8 x i16> [[TMP3]], ptr @__msan_retval_tls, align 838; CHECK-NEXT: ret <8 x i16> [[RES]]39;40 %res = call <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float> %a0, i32 0) ; <<8 x i16>> [#uses=1]41 ret <8 x i16> %res42}43declare <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float>, i32) nounwind readonly44 45 46define void @test_x86_vcvtps2ph_256_m(ptr nocapture %d, <8 x float> %a) nounwind #0 {47; CHECK-LABEL: define void @test_x86_vcvtps2ph_256_m(48; CHECK-SAME: ptr captures(none) [[D:%.*]], <8 x float> [[A:%.*]]) #[[ATTR2:[0-9]+]] {49; CHECK-NEXT: [[ENTRY:.*:]]50; CHECK-NEXT: [[TMP17:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 851; CHECK-NEXT: [[TMP18:%.*]] = load i64, ptr @__msan_param_tls, align 852; CHECK-NEXT: call void @llvm.donothing()53; CHECK-NEXT: [[TMP20:%.*]] = icmp ne <8 x i32> [[TMP17]], zeroinitializer54; CHECK-NEXT: [[TMP21:%.*]] = sext <8 x i1> [[TMP20]] to <8 x i16>55; CHECK-NEXT: [[TMP0:%.*]] = tail call <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float> [[A]], i32 3)56; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP18]], 057; CHECK-NEXT: br i1 [[_MSCMP1]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1:![0-9]+]]58; CHECK: [[BB5]]:59; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4:[0-9]+]]60; CHECK-NEXT: unreachable61; CHECK: [[BB6]]:62; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[D]] to i6463; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 8796093022208064; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr65; CHECK-NEXT: store <8 x i16> [[TMP21]], ptr [[TMP3]], align 1666; CHECK-NEXT: store <8 x i16> [[TMP0]], ptr [[D]], align 1667; CHECK-NEXT: ret void68;69entry:70 %0 = tail call <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float> %a, i32 3)71 store <8 x i16> %0, ptr %d, align 1672 ret void73}74 75define void @test_x86_vcvtps2ph_128_m(ptr nocapture %d, <4 x float> %a) nounwind #0 {76; CHECK-LABEL: define void @test_x86_vcvtps2ph_128_m(77; CHECK-SAME: ptr captures(none) [[D:%.*]], <4 x float> [[A:%.*]]) #[[ATTR2]] {78; CHECK-NEXT: [[ENTRY:.*:]]79; CHECK-NEXT: [[TMP9:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 880; CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr @__msan_param_tls, align 881; CHECK-NEXT: call void @llvm.donothing()82; CHECK-NEXT: [[TMP12:%.*]] = icmp ne <4 x i32> [[TMP9]], zeroinitializer83; CHECK-NEXT: [[TMP13:%.*]] = sext <4 x i1> [[TMP12]] to <4 x i16>84; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <4 x i16> [[TMP13]], <4 x i16> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>85; CHECK-NEXT: [[TMP0:%.*]] = tail call <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float> [[A]], i32 3)86; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i16> [[TMP11]], <8 x i16> splat (i16 -1), <4 x i32> <i32 0, i32 1, i32 2, i32 3>87; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i16> [[TMP0]], <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>88; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP10]], 089; CHECK-NEXT: br i1 [[_MSCMP1]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]90; CHECK: [[BB7]]:91; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]92; CHECK-NEXT: unreachable93; CHECK: [[BB8]]:94; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[D]] to i6495; CHECK-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 8796093022208096; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr97; CHECK-NEXT: store <4 x i16> [[_MSPROP]], ptr [[TMP4]], align 898; CHECK-NEXT: store <4 x i16> [[TMP1]], ptr [[D]], align 899; CHECK-NEXT: ret void100;101entry:102 %0 = tail call <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float> %a, i32 3)103 %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>104 store <4 x i16> %1, ptr %d, align 8105 ret void106}107 108define void @test_x86_vcvtps2ph_128_m2(ptr nocapture %hf4x16, <4 x float> %f4X86) #0 {109; CHECK-LABEL: define void @test_x86_vcvtps2ph_128_m2(110; CHECK-SAME: ptr captures(none) [[HF4X16:%.*]], <4 x float> [[F4X86:%.*]]) #[[ATTR0]] {111; CHECK-NEXT: [[ENTRY:.*:]]112; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8113; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8114; CHECK-NEXT: call void @llvm.donothing()115; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <4 x i32> [[TMP0]], zeroinitializer116; CHECK-NEXT: [[TMP3:%.*]] = sext <4 x i1> [[TMP2]] to <4 x i16>117; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <4 x i16> [[TMP3]], <4 x i16> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>118; CHECK-NEXT: [[TMP11:%.*]] = tail call <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float> [[F4X86]], i32 3)119; CHECK-NEXT: [[TMP13:%.*]] = bitcast <8 x i16> [[TMP14]] to <2 x i64>120; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x i16> [[TMP11]] to <2 x double>121; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <2 x i64> [[TMP13]], i32 0122; CHECK-NEXT: [[VECEXT:%.*]] = extractelement <2 x double> [[TMP12]], i32 0123; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP1]], 0124; CHECK-NEXT: br i1 [[_MSCMP1]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]125; CHECK: [[BB8]]:126; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]127; CHECK-NEXT: unreachable128; CHECK: [[BB9]]:129; CHECK-NEXT: [[TMP15:%.*]] = ptrtoint ptr [[HF4X16]] to i64130; CHECK-NEXT: [[TMP16:%.*]] = xor i64 [[TMP15]], 87960930222080131; CHECK-NEXT: [[TMP17:%.*]] = inttoptr i64 [[TMP16]] to ptr132; CHECK-NEXT: store i64 [[_MSPROP]], ptr [[TMP17]], align 8133; CHECK-NEXT: store double [[VECEXT]], ptr [[HF4X16]], align 8134; CHECK-NEXT: ret void135;136entry:137 %0 = tail call <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float> %f4X86, i32 3)138 %1 = bitcast <8 x i16> %0 to <2 x double>139 %vecext = extractelement <2 x double> %1, i32 0140 store double %vecext, ptr %hf4x16, align 8141 ret void142}143 144define void @test_x86_vcvtps2ph_128_m3(ptr nocapture %hf4x16, <4 x float> %f4X86) #0 {145; CHECK-LABEL: define void @test_x86_vcvtps2ph_128_m3(146; CHECK-SAME: ptr captures(none) [[HF4X16:%.*]], <4 x float> [[F4X86:%.*]]) #[[ATTR0]] {147; CHECK-NEXT: [[ENTRY:.*:]]148; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8149; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8150; CHECK-NEXT: call void @llvm.donothing()151; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <4 x i32> [[TMP0]], zeroinitializer152; CHECK-NEXT: [[TMP3:%.*]] = sext <4 x i1> [[TMP2]] to <4 x i16>153; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <4 x i16> [[TMP3]], <4 x i16> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>154; CHECK-NEXT: [[TMP11:%.*]] = tail call <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float> [[F4X86]], i32 3)155; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x i16> [[TMP13]] to <2 x i64>156; CHECK-NEXT: [[TMP14:%.*]] = bitcast <8 x i16> [[TMP11]] to <2 x i64>157; CHECK-NEXT: [[VECEXT:%.*]] = extractelement <2 x i64> [[TMP12]], i32 0158; CHECK-NEXT: [[VECEXT1:%.*]] = extractelement <2 x i64> [[TMP14]], i32 0159; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP1]], 0160; CHECK-NEXT: br i1 [[_MSCMP1]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]161; CHECK: [[BB8]]:162; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]163; CHECK-NEXT: unreachable164; CHECK: [[BB9]]:165; CHECK-NEXT: [[TMP15:%.*]] = ptrtoint ptr [[HF4X16]] to i64166; CHECK-NEXT: [[TMP16:%.*]] = xor i64 [[TMP15]], 87960930222080167; CHECK-NEXT: [[TMP17:%.*]] = inttoptr i64 [[TMP16]] to ptr168; CHECK-NEXT: store i64 [[VECEXT]], ptr [[TMP17]], align 8169; CHECK-NEXT: store i64 [[VECEXT1]], ptr [[HF4X16]], align 8170; CHECK-NEXT: ret void171;172entry:173 %0 = tail call <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float> %f4X86, i32 3)174 %1 = bitcast <8 x i16> %0 to <2 x i64>175 %vecext = extractelement <2 x i64> %1, i32 0176 store i64 %vecext, ptr %hf4x16, align 8177 ret void178}179 180attributes #0 = { sanitize_memory }181;.182; CHECK: [[PROF1]] = !{!"branch_weights", i32 1, i32 1048575}183;.184