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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 42; RUN: opt %s -S -passes=msan 2>&1 | FileCheck %s3;4; Handled strictly:5; - i32 @llvm.x86.mmx.pmovmskb(<1 x i64> %mmx_var.i) #26; - void @llvm.x86.mmx.maskmovq(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i, ptr %p) #27; - <2 x double> @llvm.x86.sse.cvtpi2pd(<1 x i64> %4) #58; - <1 x i64> @llvm.x86.sse.cvttpd2pi(<2 x double> %a) #59; - <1 x i64> @llvm.x86.sse.cvtpd2pi(<2 x double> %a) #510; - <1 x i64> @llvm.x86.mmx.palignr.b(<1 x i64> %mmx_var, <1 x i64> %mmx_var1, i8 16)11; - <4 x float> @llvm.x86.sse.cvtpi2ps(<4 x float> %a, <1 x i64> %b)12; - void @llvm.x86.mmx.emms()13; - <1 x i64> @llvm.x86.mmx.pinsr.w(<1 x i64> %a.coerce, i32 %d, i32 2)14; - i32 @llvm.x86.mmx.pextr.w(<1 x i64> %a.coerce, i32 2)15 16target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"17target triple = "x86_64-unknown-linux-gnu"18 19declare <1 x i64> @llvm.x86.ssse3.phadd.w(<1 x i64>, <1 x i64>) nounwind readnone20 21define i64 @test1(<1 x i64> %a, <1 x i64> %b) #0 {22; CHECK-LABEL: define i64 @test1(23; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1:[0-9]+]] {24; CHECK-NEXT: entry:25; CHECK-NEXT: [[TMP9:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 826; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 827; CHECK-NEXT: call void @llvm.donothing()28; CHECK-NEXT: [[TMP12:%.*]] = bitcast <1 x i64> [[TMP9]] to <4 x i16>29; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>30; CHECK-NEXT: [[TMP13:%.*]] = bitcast <1 x i64> [[TMP10]] to <4 x i16>31; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>32; CHECK-NEXT: [[TMP16:%.*]] = bitcast <4 x i16> [[TMP13]] to <1 x i64>33; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>34; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x i16> [[TMP12]] to <1 x i64>35; CHECK-NEXT: [[TMP17:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>36; CHECK-NEXT: [[TMP21:%.*]] = bitcast <1 x i64> [[TMP16]] to <4 x i16>37; CHECK-NEXT: [[TMP23:%.*]] = bitcast <1 x i64> [[TMP8]] to <4 x i16>38; CHECK-NEXT: [[TMP24:%.*]] = shufflevector <4 x i16> [[TMP21]], <4 x i16> [[TMP23]], <4 x i32> <i32 0, i32 2, i32 4, i32 6>39; CHECK-NEXT: [[TMP25:%.*]] = shufflevector <4 x i16> [[TMP21]], <4 x i16> [[TMP23]], <4 x i32> <i32 1, i32 3, i32 5, i32 7>40; CHECK-NEXT: [[TMP26:%.*]] = or <4 x i16> [[TMP24]], [[TMP25]]41; CHECK-NEXT: [[TMP27:%.*]] = bitcast <4 x i16> [[TMP26]] to i6442; CHECK-NEXT: [[_MSPROP:%.*]] = bitcast i64 [[TMP27]] to <1 x i64>43; CHECK-NEXT: [[TMP18:%.*]] = tail call <1 x i64> @llvm.x86.ssse3.phadd.w(<1 x i64> [[TMP2]], <1 x i64> [[TMP17]]) #[[ATTR5:[0-9]+]]44; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>45; CHECK-NEXT: [[TMP19:%.*]] = bitcast <1 x i64> [[TMP18]] to <4 x i16>46; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>47; CHECK-NEXT: [[TMP14:%.*]] = bitcast <4 x i16> [[TMP19]] to <1 x i64>48; CHECK-NEXT: [[TMP7:%.*]] = extractelement <1 x i64> [[TMP6]], i32 049; CHECK-NEXT: [[TMP15:%.*]] = extractelement <1 x i64> [[TMP14]], i32 050; CHECK-NEXT: store i64 [[TMP7]], ptr @__msan_retval_tls, align 851; CHECK-NEXT: ret i64 [[TMP15]]52;53entry:54 %0 = bitcast <1 x i64> %b to <4 x i16>55 %1 = bitcast <1 x i64> %a to <4 x i16>56 %2 = bitcast <4 x i16> %1 to <1 x i64>57 %3 = bitcast <4 x i16> %0 to <1 x i64>58 %4 = tail call <1 x i64> @llvm.x86.ssse3.phadd.w(<1 x i64> %2, <1 x i64> %3) nounwind readnone59 %5 = bitcast <1 x i64> %4 to <4 x i16>60 %6 = bitcast <4 x i16> %5 to <1 x i64>61 %7 = extractelement <1 x i64> %6, i32 062 ret i64 %763}64 65declare <1 x i64> @llvm.x86.mmx.pcmpgt.d(<1 x i64>, <1 x i64>) nounwind readnone66 67define i64 @test88(<1 x i64> %a, <1 x i64> %b) #0 {68; CHECK-LABEL: define i64 @test88(69; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {70; CHECK-NEXT: entry:71; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 872; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 873; CHECK-NEXT: call void @llvm.donothing()74; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <2 x i32>75; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <2 x i32>76; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <2 x i32>77; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>78; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i32> [[TMP14]] to <1 x i64>79; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <2 x i32> [[TMP1]] to <1 x i64>80; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i32> [[TMP11]] to <1 x i64>81; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>82; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]83; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pcmpgt.d(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2:[0-9]+]]84; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <2 x i32>85; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <2 x i32>86; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP9]] to <1 x i64>87; CHECK-NEXT: [[TMP12:%.*]] = bitcast <2 x i32> [[TMP16]] to <1 x i64>88; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 089; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 090; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 891; CHECK-NEXT: ret i64 [[TMP13]]92;93entry:94 %0 = bitcast <1 x i64> %b to <2 x i32>95 %1 = bitcast <1 x i64> %a to <2 x i32>96 %mmx_var.i = bitcast <2 x i32> %1 to <1 x i64>97 %mmx_var1.i = bitcast <2 x i32> %0 to <1 x i64>98 %2 = tail call <1 x i64> @llvm.x86.mmx.pcmpgt.d(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind99 %3 = bitcast <1 x i64> %2 to <2 x i32>100 %4 = bitcast <2 x i32> %3 to <1 x i64>101 %5 = extractelement <1 x i64> %4, i32 0102 ret i64 %5103}104 105declare <1 x i64> @llvm.x86.mmx.pcmpgt.w(<1 x i64>, <1 x i64>) nounwind readnone106 107define i64 @test87(<1 x i64> %a, <1 x i64> %b) #0 {108; CHECK-LABEL: define i64 @test87(109; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {110; CHECK-NEXT: entry:111; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8112; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8113; CHECK-NEXT: call void @llvm.donothing()114; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <4 x i16>115; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>116; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <4 x i16>117; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>118; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP14]] to <1 x i64>119; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>120; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>121; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>122; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]123; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pcmpgt.w(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]124; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>125; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <4 x i16>126; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP9]] to <1 x i64>127; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i16> [[TMP16]] to <1 x i64>128; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 0129; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 0130; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 8131; CHECK-NEXT: ret i64 [[TMP13]]132;133entry:134 %0 = bitcast <1 x i64> %b to <4 x i16>135 %1 = bitcast <1 x i64> %a to <4 x i16>136 %mmx_var.i = bitcast <4 x i16> %1 to <1 x i64>137 %mmx_var1.i = bitcast <4 x i16> %0 to <1 x i64>138 %2 = tail call <1 x i64> @llvm.x86.mmx.pcmpgt.w(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind139 %3 = bitcast <1 x i64> %2 to <4 x i16>140 %4 = bitcast <4 x i16> %3 to <1 x i64>141 %5 = extractelement <1 x i64> %4, i32 0142 ret i64 %5143}144 145declare <1 x i64> @llvm.x86.mmx.pcmpgt.b(<1 x i64>, <1 x i64>) nounwind readnone146 147define i64 @test86(<1 x i64> %a, <1 x i64> %b) #0 {148; CHECK-LABEL: define i64 @test86(149; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {150; CHECK-NEXT: entry:151; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8152; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8153; CHECK-NEXT: call void @llvm.donothing()154; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <8 x i8>155; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>156; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <8 x i8>157; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>158; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP14]] to <1 x i64>159; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>160; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP11]] to <1 x i64>161; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>162; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]163; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pcmpgt.b(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]164; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <8 x i8>165; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <8 x i8>166; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP9]] to <1 x i64>167; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x i8> [[TMP16]] to <1 x i64>168; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 0169; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 0170; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 8171; CHECK-NEXT: ret i64 [[TMP13]]172;173entry:174 %0 = bitcast <1 x i64> %b to <8 x i8>175 %1 = bitcast <1 x i64> %a to <8 x i8>176 %mmx_var.i = bitcast <8 x i8> %1 to <1 x i64>177 %mmx_var1.i = bitcast <8 x i8> %0 to <1 x i64>178 %2 = tail call <1 x i64> @llvm.x86.mmx.pcmpgt.b(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind179 %3 = bitcast <1 x i64> %2 to <8 x i8>180 %4 = bitcast <8 x i8> %3 to <1 x i64>181 %5 = extractelement <1 x i64> %4, i32 0182 ret i64 %5183}184 185declare <1 x i64> @llvm.x86.mmx.pcmpeq.d(<1 x i64>, <1 x i64>) nounwind readnone186 187define i64 @test85(<1 x i64> %a, <1 x i64> %b) #0 {188; CHECK-LABEL: define i64 @test85(189; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {190; CHECK-NEXT: entry:191; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8192; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8193; CHECK-NEXT: call void @llvm.donothing()194; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <2 x i32>195; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <2 x i32>196; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <2 x i32>197; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>198; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i32> [[TMP14]] to <1 x i64>199; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <2 x i32> [[TMP1]] to <1 x i64>200; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i32> [[TMP11]] to <1 x i64>201; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>202; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]203; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pcmpeq.d(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]204; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <2 x i32>205; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <2 x i32>206; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP9]] to <1 x i64>207; CHECK-NEXT: [[TMP12:%.*]] = bitcast <2 x i32> [[TMP16]] to <1 x i64>208; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 0209; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 0210; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 8211; CHECK-NEXT: ret i64 [[TMP13]]212;213entry:214 %0 = bitcast <1 x i64> %b to <2 x i32>215 %1 = bitcast <1 x i64> %a to <2 x i32>216 %mmx_var.i = bitcast <2 x i32> %1 to <1 x i64>217 %mmx_var1.i = bitcast <2 x i32> %0 to <1 x i64>218 %2 = tail call <1 x i64> @llvm.x86.mmx.pcmpeq.d(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind219 %3 = bitcast <1 x i64> %2 to <2 x i32>220 %4 = bitcast <2 x i32> %3 to <1 x i64>221 %5 = extractelement <1 x i64> %4, i32 0222 ret i64 %5223}224 225declare <1 x i64> @llvm.x86.mmx.pcmpeq.w(<1 x i64>, <1 x i64>) nounwind readnone226 227define i64 @test84(<1 x i64> %a, <1 x i64> %b) #0 {228; CHECK-LABEL: define i64 @test84(229; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {230; CHECK-NEXT: entry:231; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8232; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8233; CHECK-NEXT: call void @llvm.donothing()234; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <4 x i16>235; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>236; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <4 x i16>237; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>238; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP14]] to <1 x i64>239; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>240; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>241; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>242; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]243; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pcmpeq.w(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]244; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>245; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <4 x i16>246; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP9]] to <1 x i64>247; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i16> [[TMP16]] to <1 x i64>248; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 0249; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 0250; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 8251; CHECK-NEXT: ret i64 [[TMP13]]252;253entry:254 %0 = bitcast <1 x i64> %b to <4 x i16>255 %1 = bitcast <1 x i64> %a to <4 x i16>256 %mmx_var.i = bitcast <4 x i16> %1 to <1 x i64>257 %mmx_var1.i = bitcast <4 x i16> %0 to <1 x i64>258 %2 = tail call <1 x i64> @llvm.x86.mmx.pcmpeq.w(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind259 %3 = bitcast <1 x i64> %2 to <4 x i16>260 %4 = bitcast <4 x i16> %3 to <1 x i64>261 %5 = extractelement <1 x i64> %4, i32 0262 ret i64 %5263}264 265declare <1 x i64> @llvm.x86.mmx.pcmpeq.b(<1 x i64>, <1 x i64>) nounwind readnone266 267define i64 @test83(<1 x i64> %a, <1 x i64> %b) #0 {268; CHECK-LABEL: define i64 @test83(269; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {270; CHECK-NEXT: entry:271; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8272; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8273; CHECK-NEXT: call void @llvm.donothing()274; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <8 x i8>275; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>276; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <8 x i8>277; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>278; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP14]] to <1 x i64>279; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>280; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP11]] to <1 x i64>281; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>282; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]283; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pcmpeq.b(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]284; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <8 x i8>285; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <8 x i8>286; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP9]] to <1 x i64>287; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x i8> [[TMP16]] to <1 x i64>288; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 0289; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 0290; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 8291; CHECK-NEXT: ret i64 [[TMP13]]292;293entry:294 %0 = bitcast <1 x i64> %b to <8 x i8>295 %1 = bitcast <1 x i64> %a to <8 x i8>296 %mmx_var.i = bitcast <8 x i8> %1 to <1 x i64>297 %mmx_var1.i = bitcast <8 x i8> %0 to <1 x i64>298 %2 = tail call <1 x i64> @llvm.x86.mmx.pcmpeq.b(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind299 %3 = bitcast <1 x i64> %2 to <8 x i8>300 %4 = bitcast <8 x i8> %3 to <1 x i64>301 %5 = extractelement <1 x i64> %4, i32 0302 ret i64 %5303}304 305declare <1 x i64> @llvm.x86.mmx.punpckldq(<1 x i64>, <1 x i64>) nounwind readnone306 307define i64 @test82(<1 x i64> %a, <1 x i64> %b) #0 {308; CHECK-LABEL: define i64 @test82(309; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {310; CHECK-NEXT: entry:311; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8312; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8313; CHECK-NEXT: call void @llvm.donothing()314; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <2 x i32>315; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <2 x i32>316; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <2 x i32>317; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>318; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i32> [[TMP14]] to <1 x i64>319; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <2 x i32> [[TMP1]] to <1 x i64>320; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i32> [[TMP11]] to <1 x i64>321; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>322; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]323; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.punpckldq(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]324; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <2 x i32>325; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <2 x i32>326; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP9]] to <1 x i64>327; CHECK-NEXT: [[TMP12:%.*]] = bitcast <2 x i32> [[TMP16]] to <1 x i64>328; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 0329; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 0330; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 8331; CHECK-NEXT: ret i64 [[TMP13]]332;333entry:334 %0 = bitcast <1 x i64> %b to <2 x i32>335 %1 = bitcast <1 x i64> %a to <2 x i32>336 %mmx_var.i = bitcast <2 x i32> %1 to <1 x i64>337 %mmx_var1.i = bitcast <2 x i32> %0 to <1 x i64>338 %2 = tail call <1 x i64> @llvm.x86.mmx.punpckldq(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind339 %3 = bitcast <1 x i64> %2 to <2 x i32>340 %4 = bitcast <2 x i32> %3 to <1 x i64>341 %5 = extractelement <1 x i64> %4, i32 0342 ret i64 %5343}344 345declare <1 x i64> @llvm.x86.mmx.punpcklwd(<1 x i64>, <1 x i64>) nounwind readnone346 347define i64 @test81(<1 x i64> %a, <1 x i64> %b) #0 {348; CHECK-LABEL: define i64 @test81(349; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {350; CHECK-NEXT: entry:351; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8352; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8353; CHECK-NEXT: call void @llvm.donothing()354; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <4 x i16>355; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>356; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <4 x i16>357; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>358; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP14]] to <1 x i64>359; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>360; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>361; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>362; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]363; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.punpcklwd(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]364; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>365; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <4 x i16>366; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP9]] to <1 x i64>367; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i16> [[TMP16]] to <1 x i64>368; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 0369; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 0370; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 8371; CHECK-NEXT: ret i64 [[TMP13]]372;373entry:374 %0 = bitcast <1 x i64> %b to <4 x i16>375 %1 = bitcast <1 x i64> %a to <4 x i16>376 %mmx_var.i = bitcast <4 x i16> %1 to <1 x i64>377 %mmx_var1.i = bitcast <4 x i16> %0 to <1 x i64>378 %2 = tail call <1 x i64> @llvm.x86.mmx.punpcklwd(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind379 %3 = bitcast <1 x i64> %2 to <4 x i16>380 %4 = bitcast <4 x i16> %3 to <1 x i64>381 %5 = extractelement <1 x i64> %4, i32 0382 ret i64 %5383}384 385declare <1 x i64> @llvm.x86.mmx.punpcklbw(<1 x i64>, <1 x i64>) nounwind readnone386 387define i64 @test80(<1 x i64> %a, <1 x i64> %b) #0 {388; CHECK-LABEL: define i64 @test80(389; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {390; CHECK-NEXT: entry:391; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8392; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8393; CHECK-NEXT: call void @llvm.donothing()394; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <8 x i8>395; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>396; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <8 x i8>397; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>398; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP14]] to <1 x i64>399; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>400; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP11]] to <1 x i64>401; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>402; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]403; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.punpcklbw(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]404; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <8 x i8>405; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <8 x i8>406; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP9]] to <1 x i64>407; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x i8> [[TMP16]] to <1 x i64>408; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 0409; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 0410; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 8411; CHECK-NEXT: ret i64 [[TMP13]]412;413entry:414 %0 = bitcast <1 x i64> %b to <8 x i8>415 %1 = bitcast <1 x i64> %a to <8 x i8>416 %mmx_var.i = bitcast <8 x i8> %1 to <1 x i64>417 %mmx_var1.i = bitcast <8 x i8> %0 to <1 x i64>418 %2 = tail call <1 x i64> @llvm.x86.mmx.punpcklbw(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind419 %3 = bitcast <1 x i64> %2 to <8 x i8>420 %4 = bitcast <8 x i8> %3 to <1 x i64>421 %5 = extractelement <1 x i64> %4, i32 0422 ret i64 %5423}424 425declare <1 x i64> @llvm.x86.mmx.punpckhdq(<1 x i64>, <1 x i64>) nounwind readnone426 427define i64 @test79(<1 x i64> %a, <1 x i64> %b) #0 {428; CHECK-LABEL: define i64 @test79(429; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {430; CHECK-NEXT: entry:431; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8432; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8433; CHECK-NEXT: call void @llvm.donothing()434; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <2 x i32>435; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <2 x i32>436; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <2 x i32>437; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>438; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i32> [[TMP14]] to <1 x i64>439; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <2 x i32> [[TMP1]] to <1 x i64>440; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i32> [[TMP11]] to <1 x i64>441; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>442; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]443; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.punpckhdq(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]444; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <2 x i32>445; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <2 x i32>446; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP9]] to <1 x i64>447; CHECK-NEXT: [[TMP12:%.*]] = bitcast <2 x i32> [[TMP16]] to <1 x i64>448; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 0449; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 0450; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 8451; CHECK-NEXT: ret i64 [[TMP13]]452;453entry:454 %0 = bitcast <1 x i64> %b to <2 x i32>455 %1 = bitcast <1 x i64> %a to <2 x i32>456 %mmx_var.i = bitcast <2 x i32> %1 to <1 x i64>457 %mmx_var1.i = bitcast <2 x i32> %0 to <1 x i64>458 %2 = tail call <1 x i64> @llvm.x86.mmx.punpckhdq(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind459 %3 = bitcast <1 x i64> %2 to <2 x i32>460 %4 = bitcast <2 x i32> %3 to <1 x i64>461 %5 = extractelement <1 x i64> %4, i32 0462 ret i64 %5463}464 465declare <1 x i64> @llvm.x86.mmx.punpckhwd(<1 x i64>, <1 x i64>) nounwind readnone466 467define i64 @test78(<1 x i64> %a, <1 x i64> %b) #0 {468; CHECK-LABEL: define i64 @test78(469; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {470; CHECK-NEXT: entry:471; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8472; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8473; CHECK-NEXT: call void @llvm.donothing()474; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <4 x i16>475; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>476; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <4 x i16>477; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>478; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP14]] to <1 x i64>479; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>480; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>481; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>482; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]483; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.punpckhwd(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]484; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>485; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <4 x i16>486; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP9]] to <1 x i64>487; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i16> [[TMP16]] to <1 x i64>488; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 0489; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 0490; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 8491; CHECK-NEXT: ret i64 [[TMP13]]492;493entry:494 %0 = bitcast <1 x i64> %b to <4 x i16>495 %1 = bitcast <1 x i64> %a to <4 x i16>496 %mmx_var.i = bitcast <4 x i16> %1 to <1 x i64>497 %mmx_var1.i = bitcast <4 x i16> %0 to <1 x i64>498 %2 = tail call <1 x i64> @llvm.x86.mmx.punpckhwd(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind499 %3 = bitcast <1 x i64> %2 to <4 x i16>500 %4 = bitcast <4 x i16> %3 to <1 x i64>501 %5 = extractelement <1 x i64> %4, i32 0502 ret i64 %5503}504 505declare <1 x i64> @llvm.x86.mmx.punpckhbw(<1 x i64>, <1 x i64>) nounwind readnone506 507define i64 @test77(<1 x i64> %a, <1 x i64> %b) #0 {508; CHECK-LABEL: define i64 @test77(509; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {510; CHECK-NEXT: entry:511; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8512; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8513; CHECK-NEXT: call void @llvm.donothing()514; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <8 x i8>515; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>516; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <8 x i8>517; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>518; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP14]] to <1 x i64>519; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>520; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP11]] to <1 x i64>521; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>522; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]523; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.punpckhbw(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]524; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <8 x i8>525; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <8 x i8>526; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP9]] to <1 x i64>527; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x i8> [[TMP16]] to <1 x i64>528; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 0529; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 0530; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 8531; CHECK-NEXT: ret i64 [[TMP13]]532;533entry:534 %0 = bitcast <1 x i64> %b to <8 x i8>535 %1 = bitcast <1 x i64> %a to <8 x i8>536 %mmx_var.i = bitcast <8 x i8> %1 to <1 x i64>537 %mmx_var1.i = bitcast <8 x i8> %0 to <1 x i64>538 %2 = tail call <1 x i64> @llvm.x86.mmx.punpckhbw(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind539 %3 = bitcast <1 x i64> %2 to <8 x i8>540 %4 = bitcast <8 x i8> %3 to <1 x i64>541 %5 = extractelement <1 x i64> %4, i32 0542 ret i64 %5543}544 545declare <1 x i64> @llvm.x86.mmx.packuswb(<1 x i64>, <1 x i64>) nounwind readnone546 547define i64 @test76(<1 x i64> %a, <1 x i64> %b) #0 {548; CHECK-LABEL: define i64 @test76(549; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {550; CHECK-NEXT: entry:551; CHECK-NEXT: [[TMP16:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8552; CHECK-NEXT: [[TMP17:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8553; CHECK-NEXT: call void @llvm.donothing()554; CHECK-NEXT: [[TMP19:%.*]] = bitcast <1 x i64> [[TMP16]] to <4 x i16>555; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>556; CHECK-NEXT: [[TMP20:%.*]] = bitcast <1 x i64> [[TMP17]] to <4 x i16>557; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>558; CHECK-NEXT: [[TMP23:%.*]] = bitcast <4 x i16> [[TMP20]] to <1 x i64>559; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>560; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[TMP19]] to <1 x i64>561; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>562; CHECK-NEXT: [[TMP8:%.*]] = bitcast <1 x i64> [[TMP23]] to <4 x i16>563; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[TMP7]] to <4 x i16>564; CHECK-NEXT: [[TMP10:%.*]] = icmp ne <4 x i16> [[TMP8]], zeroinitializer565; CHECK-NEXT: [[TMP11:%.*]] = sext <4 x i1> [[TMP10]] to <4 x i16>566; CHECK-NEXT: [[TMP12:%.*]] = icmp ne <4 x i16> [[TMP9]], zeroinitializer567; CHECK-NEXT: [[TMP13:%.*]] = sext <4 x i1> [[TMP12]] to <4 x i16>568; CHECK-NEXT: [[TMP14:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>569; CHECK-NEXT: [[TMP15:%.*]] = bitcast <4 x i16> [[TMP13]] to <1 x i64>570; CHECK-NEXT: [[_MSPROP_VECTOR_PACK:%.*]] = call <1 x i64> @llvm.x86.mmx.packsswb(<1 x i64> [[TMP14]], <1 x i64> [[TMP15]])571; CHECK-NEXT: [[TMP24:%.*]] = tail call <1 x i64> @llvm.x86.mmx.packuswb(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]572; CHECK-NEXT: [[TMP18:%.*]] = bitcast <1 x i64> [[_MSPROP_VECTOR_PACK]] to <8 x i8>573; CHECK-NEXT: [[TMP4:%.*]] = bitcast <1 x i64> [[TMP24]] to <8 x i8>574; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP18]] to <1 x i64>575; CHECK-NEXT: [[TMP21:%.*]] = bitcast <8 x i8> [[TMP4]] to <1 x i64>576; CHECK-NEXT: [[TMP6:%.*]] = extractelement <1 x i64> [[TMP5]], i32 0577; CHECK-NEXT: [[TMP22:%.*]] = extractelement <1 x i64> [[TMP21]], i32 0578; CHECK-NEXT: store i64 [[TMP6]], ptr @__msan_retval_tls, align 8579; CHECK-NEXT: ret i64 [[TMP22]]580;581entry:582 %0 = bitcast <1 x i64> %b to <4 x i16>583 %1 = bitcast <1 x i64> %a to <4 x i16>584 %mmx_var.i = bitcast <4 x i16> %1 to <1 x i64>585 %mmx_var1.i = bitcast <4 x i16> %0 to <1 x i64>586 %2 = tail call <1 x i64> @llvm.x86.mmx.packuswb(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind587 %3 = bitcast <1 x i64> %2 to <8 x i8>588 %4 = bitcast <8 x i8> %3 to <1 x i64>589 %5 = extractelement <1 x i64> %4, i32 0590 ret i64 %5591}592 593declare <1 x i64> @llvm.x86.mmx.packssdw(<1 x i64>, <1 x i64>) nounwind readnone594 595define i64 @test75(<1 x i64> %a, <1 x i64> %b) #0 {596; CHECK-LABEL: define i64 @test75(597; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {598; CHECK-NEXT: entry:599; CHECK-NEXT: [[TMP16:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8600; CHECK-NEXT: [[TMP17:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8601; CHECK-NEXT: call void @llvm.donothing()602; CHECK-NEXT: [[TMP19:%.*]] = bitcast <1 x i64> [[TMP16]] to <2 x i32>603; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <2 x i32>604; CHECK-NEXT: [[TMP20:%.*]] = bitcast <1 x i64> [[TMP17]] to <2 x i32>605; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>606; CHECK-NEXT: [[TMP23:%.*]] = bitcast <2 x i32> [[TMP20]] to <1 x i64>607; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <2 x i32> [[TMP1]] to <1 x i64>608; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i32> [[TMP19]] to <1 x i64>609; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>610; CHECK-NEXT: [[TMP8:%.*]] = bitcast <1 x i64> [[TMP23]] to <2 x i32>611; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[TMP7]] to <2 x i32>612; CHECK-NEXT: [[TMP10:%.*]] = icmp ne <2 x i32> [[TMP8]], zeroinitializer613; CHECK-NEXT: [[TMP11:%.*]] = sext <2 x i1> [[TMP10]] to <2 x i32>614; CHECK-NEXT: [[TMP12:%.*]] = icmp ne <2 x i32> [[TMP9]], zeroinitializer615; CHECK-NEXT: [[TMP13:%.*]] = sext <2 x i1> [[TMP12]] to <2 x i32>616; CHECK-NEXT: [[TMP14:%.*]] = bitcast <2 x i32> [[TMP11]] to <1 x i64>617; CHECK-NEXT: [[TMP15:%.*]] = bitcast <2 x i32> [[TMP13]] to <1 x i64>618; CHECK-NEXT: [[_MSPROP_VECTOR_PACK:%.*]] = call <1 x i64> @llvm.x86.mmx.packssdw(<1 x i64> [[TMP14]], <1 x i64> [[TMP15]])619; CHECK-NEXT: [[TMP24:%.*]] = tail call <1 x i64> @llvm.x86.mmx.packssdw(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]620; CHECK-NEXT: [[TMP18:%.*]] = bitcast <1 x i64> [[_MSPROP_VECTOR_PACK]] to <4 x i16>621; CHECK-NEXT: [[TMP4:%.*]] = bitcast <1 x i64> [[TMP24]] to <4 x i16>622; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i16> [[TMP18]] to <1 x i64>623; CHECK-NEXT: [[TMP21:%.*]] = bitcast <4 x i16> [[TMP4]] to <1 x i64>624; CHECK-NEXT: [[TMP6:%.*]] = extractelement <1 x i64> [[TMP5]], i32 0625; CHECK-NEXT: [[TMP22:%.*]] = extractelement <1 x i64> [[TMP21]], i32 0626; CHECK-NEXT: store i64 [[TMP6]], ptr @__msan_retval_tls, align 8627; CHECK-NEXT: ret i64 [[TMP22]]628;629entry:630 %0 = bitcast <1 x i64> %b to <2 x i32>631 %1 = bitcast <1 x i64> %a to <2 x i32>632 %mmx_var.i = bitcast <2 x i32> %1 to <1 x i64>633 %mmx_var1.i = bitcast <2 x i32> %0 to <1 x i64>634 %2 = tail call <1 x i64> @llvm.x86.mmx.packssdw(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind635 %3 = bitcast <1 x i64> %2 to <4 x i16>636 %4 = bitcast <4 x i16> %3 to <1 x i64>637 %5 = extractelement <1 x i64> %4, i32 0638 ret i64 %5639}640 641declare <1 x i64> @llvm.x86.mmx.packsswb(<1 x i64>, <1 x i64>) nounwind readnone642 643define i64 @test74(<1 x i64> %a, <1 x i64> %b) #0 {644; CHECK-LABEL: define i64 @test74(645; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {646; CHECK-NEXT: entry:647; CHECK-NEXT: [[TMP16:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8648; CHECK-NEXT: [[TMP17:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8649; CHECK-NEXT: call void @llvm.donothing()650; CHECK-NEXT: [[TMP19:%.*]] = bitcast <1 x i64> [[TMP16]] to <4 x i16>651; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>652; CHECK-NEXT: [[TMP20:%.*]] = bitcast <1 x i64> [[TMP17]] to <4 x i16>653; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>654; CHECK-NEXT: [[TMP23:%.*]] = bitcast <4 x i16> [[TMP20]] to <1 x i64>655; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>656; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[TMP19]] to <1 x i64>657; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>658; CHECK-NEXT: [[TMP8:%.*]] = bitcast <1 x i64> [[TMP23]] to <4 x i16>659; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[TMP7]] to <4 x i16>660; CHECK-NEXT: [[TMP10:%.*]] = icmp ne <4 x i16> [[TMP8]], zeroinitializer661; CHECK-NEXT: [[TMP11:%.*]] = sext <4 x i1> [[TMP10]] to <4 x i16>662; CHECK-NEXT: [[TMP12:%.*]] = icmp ne <4 x i16> [[TMP9]], zeroinitializer663; CHECK-NEXT: [[TMP13:%.*]] = sext <4 x i1> [[TMP12]] to <4 x i16>664; CHECK-NEXT: [[TMP14:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>665; CHECK-NEXT: [[TMP15:%.*]] = bitcast <4 x i16> [[TMP13]] to <1 x i64>666; CHECK-NEXT: [[_MSPROP_VECTOR_PACK:%.*]] = call <1 x i64> @llvm.x86.mmx.packsswb(<1 x i64> [[TMP14]], <1 x i64> [[TMP15]])667; CHECK-NEXT: [[TMP24:%.*]] = tail call <1 x i64> @llvm.x86.mmx.packsswb(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]668; CHECK-NEXT: [[TMP18:%.*]] = bitcast <1 x i64> [[_MSPROP_VECTOR_PACK]] to <8 x i8>669; CHECK-NEXT: [[TMP4:%.*]] = bitcast <1 x i64> [[TMP24]] to <8 x i8>670; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP18]] to <1 x i64>671; CHECK-NEXT: [[TMP21:%.*]] = bitcast <8 x i8> [[TMP4]] to <1 x i64>672; CHECK-NEXT: [[TMP6:%.*]] = extractelement <1 x i64> [[TMP5]], i32 0673; CHECK-NEXT: [[TMP22:%.*]] = extractelement <1 x i64> [[TMP21]], i32 0674; CHECK-NEXT: store i64 [[TMP6]], ptr @__msan_retval_tls, align 8675; CHECK-NEXT: ret i64 [[TMP22]]676;677entry:678 %0 = bitcast <1 x i64> %b to <4 x i16>679 %1 = bitcast <1 x i64> %a to <4 x i16>680 %mmx_var.i = bitcast <4 x i16> %1 to <1 x i64>681 %mmx_var1.i = bitcast <4 x i16> %0 to <1 x i64>682 %2 = tail call <1 x i64> @llvm.x86.mmx.packsswb(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind683 %3 = bitcast <1 x i64> %2 to <8 x i8>684 %4 = bitcast <8 x i8> %3 to <1 x i64>685 %5 = extractelement <1 x i64> %4, i32 0686 ret i64 %5687}688 689declare <1 x i64> @llvm.x86.mmx.psrai.d(<1 x i64>, i32) nounwind readnone690 691define i64 @test73(<1 x i64> %a) #0 {692; CHECK-LABEL: define i64 @test73(693; CHECK-SAME: <1 x i64> [[A:%.*]]) #[[ATTR1]] {694; CHECK-NEXT: entry:695; CHECK-NEXT: [[TMP7:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8696; CHECK-NEXT: call void @llvm.donothing()697; CHECK-NEXT: [[TMP8:%.*]] = bitcast <1 x i64> [[TMP7]] to <2 x i32>698; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>699; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP8]] to <1 x i64>700; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>701; CHECK-NEXT: [[TMP2:%.*]] = call <1 x i64> @llvm.x86.mmx.psrai.d(<1 x i64> [[TMP1]], i32 3)702; CHECK-NEXT: [[TMP11:%.*]] = or <1 x i64> [[TMP2]], zeroinitializer703; CHECK-NEXT: [[TMP9:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psrai.d(<1 x i64> [[MMX_VAR_I]], i32 3) #[[ATTR2]]704; CHECK-NEXT: [[TMP10:%.*]] = bitcast <1 x i64> [[TMP11]] to <2 x i32>705; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP9]] to <2 x i32>706; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i32> [[TMP10]] to <1 x i64>707; CHECK-NEXT: [[TMP12:%.*]] = bitcast <2 x i32> [[TMP14]] to <1 x i64>708; CHECK-NEXT: [[TMP6:%.*]] = extractelement <1 x i64> [[TMP5]], i32 0709; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 0710; CHECK-NEXT: store i64 [[TMP6]], ptr @__msan_retval_tls, align 8711; CHECK-NEXT: ret i64 [[TMP13]]712;713entry:714 %0 = bitcast <1 x i64> %a to <2 x i32>715 %mmx_var.i = bitcast <2 x i32> %0 to <1 x i64>716 %1 = tail call <1 x i64> @llvm.x86.mmx.psrai.d(<1 x i64> %mmx_var.i, i32 3) nounwind717 %2 = bitcast <1 x i64> %1 to <2 x i32>718 %3 = bitcast <2 x i32> %2 to <1 x i64>719 %4 = extractelement <1 x i64> %3, i32 0720 ret i64 %4721}722 723declare <1 x i64> @llvm.x86.mmx.psrai.w(<1 x i64>, i32) nounwind readnone724 725define i64 @test72(<1 x i64> %a) #0 {726; CHECK-LABEL: define i64 @test72(727; CHECK-SAME: <1 x i64> [[A:%.*]]) #[[ATTR1]] {728; CHECK-NEXT: entry:729; CHECK-NEXT: [[TMP7:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8730; CHECK-NEXT: call void @llvm.donothing()731; CHECK-NEXT: [[TMP8:%.*]] = bitcast <1 x i64> [[TMP7]] to <4 x i16>732; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>733; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP8]] to <1 x i64>734; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>735; CHECK-NEXT: [[TMP2:%.*]] = call <1 x i64> @llvm.x86.mmx.psrai.w(<1 x i64> [[TMP1]], i32 3)736; CHECK-NEXT: [[TMP11:%.*]] = or <1 x i64> [[TMP2]], zeroinitializer737; CHECK-NEXT: [[TMP9:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psrai.w(<1 x i64> [[MMX_VAR_I]], i32 3) #[[ATTR2]]738; CHECK-NEXT: [[TMP10:%.*]] = bitcast <1 x i64> [[TMP11]] to <4 x i16>739; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP9]] to <4 x i16>740; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i16> [[TMP10]] to <1 x i64>741; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i16> [[TMP14]] to <1 x i64>742; CHECK-NEXT: [[TMP6:%.*]] = extractelement <1 x i64> [[TMP5]], i32 0743; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 0744; CHECK-NEXT: store i64 [[TMP6]], ptr @__msan_retval_tls, align 8745; CHECK-NEXT: ret i64 [[TMP13]]746;747entry:748 %0 = bitcast <1 x i64> %a to <4 x i16>749 %mmx_var.i = bitcast <4 x i16> %0 to <1 x i64>750 %1 = tail call <1 x i64> @llvm.x86.mmx.psrai.w(<1 x i64> %mmx_var.i, i32 3) nounwind751 %2 = bitcast <1 x i64> %1 to <4 x i16>752 %3 = bitcast <4 x i16> %2 to <1 x i64>753 %4 = extractelement <1 x i64> %3, i32 0754 ret i64 %4755}756 757define i64 @test72_2(<1 x i64> %a) #0 {758; CHECK-LABEL: define i64 @test72_2(759; CHECK-SAME: <1 x i64> [[A:%.*]]) #[[ATTR1]] {760; CHECK-NEXT: entry:761; CHECK-NEXT: [[TMP7:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8762; CHECK-NEXT: call void @llvm.donothing()763; CHECK-NEXT: [[TMP8:%.*]] = bitcast <1 x i64> [[TMP7]] to <4 x i16>764; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>765; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP8]] to <1 x i64>766; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>767; CHECK-NEXT: [[TMP2:%.*]] = call <1 x i64> @llvm.x86.mmx.psrai.w(<1 x i64> [[TMP1]], i32 0)768; CHECK-NEXT: [[TMP11:%.*]] = or <1 x i64> [[TMP2]], zeroinitializer769; CHECK-NEXT: [[TMP9:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psrai.w(<1 x i64> [[MMX_VAR_I]], i32 0) #[[ATTR2]]770; CHECK-NEXT: [[TMP10:%.*]] = bitcast <1 x i64> [[TMP11]] to <4 x i16>771; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP9]] to <4 x i16>772; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i16> [[TMP10]] to <1 x i64>773; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i16> [[TMP14]] to <1 x i64>774; CHECK-NEXT: [[TMP6:%.*]] = extractelement <1 x i64> [[TMP5]], i32 0775; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 0776; CHECK-NEXT: store i64 [[TMP6]], ptr @__msan_retval_tls, align 8777; CHECK-NEXT: ret i64 [[TMP13]]778;779entry:780 %0 = bitcast <1 x i64> %a to <4 x i16>781 %mmx_var.i = bitcast <4 x i16> %0 to <1 x i64>782 %1 = tail call <1 x i64> @llvm.x86.mmx.psrai.w(<1 x i64> %mmx_var.i, i32 0) nounwind783 %2 = bitcast <1 x i64> %1 to <4 x i16>784 %3 = bitcast <4 x i16> %2 to <1 x i64>785 %4 = extractelement <1 x i64> %3, i32 0786 ret i64 %4787}788 789declare <1 x i64> @llvm.x86.mmx.psrli.q(<1 x i64>, i32) nounwind readnone790 791define i64 @test71(<1 x i64> %a) #0 {792; CHECK-LABEL: define i64 @test71(793; CHECK-SAME: <1 x i64> [[A:%.*]]) #[[ATTR1]] {794; CHECK-NEXT: entry:795; CHECK-NEXT: [[TMP5:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8796; CHECK-NEXT: call void @llvm.donothing()797; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <1 x i64> [[TMP5]], i32 0798; CHECK-NEXT: [[TMP0:%.*]] = extractelement <1 x i64> [[A]], i32 0799; CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[_MSPROP]] to <1 x i64>800; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast i64 [[TMP0]] to <1 x i64>801; CHECK-NEXT: [[TMP3:%.*]] = call <1 x i64> @llvm.x86.mmx.psrli.q(<1 x i64> [[TMP2]], i32 3)802; CHECK-NEXT: [[TMP6:%.*]] = or <1 x i64> [[TMP3]], zeroinitializer803; CHECK-NEXT: [[TMP8:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psrli.q(<1 x i64> [[MMX_VAR_I]], i32 3) #[[ATTR2]]804; CHECK-NEXT: [[TMP7:%.*]] = bitcast <1 x i64> [[TMP6]] to i64805; CHECK-NEXT: [[TMP4:%.*]] = bitcast <1 x i64> [[TMP8]] to i64806; CHECK-NEXT: store i64 [[TMP7]], ptr @__msan_retval_tls, align 8807; CHECK-NEXT: ret i64 [[TMP4]]808;809entry:810 %0 = extractelement <1 x i64> %a, i32 0811 %mmx_var.i = bitcast i64 %0 to <1 x i64>812 %1 = tail call <1 x i64> @llvm.x86.mmx.psrli.q(<1 x i64> %mmx_var.i, i32 3) nounwind813 %2 = bitcast <1 x i64> %1 to i64814 ret i64 %2815}816 817declare <1 x i64> @llvm.x86.mmx.psrli.d(<1 x i64>, i32) nounwind readnone818 819define i64 @test70(<1 x i64> %a) #0 {820; CHECK-LABEL: define i64 @test70(821; CHECK-SAME: <1 x i64> [[A:%.*]]) #[[ATTR1]] {822; CHECK-NEXT: entry:823; CHECK-NEXT: [[TMP7:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8824; CHECK-NEXT: call void @llvm.donothing()825; CHECK-NEXT: [[TMP8:%.*]] = bitcast <1 x i64> [[TMP7]] to <2 x i32>826; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>827; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP8]] to <1 x i64>828; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>829; CHECK-NEXT: [[TMP2:%.*]] = call <1 x i64> @llvm.x86.mmx.psrli.d(<1 x i64> [[TMP1]], i32 3)830; CHECK-NEXT: [[TMP11:%.*]] = or <1 x i64> [[TMP2]], zeroinitializer831; CHECK-NEXT: [[TMP9:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psrli.d(<1 x i64> [[MMX_VAR_I]], i32 3) #[[ATTR2]]832; CHECK-NEXT: [[TMP10:%.*]] = bitcast <1 x i64> [[TMP11]] to <2 x i32>833; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP9]] to <2 x i32>834; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i32> [[TMP10]] to <1 x i64>835; CHECK-NEXT: [[TMP12:%.*]] = bitcast <2 x i32> [[TMP14]] to <1 x i64>836; CHECK-NEXT: [[TMP6:%.*]] = extractelement <1 x i64> [[TMP5]], i32 0837; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 0838; CHECK-NEXT: store i64 [[TMP6]], ptr @__msan_retval_tls, align 8839; CHECK-NEXT: ret i64 [[TMP13]]840;841entry:842 %0 = bitcast <1 x i64> %a to <2 x i32>843 %mmx_var.i = bitcast <2 x i32> %0 to <1 x i64>844 %1 = tail call <1 x i64> @llvm.x86.mmx.psrli.d(<1 x i64> %mmx_var.i, i32 3) nounwind845 %2 = bitcast <1 x i64> %1 to <2 x i32>846 %3 = bitcast <2 x i32> %2 to <1 x i64>847 %4 = extractelement <1 x i64> %3, i32 0848 ret i64 %4849}850 851define i64 @test70_2(<1 x i64> %a) #0 {852; CHECK-LABEL: define i64 @test70_2(853; CHECK-SAME: <1 x i64> [[A:%.*]]) #[[ATTR1]] {854; CHECK-NEXT: entry:855; CHECK-NEXT: [[TMP7:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8856; CHECK-NEXT: call void @llvm.donothing()857; CHECK-NEXT: [[TMP8:%.*]] = bitcast <1 x i64> [[TMP7]] to <2 x i32>858; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>859; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP8]] to <1 x i64>860; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>861; CHECK-NEXT: [[TMP2:%.*]] = call <1 x i64> @llvm.x86.mmx.psrli.d(<1 x i64> [[TMP1]], i32 0)862; CHECK-NEXT: [[TMP11:%.*]] = or <1 x i64> [[TMP2]], zeroinitializer863; CHECK-NEXT: [[TMP9:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psrli.d(<1 x i64> [[MMX_VAR_I]], i32 0) #[[ATTR2]]864; CHECK-NEXT: [[TMP10:%.*]] = bitcast <1 x i64> [[TMP11]] to <2 x i32>865; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP9]] to <2 x i32>866; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i32> [[TMP10]] to <1 x i64>867; CHECK-NEXT: [[TMP12:%.*]] = bitcast <2 x i32> [[TMP14]] to <1 x i64>868; CHECK-NEXT: [[TMP6:%.*]] = extractelement <1 x i64> [[TMP5]], i32 0869; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 0870; CHECK-NEXT: store i64 [[TMP6]], ptr @__msan_retval_tls, align 8871; CHECK-NEXT: ret i64 [[TMP13]]872;873entry:874 %0 = bitcast <1 x i64> %a to <2 x i32>875 %mmx_var.i = bitcast <2 x i32> %0 to <1 x i64>876 %1 = tail call <1 x i64> @llvm.x86.mmx.psrli.d(<1 x i64> %mmx_var.i, i32 0) nounwind877 %2 = bitcast <1 x i64> %1 to <2 x i32>878 %3 = bitcast <2 x i32> %2 to <1 x i64>879 %4 = extractelement <1 x i64> %3, i32 0880 ret i64 %4881}882 883declare <1 x i64> @llvm.x86.mmx.psrli.w(<1 x i64>, i32) nounwind readnone884 885define i64 @test69(<1 x i64> %a) #0 {886; CHECK-LABEL: define i64 @test69(887; CHECK-SAME: <1 x i64> [[A:%.*]]) #[[ATTR1]] {888; CHECK-NEXT: entry:889; CHECK-NEXT: [[TMP7:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8890; CHECK-NEXT: call void @llvm.donothing()891; CHECK-NEXT: [[TMP8:%.*]] = bitcast <1 x i64> [[TMP7]] to <4 x i16>892; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>893; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP8]] to <1 x i64>894; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>895; CHECK-NEXT: [[TMP2:%.*]] = call <1 x i64> @llvm.x86.mmx.psrli.w(<1 x i64> [[TMP1]], i32 3)896; CHECK-NEXT: [[TMP11:%.*]] = or <1 x i64> [[TMP2]], zeroinitializer897; CHECK-NEXT: [[TMP9:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psrli.w(<1 x i64> [[MMX_VAR_I]], i32 3) #[[ATTR2]]898; CHECK-NEXT: [[TMP10:%.*]] = bitcast <1 x i64> [[TMP11]] to <4 x i16>899; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP9]] to <4 x i16>900; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i16> [[TMP10]] to <1 x i64>901; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i16> [[TMP14]] to <1 x i64>902; CHECK-NEXT: [[TMP6:%.*]] = extractelement <1 x i64> [[TMP5]], i32 0903; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 0904; CHECK-NEXT: store i64 [[TMP6]], ptr @__msan_retval_tls, align 8905; CHECK-NEXT: ret i64 [[TMP13]]906;907entry:908 %0 = bitcast <1 x i64> %a to <4 x i16>909 %mmx_var.i = bitcast <4 x i16> %0 to <1 x i64>910 %1 = tail call <1 x i64> @llvm.x86.mmx.psrli.w(<1 x i64> %mmx_var.i, i32 3) nounwind911 %2 = bitcast <1 x i64> %1 to <4 x i16>912 %3 = bitcast <4 x i16> %2 to <1 x i64>913 %4 = extractelement <1 x i64> %3, i32 0914 ret i64 %4915}916 917declare <1 x i64> @llvm.x86.mmx.pslli.q(<1 x i64>, i32) nounwind readnone918 919define i64 @test68(<1 x i64> %a) #0 {920; CHECK-LABEL: define i64 @test68(921; CHECK-SAME: <1 x i64> [[A:%.*]]) #[[ATTR1]] {922; CHECK-NEXT: entry:923; CHECK-NEXT: [[TMP5:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8924; CHECK-NEXT: call void @llvm.donothing()925; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <1 x i64> [[TMP5]], i32 0926; CHECK-NEXT: [[TMP0:%.*]] = extractelement <1 x i64> [[A]], i32 0927; CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[_MSPROP]] to <1 x i64>928; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast i64 [[TMP0]] to <1 x i64>929; CHECK-NEXT: [[TMP3:%.*]] = call <1 x i64> @llvm.x86.mmx.pslli.q(<1 x i64> [[TMP2]], i32 3)930; CHECK-NEXT: [[TMP6:%.*]] = or <1 x i64> [[TMP3]], zeroinitializer931; CHECK-NEXT: [[TMP8:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pslli.q(<1 x i64> [[MMX_VAR_I]], i32 3) #[[ATTR2]]932; CHECK-NEXT: [[TMP7:%.*]] = bitcast <1 x i64> [[TMP6]] to i64933; CHECK-NEXT: [[TMP4:%.*]] = bitcast <1 x i64> [[TMP8]] to i64934; CHECK-NEXT: store i64 [[TMP7]], ptr @__msan_retval_tls, align 8935; CHECK-NEXT: ret i64 [[TMP4]]936;937entry:938 %0 = extractelement <1 x i64> %a, i32 0939 %mmx_var.i = bitcast i64 %0 to <1 x i64>940 %1 = tail call <1 x i64> @llvm.x86.mmx.pslli.q(<1 x i64> %mmx_var.i, i32 3) nounwind941 %2 = bitcast <1 x i64> %1 to i64942 ret i64 %2943}944 945declare <1 x i64> @llvm.x86.mmx.pslli.d(<1 x i64>, i32) nounwind readnone946 947define i64 @test67(<1 x i64> %a) #0 {948; CHECK-LABEL: define i64 @test67(949; CHECK-SAME: <1 x i64> [[A:%.*]]) #[[ATTR1]] {950; CHECK-NEXT: entry:951; CHECK-NEXT: [[TMP7:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8952; CHECK-NEXT: call void @llvm.donothing()953; CHECK-NEXT: [[TMP8:%.*]] = bitcast <1 x i64> [[TMP7]] to <2 x i32>954; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>955; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP8]] to <1 x i64>956; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>957; CHECK-NEXT: [[TMP2:%.*]] = call <1 x i64> @llvm.x86.mmx.pslli.d(<1 x i64> [[TMP1]], i32 3)958; CHECK-NEXT: [[TMP11:%.*]] = or <1 x i64> [[TMP2]], zeroinitializer959; CHECK-NEXT: [[TMP9:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pslli.d(<1 x i64> [[MMX_VAR_I]], i32 3) #[[ATTR2]]960; CHECK-NEXT: [[TMP10:%.*]] = bitcast <1 x i64> [[TMP11]] to <2 x i32>961; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP9]] to <2 x i32>962; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i32> [[TMP10]] to <1 x i64>963; CHECK-NEXT: [[TMP12:%.*]] = bitcast <2 x i32> [[TMP14]] to <1 x i64>964; CHECK-NEXT: [[TMP6:%.*]] = extractelement <1 x i64> [[TMP5]], i32 0965; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 0966; CHECK-NEXT: store i64 [[TMP6]], ptr @__msan_retval_tls, align 8967; CHECK-NEXT: ret i64 [[TMP13]]968;969entry:970 %0 = bitcast <1 x i64> %a to <2 x i32>971 %mmx_var.i = bitcast <2 x i32> %0 to <1 x i64>972 %1 = tail call <1 x i64> @llvm.x86.mmx.pslli.d(<1 x i64> %mmx_var.i, i32 3) nounwind973 %2 = bitcast <1 x i64> %1 to <2 x i32>974 %3 = bitcast <2 x i32> %2 to <1 x i64>975 %4 = extractelement <1 x i64> %3, i32 0976 ret i64 %4977}978 979declare <1 x i64> @llvm.x86.mmx.pslli.w(<1 x i64>, i32) nounwind readnone980 981define i64 @test66(<1 x i64> %a) #0 {982; CHECK-LABEL: define i64 @test66(983; CHECK-SAME: <1 x i64> [[A:%.*]]) #[[ATTR1]] {984; CHECK-NEXT: entry:985; CHECK-NEXT: [[TMP7:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8986; CHECK-NEXT: call void @llvm.donothing()987; CHECK-NEXT: [[TMP8:%.*]] = bitcast <1 x i64> [[TMP7]] to <4 x i16>988; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>989; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP8]] to <1 x i64>990; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>991; CHECK-NEXT: [[TMP2:%.*]] = call <1 x i64> @llvm.x86.mmx.pslli.w(<1 x i64> [[TMP1]], i32 3)992; CHECK-NEXT: [[TMP11:%.*]] = or <1 x i64> [[TMP2]], zeroinitializer993; CHECK-NEXT: [[TMP9:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pslli.w(<1 x i64> [[MMX_VAR_I]], i32 3) #[[ATTR2]]994; CHECK-NEXT: [[TMP10:%.*]] = bitcast <1 x i64> [[TMP11]] to <4 x i16>995; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP9]] to <4 x i16>996; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i16> [[TMP10]] to <1 x i64>997; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i16> [[TMP14]] to <1 x i64>998; CHECK-NEXT: [[TMP6:%.*]] = extractelement <1 x i64> [[TMP5]], i32 0999; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 01000; CHECK-NEXT: store i64 [[TMP6]], ptr @__msan_retval_tls, align 81001; CHECK-NEXT: ret i64 [[TMP13]]1002;1003entry:1004 %0 = bitcast <1 x i64> %a to <4 x i16>1005 %mmx_var.i = bitcast <4 x i16> %0 to <1 x i64>1006 %1 = tail call <1 x i64> @llvm.x86.mmx.pslli.w(<1 x i64> %mmx_var.i, i32 3) nounwind1007 %2 = bitcast <1 x i64> %1 to <4 x i16>1008 %3 = bitcast <4 x i16> %2 to <1 x i64>1009 %4 = extractelement <1 x i64> %3, i32 01010 ret i64 %41011}1012 1013define i64 @test66_2(<1 x i64> %a) #0 {1014; CHECK-LABEL: define i64 @test66_2(1015; CHECK-SAME: <1 x i64> [[A:%.*]]) #[[ATTR1]] {1016; CHECK-NEXT: entry:1017; CHECK-NEXT: [[TMP7:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81018; CHECK-NEXT: call void @llvm.donothing()1019; CHECK-NEXT: [[TMP8:%.*]] = bitcast <1 x i64> [[TMP7]] to <4 x i16>1020; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>1021; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP8]] to <1 x i64>1022; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>1023; CHECK-NEXT: [[TMP2:%.*]] = call <1 x i64> @llvm.x86.mmx.pslli.w(<1 x i64> [[TMP1]], i32 0)1024; CHECK-NEXT: [[TMP11:%.*]] = or <1 x i64> [[TMP2]], zeroinitializer1025; CHECK-NEXT: [[TMP9:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pslli.w(<1 x i64> [[MMX_VAR_I]], i32 0) #[[ATTR2]]1026; CHECK-NEXT: [[TMP10:%.*]] = bitcast <1 x i64> [[TMP11]] to <4 x i16>1027; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP9]] to <4 x i16>1028; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i16> [[TMP10]] to <1 x i64>1029; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i16> [[TMP14]] to <1 x i64>1030; CHECK-NEXT: [[TMP6:%.*]] = extractelement <1 x i64> [[TMP5]], i32 01031; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 01032; CHECK-NEXT: store i64 [[TMP6]], ptr @__msan_retval_tls, align 81033; CHECK-NEXT: ret i64 [[TMP13]]1034;1035entry:1036 %0 = bitcast <1 x i64> %a to <4 x i16>1037 %mmx_var.i = bitcast <4 x i16> %0 to <1 x i64>1038 %1 = tail call <1 x i64> @llvm.x86.mmx.pslli.w(<1 x i64> %mmx_var.i, i32 0) nounwind1039 %2 = bitcast <1 x i64> %1 to <4 x i16>1040 %3 = bitcast <4 x i16> %2 to <1 x i64>1041 %4 = extractelement <1 x i64> %3, i32 01042 ret i64 %41043}1044 1045declare <1 x i64> @llvm.x86.mmx.psra.d(<1 x i64>, <1 x i64>) nounwind readnone1046 1047define i64 @test65(<1 x i64> %a, <1 x i64> %b) #0 {1048; CHECK-LABEL: define i64 @test65(1049; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {1050; CHECK-NEXT: entry:1051; CHECK-NEXT: [[TMP9:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81052; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81053; CHECK-NEXT: call void @llvm.donothing()1054; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP9]] to <2 x i32>1055; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>1056; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP11]] to <1 x i64>1057; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>1058; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <1 x i64> [[TMP10]], i32 01059; CHECK-NEXT: [[TMP1:%.*]] = extractelement <1 x i64> [[B]], i32 01060; CHECK-NEXT: [[TMP8:%.*]] = bitcast i64 [[_MSPROP]] to <1 x i64>1061; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast i64 [[TMP1]] to <1 x i64>1062; CHECK-NEXT: [[TMP15:%.*]] = bitcast <1 x i64> [[TMP8]] to i641063; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[TMP15]], 01064; CHECK-NEXT: [[TMP14:%.*]] = sext i1 [[TMP13]] to i641065; CHECK-NEXT: [[TMP19:%.*]] = bitcast i64 [[TMP14]] to <1 x i64>1066; CHECK-NEXT: [[TMP20:%.*]] = call <1 x i64> @llvm.x86.mmx.psra.d(<1 x i64> [[TMP4]], <1 x i64> [[MMX_VAR1_I]])1067; CHECK-NEXT: [[TMP12:%.*]] = or <1 x i64> [[TMP20]], [[TMP19]]1068; CHECK-NEXT: [[TMP21:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psra.d(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]1069; CHECK-NEXT: [[TMP18:%.*]] = bitcast <1 x i64> [[TMP12]] to <2 x i32>1070; CHECK-NEXT: [[TMP5:%.*]] = bitcast <1 x i64> [[TMP21]] to <2 x i32>1071; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i32> [[TMP18]] to <1 x i64>1072; CHECK-NEXT: [[TMP16:%.*]] = bitcast <2 x i32> [[TMP5]] to <1 x i64>1073; CHECK-NEXT: [[TMP7:%.*]] = extractelement <1 x i64> [[TMP6]], i32 01074; CHECK-NEXT: [[TMP17:%.*]] = extractelement <1 x i64> [[TMP16]], i32 01075; CHECK-NEXT: store i64 [[TMP7]], ptr @__msan_retval_tls, align 81076; CHECK-NEXT: ret i64 [[TMP17]]1077;1078entry:1079 %0 = bitcast <1 x i64> %a to <2 x i32>1080 %mmx_var.i = bitcast <2 x i32> %0 to <1 x i64>1081 %1 = extractelement <1 x i64> %b, i32 01082 %mmx_var1.i = bitcast i64 %1 to <1 x i64>1083 %2 = tail call <1 x i64> @llvm.x86.mmx.psra.d(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind1084 %3 = bitcast <1 x i64> %2 to <2 x i32>1085 %4 = bitcast <2 x i32> %3 to <1 x i64>1086 %5 = extractelement <1 x i64> %4, i32 01087 ret i64 %51088}1089 1090declare <1 x i64> @llvm.x86.mmx.psra.w(<1 x i64>, <1 x i64>) nounwind readnone1091 1092define i64 @test64(<1 x i64> %a, <1 x i64> %b) #0 {1093; CHECK-LABEL: define i64 @test64(1094; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {1095; CHECK-NEXT: entry:1096; CHECK-NEXT: [[TMP9:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81097; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81098; CHECK-NEXT: call void @llvm.donothing()1099; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP9]] to <4 x i16>1100; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>1101; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>1102; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>1103; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <1 x i64> [[TMP10]], i32 01104; CHECK-NEXT: [[TMP1:%.*]] = extractelement <1 x i64> [[B]], i32 01105; CHECK-NEXT: [[TMP8:%.*]] = bitcast i64 [[_MSPROP]] to <1 x i64>1106; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast i64 [[TMP1]] to <1 x i64>1107; CHECK-NEXT: [[TMP15:%.*]] = bitcast <1 x i64> [[TMP8]] to i641108; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[TMP15]], 01109; CHECK-NEXT: [[TMP14:%.*]] = sext i1 [[TMP13]] to i641110; CHECK-NEXT: [[TMP19:%.*]] = bitcast i64 [[TMP14]] to <1 x i64>1111; CHECK-NEXT: [[TMP20:%.*]] = call <1 x i64> @llvm.x86.mmx.psra.w(<1 x i64> [[TMP4]], <1 x i64> [[MMX_VAR1_I]])1112; CHECK-NEXT: [[TMP12:%.*]] = or <1 x i64> [[TMP20]], [[TMP19]]1113; CHECK-NEXT: [[TMP21:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psra.w(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]1114; CHECK-NEXT: [[TMP18:%.*]] = bitcast <1 x i64> [[TMP12]] to <4 x i16>1115; CHECK-NEXT: [[TMP5:%.*]] = bitcast <1 x i64> [[TMP21]] to <4 x i16>1116; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP18]] to <1 x i64>1117; CHECK-NEXT: [[TMP16:%.*]] = bitcast <4 x i16> [[TMP5]] to <1 x i64>1118; CHECK-NEXT: [[TMP7:%.*]] = extractelement <1 x i64> [[TMP6]], i32 01119; CHECK-NEXT: [[TMP17:%.*]] = extractelement <1 x i64> [[TMP16]], i32 01120; CHECK-NEXT: store i64 [[TMP7]], ptr @__msan_retval_tls, align 81121; CHECK-NEXT: ret i64 [[TMP17]]1122;1123entry:1124 %0 = bitcast <1 x i64> %a to <4 x i16>1125 %mmx_var.i = bitcast <4 x i16> %0 to <1 x i64>1126 %1 = extractelement <1 x i64> %b, i32 01127 %mmx_var1.i = bitcast i64 %1 to <1 x i64>1128 %2 = tail call <1 x i64> @llvm.x86.mmx.psra.w(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind1129 %3 = bitcast <1 x i64> %2 to <4 x i16>1130 %4 = bitcast <4 x i16> %3 to <1 x i64>1131 %5 = extractelement <1 x i64> %4, i32 01132 ret i64 %51133}1134 1135declare <1 x i64> @llvm.x86.mmx.psrl.q(<1 x i64>, <1 x i64>) nounwind readnone1136 1137define i64 @test63(<1 x i64> %a, <1 x i64> %b) #0 {1138; CHECK-LABEL: define i64 @test63(1139; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {1140; CHECK-NEXT: entry:1141; CHECK-NEXT: [[TMP7:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81142; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81143; CHECK-NEXT: call void @llvm.donothing()1144; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <1 x i64> [[TMP7]], i32 01145; CHECK-NEXT: [[TMP0:%.*]] = extractelement <1 x i64> [[A]], i32 01146; CHECK-NEXT: [[TMP3:%.*]] = bitcast i64 [[_MSPROP]] to <1 x i64>1147; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast i64 [[TMP0]] to <1 x i64>1148; CHECK-NEXT: [[_MSPROP1:%.*]] = extractelement <1 x i64> [[TMP8]], i32 01149; CHECK-NEXT: [[TMP1:%.*]] = extractelement <1 x i64> [[B]], i32 01150; CHECK-NEXT: [[TMP13:%.*]] = bitcast i64 [[_MSPROP1]] to <1 x i64>1151; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast i64 [[TMP1]] to <1 x i64>1152; CHECK-NEXT: [[TMP6:%.*]] = bitcast <1 x i64> [[TMP13]] to i641153; CHECK-NEXT: [[TMP9:%.*]] = icmp ne i64 [[TMP6]], 01154; CHECK-NEXT: [[TMP10:%.*]] = sext i1 [[TMP9]] to i641155; CHECK-NEXT: [[TMP14:%.*]] = bitcast i64 [[TMP10]] to <1 x i64>1156; CHECK-NEXT: [[TMP15:%.*]] = call <1 x i64> @llvm.x86.mmx.psrl.q(<1 x i64> [[TMP3]], <1 x i64> [[MMX_VAR1_I]])1157; CHECK-NEXT: [[TMP16:%.*]] = or <1 x i64> [[TMP15]], [[TMP14]]1158; CHECK-NEXT: [[TMP12:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psrl.q(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]1159; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP16]] to i641160; CHECK-NEXT: [[TMP5:%.*]] = bitcast <1 x i64> [[TMP12]] to i641161; CHECK-NEXT: store i64 [[TMP11]], ptr @__msan_retval_tls, align 81162; CHECK-NEXT: ret i64 [[TMP5]]1163;1164entry:1165 %0 = extractelement <1 x i64> %a, i32 01166 %mmx_var.i = bitcast i64 %0 to <1 x i64>1167 %1 = extractelement <1 x i64> %b, i32 01168 %mmx_var1.i = bitcast i64 %1 to <1 x i64>1169 %2 = tail call <1 x i64> @llvm.x86.mmx.psrl.q(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind1170 %3 = bitcast <1 x i64> %2 to i641171 ret i64 %31172}1173 1174declare <1 x i64> @llvm.x86.mmx.psrl.d(<1 x i64>, <1 x i64>) nounwind readnone1175 1176define i64 @test62(<1 x i64> %a, <1 x i64> %b) #0 {1177; CHECK-LABEL: define i64 @test62(1178; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {1179; CHECK-NEXT: entry:1180; CHECK-NEXT: [[TMP9:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81181; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81182; CHECK-NEXT: call void @llvm.donothing()1183; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP9]] to <2 x i32>1184; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>1185; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP11]] to <1 x i64>1186; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>1187; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <1 x i64> [[TMP10]], i32 01188; CHECK-NEXT: [[TMP1:%.*]] = extractelement <1 x i64> [[B]], i32 01189; CHECK-NEXT: [[TMP8:%.*]] = bitcast i64 [[_MSPROP]] to <1 x i64>1190; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast i64 [[TMP1]] to <1 x i64>1191; CHECK-NEXT: [[TMP15:%.*]] = bitcast <1 x i64> [[TMP8]] to i641192; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[TMP15]], 01193; CHECK-NEXT: [[TMP14:%.*]] = sext i1 [[TMP13]] to i641194; CHECK-NEXT: [[TMP19:%.*]] = bitcast i64 [[TMP14]] to <1 x i64>1195; CHECK-NEXT: [[TMP20:%.*]] = call <1 x i64> @llvm.x86.mmx.psrl.d(<1 x i64> [[TMP4]], <1 x i64> [[MMX_VAR1_I]])1196; CHECK-NEXT: [[TMP12:%.*]] = or <1 x i64> [[TMP20]], [[TMP19]]1197; CHECK-NEXT: [[TMP21:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psrl.d(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]1198; CHECK-NEXT: [[TMP18:%.*]] = bitcast <1 x i64> [[TMP12]] to <2 x i32>1199; CHECK-NEXT: [[TMP5:%.*]] = bitcast <1 x i64> [[TMP21]] to <2 x i32>1200; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i32> [[TMP18]] to <1 x i64>1201; CHECK-NEXT: [[TMP16:%.*]] = bitcast <2 x i32> [[TMP5]] to <1 x i64>1202; CHECK-NEXT: [[TMP7:%.*]] = extractelement <1 x i64> [[TMP6]], i32 01203; CHECK-NEXT: [[TMP17:%.*]] = extractelement <1 x i64> [[TMP16]], i32 01204; CHECK-NEXT: store i64 [[TMP7]], ptr @__msan_retval_tls, align 81205; CHECK-NEXT: ret i64 [[TMP17]]1206;1207entry:1208 %0 = bitcast <1 x i64> %a to <2 x i32>1209 %mmx_var.i = bitcast <2 x i32> %0 to <1 x i64>1210 %1 = extractelement <1 x i64> %b, i32 01211 %mmx_var1.i = bitcast i64 %1 to <1 x i64>1212 %2 = tail call <1 x i64> @llvm.x86.mmx.psrl.d(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind1213 %3 = bitcast <1 x i64> %2 to <2 x i32>1214 %4 = bitcast <2 x i32> %3 to <1 x i64>1215 %5 = extractelement <1 x i64> %4, i32 01216 ret i64 %51217}1218 1219declare <1 x i64> @llvm.x86.mmx.psrl.w(<1 x i64>, <1 x i64>) nounwind readnone1220 1221define i64 @test61(<1 x i64> %a, <1 x i64> %b) #0 {1222; CHECK-LABEL: define i64 @test61(1223; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {1224; CHECK-NEXT: entry:1225; CHECK-NEXT: [[TMP9:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81226; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81227; CHECK-NEXT: call void @llvm.donothing()1228; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP9]] to <4 x i16>1229; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>1230; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>1231; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>1232; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <1 x i64> [[TMP10]], i32 01233; CHECK-NEXT: [[TMP1:%.*]] = extractelement <1 x i64> [[B]], i32 01234; CHECK-NEXT: [[TMP8:%.*]] = bitcast i64 [[_MSPROP]] to <1 x i64>1235; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast i64 [[TMP1]] to <1 x i64>1236; CHECK-NEXT: [[TMP15:%.*]] = bitcast <1 x i64> [[TMP8]] to i641237; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[TMP15]], 01238; CHECK-NEXT: [[TMP14:%.*]] = sext i1 [[TMP13]] to i641239; CHECK-NEXT: [[TMP19:%.*]] = bitcast i64 [[TMP14]] to <1 x i64>1240; CHECK-NEXT: [[TMP20:%.*]] = call <1 x i64> @llvm.x86.mmx.psrl.w(<1 x i64> [[TMP4]], <1 x i64> [[MMX_VAR1_I]])1241; CHECK-NEXT: [[TMP12:%.*]] = or <1 x i64> [[TMP20]], [[TMP19]]1242; CHECK-NEXT: [[TMP21:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psrl.w(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]1243; CHECK-NEXT: [[TMP18:%.*]] = bitcast <1 x i64> [[TMP12]] to <4 x i16>1244; CHECK-NEXT: [[TMP5:%.*]] = bitcast <1 x i64> [[TMP21]] to <4 x i16>1245; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP18]] to <1 x i64>1246; CHECK-NEXT: [[TMP16:%.*]] = bitcast <4 x i16> [[TMP5]] to <1 x i64>1247; CHECK-NEXT: [[TMP7:%.*]] = extractelement <1 x i64> [[TMP6]], i32 01248; CHECK-NEXT: [[TMP17:%.*]] = extractelement <1 x i64> [[TMP16]], i32 01249; CHECK-NEXT: store i64 [[TMP7]], ptr @__msan_retval_tls, align 81250; CHECK-NEXT: ret i64 [[TMP17]]1251;1252entry:1253 %0 = bitcast <1 x i64> %a to <4 x i16>1254 %mmx_var.i = bitcast <4 x i16> %0 to <1 x i64>1255 %1 = extractelement <1 x i64> %b, i32 01256 %mmx_var1.i = bitcast i64 %1 to <1 x i64>1257 %2 = tail call <1 x i64> @llvm.x86.mmx.psrl.w(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind1258 %3 = bitcast <1 x i64> %2 to <4 x i16>1259 %4 = bitcast <4 x i16> %3 to <1 x i64>1260 %5 = extractelement <1 x i64> %4, i32 01261 ret i64 %51262}1263 1264declare <1 x i64> @llvm.x86.mmx.psll.q(<1 x i64>, <1 x i64>) nounwind readnone1265 1266define i64 @test60(<1 x i64> %a, <1 x i64> %b) #0 {1267; CHECK-LABEL: define i64 @test60(1268; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {1269; CHECK-NEXT: entry:1270; CHECK-NEXT: [[TMP7:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81271; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81272; CHECK-NEXT: call void @llvm.donothing()1273; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <1 x i64> [[TMP7]], i32 01274; CHECK-NEXT: [[TMP0:%.*]] = extractelement <1 x i64> [[A]], i32 01275; CHECK-NEXT: [[TMP3:%.*]] = bitcast i64 [[_MSPROP]] to <1 x i64>1276; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast i64 [[TMP0]] to <1 x i64>1277; CHECK-NEXT: [[_MSPROP1:%.*]] = extractelement <1 x i64> [[TMP8]], i32 01278; CHECK-NEXT: [[TMP1:%.*]] = extractelement <1 x i64> [[B]], i32 01279; CHECK-NEXT: [[TMP13:%.*]] = bitcast i64 [[_MSPROP1]] to <1 x i64>1280; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast i64 [[TMP1]] to <1 x i64>1281; CHECK-NEXT: [[TMP6:%.*]] = bitcast <1 x i64> [[TMP13]] to i641282; CHECK-NEXT: [[TMP9:%.*]] = icmp ne i64 [[TMP6]], 01283; CHECK-NEXT: [[TMP10:%.*]] = sext i1 [[TMP9]] to i641284; CHECK-NEXT: [[TMP14:%.*]] = bitcast i64 [[TMP10]] to <1 x i64>1285; CHECK-NEXT: [[TMP15:%.*]] = call <1 x i64> @llvm.x86.mmx.psll.q(<1 x i64> [[TMP3]], <1 x i64> [[MMX_VAR1_I]])1286; CHECK-NEXT: [[TMP16:%.*]] = or <1 x i64> [[TMP15]], [[TMP14]]1287; CHECK-NEXT: [[TMP12:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psll.q(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]1288; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP16]] to i641289; CHECK-NEXT: [[TMP5:%.*]] = bitcast <1 x i64> [[TMP12]] to i641290; CHECK-NEXT: store i64 [[TMP11]], ptr @__msan_retval_tls, align 81291; CHECK-NEXT: ret i64 [[TMP5]]1292;1293entry:1294 %0 = extractelement <1 x i64> %a, i32 01295 %mmx_var.i = bitcast i64 %0 to <1 x i64>1296 %1 = extractelement <1 x i64> %b, i32 01297 %mmx_var1.i = bitcast i64 %1 to <1 x i64>1298 %2 = tail call <1 x i64> @llvm.x86.mmx.psll.q(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind1299 %3 = bitcast <1 x i64> %2 to i641300 ret i64 %31301}1302 1303declare <1 x i64> @llvm.x86.mmx.psll.d(<1 x i64>, <1 x i64>) nounwind readnone1304 1305define i64 @test59(<1 x i64> %a, <1 x i64> %b) #0 {1306; CHECK-LABEL: define i64 @test59(1307; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {1308; CHECK-NEXT: entry:1309; CHECK-NEXT: [[TMP9:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81310; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81311; CHECK-NEXT: call void @llvm.donothing()1312; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP9]] to <2 x i32>1313; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>1314; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP11]] to <1 x i64>1315; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>1316; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <1 x i64> [[TMP10]], i32 01317; CHECK-NEXT: [[TMP1:%.*]] = extractelement <1 x i64> [[B]], i32 01318; CHECK-NEXT: [[TMP8:%.*]] = bitcast i64 [[_MSPROP]] to <1 x i64>1319; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast i64 [[TMP1]] to <1 x i64>1320; CHECK-NEXT: [[TMP15:%.*]] = bitcast <1 x i64> [[TMP8]] to i641321; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[TMP15]], 01322; CHECK-NEXT: [[TMP14:%.*]] = sext i1 [[TMP13]] to i641323; CHECK-NEXT: [[TMP19:%.*]] = bitcast i64 [[TMP14]] to <1 x i64>1324; CHECK-NEXT: [[TMP20:%.*]] = call <1 x i64> @llvm.x86.mmx.psll.d(<1 x i64> [[TMP4]], <1 x i64> [[MMX_VAR1_I]])1325; CHECK-NEXT: [[TMP12:%.*]] = or <1 x i64> [[TMP20]], [[TMP19]]1326; CHECK-NEXT: [[TMP21:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psll.d(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]1327; CHECK-NEXT: [[TMP18:%.*]] = bitcast <1 x i64> [[TMP12]] to <2 x i32>1328; CHECK-NEXT: [[TMP5:%.*]] = bitcast <1 x i64> [[TMP21]] to <2 x i32>1329; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i32> [[TMP18]] to <1 x i64>1330; CHECK-NEXT: [[TMP16:%.*]] = bitcast <2 x i32> [[TMP5]] to <1 x i64>1331; CHECK-NEXT: [[TMP7:%.*]] = extractelement <1 x i64> [[TMP6]], i32 01332; CHECK-NEXT: [[TMP17:%.*]] = extractelement <1 x i64> [[TMP16]], i32 01333; CHECK-NEXT: store i64 [[TMP7]], ptr @__msan_retval_tls, align 81334; CHECK-NEXT: ret i64 [[TMP17]]1335;1336entry:1337 %0 = bitcast <1 x i64> %a to <2 x i32>1338 %mmx_var.i = bitcast <2 x i32> %0 to <1 x i64>1339 %1 = extractelement <1 x i64> %b, i32 01340 %mmx_var1.i = bitcast i64 %1 to <1 x i64>1341 %2 = tail call <1 x i64> @llvm.x86.mmx.psll.d(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind1342 %3 = bitcast <1 x i64> %2 to <2 x i32>1343 %4 = bitcast <2 x i32> %3 to <1 x i64>1344 %5 = extractelement <1 x i64> %4, i32 01345 ret i64 %51346}1347 1348declare <1 x i64> @llvm.x86.mmx.psll.w(<1 x i64>, <1 x i64>) nounwind readnone1349 1350define i64 @test58(<1 x i64> %a, <1 x i64> %b) #0 {1351; CHECK-LABEL: define i64 @test58(1352; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {1353; CHECK-NEXT: entry:1354; CHECK-NEXT: [[TMP9:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81355; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81356; CHECK-NEXT: call void @llvm.donothing()1357; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP9]] to <4 x i16>1358; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>1359; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>1360; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>1361; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <1 x i64> [[TMP10]], i32 01362; CHECK-NEXT: [[TMP1:%.*]] = extractelement <1 x i64> [[B]], i32 01363; CHECK-NEXT: [[TMP8:%.*]] = bitcast i64 [[_MSPROP]] to <1 x i64>1364; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast i64 [[TMP1]] to <1 x i64>1365; CHECK-NEXT: [[TMP15:%.*]] = bitcast <1 x i64> [[TMP8]] to i641366; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[TMP15]], 01367; CHECK-NEXT: [[TMP14:%.*]] = sext i1 [[TMP13]] to i641368; CHECK-NEXT: [[TMP19:%.*]] = bitcast i64 [[TMP14]] to <1 x i64>1369; CHECK-NEXT: [[TMP20:%.*]] = call <1 x i64> @llvm.x86.mmx.psll.w(<1 x i64> [[TMP4]], <1 x i64> [[MMX_VAR1_I]])1370; CHECK-NEXT: [[TMP12:%.*]] = or <1 x i64> [[TMP20]], [[TMP19]]1371; CHECK-NEXT: [[TMP21:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psll.w(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]1372; CHECK-NEXT: [[TMP18:%.*]] = bitcast <1 x i64> [[TMP12]] to <4 x i16>1373; CHECK-NEXT: [[TMP5:%.*]] = bitcast <1 x i64> [[TMP21]] to <4 x i16>1374; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP18]] to <1 x i64>1375; CHECK-NEXT: [[TMP16:%.*]] = bitcast <4 x i16> [[TMP5]] to <1 x i64>1376; CHECK-NEXT: [[TMP7:%.*]] = extractelement <1 x i64> [[TMP6]], i32 01377; CHECK-NEXT: [[TMP17:%.*]] = extractelement <1 x i64> [[TMP16]], i32 01378; CHECK-NEXT: store i64 [[TMP7]], ptr @__msan_retval_tls, align 81379; CHECK-NEXT: ret i64 [[TMP17]]1380;1381entry:1382 %0 = bitcast <1 x i64> %a to <4 x i16>1383 %mmx_var.i = bitcast <4 x i16> %0 to <1 x i64>1384 %1 = extractelement <1 x i64> %b, i32 01385 %mmx_var1.i = bitcast i64 %1 to <1 x i64>1386 %2 = tail call <1 x i64> @llvm.x86.mmx.psll.w(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind1387 %3 = bitcast <1 x i64> %2 to <4 x i16>1388 %4 = bitcast <4 x i16> %3 to <1 x i64>1389 %5 = extractelement <1 x i64> %4, i32 01390 ret i64 %51391}1392 1393declare <1 x i64> @llvm.x86.mmx.pxor(<1 x i64>, <1 x i64>) nounwind readnone1394 1395define i64 @test56(<1 x i64> %a, <1 x i64> %b) #0 {1396; CHECK-LABEL: define i64 @test56(1397; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {1398; CHECK-NEXT: entry:1399; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81400; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81401; CHECK-NEXT: call void @llvm.donothing()1402; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <2 x i32>1403; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <2 x i32>1404; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <2 x i32>1405; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>1406; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i32> [[TMP14]] to <1 x i64>1407; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <2 x i32> [[TMP1]] to <1 x i64>1408; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i32> [[TMP11]] to <1 x i64>1409; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>1410; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]1411; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pxor(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]1412; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <2 x i32>1413; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <2 x i32>1414; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP9]] to <1 x i64>1415; CHECK-NEXT: [[TMP12:%.*]] = bitcast <2 x i32> [[TMP16]] to <1 x i64>1416; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 01417; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 01418; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 81419; CHECK-NEXT: ret i64 [[TMP13]]1420;1421entry:1422 %0 = bitcast <1 x i64> %b to <2 x i32>1423 %1 = bitcast <1 x i64> %a to <2 x i32>1424 %mmx_var.i = bitcast <2 x i32> %1 to <1 x i64>1425 %mmx_var1.i = bitcast <2 x i32> %0 to <1 x i64>1426 %2 = tail call <1 x i64> @llvm.x86.mmx.pxor(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind1427 %3 = bitcast <1 x i64> %2 to <2 x i32>1428 %4 = bitcast <2 x i32> %3 to <1 x i64>1429 %5 = extractelement <1 x i64> %4, i32 01430 ret i64 %51431}1432 1433declare <1 x i64> @llvm.x86.mmx.por(<1 x i64>, <1 x i64>) nounwind readnone1434 1435define i64 @test55(<1 x i64> %a, <1 x i64> %b) #0 {1436; CHECK-LABEL: define i64 @test55(1437; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {1438; CHECK-NEXT: entry:1439; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81440; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81441; CHECK-NEXT: call void @llvm.donothing()1442; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <2 x i32>1443; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <2 x i32>1444; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <2 x i32>1445; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>1446; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i32> [[TMP14]] to <1 x i64>1447; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <2 x i32> [[TMP1]] to <1 x i64>1448; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i32> [[TMP11]] to <1 x i64>1449; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>1450; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]1451; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.por(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]1452; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <2 x i32>1453; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <2 x i32>1454; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP9]] to <1 x i64>1455; CHECK-NEXT: [[TMP12:%.*]] = bitcast <2 x i32> [[TMP16]] to <1 x i64>1456; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 01457; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 01458; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 81459; CHECK-NEXT: ret i64 [[TMP13]]1460;1461entry:1462 %0 = bitcast <1 x i64> %b to <2 x i32>1463 %1 = bitcast <1 x i64> %a to <2 x i32>1464 %mmx_var.i = bitcast <2 x i32> %1 to <1 x i64>1465 %mmx_var1.i = bitcast <2 x i32> %0 to <1 x i64>1466 %2 = tail call <1 x i64> @llvm.x86.mmx.por(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind1467 %3 = bitcast <1 x i64> %2 to <2 x i32>1468 %4 = bitcast <2 x i32> %3 to <1 x i64>1469 %5 = extractelement <1 x i64> %4, i32 01470 ret i64 %51471}1472 1473declare <1 x i64> @llvm.x86.mmx.pandn(<1 x i64>, <1 x i64>) nounwind readnone1474 1475define i64 @test54(<1 x i64> %a, <1 x i64> %b) #0 {1476; CHECK-LABEL: define i64 @test54(1477; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {1478; CHECK-NEXT: entry:1479; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81480; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81481; CHECK-NEXT: call void @llvm.donothing()1482; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <2 x i32>1483; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <2 x i32>1484; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <2 x i32>1485; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>1486; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i32> [[TMP14]] to <1 x i64>1487; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <2 x i32> [[TMP1]] to <1 x i64>1488; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i32> [[TMP11]] to <1 x i64>1489; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>1490; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]1491; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pandn(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]1492; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <2 x i32>1493; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <2 x i32>1494; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP9]] to <1 x i64>1495; CHECK-NEXT: [[TMP12:%.*]] = bitcast <2 x i32> [[TMP16]] to <1 x i64>1496; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 01497; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 01498; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 81499; CHECK-NEXT: ret i64 [[TMP13]]1500;1501entry:1502 %0 = bitcast <1 x i64> %b to <2 x i32>1503 %1 = bitcast <1 x i64> %a to <2 x i32>1504 %mmx_var.i = bitcast <2 x i32> %1 to <1 x i64>1505 %mmx_var1.i = bitcast <2 x i32> %0 to <1 x i64>1506 %2 = tail call <1 x i64> @llvm.x86.mmx.pandn(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind1507 %3 = bitcast <1 x i64> %2 to <2 x i32>1508 %4 = bitcast <2 x i32> %3 to <1 x i64>1509 %5 = extractelement <1 x i64> %4, i32 01510 ret i64 %51511}1512 1513declare <1 x i64> @llvm.x86.mmx.pand(<1 x i64>, <1 x i64>) nounwind readnone1514 1515define i64 @test53(<1 x i64> %a, <1 x i64> %b) #0 {1516; CHECK-LABEL: define i64 @test53(1517; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {1518; CHECK-NEXT: entry:1519; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81520; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81521; CHECK-NEXT: call void @llvm.donothing()1522; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <2 x i32>1523; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <2 x i32>1524; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <2 x i32>1525; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>1526; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i32> [[TMP14]] to <1 x i64>1527; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <2 x i32> [[TMP1]] to <1 x i64>1528; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i32> [[TMP11]] to <1 x i64>1529; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>1530; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]1531; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pand(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]1532; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <2 x i32>1533; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <2 x i32>1534; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP9]] to <1 x i64>1535; CHECK-NEXT: [[TMP12:%.*]] = bitcast <2 x i32> [[TMP16]] to <1 x i64>1536; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 01537; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 01538; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 81539; CHECK-NEXT: ret i64 [[TMP13]]1540;1541entry:1542 %0 = bitcast <1 x i64> %b to <2 x i32>1543 %1 = bitcast <1 x i64> %a to <2 x i32>1544 %mmx_var.i = bitcast <2 x i32> %1 to <1 x i64>1545 %mmx_var1.i = bitcast <2 x i32> %0 to <1 x i64>1546 %2 = tail call <1 x i64> @llvm.x86.mmx.pand(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind1547 %3 = bitcast <1 x i64> %2 to <2 x i32>1548 %4 = bitcast <2 x i32> %3 to <1 x i64>1549 %5 = extractelement <1 x i64> %4, i32 01550 ret i64 %51551}1552 1553declare <1 x i64> @llvm.x86.mmx.pmull.w(<1 x i64>, <1 x i64>) nounwind readnone1554 1555define i64 @test52(<1 x i64> %a, <1 x i64> %b) #0 {1556; CHECK-LABEL: define i64 @test52(1557; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {1558; CHECK-NEXT: entry:1559; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81560; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81561; CHECK-NEXT: call void @llvm.donothing()1562; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <4 x i16>1563; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>1564; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <4 x i16>1565; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>1566; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP14]] to <1 x i64>1567; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>1568; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>1569; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>1570; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]1571; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pmull.w(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]1572; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>1573; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <4 x i16>1574; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP9]] to <1 x i64>1575; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i16> [[TMP16]] to <1 x i64>1576; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 01577; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 01578; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 81579; CHECK-NEXT: ret i64 [[TMP13]]1580;1581entry:1582 %0 = bitcast <1 x i64> %b to <4 x i16>1583 %1 = bitcast <1 x i64> %a to <4 x i16>1584 %mmx_var.i = bitcast <4 x i16> %1 to <1 x i64>1585 %mmx_var1.i = bitcast <4 x i16> %0 to <1 x i64>1586 %2 = tail call <1 x i64> @llvm.x86.mmx.pmull.w(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind1587 %3 = bitcast <1 x i64> %2 to <4 x i16>1588 %4 = bitcast <4 x i16> %3 to <1 x i64>1589 %5 = extractelement <1 x i64> %4, i32 01590 ret i64 %51591}1592 1593define i64 @test51(<1 x i64> %a, <1 x i64> %b) #0 {1594; CHECK-LABEL: define i64 @test51(1595; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {1596; CHECK-NEXT: entry:1597; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81598; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81599; CHECK-NEXT: call void @llvm.donothing()1600; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <4 x i16>1601; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>1602; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <4 x i16>1603; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>1604; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP14]] to <1 x i64>1605; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>1606; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>1607; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>1608; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]1609; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pmull.w(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]1610; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>1611; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <4 x i16>1612; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP9]] to <1 x i64>1613; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i16> [[TMP16]] to <1 x i64>1614; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 01615; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 01616; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 81617; CHECK-NEXT: ret i64 [[TMP13]]1618;1619entry:1620 %0 = bitcast <1 x i64> %b to <4 x i16>1621 %1 = bitcast <1 x i64> %a to <4 x i16>1622 %mmx_var.i = bitcast <4 x i16> %1 to <1 x i64>1623 %mmx_var1.i = bitcast <4 x i16> %0 to <1 x i64>1624 %2 = tail call <1 x i64> @llvm.x86.mmx.pmull.w(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind1625 %3 = bitcast <1 x i64> %2 to <4 x i16>1626 %4 = bitcast <4 x i16> %3 to <1 x i64>1627 %5 = extractelement <1 x i64> %4, i32 01628 ret i64 %51629}1630 1631declare <1 x i64> @llvm.x86.mmx.pmulh.w(<1 x i64>, <1 x i64>) nounwind readnone1632 1633define i64 @test50(<1 x i64> %a, <1 x i64> %b) #0 {1634; CHECK-LABEL: define i64 @test50(1635; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {1636; CHECK-NEXT: entry:1637; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81638; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81639; CHECK-NEXT: call void @llvm.donothing()1640; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <4 x i16>1641; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>1642; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <4 x i16>1643; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>1644; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP14]] to <1 x i64>1645; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>1646; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>1647; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>1648; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]1649; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pmulh.w(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]1650; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>1651; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <4 x i16>1652; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP9]] to <1 x i64>1653; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i16> [[TMP16]] to <1 x i64>1654; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 01655; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 01656; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 81657; CHECK-NEXT: ret i64 [[TMP13]]1658;1659entry:1660 %0 = bitcast <1 x i64> %b to <4 x i16>1661 %1 = bitcast <1 x i64> %a to <4 x i16>1662 %mmx_var.i = bitcast <4 x i16> %1 to <1 x i64>1663 %mmx_var1.i = bitcast <4 x i16> %0 to <1 x i64>1664 %2 = tail call <1 x i64> @llvm.x86.mmx.pmulh.w(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind1665 %3 = bitcast <1 x i64> %2 to <4 x i16>1666 %4 = bitcast <4 x i16> %3 to <1 x i64>1667 %5 = extractelement <1 x i64> %4, i32 01668 ret i64 %51669}1670 1671declare <1 x i64> @llvm.x86.mmx.pmadd.wd(<1 x i64>, <1 x i64>) nounwind readnone1672 1673define i64 @test49(<1 x i64> %a, <1 x i64> %b) #0 {1674; CHECK-LABEL: define i64 @test49(1675; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {1676; CHECK-NEXT: entry:1677; CHECK-NEXT: [[TMP13:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81678; CHECK-NEXT: [[TMP15:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81679; CHECK-NEXT: call void @llvm.donothing()1680; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP13]] to <4 x i16>1681; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>1682; CHECK-NEXT: [[TMP19:%.*]] = bitcast <1 x i64> [[TMP15]] to <4 x i16>1683; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>1684; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP19]] to <1 x i64>1685; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>1686; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[TMP16]] to <1 x i64>1687; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>1688; CHECK-NEXT: [[TMP8:%.*]] = bitcast <1 x i64> [[MMX_VAR_I]] to <4 x i16>1689; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[MMX_VAR1_I]] to <4 x i16>1690; CHECK-NEXT: [[TMP10:%.*]] = bitcast <1 x i64> [[TMP6]] to <4 x i16>1691; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP7]] to <4 x i16>1692; CHECK-NEXT: [[TMP29:%.*]] = icmp ne <4 x i16> [[TMP10]], zeroinitializer1693; CHECK-NEXT: [[TMP30:%.*]] = icmp ne <4 x i16> [[TMP11]], zeroinitializer1694; CHECK-NEXT: [[TMP22:%.*]] = icmp ne <4 x i16> [[TMP8]], zeroinitializer1695; CHECK-NEXT: [[TMP32:%.*]] = icmp ne <4 x i16> [[TMP9]], zeroinitializer1696; CHECK-NEXT: [[TMP31:%.*]] = and <4 x i1> [[TMP29]], [[TMP30]]1697; CHECK-NEXT: [[TMP35:%.*]] = and <4 x i1> [[TMP22]], [[TMP30]]1698; CHECK-NEXT: [[TMP36:%.*]] = and <4 x i1> [[TMP29]], [[TMP32]]1699; CHECK-NEXT: [[TMP37:%.*]] = or <4 x i1> [[TMP31]], [[TMP35]]1700; CHECK-NEXT: [[TMP38:%.*]] = or <4 x i1> [[TMP37]], [[TMP36]]1701; CHECK-NEXT: [[TMP23:%.*]] = sext <4 x i1> [[TMP38]] to <4 x i16>1702; CHECK-NEXT: [[TMP24:%.*]] = bitcast <4 x i16> [[TMP23]] to <2 x i32>1703; CHECK-NEXT: [[TMP25:%.*]] = icmp ne <2 x i32> [[TMP24]], zeroinitializer1704; CHECK-NEXT: [[TMP27:%.*]] = sext <2 x i1> [[TMP25]] to <2 x i32>1705; CHECK-NEXT: [[TMP28:%.*]] = bitcast <2 x i32> [[TMP27]] to i641706; CHECK-NEXT: [[TMP14:%.*]] = bitcast i64 [[TMP28]] to <1 x i64>1707; CHECK-NEXT: [[TMP33:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pmadd.wd(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]1708; CHECK-NEXT: [[TMP20:%.*]] = bitcast <1 x i64> [[TMP14]] to <2 x i32>1709; CHECK-NEXT: [[TMP34:%.*]] = bitcast <1 x i64> [[TMP33]] to <2 x i32>1710; CHECK-NEXT: [[TMP17:%.*]] = bitcast <2 x i32> [[TMP20]] to <1 x i64>1711; CHECK-NEXT: [[TMP21:%.*]] = bitcast <2 x i32> [[TMP34]] to <1 x i64>1712; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP17]], i32 01713; CHECK-NEXT: [[TMP18:%.*]] = extractelement <1 x i64> [[TMP21]], i32 01714; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 81715; CHECK-NEXT: ret i64 [[TMP18]]1716;1717entry:1718 %0 = bitcast <1 x i64> %b to <4 x i16>1719 %1 = bitcast <1 x i64> %a to <4 x i16>1720 %mmx_var.i = bitcast <4 x i16> %1 to <1 x i64>1721 %mmx_var1.i = bitcast <4 x i16> %0 to <1 x i64>1722 %2 = tail call <1 x i64> @llvm.x86.mmx.pmadd.wd(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind1723 %3 = bitcast <1 x i64> %2 to <2 x i32>1724 %4 = bitcast <2 x i32> %3 to <1 x i64>1725 %5 = extractelement <1 x i64> %4, i32 01726 ret i64 %51727}1728 1729declare <1 x i64> @llvm.x86.mmx.psubus.w(<1 x i64>, <1 x i64>) nounwind readnone1730 1731define i64 @test48(<1 x i64> %a, <1 x i64> %b) #0 {1732; CHECK-LABEL: define i64 @test48(1733; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {1734; CHECK-NEXT: entry:1735; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81736; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81737; CHECK-NEXT: call void @llvm.donothing()1738; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <4 x i16>1739; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>1740; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <4 x i16>1741; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>1742; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP14]] to <1 x i64>1743; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>1744; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>1745; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>1746; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]1747; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psubus.w(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]1748; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>1749; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <4 x i16>1750; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP9]] to <1 x i64>1751; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i16> [[TMP16]] to <1 x i64>1752; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 01753; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 01754; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 81755; CHECK-NEXT: ret i64 [[TMP13]]1756;1757entry:1758 %0 = bitcast <1 x i64> %b to <4 x i16>1759 %1 = bitcast <1 x i64> %a to <4 x i16>1760 %mmx_var.i = bitcast <4 x i16> %1 to <1 x i64>1761 %mmx_var1.i = bitcast <4 x i16> %0 to <1 x i64>1762 %2 = tail call <1 x i64> @llvm.x86.mmx.psubus.w(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind1763 %3 = bitcast <1 x i64> %2 to <4 x i16>1764 %4 = bitcast <4 x i16> %3 to <1 x i64>1765 %5 = extractelement <1 x i64> %4, i32 01766 ret i64 %51767}1768 1769declare <1 x i64> @llvm.x86.mmx.psubus.b(<1 x i64>, <1 x i64>) nounwind readnone1770 1771define i64 @test47(<1 x i64> %a, <1 x i64> %b) #0 {1772; CHECK-LABEL: define i64 @test47(1773; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {1774; CHECK-NEXT: entry:1775; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81776; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81777; CHECK-NEXT: call void @llvm.donothing()1778; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <8 x i8>1779; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>1780; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <8 x i8>1781; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>1782; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP14]] to <1 x i64>1783; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>1784; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP11]] to <1 x i64>1785; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>1786; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]1787; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psubus.b(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]1788; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <8 x i8>1789; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <8 x i8>1790; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP9]] to <1 x i64>1791; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x i8> [[TMP16]] to <1 x i64>1792; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 01793; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 01794; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 81795; CHECK-NEXT: ret i64 [[TMP13]]1796;1797entry:1798 %0 = bitcast <1 x i64> %b to <8 x i8>1799 %1 = bitcast <1 x i64> %a to <8 x i8>1800 %mmx_var.i = bitcast <8 x i8> %1 to <1 x i64>1801 %mmx_var1.i = bitcast <8 x i8> %0 to <1 x i64>1802 %2 = tail call <1 x i64> @llvm.x86.mmx.psubus.b(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind1803 %3 = bitcast <1 x i64> %2 to <8 x i8>1804 %4 = bitcast <8 x i8> %3 to <1 x i64>1805 %5 = extractelement <1 x i64> %4, i32 01806 ret i64 %51807}1808 1809declare <1 x i64> @llvm.x86.mmx.psubs.w(<1 x i64>, <1 x i64>) nounwind readnone1810 1811define i64 @test46(<1 x i64> %a, <1 x i64> %b) #0 {1812; CHECK-LABEL: define i64 @test46(1813; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {1814; CHECK-NEXT: entry:1815; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81816; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81817; CHECK-NEXT: call void @llvm.donothing()1818; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <4 x i16>1819; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>1820; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <4 x i16>1821; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>1822; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP14]] to <1 x i64>1823; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>1824; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>1825; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>1826; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]1827; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psubs.w(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]1828; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>1829; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <4 x i16>1830; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP9]] to <1 x i64>1831; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i16> [[TMP16]] to <1 x i64>1832; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 01833; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 01834; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 81835; CHECK-NEXT: ret i64 [[TMP13]]1836;1837entry:1838 %0 = bitcast <1 x i64> %b to <4 x i16>1839 %1 = bitcast <1 x i64> %a to <4 x i16>1840 %mmx_var.i = bitcast <4 x i16> %1 to <1 x i64>1841 %mmx_var1.i = bitcast <4 x i16> %0 to <1 x i64>1842 %2 = tail call <1 x i64> @llvm.x86.mmx.psubs.w(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind1843 %3 = bitcast <1 x i64> %2 to <4 x i16>1844 %4 = bitcast <4 x i16> %3 to <1 x i64>1845 %5 = extractelement <1 x i64> %4, i32 01846 ret i64 %51847}1848 1849declare <1 x i64> @llvm.x86.mmx.psubs.b(<1 x i64>, <1 x i64>) nounwind readnone1850 1851define i64 @test45(<1 x i64> %a, <1 x i64> %b) #0 {1852; CHECK-LABEL: define i64 @test45(1853; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {1854; CHECK-NEXT: entry:1855; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81856; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81857; CHECK-NEXT: call void @llvm.donothing()1858; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <8 x i8>1859; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>1860; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <8 x i8>1861; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>1862; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP14]] to <1 x i64>1863; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>1864; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP11]] to <1 x i64>1865; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>1866; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]1867; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psubs.b(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]1868; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <8 x i8>1869; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <8 x i8>1870; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP9]] to <1 x i64>1871; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x i8> [[TMP16]] to <1 x i64>1872; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 01873; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 01874; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 81875; CHECK-NEXT: ret i64 [[TMP13]]1876;1877entry:1878 %0 = bitcast <1 x i64> %b to <8 x i8>1879 %1 = bitcast <1 x i64> %a to <8 x i8>1880 %mmx_var.i = bitcast <8 x i8> %1 to <1 x i64>1881 %mmx_var1.i = bitcast <8 x i8> %0 to <1 x i64>1882 %2 = tail call <1 x i64> @llvm.x86.mmx.psubs.b(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind1883 %3 = bitcast <1 x i64> %2 to <8 x i8>1884 %4 = bitcast <8 x i8> %3 to <1 x i64>1885 %5 = extractelement <1 x i64> %4, i32 01886 ret i64 %51887}1888 1889define i64 @test44(<1 x i64> %a, <1 x i64> %b) #0 {1890; CHECK-LABEL: define i64 @test44(1891; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {1892; CHECK-NEXT: entry:1893; CHECK-NEXT: [[TMP4:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81894; CHECK-NEXT: [[TMP5:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81895; CHECK-NEXT: call void @llvm.donothing()1896; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <1 x i64> [[TMP4]], i32 01897; CHECK-NEXT: [[TMP0:%.*]] = extractelement <1 x i64> [[A]], i32 01898; CHECK-NEXT: [[TMP7:%.*]] = bitcast i64 [[_MSPROP]] to <1 x i64>1899; CHECK-NEXT: [[MMX_VAR:%.*]] = bitcast i64 [[TMP0]] to <1 x i64>1900; CHECK-NEXT: [[_MSPROP1:%.*]] = extractelement <1 x i64> [[TMP5]], i32 01901; CHECK-NEXT: [[TMP1:%.*]] = extractelement <1 x i64> [[B]], i32 01902; CHECK-NEXT: [[TMP8:%.*]] = bitcast i64 [[_MSPROP1]] to <1 x i64>1903; CHECK-NEXT: [[MMX_VAR1:%.*]] = bitcast i64 [[TMP1]] to <1 x i64>1904; CHECK-NEXT: [[_MSPROP3:%.*]] = or <1 x i64> [[TMP7]], [[TMP8]]1905; CHECK-NEXT: [[TMP6:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psub.q(<1 x i64> [[MMX_VAR]], <1 x i64> [[MMX_VAR1]])1906; CHECK-NEXT: [[_MSPROP2:%.*]] = bitcast <1 x i64> [[_MSPROP3]] to i641907; CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[TMP6]] to i641908; CHECK-NEXT: store i64 [[_MSPROP2]], ptr @__msan_retval_tls, align 81909; CHECK-NEXT: ret i64 [[TMP3]]1910;1911entry:1912 %0 = extractelement <1 x i64> %a, i32 01913 %mmx_var = bitcast i64 %0 to <1 x i64>1914 %1 = extractelement <1 x i64> %b, i32 01915 %mmx_var1 = bitcast i64 %1 to <1 x i64>1916 %2 = tail call <1 x i64> @llvm.x86.mmx.psub.q(<1 x i64> %mmx_var, <1 x i64> %mmx_var1)1917 %3 = bitcast <1 x i64> %2 to i641918 ret i64 %31919}1920 1921declare <1 x i64> @llvm.x86.mmx.psub.q(<1 x i64>, <1 x i64>) nounwind readnone1922 1923declare <1 x i64> @llvm.x86.mmx.psub.d(<1 x i64>, <1 x i64>) nounwind readnone1924 1925define i64 @test43(<1 x i64> %a, <1 x i64> %b) #0 {1926; CHECK-LABEL: define i64 @test43(1927; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {1928; CHECK-NEXT: entry:1929; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81930; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81931; CHECK-NEXT: call void @llvm.donothing()1932; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <2 x i32>1933; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <2 x i32>1934; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <2 x i32>1935; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>1936; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i32> [[TMP14]] to <1 x i64>1937; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <2 x i32> [[TMP1]] to <1 x i64>1938; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i32> [[TMP11]] to <1 x i64>1939; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>1940; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]1941; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psub.d(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]1942; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <2 x i32>1943; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <2 x i32>1944; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP9]] to <1 x i64>1945; CHECK-NEXT: [[TMP12:%.*]] = bitcast <2 x i32> [[TMP16]] to <1 x i64>1946; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 01947; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 01948; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 81949; CHECK-NEXT: ret i64 [[TMP13]]1950;1951entry:1952 %0 = bitcast <1 x i64> %b to <2 x i32>1953 %1 = bitcast <1 x i64> %a to <2 x i32>1954 %mmx_var.i = bitcast <2 x i32> %1 to <1 x i64>1955 %mmx_var1.i = bitcast <2 x i32> %0 to <1 x i64>1956 %2 = tail call <1 x i64> @llvm.x86.mmx.psub.d(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind1957 %3 = bitcast <1 x i64> %2 to <2 x i32>1958 %4 = bitcast <2 x i32> %3 to <1 x i64>1959 %5 = extractelement <1 x i64> %4, i32 01960 ret i64 %51961}1962 1963declare <1 x i64> @llvm.x86.mmx.psub.w(<1 x i64>, <1 x i64>) nounwind readnone1964 1965define i64 @test42(<1 x i64> %a, <1 x i64> %b) #0 {1966; CHECK-LABEL: define i64 @test42(1967; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {1968; CHECK-NEXT: entry:1969; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81970; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81971; CHECK-NEXT: call void @llvm.donothing()1972; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <4 x i16>1973; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>1974; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <4 x i16>1975; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>1976; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP14]] to <1 x i64>1977; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>1978; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>1979; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>1980; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]1981; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psub.w(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]1982; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>1983; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <4 x i16>1984; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP9]] to <1 x i64>1985; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i16> [[TMP16]] to <1 x i64>1986; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 01987; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 01988; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 81989; CHECK-NEXT: ret i64 [[TMP13]]1990;1991entry:1992 %0 = bitcast <1 x i64> %b to <4 x i16>1993 %1 = bitcast <1 x i64> %a to <4 x i16>1994 %mmx_var.i = bitcast <4 x i16> %1 to <1 x i64>1995 %mmx_var1.i = bitcast <4 x i16> %0 to <1 x i64>1996 %2 = tail call <1 x i64> @llvm.x86.mmx.psub.w(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind1997 %3 = bitcast <1 x i64> %2 to <4 x i16>1998 %4 = bitcast <4 x i16> %3 to <1 x i64>1999 %5 = extractelement <1 x i64> %4, i32 02000 ret i64 %52001}2002 2003declare <1 x i64> @llvm.x86.mmx.psub.b(<1 x i64>, <1 x i64>) nounwind readnone2004 2005define i64 @test41(<1 x i64> %a, <1 x i64> %b) #0 {2006; CHECK-LABEL: define i64 @test41(2007; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {2008; CHECK-NEXT: entry:2009; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82010; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82011; CHECK-NEXT: call void @llvm.donothing()2012; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <8 x i8>2013; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>2014; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <8 x i8>2015; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>2016; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP14]] to <1 x i64>2017; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>2018; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP11]] to <1 x i64>2019; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>2020; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]2021; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psub.b(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]2022; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <8 x i8>2023; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <8 x i8>2024; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP9]] to <1 x i64>2025; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x i8> [[TMP16]] to <1 x i64>2026; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 02027; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 02028; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 82029; CHECK-NEXT: ret i64 [[TMP13]]2030;2031entry:2032 %0 = bitcast <1 x i64> %b to <8 x i8>2033 %1 = bitcast <1 x i64> %a to <8 x i8>2034 %mmx_var.i = bitcast <8 x i8> %1 to <1 x i64>2035 %mmx_var1.i = bitcast <8 x i8> %0 to <1 x i64>2036 %2 = tail call <1 x i64> @llvm.x86.mmx.psub.b(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind2037 %3 = bitcast <1 x i64> %2 to <8 x i8>2038 %4 = bitcast <8 x i8> %3 to <1 x i64>2039 %5 = extractelement <1 x i64> %4, i32 02040 ret i64 %52041}2042 2043declare <1 x i64> @llvm.x86.mmx.paddus.w(<1 x i64>, <1 x i64>) nounwind readnone2044 2045define i64 @test40(<1 x i64> %a, <1 x i64> %b) #0 {2046; CHECK-LABEL: define i64 @test40(2047; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {2048; CHECK-NEXT: entry:2049; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82050; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82051; CHECK-NEXT: call void @llvm.donothing()2052; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <4 x i16>2053; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>2054; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <4 x i16>2055; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>2056; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP14]] to <1 x i64>2057; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>2058; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>2059; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>2060; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]2061; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.paddus.w(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]2062; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>2063; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <4 x i16>2064; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP9]] to <1 x i64>2065; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i16> [[TMP16]] to <1 x i64>2066; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 02067; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 02068; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 82069; CHECK-NEXT: ret i64 [[TMP13]]2070;2071entry:2072 %0 = bitcast <1 x i64> %b to <4 x i16>2073 %1 = bitcast <1 x i64> %a to <4 x i16>2074 %mmx_var.i = bitcast <4 x i16> %1 to <1 x i64>2075 %mmx_var1.i = bitcast <4 x i16> %0 to <1 x i64>2076 %2 = tail call <1 x i64> @llvm.x86.mmx.paddus.w(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind2077 %3 = bitcast <1 x i64> %2 to <4 x i16>2078 %4 = bitcast <4 x i16> %3 to <1 x i64>2079 %5 = extractelement <1 x i64> %4, i32 02080 ret i64 %52081}2082 2083declare <1 x i64> @llvm.x86.mmx.paddus.b(<1 x i64>, <1 x i64>) nounwind readnone2084 2085define i64 @test39(<1 x i64> %a, <1 x i64> %b) #0 {2086; CHECK-LABEL: define i64 @test39(2087; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {2088; CHECK-NEXT: entry:2089; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82090; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82091; CHECK-NEXT: call void @llvm.donothing()2092; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <8 x i8>2093; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>2094; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <8 x i8>2095; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>2096; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP14]] to <1 x i64>2097; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>2098; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP11]] to <1 x i64>2099; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>2100; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]2101; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.paddus.b(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]2102; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <8 x i8>2103; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <8 x i8>2104; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP9]] to <1 x i64>2105; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x i8> [[TMP16]] to <1 x i64>2106; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 02107; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 02108; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 82109; CHECK-NEXT: ret i64 [[TMP13]]2110;2111entry:2112 %0 = bitcast <1 x i64> %b to <8 x i8>2113 %1 = bitcast <1 x i64> %a to <8 x i8>2114 %mmx_var.i = bitcast <8 x i8> %1 to <1 x i64>2115 %mmx_var1.i = bitcast <8 x i8> %0 to <1 x i64>2116 %2 = tail call <1 x i64> @llvm.x86.mmx.paddus.b(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind2117 %3 = bitcast <1 x i64> %2 to <8 x i8>2118 %4 = bitcast <8 x i8> %3 to <1 x i64>2119 %5 = extractelement <1 x i64> %4, i32 02120 ret i64 %52121}2122 2123declare <1 x i64> @llvm.x86.mmx.padds.w(<1 x i64>, <1 x i64>) nounwind readnone2124 2125define i64 @test38(<1 x i64> %a, <1 x i64> %b) #0 {2126; CHECK-LABEL: define i64 @test38(2127; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {2128; CHECK-NEXT: entry:2129; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82130; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82131; CHECK-NEXT: call void @llvm.donothing()2132; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <4 x i16>2133; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>2134; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <4 x i16>2135; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>2136; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP14]] to <1 x i64>2137; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>2138; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>2139; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>2140; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]2141; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.padds.w(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]2142; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>2143; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <4 x i16>2144; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP9]] to <1 x i64>2145; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i16> [[TMP16]] to <1 x i64>2146; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 02147; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 02148; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 82149; CHECK-NEXT: ret i64 [[TMP13]]2150;2151entry:2152 %0 = bitcast <1 x i64> %b to <4 x i16>2153 %1 = bitcast <1 x i64> %a to <4 x i16>2154 %mmx_var.i = bitcast <4 x i16> %1 to <1 x i64>2155 %mmx_var1.i = bitcast <4 x i16> %0 to <1 x i64>2156 %2 = tail call <1 x i64> @llvm.x86.mmx.padds.w(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind2157 %3 = bitcast <1 x i64> %2 to <4 x i16>2158 %4 = bitcast <4 x i16> %3 to <1 x i64>2159 %5 = extractelement <1 x i64> %4, i32 02160 ret i64 %52161}2162 2163declare <1 x i64> @llvm.x86.mmx.padds.b(<1 x i64>, <1 x i64>) nounwind readnone2164 2165define i64 @test37(<1 x i64> %a, <1 x i64> %b) #0 {2166; CHECK-LABEL: define i64 @test37(2167; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {2168; CHECK-NEXT: entry:2169; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82170; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82171; CHECK-NEXT: call void @llvm.donothing()2172; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <8 x i8>2173; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>2174; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <8 x i8>2175; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>2176; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP14]] to <1 x i64>2177; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>2178; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP11]] to <1 x i64>2179; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>2180; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]2181; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.padds.b(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]2182; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <8 x i8>2183; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <8 x i8>2184; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP9]] to <1 x i64>2185; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x i8> [[TMP16]] to <1 x i64>2186; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 02187; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 02188; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 82189; CHECK-NEXT: ret i64 [[TMP13]]2190;2191entry:2192 %0 = bitcast <1 x i64> %b to <8 x i8>2193 %1 = bitcast <1 x i64> %a to <8 x i8>2194 %mmx_var.i = bitcast <8 x i8> %1 to <1 x i64>2195 %mmx_var1.i = bitcast <8 x i8> %0 to <1 x i64>2196 %2 = tail call <1 x i64> @llvm.x86.mmx.padds.b(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind2197 %3 = bitcast <1 x i64> %2 to <8 x i8>2198 %4 = bitcast <8 x i8> %3 to <1 x i64>2199 %5 = extractelement <1 x i64> %4, i32 02200 ret i64 %52201}2202 2203declare <1 x i64> @llvm.x86.mmx.padd.q(<1 x i64>, <1 x i64>) nounwind readnone2204 2205define i64 @test36(<1 x i64> %a, <1 x i64> %b) #0 {2206; CHECK-LABEL: define i64 @test36(2207; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {2208; CHECK-NEXT: entry:2209; CHECK-NEXT: [[TMP4:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82210; CHECK-NEXT: [[TMP5:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82211; CHECK-NEXT: call void @llvm.donothing()2212; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <1 x i64> [[TMP4]], i32 02213; CHECK-NEXT: [[TMP0:%.*]] = extractelement <1 x i64> [[A]], i32 02214; CHECK-NEXT: [[TMP7:%.*]] = bitcast i64 [[_MSPROP]] to <1 x i64>2215; CHECK-NEXT: [[MMX_VAR:%.*]] = bitcast i64 [[TMP0]] to <1 x i64>2216; CHECK-NEXT: [[_MSPROP1:%.*]] = extractelement <1 x i64> [[TMP5]], i32 02217; CHECK-NEXT: [[TMP1:%.*]] = extractelement <1 x i64> [[B]], i32 02218; CHECK-NEXT: [[TMP8:%.*]] = bitcast i64 [[_MSPROP1]] to <1 x i64>2219; CHECK-NEXT: [[MMX_VAR1:%.*]] = bitcast i64 [[TMP1]] to <1 x i64>2220; CHECK-NEXT: [[_MSPROP3:%.*]] = or <1 x i64> [[TMP7]], [[TMP8]]2221; CHECK-NEXT: [[TMP6:%.*]] = tail call <1 x i64> @llvm.x86.mmx.padd.q(<1 x i64> [[MMX_VAR]], <1 x i64> [[MMX_VAR1]])2222; CHECK-NEXT: [[_MSPROP2:%.*]] = bitcast <1 x i64> [[_MSPROP3]] to i642223; CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[TMP6]] to i642224; CHECK-NEXT: store i64 [[_MSPROP2]], ptr @__msan_retval_tls, align 82225; CHECK-NEXT: ret i64 [[TMP3]]2226;2227entry:2228 %0 = extractelement <1 x i64> %a, i32 02229 %mmx_var = bitcast i64 %0 to <1 x i64>2230 %1 = extractelement <1 x i64> %b, i32 02231 %mmx_var1 = bitcast i64 %1 to <1 x i64>2232 %2 = tail call <1 x i64> @llvm.x86.mmx.padd.q(<1 x i64> %mmx_var, <1 x i64> %mmx_var1)2233 %3 = bitcast <1 x i64> %2 to i642234 ret i64 %32235}2236 2237declare <1 x i64> @llvm.x86.mmx.padd.d(<1 x i64>, <1 x i64>) nounwind readnone2238 2239define i64 @test35(<1 x i64> %a, <1 x i64> %b) #0 {2240; CHECK-LABEL: define i64 @test35(2241; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {2242; CHECK-NEXT: entry:2243; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82244; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82245; CHECK-NEXT: call void @llvm.donothing()2246; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <2 x i32>2247; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <2 x i32>2248; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <2 x i32>2249; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>2250; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i32> [[TMP14]] to <1 x i64>2251; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <2 x i32> [[TMP1]] to <1 x i64>2252; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i32> [[TMP11]] to <1 x i64>2253; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>2254; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]2255; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.padd.d(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]2256; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <2 x i32>2257; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <2 x i32>2258; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP9]] to <1 x i64>2259; CHECK-NEXT: [[TMP12:%.*]] = bitcast <2 x i32> [[TMP16]] to <1 x i64>2260; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 02261; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 02262; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 82263; CHECK-NEXT: ret i64 [[TMP13]]2264;2265entry:2266 %0 = bitcast <1 x i64> %b to <2 x i32>2267 %1 = bitcast <1 x i64> %a to <2 x i32>2268 %mmx_var.i = bitcast <2 x i32> %1 to <1 x i64>2269 %mmx_var1.i = bitcast <2 x i32> %0 to <1 x i64>2270 %2 = tail call <1 x i64> @llvm.x86.mmx.padd.d(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind2271 %3 = bitcast <1 x i64> %2 to <2 x i32>2272 %4 = bitcast <2 x i32> %3 to <1 x i64>2273 %5 = extractelement <1 x i64> %4, i32 02274 ret i64 %52275}2276 2277declare <1 x i64> @llvm.x86.mmx.padd.w(<1 x i64>, <1 x i64>) nounwind readnone2278 2279define i64 @test34(<1 x i64> %a, <1 x i64> %b) #0 {2280; CHECK-LABEL: define i64 @test34(2281; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {2282; CHECK-NEXT: entry:2283; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82284; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82285; CHECK-NEXT: call void @llvm.donothing()2286; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <4 x i16>2287; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>2288; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <4 x i16>2289; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>2290; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP14]] to <1 x i64>2291; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>2292; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>2293; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>2294; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]2295; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.padd.w(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]2296; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>2297; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <4 x i16>2298; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP9]] to <1 x i64>2299; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i16> [[TMP16]] to <1 x i64>2300; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 02301; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 02302; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 82303; CHECK-NEXT: ret i64 [[TMP13]]2304;2305entry:2306 %0 = bitcast <1 x i64> %b to <4 x i16>2307 %1 = bitcast <1 x i64> %a to <4 x i16>2308 %mmx_var.i = bitcast <4 x i16> %1 to <1 x i64>2309 %mmx_var1.i = bitcast <4 x i16> %0 to <1 x i64>2310 %2 = tail call <1 x i64> @llvm.x86.mmx.padd.w(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind2311 %3 = bitcast <1 x i64> %2 to <4 x i16>2312 %4 = bitcast <4 x i16> %3 to <1 x i64>2313 %5 = extractelement <1 x i64> %4, i32 02314 ret i64 %52315}2316 2317declare <1 x i64> @llvm.x86.mmx.padd.b(<1 x i64>, <1 x i64>) nounwind readnone2318 2319define i64 @test33(<1 x i64> %a, <1 x i64> %b) #0 {2320; CHECK-LABEL: define i64 @test33(2321; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {2322; CHECK-NEXT: entry:2323; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82324; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82325; CHECK-NEXT: call void @llvm.donothing()2326; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <8 x i8>2327; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>2328; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <8 x i8>2329; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>2330; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP14]] to <1 x i64>2331; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>2332; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP11]] to <1 x i64>2333; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>2334; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]2335; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.padd.b(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]2336; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <8 x i8>2337; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <8 x i8>2338; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP9]] to <1 x i64>2339; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x i8> [[TMP16]] to <1 x i64>2340; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 02341; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 02342; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 82343; CHECK-NEXT: ret i64 [[TMP13]]2344;2345entry:2346 %0 = bitcast <1 x i64> %b to <8 x i8>2347 %1 = bitcast <1 x i64> %a to <8 x i8>2348 %mmx_var.i = bitcast <8 x i8> %1 to <1 x i64>2349 %mmx_var1.i = bitcast <8 x i8> %0 to <1 x i64>2350 %2 = tail call <1 x i64> @llvm.x86.mmx.padd.b(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind2351 %3 = bitcast <1 x i64> %2 to <8 x i8>2352 %4 = bitcast <8 x i8> %3 to <1 x i64>2353 %5 = extractelement <1 x i64> %4, i32 02354 ret i64 %52355}2356 2357declare <1 x i64> @llvm.x86.mmx.psad.bw(<1 x i64>, <1 x i64>) nounwind readnone2358 2359define i64 @test32(<1 x i64> %a, <1 x i64> %b) #0 {2360; CHECK-LABEL: define i64 @test32(2361; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {2362; CHECK-NEXT: entry:2363; CHECK-NEXT: [[TMP5:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82364; CHECK-NEXT: [[TMP12:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82365; CHECK-NEXT: call void @llvm.donothing()2366; CHECK-NEXT: [[TMP13:%.*]] = bitcast <1 x i64> [[TMP5]] to <8 x i8>2367; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>2368; CHECK-NEXT: [[TMP4:%.*]] = bitcast <1 x i64> [[TMP12]] to <8 x i8>2369; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>2370; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP4]] to <1 x i64>2371; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>2372; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP13]] to <1 x i64>2373; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>2374; CHECK-NEXT: [[TMP16:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]2375; CHECK-NEXT: [[TMP8:%.*]] = bitcast <1 x i64> [[TMP16]] to i642376; CHECK-NEXT: [[TMP9:%.*]] = icmp ne i64 [[TMP8]], 02377; CHECK-NEXT: [[TMP10:%.*]] = sext i1 [[TMP9]] to i642378; CHECK-NEXT: [[TMP11:%.*]] = lshr i64 [[TMP10]], 482379; CHECK-NEXT: [[TMP17:%.*]] = bitcast i64 [[TMP11]] to <1 x i64>2380; CHECK-NEXT: [[TMP14:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psad.bw(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]2381; CHECK-NEXT: [[TMP15:%.*]] = bitcast <1 x i64> [[TMP17]] to i642382; CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[TMP14]] to i642383; CHECK-NEXT: store i64 [[TMP15]], ptr @__msan_retval_tls, align 82384; CHECK-NEXT: ret i64 [[TMP3]]2385;2386entry:2387 %0 = bitcast <1 x i64> %b to <8 x i8>2388 %1 = bitcast <1 x i64> %a to <8 x i8>2389 %mmx_var.i = bitcast <8 x i8> %1 to <1 x i64>2390 %mmx_var1.i = bitcast <8 x i8> %0 to <1 x i64>2391 %2 = tail call <1 x i64> @llvm.x86.mmx.psad.bw(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind2392 %3 = bitcast <1 x i64> %2 to i642393 ret i64 %32394}2395 2396declare <1 x i64> @llvm.x86.mmx.pmins.w(<1 x i64>, <1 x i64>) nounwind readnone2397 2398define i64 @test31(<1 x i64> %a, <1 x i64> %b) #0 {2399; CHECK-LABEL: define i64 @test31(2400; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {2401; CHECK-NEXT: entry:2402; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82403; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82404; CHECK-NEXT: call void @llvm.donothing()2405; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <4 x i16>2406; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>2407; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <4 x i16>2408; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>2409; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP14]] to <1 x i64>2410; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>2411; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>2412; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>2413; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]2414; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pmins.w(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]2415; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>2416; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <4 x i16>2417; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP9]] to <1 x i64>2418; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i16> [[TMP16]] to <1 x i64>2419; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 02420; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 02421; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 82422; CHECK-NEXT: ret i64 [[TMP13]]2423;2424entry:2425 %0 = bitcast <1 x i64> %b to <4 x i16>2426 %1 = bitcast <1 x i64> %a to <4 x i16>2427 %mmx_var.i = bitcast <4 x i16> %1 to <1 x i64>2428 %mmx_var1.i = bitcast <4 x i16> %0 to <1 x i64>2429 %2 = tail call <1 x i64> @llvm.x86.mmx.pmins.w(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind2430 %3 = bitcast <1 x i64> %2 to <4 x i16>2431 %4 = bitcast <4 x i16> %3 to <1 x i64>2432 %5 = extractelement <1 x i64> %4, i32 02433 ret i64 %52434}2435 2436declare <1 x i64> @llvm.x86.mmx.pminu.b(<1 x i64>, <1 x i64>) nounwind readnone2437 2438define i64 @test30(<1 x i64> %a, <1 x i64> %b) #0 {2439; CHECK-LABEL: define i64 @test30(2440; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {2441; CHECK-NEXT: entry:2442; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82443; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82444; CHECK-NEXT: call void @llvm.donothing()2445; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <8 x i8>2446; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>2447; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <8 x i8>2448; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>2449; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP14]] to <1 x i64>2450; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>2451; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP11]] to <1 x i64>2452; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>2453; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]2454; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pminu.b(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]2455; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <8 x i8>2456; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <8 x i8>2457; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP9]] to <1 x i64>2458; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x i8> [[TMP16]] to <1 x i64>2459; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 02460; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 02461; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 82462; CHECK-NEXT: ret i64 [[TMP13]]2463;2464entry:2465 %0 = bitcast <1 x i64> %b to <8 x i8>2466 %1 = bitcast <1 x i64> %a to <8 x i8>2467 %mmx_var.i = bitcast <8 x i8> %1 to <1 x i64>2468 %mmx_var1.i = bitcast <8 x i8> %0 to <1 x i64>2469 %2 = tail call <1 x i64> @llvm.x86.mmx.pminu.b(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind2470 %3 = bitcast <1 x i64> %2 to <8 x i8>2471 %4 = bitcast <8 x i8> %3 to <1 x i64>2472 %5 = extractelement <1 x i64> %4, i32 02473 ret i64 %52474}2475 2476declare <1 x i64> @llvm.x86.mmx.pmaxs.w(<1 x i64>, <1 x i64>) nounwind readnone2477 2478define i64 @test29(<1 x i64> %a, <1 x i64> %b) #0 {2479; CHECK-LABEL: define i64 @test29(2480; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {2481; CHECK-NEXT: entry:2482; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82483; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82484; CHECK-NEXT: call void @llvm.donothing()2485; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <4 x i16>2486; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>2487; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <4 x i16>2488; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>2489; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP14]] to <1 x i64>2490; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>2491; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>2492; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>2493; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]2494; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pmaxs.w(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]2495; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>2496; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <4 x i16>2497; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP9]] to <1 x i64>2498; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i16> [[TMP16]] to <1 x i64>2499; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 02500; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 02501; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 82502; CHECK-NEXT: ret i64 [[TMP13]]2503;2504entry:2505 %0 = bitcast <1 x i64> %b to <4 x i16>2506 %1 = bitcast <1 x i64> %a to <4 x i16>2507 %mmx_var.i = bitcast <4 x i16> %1 to <1 x i64>2508 %mmx_var1.i = bitcast <4 x i16> %0 to <1 x i64>2509 %2 = tail call <1 x i64> @llvm.x86.mmx.pmaxs.w(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind2510 %3 = bitcast <1 x i64> %2 to <4 x i16>2511 %4 = bitcast <4 x i16> %3 to <1 x i64>2512 %5 = extractelement <1 x i64> %4, i32 02513 ret i64 %52514}2515 2516declare <1 x i64> @llvm.x86.mmx.pmaxu.b(<1 x i64>, <1 x i64>) nounwind readnone2517 2518define i64 @test28(<1 x i64> %a, <1 x i64> %b) #0 {2519; CHECK-LABEL: define i64 @test28(2520; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {2521; CHECK-NEXT: entry:2522; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82523; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82524; CHECK-NEXT: call void @llvm.donothing()2525; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <8 x i8>2526; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>2527; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <8 x i8>2528; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>2529; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP14]] to <1 x i64>2530; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>2531; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP11]] to <1 x i64>2532; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>2533; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]2534; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pmaxu.b(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]2535; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <8 x i8>2536; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <8 x i8>2537; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP9]] to <1 x i64>2538; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x i8> [[TMP16]] to <1 x i64>2539; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 02540; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 02541; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 82542; CHECK-NEXT: ret i64 [[TMP13]]2543;2544entry:2545 %0 = bitcast <1 x i64> %b to <8 x i8>2546 %1 = bitcast <1 x i64> %a to <8 x i8>2547 %mmx_var.i = bitcast <8 x i8> %1 to <1 x i64>2548 %mmx_var1.i = bitcast <8 x i8> %0 to <1 x i64>2549 %2 = tail call <1 x i64> @llvm.x86.mmx.pmaxu.b(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind2550 %3 = bitcast <1 x i64> %2 to <8 x i8>2551 %4 = bitcast <8 x i8> %3 to <1 x i64>2552 %5 = extractelement <1 x i64> %4, i32 02553 ret i64 %52554}2555 2556declare <1 x i64> @llvm.x86.mmx.pavg.w(<1 x i64>, <1 x i64>) nounwind readnone2557 2558define i64 @test27(<1 x i64> %a, <1 x i64> %b) #0 {2559; CHECK-LABEL: define i64 @test27(2560; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {2561; CHECK-NEXT: entry:2562; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82563; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82564; CHECK-NEXT: call void @llvm.donothing()2565; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <4 x i16>2566; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>2567; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <4 x i16>2568; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>2569; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP14]] to <1 x i64>2570; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>2571; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>2572; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>2573; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]2574; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pavg.w(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]2575; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>2576; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <4 x i16>2577; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP9]] to <1 x i64>2578; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i16> [[TMP16]] to <1 x i64>2579; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 02580; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 02581; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 82582; CHECK-NEXT: ret i64 [[TMP13]]2583;2584entry:2585 %0 = bitcast <1 x i64> %b to <4 x i16>2586 %1 = bitcast <1 x i64> %a to <4 x i16>2587 %mmx_var.i = bitcast <4 x i16> %1 to <1 x i64>2588 %mmx_var1.i = bitcast <4 x i16> %0 to <1 x i64>2589 %2 = tail call <1 x i64> @llvm.x86.mmx.pavg.w(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind2590 %3 = bitcast <1 x i64> %2 to <4 x i16>2591 %4 = bitcast <4 x i16> %3 to <1 x i64>2592 %5 = extractelement <1 x i64> %4, i32 02593 ret i64 %52594}2595 2596declare <1 x i64> @llvm.x86.mmx.pavg.b(<1 x i64>, <1 x i64>) nounwind readnone2597 2598define i64 @test26(<1 x i64> %a, <1 x i64> %b) #0 {2599; CHECK-LABEL: define i64 @test26(2600; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {2601; CHECK-NEXT: entry:2602; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82603; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82604; CHECK-NEXT: call void @llvm.donothing()2605; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <8 x i8>2606; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>2607; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <8 x i8>2608; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>2609; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP14]] to <1 x i64>2610; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>2611; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP11]] to <1 x i64>2612; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>2613; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]2614; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pavg.b(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]2615; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <8 x i8>2616; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <8 x i8>2617; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP9]] to <1 x i64>2618; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x i8> [[TMP16]] to <1 x i64>2619; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 02620; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 02621; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 82622; CHECK-NEXT: ret i64 [[TMP13]]2623;2624entry:2625 %0 = bitcast <1 x i64> %b to <8 x i8>2626 %1 = bitcast <1 x i64> %a to <8 x i8>2627 %mmx_var.i = bitcast <8 x i8> %1 to <1 x i64>2628 %mmx_var1.i = bitcast <8 x i8> %0 to <1 x i64>2629 %2 = tail call <1 x i64> @llvm.x86.mmx.pavg.b(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind2630 %3 = bitcast <1 x i64> %2 to <8 x i8>2631 %4 = bitcast <8 x i8> %3 to <1 x i64>2632 %5 = extractelement <1 x i64> %4, i32 02633 ret i64 %52634}2635 2636declare void @llvm.x86.mmx.movnt.dq(ptr, <1 x i64>) nounwind2637 2638define void @test25(ptr %p, <1 x i64> %a) nounwind optsize ssp #0 {2639; CHECK-LABEL: define void @test25(2640; CHECK-SAME: ptr [[P:%.*]], <1 x i64> [[A:%.*]]) #[[ATTR3:[0-9]+]] {2641; CHECK-NEXT: entry:2642; CHECK-NEXT: [[TMP2:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82643; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82644; CHECK-NEXT: call void @llvm.donothing()2645; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <1 x i64> [[TMP2]], i32 02646; CHECK-NEXT: [[TMP0:%.*]] = extractelement <1 x i64> [[A]], i32 02647; CHECK-NEXT: [[TMP3:%.*]] = bitcast i64 [[_MSPROP]] to <1 x i64>2648; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast i64 [[TMP0]] to <1 x i64>2649; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P]] to i642650; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 879609302220802651; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr2652; CHECK-NEXT: store <1 x i64> [[TMP3]], ptr [[TMP6]], align 12653; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02654; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1:![0-9]+]]2655; CHECK: 7:2656; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6:[0-9]+]]2657; CHECK-NEXT: unreachable2658; CHECK: 8:2659; CHECK-NEXT: tail call void @llvm.x86.mmx.movnt.dq(ptr [[P]], <1 x i64> [[MMX_VAR_I]]) #[[ATTR2]]2660; CHECK-NEXT: ret void2661;2662entry:2663 %0 = extractelement <1 x i64> %a, i32 02664 %mmx_var.i = bitcast i64 %0 to <1 x i64>2665 tail call void @llvm.x86.mmx.movnt.dq(ptr %p, <1 x i64> %mmx_var.i) nounwind2666 ret void2667}2668 2669declare i32 @llvm.x86.mmx.pmovmskb(<1 x i64>) nounwind readnone2670 2671define i32 @test24(<1 x i64> %a) #0 {2672; CHECK-LABEL: define i32 @test24(2673; CHECK-SAME: <1 x i64> [[A:%.*]]) #[[ATTR1]] {2674; CHECK-NEXT: entry:2675; CHECK-NEXT: [[TMP2:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82676; CHECK-NEXT: call void @llvm.donothing()2677; CHECK-NEXT: [[TMP6:%.*]] = bitcast <1 x i64> [[TMP2]] to <8 x i8>2678; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>2679; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP6]] to <1 x i64>2680; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>2681; CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[TMP4]] to i642682; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP3]], 02683; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP5:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]2684; CHECK: 5:2685; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]2686; CHECK-NEXT: unreachable2687; CHECK: 6:2688; CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.x86.mmx.pmovmskb(<1 x i64> [[MMX_VAR_I]]) #[[ATTR2]]2689; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 82690; CHECK-NEXT: ret i32 [[TMP1]]2691;2692entry:2693 %0 = bitcast <1 x i64> %a to <8 x i8>2694 %mmx_var.i = bitcast <8 x i8> %0 to <1 x i64>2695 %1 = tail call i32 @llvm.x86.mmx.pmovmskb(<1 x i64> %mmx_var.i) nounwind2696 ret i32 %12697}2698 2699declare void @llvm.x86.mmx.maskmovq(<1 x i64>, <1 x i64>, ptr) nounwind2700 2701define void @test23(<1 x i64> %d, <1 x i64> %n, ptr %p) nounwind optsize ssp #0 {2702; CHECK-LABEL: define void @test23(2703; CHECK-SAME: <1 x i64> [[D:%.*]], <1 x i64> [[N:%.*]], ptr [[P:%.*]]) #[[ATTR3]] {2704; CHECK-NEXT: entry:2705; CHECK-NEXT: [[TMP4:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82706; CHECK-NEXT: [[TMP6:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82707; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 82708; CHECK-NEXT: call void @llvm.donothing()2709; CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[TMP4]] to <8 x i8>2710; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[N]] to <8 x i8>2711; CHECK-NEXT: [[TMP5:%.*]] = bitcast <1 x i64> [[TMP6]] to <8 x i8>2712; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[D]] to <8 x i8>2713; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i8> [[TMP5]] to <1 x i64>2714; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>2715; CHECK-NEXT: [[TMP10:%.*]] = bitcast <8 x i8> [[TMP3]] to <1 x i64>2716; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>2717; CHECK-NEXT: [[TMP7:%.*]] = bitcast <1 x i64> [[TMP9]] to i642718; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP7]], 02719; CHECK-NEXT: [[TMP8:%.*]] = bitcast <1 x i64> [[TMP10]] to i642720; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP8]], 02721; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]2722; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 02723; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]2724; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP11:%.*]], label [[TMP12:%.*]], !prof [[PROF1]]2725; CHECK: 11:2726; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]2727; CHECK-NEXT: unreachable2728; CHECK: 12:2729; CHECK-NEXT: tail call void @llvm.x86.mmx.maskmovq(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]], ptr [[P]]) #[[ATTR2]]2730; CHECK-NEXT: ret void2731;2732entry:2733 %0 = bitcast <1 x i64> %n to <8 x i8>2734 %1 = bitcast <1 x i64> %d to <8 x i8>2735 %mmx_var.i = bitcast <8 x i8> %1 to <1 x i64>2736 %mmx_var1.i = bitcast <8 x i8> %0 to <1 x i64>2737 tail call void @llvm.x86.mmx.maskmovq(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i, ptr %p) nounwind2738 ret void2739}2740 2741declare <1 x i64> @llvm.x86.mmx.pmulhu.w(<1 x i64>, <1 x i64>) nounwind readnone2742 2743define i64 @test22(<1 x i64> %a, <1 x i64> %b) #0 {2744; CHECK-LABEL: define i64 @test22(2745; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {2746; CHECK-NEXT: entry:2747; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82748; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82749; CHECK-NEXT: call void @llvm.donothing()2750; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <4 x i16>2751; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>2752; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <4 x i16>2753; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>2754; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP14]] to <1 x i64>2755; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>2756; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>2757; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>2758; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]2759; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pmulhu.w(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]2760; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>2761; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <4 x i16>2762; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP9]] to <1 x i64>2763; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i16> [[TMP16]] to <1 x i64>2764; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 02765; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 02766; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 82767; CHECK-NEXT: ret i64 [[TMP13]]2768;2769entry:2770 %0 = bitcast <1 x i64> %b to <4 x i16>2771 %1 = bitcast <1 x i64> %a to <4 x i16>2772 %mmx_var.i = bitcast <4 x i16> %1 to <1 x i64>2773 %mmx_var1.i = bitcast <4 x i16> %0 to <1 x i64>2774 %2 = tail call <1 x i64> @llvm.x86.mmx.pmulhu.w(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind2775 %3 = bitcast <1 x i64> %2 to <4 x i16>2776 %4 = bitcast <4 x i16> %3 to <1 x i64>2777 %5 = extractelement <1 x i64> %4, i32 02778 ret i64 %52779}2780 2781declare <1 x i64> @llvm.x86.sse.pshuf.w(<1 x i64>, i8) nounwind readnone2782 2783define i64 @test21(<1 x i64> %a) #0 {2784; CHECK-LABEL: define i64 @test21(2785; CHECK-SAME: <1 x i64> [[A:%.*]]) #[[ATTR1]] {2786; CHECK-NEXT: entry:2787; CHECK-NEXT: [[TMP7:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82788; CHECK-NEXT: call void @llvm.donothing()2789; CHECK-NEXT: [[TMP8:%.*]] = bitcast <1 x i64> [[TMP7]] to <4 x i16>2790; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>2791; CHECK-NEXT: [[TMP10:%.*]] = bitcast <4 x i16> [[TMP8]] to <1 x i64>2792; CHECK-NEXT: [[TMP11:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>2793; CHECK-NEXT: [[TMP9:%.*]] = call <1 x i64> @llvm.x86.sse.pshuf.w(<1 x i64> [[TMP10]], i8 3)2794; CHECK-NEXT: [[TMP13:%.*]] = or <1 x i64> zeroinitializer, [[TMP9]]2795; CHECK-NEXT: [[TMP6:%.*]] = tail call <1 x i64> @llvm.x86.sse.pshuf.w(<1 x i64> [[TMP11]], i8 3) #[[ATTR5]]2796; CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[TMP13]] to <4 x i16>2797; CHECK-NEXT: [[TMP12:%.*]] = bitcast <1 x i64> [[TMP6]] to <4 x i16>2798; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP3]] to <1 x i64>2799; CHECK-NEXT: [[TMP14:%.*]] = bitcast <4 x i16> [[TMP12]] to <1 x i64>2800; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 02801; CHECK-NEXT: [[TMP15:%.*]] = extractelement <1 x i64> [[TMP14]], i32 02802; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 82803; CHECK-NEXT: ret i64 [[TMP15]]2804;2805entry:2806 %0 = bitcast <1 x i64> %a to <4 x i16>2807 %1 = bitcast <4 x i16> %0 to <1 x i64>2808 %2 = tail call <1 x i64> @llvm.x86.sse.pshuf.w(<1 x i64> %1, i8 3) nounwind readnone2809 %3 = bitcast <1 x i64> %2 to <4 x i16>2810 %4 = bitcast <4 x i16> %3 to <1 x i64>2811 %5 = extractelement <1 x i64> %4, i32 02812 ret i64 %52813}2814 2815define i32 @test21_2(<1 x i64> %a) #0 {2816; CHECK-LABEL: define i32 @test21_2(2817; CHECK-SAME: <1 x i64> [[A:%.*]]) #[[ATTR1]] {2818; CHECK-NEXT: entry:2819; CHECK-NEXT: [[TMP7:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82820; CHECK-NEXT: call void @llvm.donothing()2821; CHECK-NEXT: [[TMP8:%.*]] = bitcast <1 x i64> [[TMP7]] to <4 x i16>2822; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>2823; CHECK-NEXT: [[TMP10:%.*]] = bitcast <4 x i16> [[TMP8]] to <1 x i64>2824; CHECK-NEXT: [[TMP11:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>2825; CHECK-NEXT: [[TMP9:%.*]] = call <1 x i64> @llvm.x86.sse.pshuf.w(<1 x i64> [[TMP10]], i8 3)2826; CHECK-NEXT: [[TMP13:%.*]] = or <1 x i64> zeroinitializer, [[TMP9]]2827; CHECK-NEXT: [[TMP6:%.*]] = tail call <1 x i64> @llvm.x86.sse.pshuf.w(<1 x i64> [[TMP11]], i8 3) #[[ATTR5]]2828; CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[TMP13]] to <4 x i16>2829; CHECK-NEXT: [[TMP12:%.*]] = bitcast <1 x i64> [[TMP6]] to <4 x i16>2830; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP3]] to <2 x i32>2831; CHECK-NEXT: [[TMP14:%.*]] = bitcast <4 x i16> [[TMP12]] to <2 x i32>2832; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i32> [[TMP4]], i32 02833; CHECK-NEXT: [[TMP15:%.*]] = extractelement <2 x i32> [[TMP14]], i32 02834; CHECK-NEXT: store i32 [[TMP5]], ptr @__msan_retval_tls, align 82835; CHECK-NEXT: ret i32 [[TMP15]]2836;2837entry:2838 %0 = bitcast <1 x i64> %a to <4 x i16>2839 %1 = bitcast <4 x i16> %0 to <1 x i64>2840 %2 = tail call <1 x i64> @llvm.x86.sse.pshuf.w(<1 x i64> %1, i8 3) nounwind readnone2841 %3 = bitcast <1 x i64> %2 to <4 x i16>2842 %4 = bitcast <4 x i16> %3 to <2 x i32>2843 %5 = extractelement <2 x i32> %4, i32 02844 ret i32 %52845}2846 2847declare <1 x i64> @llvm.x86.mmx.pmulu.dq(<1 x i64>, <1 x i64>) nounwind readnone2848 2849define i64 @test20(<1 x i64> %a, <1 x i64> %b) #0 {2850; CHECK-LABEL: define i64 @test20(2851; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {2852; CHECK-NEXT: entry:2853; CHECK-NEXT: [[TMP5:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82854; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82855; CHECK-NEXT: call void @llvm.donothing()2856; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[TMP5]] to <2 x i32>2857; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <2 x i32>2858; CHECK-NEXT: [[TMP4:%.*]] = bitcast <1 x i64> [[TMP8]] to <2 x i32>2859; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>2860; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i32> [[TMP4]] to <1 x i64>2861; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <2 x i32> [[TMP1]] to <1 x i64>2862; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i32> [[TMP9]] to <1 x i64>2863; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>2864; CHECK-NEXT: [[_MSPROP1:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]2865; CHECK-NEXT: [[TMP10:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pmulu.dq(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]2866; CHECK-NEXT: [[_MSPROP:%.*]] = bitcast <1 x i64> [[_MSPROP1]] to i642867; CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[TMP10]] to i642868; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 82869; CHECK-NEXT: ret i64 [[TMP3]]2870;2871entry:2872 %0 = bitcast <1 x i64> %b to <2 x i32>2873 %1 = bitcast <1 x i64> %a to <2 x i32>2874 %mmx_var.i = bitcast <2 x i32> %1 to <1 x i64>2875 %mmx_var1.i = bitcast <2 x i32> %0 to <1 x i64>2876 %2 = tail call <1 x i64> @llvm.x86.mmx.pmulu.dq(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind2877 %3 = bitcast <1 x i64> %2 to i642878 ret i64 %32879}2880 2881declare <2 x double> @llvm.x86.sse.cvtpi2pd(<1 x i64>) nounwind readnone2882 2883define <2 x double> @test19(<1 x i64> %a) #0 {2884; CHECK-LABEL: define <2 x double> @test19(2885; CHECK-SAME: <1 x i64> [[A:%.*]]) #[[ATTR1]] {2886; CHECK-NEXT: entry:2887; CHECK-NEXT: [[TMP4:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82888; CHECK-NEXT: call void @llvm.donothing()2889; CHECK-NEXT: [[TMP7:%.*]] = bitcast <1 x i64> [[TMP4]] to <2 x i32>2890; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>2891; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i32> [[TMP7]] to <1 x i64>2892; CHECK-NEXT: [[TMP8:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>2893; CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[TMP5]] to i642894; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP3]], 02895; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP6:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]2896; CHECK: 6:2897; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]2898; CHECK-NEXT: unreachable2899; CHECK: 7:2900; CHECK-NEXT: [[TMP2:%.*]] = tail call <2 x double> @llvm.x86.sse.cvtpi2pd(<1 x i64> [[TMP8]]) #[[ATTR5]]2901; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 82902; CHECK-NEXT: ret <2 x double> [[TMP2]]2903;2904entry:2905 %0 = bitcast <1 x i64> %a to <2 x i32>2906 %1 = bitcast <2 x i32> %0 to <1 x i64>2907 %2 = tail call <2 x double> @llvm.x86.sse.cvtpi2pd(<1 x i64> %1) nounwind readnone2908 ret <2 x double> %22909}2910 2911declare <1 x i64> @llvm.x86.sse.cvttpd2pi(<2 x double>) nounwind readnone2912 2913define i64 @test18(<2 x double> %a) #0 {2914; CHECK-LABEL: define i64 @test18(2915; CHECK-SAME: <2 x double> [[A:%.*]]) #[[ATTR1]] {2916; CHECK-NEXT: entry:2917; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 82918; CHECK-NEXT: call void @llvm.donothing()2919; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to i1282920; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 02921; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]2922; CHECK: 2:2923; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]2924; CHECK-NEXT: unreachable2925; CHECK: 3:2926; CHECK-NEXT: [[TMP8:%.*]] = tail call <1 x i64> @llvm.x86.sse.cvttpd2pi(<2 x double> [[A]]) #[[ATTR5]]2927; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[TMP8]] to <2 x i32>2928; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP1]] to <1 x i64>2929; CHECK-NEXT: [[TMP3:%.*]] = extractelement <1 x i64> [[TMP2]], i32 02930; CHECK-NEXT: store i64 0, ptr @__msan_retval_tls, align 82931; CHECK-NEXT: ret i64 [[TMP3]]2932;2933entry:2934 %0 = tail call <1 x i64> @llvm.x86.sse.cvttpd2pi(<2 x double> %a) nounwind readnone2935 %1 = bitcast <1 x i64> %0 to <2 x i32>2936 %2 = bitcast <2 x i32> %1 to <1 x i64>2937 %3 = extractelement <1 x i64> %2, i32 02938 ret i64 %32939}2940 2941declare <1 x i64> @llvm.x86.sse.cvtpd2pi(<2 x double>) nounwind readnone2942 2943define i64 @test17(<2 x double> %a) #0 {2944; CHECK-LABEL: define i64 @test17(2945; CHECK-SAME: <2 x double> [[A:%.*]]) #[[ATTR1]] {2946; CHECK-NEXT: entry:2947; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 82948; CHECK-NEXT: call void @llvm.donothing()2949; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to i1282950; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 02951; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]2952; CHECK: 2:2953; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]2954; CHECK-NEXT: unreachable2955; CHECK: 3:2956; CHECK-NEXT: [[TMP8:%.*]] = tail call <1 x i64> @llvm.x86.sse.cvtpd2pi(<2 x double> [[A]]) #[[ATTR5]]2957; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[TMP8]] to <2 x i32>2958; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP1]] to <1 x i64>2959; CHECK-NEXT: [[TMP3:%.*]] = extractelement <1 x i64> [[TMP2]], i32 02960; CHECK-NEXT: store i64 0, ptr @__msan_retval_tls, align 82961; CHECK-NEXT: ret i64 [[TMP3]]2962;2963entry:2964 %0 = tail call <1 x i64> @llvm.x86.sse.cvtpd2pi(<2 x double> %a) nounwind readnone2965 %1 = bitcast <1 x i64> %0 to <2 x i32>2966 %2 = bitcast <2 x i32> %1 to <1 x i64>2967 %3 = extractelement <1 x i64> %2, i32 02968 ret i64 %32969}2970 2971declare <1 x i64> @llvm.x86.mmx.palignr.b(<1 x i64>, <1 x i64>, i8) nounwind readnone2972 2973define i64 @test16(<1 x i64> %a, <1 x i64> %b) #0 {2974; CHECK-LABEL: define i64 @test16(2975; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {2976; CHECK-NEXT: entry:2977; CHECK-NEXT: [[TMP6:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82978; CHECK-NEXT: [[TMP7:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82979; CHECK-NEXT: call void @llvm.donothing()2980; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <1 x i64> [[TMP6]], i32 02981; CHECK-NEXT: [[TMP0:%.*]] = extractelement <1 x i64> [[A]], i32 02982; CHECK-NEXT: [[TMP4:%.*]] = bitcast i64 [[_MSPROP]] to <1 x i64>2983; CHECK-NEXT: [[MMX_VAR:%.*]] = bitcast i64 [[TMP0]] to <1 x i64>2984; CHECK-NEXT: [[_MSPROP1:%.*]] = extractelement <1 x i64> [[TMP7]], i32 02985; CHECK-NEXT: [[TMP1:%.*]] = extractelement <1 x i64> [[B]], i32 02986; CHECK-NEXT: [[TMP5:%.*]] = bitcast i64 [[_MSPROP1]] to <1 x i64>2987; CHECK-NEXT: [[MMX_VAR1:%.*]] = bitcast i64 [[TMP1]] to <1 x i64>2988; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP4]] to i642989; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP11]], 02990; CHECK-NEXT: [[TMP12:%.*]] = bitcast <1 x i64> [[TMP5]] to i642991; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP12]], 02992; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP2]]2993; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]2994; CHECK: 8:2995; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]2996; CHECK-NEXT: unreachable2997; CHECK: 9:2998; CHECK-NEXT: [[TMP10:%.*]] = tail call <1 x i64> @llvm.x86.mmx.palignr.b(<1 x i64> [[MMX_VAR]], <1 x i64> [[MMX_VAR1]], i8 16)2999; CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[TMP10]] to i643000; CHECK-NEXT: store i64 0, ptr @__msan_retval_tls, align 83001; CHECK-NEXT: ret i64 [[TMP3]]3002;3003entry:3004 %0 = extractelement <1 x i64> %a, i32 03005 %mmx_var = bitcast i64 %0 to <1 x i64>3006 %1 = extractelement <1 x i64> %b, i32 03007 %mmx_var1 = bitcast i64 %1 to <1 x i64>3008 %2 = tail call <1 x i64> @llvm.x86.mmx.palignr.b(<1 x i64> %mmx_var, <1 x i64> %mmx_var1, i8 16)3009 %3 = bitcast <1 x i64> %2 to i643010 ret i64 %33011}3012 3013declare <1 x i64> @llvm.x86.ssse3.pabs.d(<1 x i64>) nounwind readnone3014 3015define i64 @test15(<1 x i64> %a) #0 {3016; CHECK-LABEL: define i64 @test15(3017; CHECK-SAME: <1 x i64> [[A:%.*]]) #[[ATTR1]] {3018; CHECK-NEXT: entry:3019; CHECK-NEXT: [[TMP7:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 83020; CHECK-NEXT: call void @llvm.donothing()3021; CHECK-NEXT: [[TMP8:%.*]] = bitcast <1 x i64> [[TMP7]] to <2 x i32>3022; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>3023; CHECK-NEXT: [[TMP11:%.*]] = bitcast <2 x i32> [[TMP8]] to <1 x i64>3024; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>3025; CHECK-NEXT: [[TMP12:%.*]] = tail call <1 x i64> @llvm.x86.ssse3.pabs.d(<1 x i64> [[TMP1]]) #[[ATTR5]]3026; CHECK-NEXT: [[TMP6:%.*]] = bitcast <1 x i64> [[TMP11]] to <2 x i32>3027; CHECK-NEXT: [[TMP13:%.*]] = bitcast <1 x i64> [[TMP12]] to <2 x i32>3028; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP6]] to <1 x i64>3029; CHECK-NEXT: [[TMP9:%.*]] = bitcast <2 x i32> [[TMP13]] to <1 x i64>3030; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 03031; CHECK-NEXT: [[TMP10:%.*]] = extractelement <1 x i64> [[TMP9]], i32 03032; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 83033; CHECK-NEXT: ret i64 [[TMP10]]3034;3035entry:3036 %0 = bitcast <1 x i64> %a to <2 x i32>3037 %1 = bitcast <2 x i32> %0 to <1 x i64>3038 %2 = tail call <1 x i64> @llvm.x86.ssse3.pabs.d(<1 x i64> %1) nounwind readnone3039 %3 = bitcast <1 x i64> %2 to <2 x i32>3040 %4 = bitcast <2 x i32> %3 to <1 x i64>3041 %5 = extractelement <1 x i64> %4, i32 03042 ret i64 %53043}3044 3045declare <1 x i64> @llvm.x86.ssse3.pabs.w(<1 x i64>) nounwind readnone3046 3047define i64 @test14(<1 x i64> %a) #0 {3048; CHECK-LABEL: define i64 @test14(3049; CHECK-SAME: <1 x i64> [[A:%.*]]) #[[ATTR1]] {3050; CHECK-NEXT: entry:3051; CHECK-NEXT: [[TMP7:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 83052; CHECK-NEXT: call void @llvm.donothing()3053; CHECK-NEXT: [[TMP8:%.*]] = bitcast <1 x i64> [[TMP7]] to <4 x i16>3054; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>3055; CHECK-NEXT: [[TMP11:%.*]] = bitcast <4 x i16> [[TMP8]] to <1 x i64>3056; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>3057; CHECK-NEXT: [[TMP12:%.*]] = tail call <1 x i64> @llvm.x86.ssse3.pabs.w(<1 x i64> [[TMP1]]) #[[ATTR5]]3058; CHECK-NEXT: [[TMP6:%.*]] = bitcast <1 x i64> [[TMP11]] to <4 x i16>3059; CHECK-NEXT: [[TMP13:%.*]] = bitcast <1 x i64> [[TMP12]] to <4 x i16>3060; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP6]] to <1 x i64>3061; CHECK-NEXT: [[TMP9:%.*]] = bitcast <4 x i16> [[TMP13]] to <1 x i64>3062; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 03063; CHECK-NEXT: [[TMP10:%.*]] = extractelement <1 x i64> [[TMP9]], i32 03064; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 83065; CHECK-NEXT: ret i64 [[TMP10]]3066;3067entry:3068 %0 = bitcast <1 x i64> %a to <4 x i16>3069 %1 = bitcast <4 x i16> %0 to <1 x i64>3070 %2 = tail call <1 x i64> @llvm.x86.ssse3.pabs.w(<1 x i64> %1) nounwind readnone3071 %3 = bitcast <1 x i64> %2 to <4 x i16>3072 %4 = bitcast <4 x i16> %3 to <1 x i64>3073 %5 = extractelement <1 x i64> %4, i32 03074 ret i64 %53075}3076 3077declare <1 x i64> @llvm.x86.ssse3.pabs.b(<1 x i64>) nounwind readnone3078 3079define i64 @test13(<1 x i64> %a) #0 {3080; CHECK-LABEL: define i64 @test13(3081; CHECK-SAME: <1 x i64> [[A:%.*]]) #[[ATTR1]] {3082; CHECK-NEXT: entry:3083; CHECK-NEXT: [[TMP7:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 83084; CHECK-NEXT: call void @llvm.donothing()3085; CHECK-NEXT: [[TMP8:%.*]] = bitcast <1 x i64> [[TMP7]] to <8 x i8>3086; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>3087; CHECK-NEXT: [[TMP11:%.*]] = bitcast <8 x i8> [[TMP8]] to <1 x i64>3088; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>3089; CHECK-NEXT: [[TMP12:%.*]] = tail call <1 x i64> @llvm.x86.ssse3.pabs.b(<1 x i64> [[TMP1]]) #[[ATTR5]]3090; CHECK-NEXT: [[TMP6:%.*]] = bitcast <1 x i64> [[TMP11]] to <8 x i8>3091; CHECK-NEXT: [[TMP13:%.*]] = bitcast <1 x i64> [[TMP12]] to <8 x i8>3092; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP6]] to <1 x i64>3093; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i8> [[TMP13]] to <1 x i64>3094; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 03095; CHECK-NEXT: [[TMP10:%.*]] = extractelement <1 x i64> [[TMP9]], i32 03096; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 83097; CHECK-NEXT: ret i64 [[TMP10]]3098;3099entry:3100 %0 = bitcast <1 x i64> %a to <8 x i8>3101 %1 = bitcast <8 x i8> %0 to <1 x i64>3102 %2 = tail call <1 x i64> @llvm.x86.ssse3.pabs.b(<1 x i64> %1) nounwind readnone3103 %3 = bitcast <1 x i64> %2 to <8 x i8>3104 %4 = bitcast <8 x i8> %3 to <1 x i64>3105 %5 = extractelement <1 x i64> %4, i32 03106 ret i64 %53107}3108 3109declare <1 x i64> @llvm.x86.ssse3.psign.d(<1 x i64>, <1 x i64>) nounwind readnone3110 3111define i64 @test12(<1 x i64> %a, <1 x i64> %b) #0 {3112; CHECK-LABEL: define i64 @test12(3113; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {3114; CHECK-NEXT: entry:3115; CHECK-NEXT: [[TMP9:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83116; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 83117; CHECK-NEXT: call void @llvm.donothing()3118; CHECK-NEXT: [[TMP12:%.*]] = bitcast <1 x i64> [[TMP9]] to <2 x i32>3119; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <2 x i32>3120; CHECK-NEXT: [[TMP13:%.*]] = bitcast <1 x i64> [[TMP10]] to <2 x i32>3121; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>3122; CHECK-NEXT: [[TMP16:%.*]] = bitcast <2 x i32> [[TMP13]] to <1 x i64>3123; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP1]] to <1 x i64>3124; CHECK-NEXT: [[TMP8:%.*]] = bitcast <2 x i32> [[TMP12]] to <1 x i64>3125; CHECK-NEXT: [[TMP17:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>3126; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP16]], [[TMP8]]3127; CHECK-NEXT: [[TMP18:%.*]] = tail call <1 x i64> @llvm.x86.ssse3.psign.d(<1 x i64> [[TMP2]], <1 x i64> [[TMP17]]) #[[ATTR5]]3128; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <2 x i32>3129; CHECK-NEXT: [[TMP19:%.*]] = bitcast <1 x i64> [[TMP18]] to <2 x i32>3130; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i32> [[TMP11]] to <1 x i64>3131; CHECK-NEXT: [[TMP14:%.*]] = bitcast <2 x i32> [[TMP19]] to <1 x i64>3132; CHECK-NEXT: [[TMP7:%.*]] = extractelement <1 x i64> [[TMP6]], i32 03133; CHECK-NEXT: [[TMP15:%.*]] = extractelement <1 x i64> [[TMP14]], i32 03134; CHECK-NEXT: store i64 [[TMP7]], ptr @__msan_retval_tls, align 83135; CHECK-NEXT: ret i64 [[TMP15]]3136;3137entry:3138 %0 = bitcast <1 x i64> %b to <2 x i32>3139 %1 = bitcast <1 x i64> %a to <2 x i32>3140 %2 = bitcast <2 x i32> %1 to <1 x i64>3141 %3 = bitcast <2 x i32> %0 to <1 x i64>3142 %4 = tail call <1 x i64> @llvm.x86.ssse3.psign.d(<1 x i64> %2, <1 x i64> %3) nounwind readnone3143 %5 = bitcast <1 x i64> %4 to <2 x i32>3144 %6 = bitcast <2 x i32> %5 to <1 x i64>3145 %7 = extractelement <1 x i64> %6, i32 03146 ret i64 %73147}3148 3149declare <1 x i64> @llvm.x86.ssse3.psign.w(<1 x i64>, <1 x i64>) nounwind readnone3150 3151define i64 @test11(<1 x i64> %a, <1 x i64> %b) #0 {3152; CHECK-LABEL: define i64 @test11(3153; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {3154; CHECK-NEXT: entry:3155; CHECK-NEXT: [[TMP9:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83156; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 83157; CHECK-NEXT: call void @llvm.donothing()3158; CHECK-NEXT: [[TMP12:%.*]] = bitcast <1 x i64> [[TMP9]] to <4 x i16>3159; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>3160; CHECK-NEXT: [[TMP13:%.*]] = bitcast <1 x i64> [[TMP10]] to <4 x i16>3161; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>3162; CHECK-NEXT: [[TMP16:%.*]] = bitcast <4 x i16> [[TMP13]] to <1 x i64>3163; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>3164; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x i16> [[TMP12]] to <1 x i64>3165; CHECK-NEXT: [[TMP17:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>3166; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP16]], [[TMP8]]3167; CHECK-NEXT: [[TMP18:%.*]] = tail call <1 x i64> @llvm.x86.ssse3.psign.w(<1 x i64> [[TMP2]], <1 x i64> [[TMP17]]) #[[ATTR5]]3168; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>3169; CHECK-NEXT: [[TMP19:%.*]] = bitcast <1 x i64> [[TMP18]] to <4 x i16>3170; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>3171; CHECK-NEXT: [[TMP14:%.*]] = bitcast <4 x i16> [[TMP19]] to <1 x i64>3172; CHECK-NEXT: [[TMP7:%.*]] = extractelement <1 x i64> [[TMP6]], i32 03173; CHECK-NEXT: [[TMP15:%.*]] = extractelement <1 x i64> [[TMP14]], i32 03174; CHECK-NEXT: store i64 [[TMP7]], ptr @__msan_retval_tls, align 83175; CHECK-NEXT: ret i64 [[TMP15]]3176;3177entry:3178 %0 = bitcast <1 x i64> %b to <4 x i16>3179 %1 = bitcast <1 x i64> %a to <4 x i16>3180 %2 = bitcast <4 x i16> %1 to <1 x i64>3181 %3 = bitcast <4 x i16> %0 to <1 x i64>3182 %4 = tail call <1 x i64> @llvm.x86.ssse3.psign.w(<1 x i64> %2, <1 x i64> %3) nounwind readnone3183 %5 = bitcast <1 x i64> %4 to <4 x i16>3184 %6 = bitcast <4 x i16> %5 to <1 x i64>3185 %7 = extractelement <1 x i64> %6, i32 03186 ret i64 %73187}3188 3189declare <1 x i64> @llvm.x86.ssse3.psign.b(<1 x i64>, <1 x i64>) nounwind readnone3190 3191define i64 @test10(<1 x i64> %a, <1 x i64> %b) #0 {3192; CHECK-LABEL: define i64 @test10(3193; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {3194; CHECK-NEXT: entry:3195; CHECK-NEXT: [[TMP9:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83196; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 83197; CHECK-NEXT: call void @llvm.donothing()3198; CHECK-NEXT: [[TMP12:%.*]] = bitcast <1 x i64> [[TMP9]] to <8 x i8>3199; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>3200; CHECK-NEXT: [[TMP13:%.*]] = bitcast <1 x i64> [[TMP10]] to <8 x i8>3201; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>3202; CHECK-NEXT: [[TMP16:%.*]] = bitcast <8 x i8> [[TMP13]] to <1 x i64>3203; CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>3204; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP12]] to <1 x i64>3205; CHECK-NEXT: [[TMP17:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>3206; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP16]], [[TMP8]]3207; CHECK-NEXT: [[TMP18:%.*]] = tail call <1 x i64> @llvm.x86.ssse3.psign.b(<1 x i64> [[TMP2]], <1 x i64> [[TMP17]]) #[[ATTR5]]3208; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <8 x i8>3209; CHECK-NEXT: [[TMP19:%.*]] = bitcast <1 x i64> [[TMP18]] to <8 x i8>3210; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP11]] to <1 x i64>3211; CHECK-NEXT: [[TMP14:%.*]] = bitcast <8 x i8> [[TMP19]] to <1 x i64>3212; CHECK-NEXT: [[TMP7:%.*]] = extractelement <1 x i64> [[TMP6]], i32 03213; CHECK-NEXT: [[TMP15:%.*]] = extractelement <1 x i64> [[TMP14]], i32 03214; CHECK-NEXT: store i64 [[TMP7]], ptr @__msan_retval_tls, align 83215; CHECK-NEXT: ret i64 [[TMP15]]3216;3217entry:3218 %0 = bitcast <1 x i64> %b to <8 x i8>3219 %1 = bitcast <1 x i64> %a to <8 x i8>3220 %2 = bitcast <8 x i8> %1 to <1 x i64>3221 %3 = bitcast <8 x i8> %0 to <1 x i64>3222 %4 = tail call <1 x i64> @llvm.x86.ssse3.psign.b(<1 x i64> %2, <1 x i64> %3) nounwind readnone3223 %5 = bitcast <1 x i64> %4 to <8 x i8>3224 %6 = bitcast <8 x i8> %5 to <1 x i64>3225 %7 = extractelement <1 x i64> %6, i32 03226 ret i64 %73227}3228 3229declare <1 x i64> @llvm.x86.ssse3.pshuf.b(<1 x i64>, <1 x i64>) nounwind readnone3230 3231define i64 @test9(<1 x i64> %a, <1 x i64> %b) #0 {3232; CHECK-LABEL: define i64 @test9(3233; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {3234; CHECK-NEXT: entry:3235; CHECK-NEXT: [[TMP9:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83236; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 83237; CHECK-NEXT: call void @llvm.donothing()3238; CHECK-NEXT: [[TMP12:%.*]] = bitcast <1 x i64> [[TMP9]] to <8 x i8>3239; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>3240; CHECK-NEXT: [[TMP13:%.*]] = bitcast <1 x i64> [[TMP10]] to <8 x i8>3241; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>3242; CHECK-NEXT: [[TMP16:%.*]] = bitcast <8 x i8> [[TMP13]] to <1 x i64>3243; CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>3244; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP12]] to <1 x i64>3245; CHECK-NEXT: [[TMP17:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>3246; CHECK-NEXT: [[TMP20:%.*]] = call <1 x i64> @llvm.x86.ssse3.pshuf.b(<1 x i64> [[TMP16]], <1 x i64> [[TMP17]])3247; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP8]], [[TMP20]]3248; CHECK-NEXT: [[TMP18:%.*]] = tail call <1 x i64> @llvm.x86.ssse3.pshuf.b(<1 x i64> [[TMP2]], <1 x i64> [[TMP17]]) #[[ATTR5]]3249; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <8 x i8>3250; CHECK-NEXT: [[TMP19:%.*]] = bitcast <1 x i64> [[TMP18]] to <8 x i8>3251; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP11]] to <1 x i64>3252; CHECK-NEXT: [[TMP14:%.*]] = bitcast <8 x i8> [[TMP19]] to <1 x i64>3253; CHECK-NEXT: [[TMP7:%.*]] = extractelement <1 x i64> [[TMP6]], i32 03254; CHECK-NEXT: [[TMP15:%.*]] = extractelement <1 x i64> [[TMP14]], i32 03255; CHECK-NEXT: store i64 [[TMP7]], ptr @__msan_retval_tls, align 83256; CHECK-NEXT: ret i64 [[TMP15]]3257;3258entry:3259 %0 = bitcast <1 x i64> %b to <8 x i8>3260 %1 = bitcast <1 x i64> %a to <8 x i8>3261 %2 = bitcast <8 x i8> %1 to <1 x i64>3262 %3 = bitcast <8 x i8> %0 to <1 x i64>3263 %4 = tail call <1 x i64> @llvm.x86.ssse3.pshuf.b(<1 x i64> %2, <1 x i64> %3) nounwind readnone3264 %5 = bitcast <1 x i64> %4 to <8 x i8>3265 %6 = bitcast <8 x i8> %5 to <1 x i64>3266 %7 = extractelement <1 x i64> %6, i32 03267 ret i64 %73268}3269 3270declare <1 x i64> @llvm.x86.ssse3.pmul.hr.sw(<1 x i64>, <1 x i64>) nounwind readnone3271 3272define i64 @test8(<1 x i64> %a, <1 x i64> %b) #0 {3273; CHECK-LABEL: define i64 @test8(3274; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {3275; CHECK-NEXT: entry:3276; CHECK-NEXT: [[TMP9:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83277; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 83278; CHECK-NEXT: call void @llvm.donothing()3279; CHECK-NEXT: [[TMP12:%.*]] = bitcast <1 x i64> [[TMP9]] to <4 x i16>3280; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>3281; CHECK-NEXT: [[TMP13:%.*]] = bitcast <1 x i64> [[TMP10]] to <4 x i16>3282; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>3283; CHECK-NEXT: [[TMP16:%.*]] = bitcast <4 x i16> [[TMP13]] to <1 x i64>3284; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>3285; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x i16> [[TMP12]] to <1 x i64>3286; CHECK-NEXT: [[TMP17:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>3287; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP16]], [[TMP8]]3288; CHECK-NEXT: [[TMP18:%.*]] = tail call <1 x i64> @llvm.x86.ssse3.pmul.hr.sw(<1 x i64> [[TMP2]], <1 x i64> [[TMP17]]) #[[ATTR5]]3289; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>3290; CHECK-NEXT: [[TMP19:%.*]] = bitcast <1 x i64> [[TMP18]] to <4 x i16>3291; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>3292; CHECK-NEXT: [[TMP14:%.*]] = bitcast <4 x i16> [[TMP19]] to <1 x i64>3293; CHECK-NEXT: [[TMP7:%.*]] = extractelement <1 x i64> [[TMP6]], i32 03294; CHECK-NEXT: [[TMP15:%.*]] = extractelement <1 x i64> [[TMP14]], i32 03295; CHECK-NEXT: store i64 [[TMP7]], ptr @__msan_retval_tls, align 83296; CHECK-NEXT: ret i64 [[TMP15]]3297;3298entry:3299 %0 = bitcast <1 x i64> %b to <4 x i16>3300 %1 = bitcast <1 x i64> %a to <4 x i16>3301 %2 = bitcast <4 x i16> %1 to <1 x i64>3302 %3 = bitcast <4 x i16> %0 to <1 x i64>3303 %4 = tail call <1 x i64> @llvm.x86.ssse3.pmul.hr.sw(<1 x i64> %2, <1 x i64> %3) nounwind readnone3304 %5 = bitcast <1 x i64> %4 to <4 x i16>3305 %6 = bitcast <4 x i16> %5 to <1 x i64>3306 %7 = extractelement <1 x i64> %6, i32 03307 ret i64 %73308}3309 3310declare <1 x i64> @llvm.x86.ssse3.pmadd.ub.sw(<1 x i64>, <1 x i64>) nounwind readnone3311 3312define i64 @test7(<1 x i64> %a, <1 x i64> %b) #0 {3313; CHECK-LABEL: define i64 @test7(3314; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {3315; CHECK-NEXT: entry:3316; CHECK-NEXT: [[TMP9:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83317; CHECK-NEXT: [[TMP15:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 83318; CHECK-NEXT: call void @llvm.donothing()3319; CHECK-NEXT: [[TMP17:%.*]] = bitcast <1 x i64> [[TMP9]] to <8 x i8>3320; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>3321; CHECK-NEXT: [[TMP18:%.*]] = bitcast <1 x i64> [[TMP15]] to <8 x i8>3322; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>3323; CHECK-NEXT: [[TMP21:%.*]] = bitcast <8 x i8> [[TMP18]] to <1 x i64>3324; CHECK-NEXT: [[TMP22:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>3325; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP17]] to <1 x i64>3326; CHECK-NEXT: [[TMP23:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>3327; CHECK-NEXT: [[TMP10:%.*]] = bitcast <1 x i64> [[TMP22]] to <8 x i8>3328; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP23]] to <8 x i8>3329; CHECK-NEXT: [[TMP12:%.*]] = bitcast <1 x i64> [[TMP21]] to <8 x i8>3330; CHECK-NEXT: [[TMP13:%.*]] = bitcast <1 x i64> [[TMP8]] to <8 x i8>3331; CHECK-NEXT: [[TMP32:%.*]] = icmp ne <8 x i8> [[TMP12]], zeroinitializer3332; CHECK-NEXT: [[TMP33:%.*]] = icmp ne <8 x i8> [[TMP13]], zeroinitializer3333; CHECK-NEXT: [[TMP35:%.*]] = icmp ne <8 x i8> [[TMP10]], zeroinitializer3334; CHECK-NEXT: [[TMP37:%.*]] = icmp ne <8 x i8> [[TMP11]], zeroinitializer3335; CHECK-NEXT: [[TMP34:%.*]] = and <8 x i1> [[TMP32]], [[TMP33]]3336; CHECK-NEXT: [[TMP38:%.*]] = and <8 x i1> [[TMP35]], [[TMP33]]3337; CHECK-NEXT: [[TMP39:%.*]] = and <8 x i1> [[TMP32]], [[TMP37]]3338; CHECK-NEXT: [[TMP40:%.*]] = or <8 x i1> [[TMP34]], [[TMP38]]3339; CHECK-NEXT: [[TMP41:%.*]] = or <8 x i1> [[TMP40]], [[TMP39]]3340; CHECK-NEXT: [[TMP16:%.*]] = sext <8 x i1> [[TMP41]] to <8 x i8>3341; CHECK-NEXT: [[TMP26:%.*]] = bitcast <8 x i8> [[TMP16]] to <4 x i16>3342; CHECK-NEXT: [[TMP25:%.*]] = icmp ne <4 x i16> [[TMP26]], zeroinitializer3343; CHECK-NEXT: [[TMP29:%.*]] = sext <4 x i1> [[TMP25]] to <4 x i16>3344; CHECK-NEXT: [[TMP24:%.*]] = bitcast <4 x i16> [[TMP29]] to i643345; CHECK-NEXT: [[TMP30:%.*]] = bitcast i64 [[TMP24]] to <1 x i64>3346; CHECK-NEXT: [[TMP36:%.*]] = tail call <1 x i64> @llvm.x86.ssse3.pmadd.ub.sw(<1 x i64> [[TMP22]], <1 x i64> [[TMP23]]) #[[ATTR5]]3347; CHECK-NEXT: [[TMP31:%.*]] = bitcast <1 x i64> [[TMP30]] to <8 x i8>3348; CHECK-NEXT: [[TMP28:%.*]] = bitcast <1 x i64> [[TMP36]] to <8 x i8>3349; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP31]] to <1 x i64>3350; CHECK-NEXT: [[TMP19:%.*]] = bitcast <8 x i8> [[TMP28]] to <1 x i64>3351; CHECK-NEXT: [[TMP7:%.*]] = extractelement <1 x i64> [[TMP6]], i32 03352; CHECK-NEXT: [[TMP20:%.*]] = extractelement <1 x i64> [[TMP19]], i32 03353; CHECK-NEXT: store i64 [[TMP7]], ptr @__msan_retval_tls, align 83354; CHECK-NEXT: ret i64 [[TMP20]]3355;3356entry:3357 %0 = bitcast <1 x i64> %b to <8 x i8>3358 %1 = bitcast <1 x i64> %a to <8 x i8>3359 %2 = bitcast <8 x i8> %1 to <1 x i64>3360 %3 = bitcast <8 x i8> %0 to <1 x i64>3361 %4 = tail call <1 x i64> @llvm.x86.ssse3.pmadd.ub.sw(<1 x i64> %2, <1 x i64> %3) nounwind readnone3362 %5 = bitcast <1 x i64> %4 to <8 x i8>3363 %6 = bitcast <8 x i8> %5 to <1 x i64>3364 %7 = extractelement <1 x i64> %6, i32 03365 ret i64 %73366}3367 3368declare <1 x i64> @llvm.x86.ssse3.phsub.sw(<1 x i64>, <1 x i64>) nounwind readnone3369 3370define i64 @test6(<1 x i64> %a, <1 x i64> %b) #0 {3371; CHECK-LABEL: define i64 @test6(3372; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {3373; CHECK-NEXT: entry:3374; CHECK-NEXT: [[TMP9:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83375; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 83376; CHECK-NEXT: call void @llvm.donothing()3377; CHECK-NEXT: [[TMP12:%.*]] = bitcast <1 x i64> [[TMP9]] to <4 x i16>3378; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>3379; CHECK-NEXT: [[TMP13:%.*]] = bitcast <1 x i64> [[TMP10]] to <4 x i16>3380; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>3381; CHECK-NEXT: [[TMP16:%.*]] = bitcast <4 x i16> [[TMP13]] to <1 x i64>3382; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>3383; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x i16> [[TMP12]] to <1 x i64>3384; CHECK-NEXT: [[TMP17:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>3385; CHECK-NEXT: [[TMP21:%.*]] = bitcast <1 x i64> [[TMP16]] to <4 x i16>3386; CHECK-NEXT: [[TMP23:%.*]] = bitcast <1 x i64> [[TMP8]] to <4 x i16>3387; CHECK-NEXT: [[TMP24:%.*]] = shufflevector <4 x i16> [[TMP21]], <4 x i16> [[TMP23]], <4 x i32> <i32 0, i32 2, i32 4, i32 6>3388; CHECK-NEXT: [[TMP25:%.*]] = shufflevector <4 x i16> [[TMP21]], <4 x i16> [[TMP23]], <4 x i32> <i32 1, i32 3, i32 5, i32 7>3389; CHECK-NEXT: [[TMP26:%.*]] = or <4 x i16> [[TMP24]], [[TMP25]]3390; CHECK-NEXT: [[TMP27:%.*]] = bitcast <4 x i16> [[TMP26]] to i643391; CHECK-NEXT: [[_MSPROP:%.*]] = bitcast i64 [[TMP27]] to <1 x i64>3392; CHECK-NEXT: [[TMP18:%.*]] = tail call <1 x i64> @llvm.x86.ssse3.phsub.sw(<1 x i64> [[TMP2]], <1 x i64> [[TMP17]]) #[[ATTR5]]3393; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>3394; CHECK-NEXT: [[TMP19:%.*]] = bitcast <1 x i64> [[TMP18]] to <4 x i16>3395; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>3396; CHECK-NEXT: [[TMP14:%.*]] = bitcast <4 x i16> [[TMP19]] to <1 x i64>3397; CHECK-NEXT: [[TMP7:%.*]] = extractelement <1 x i64> [[TMP6]], i32 03398; CHECK-NEXT: [[TMP15:%.*]] = extractelement <1 x i64> [[TMP14]], i32 03399; CHECK-NEXT: store i64 [[TMP7]], ptr @__msan_retval_tls, align 83400; CHECK-NEXT: ret i64 [[TMP15]]3401;3402entry:3403 %0 = bitcast <1 x i64> %b to <4 x i16>3404 %1 = bitcast <1 x i64> %a to <4 x i16>3405 %2 = bitcast <4 x i16> %1 to <1 x i64>3406 %3 = bitcast <4 x i16> %0 to <1 x i64>3407 %4 = tail call <1 x i64> @llvm.x86.ssse3.phsub.sw(<1 x i64> %2, <1 x i64> %3) nounwind readnone3408 %5 = bitcast <1 x i64> %4 to <4 x i16>3409 %6 = bitcast <4 x i16> %5 to <1 x i64>3410 %7 = extractelement <1 x i64> %6, i32 03411 ret i64 %73412}3413 3414declare <1 x i64> @llvm.x86.ssse3.phsub.d(<1 x i64>, <1 x i64>) nounwind readnone3415 3416define i64 @test5(<1 x i64> %a, <1 x i64> %b) #0 {3417; CHECK-LABEL: define i64 @test5(3418; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {3419; CHECK-NEXT: entry:3420; CHECK-NEXT: [[TMP9:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83421; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 83422; CHECK-NEXT: call void @llvm.donothing()3423; CHECK-NEXT: [[TMP12:%.*]] = bitcast <1 x i64> [[TMP9]] to <2 x i32>3424; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <2 x i32>3425; CHECK-NEXT: [[TMP13:%.*]] = bitcast <1 x i64> [[TMP10]] to <2 x i32>3426; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>3427; CHECK-NEXT: [[TMP16:%.*]] = bitcast <2 x i32> [[TMP13]] to <1 x i64>3428; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP1]] to <1 x i64>3429; CHECK-NEXT: [[TMP8:%.*]] = bitcast <2 x i32> [[TMP12]] to <1 x i64>3430; CHECK-NEXT: [[TMP17:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>3431; CHECK-NEXT: [[TMP21:%.*]] = bitcast <1 x i64> [[TMP16]] to <2 x i32>3432; CHECK-NEXT: [[TMP23:%.*]] = bitcast <1 x i64> [[TMP8]] to <2 x i32>3433; CHECK-NEXT: [[TMP24:%.*]] = shufflevector <2 x i32> [[TMP21]], <2 x i32> [[TMP23]], <2 x i32> <i32 0, i32 2>3434; CHECK-NEXT: [[TMP25:%.*]] = shufflevector <2 x i32> [[TMP21]], <2 x i32> [[TMP23]], <2 x i32> <i32 1, i32 3>3435; CHECK-NEXT: [[TMP26:%.*]] = or <2 x i32> [[TMP24]], [[TMP25]]3436; CHECK-NEXT: [[TMP27:%.*]] = bitcast <2 x i32> [[TMP26]] to i643437; CHECK-NEXT: [[_MSPROP:%.*]] = bitcast i64 [[TMP27]] to <1 x i64>3438; CHECK-NEXT: [[TMP18:%.*]] = tail call <1 x i64> @llvm.x86.ssse3.phsub.d(<1 x i64> [[TMP2]], <1 x i64> [[TMP17]]) #[[ATTR5]]3439; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <2 x i32>3440; CHECK-NEXT: [[TMP19:%.*]] = bitcast <1 x i64> [[TMP18]] to <2 x i32>3441; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i32> [[TMP11]] to <1 x i64>3442; CHECK-NEXT: [[TMP14:%.*]] = bitcast <2 x i32> [[TMP19]] to <1 x i64>3443; CHECK-NEXT: [[TMP7:%.*]] = extractelement <1 x i64> [[TMP6]], i32 03444; CHECK-NEXT: [[TMP15:%.*]] = extractelement <1 x i64> [[TMP14]], i32 03445; CHECK-NEXT: store i64 [[TMP7]], ptr @__msan_retval_tls, align 83446; CHECK-NEXT: ret i64 [[TMP15]]3447;3448entry:3449 %0 = bitcast <1 x i64> %b to <2 x i32>3450 %1 = bitcast <1 x i64> %a to <2 x i32>3451 %2 = bitcast <2 x i32> %1 to <1 x i64>3452 %3 = bitcast <2 x i32> %0 to <1 x i64>3453 %4 = tail call <1 x i64> @llvm.x86.ssse3.phsub.d(<1 x i64> %2, <1 x i64> %3) nounwind readnone3454 %5 = bitcast <1 x i64> %4 to <2 x i32>3455 %6 = bitcast <2 x i32> %5 to <1 x i64>3456 %7 = extractelement <1 x i64> %6, i32 03457 ret i64 %73458}3459 3460declare <1 x i64> @llvm.x86.ssse3.phsub.w(<1 x i64>, <1 x i64>) nounwind readnone3461 3462define i64 @test4(<1 x i64> %a, <1 x i64> %b) #0 {3463; CHECK-LABEL: define i64 @test4(3464; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {3465; CHECK-NEXT: entry:3466; CHECK-NEXT: [[TMP9:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83467; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 83468; CHECK-NEXT: call void @llvm.donothing()3469; CHECK-NEXT: [[TMP12:%.*]] = bitcast <1 x i64> [[TMP9]] to <4 x i16>3470; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>3471; CHECK-NEXT: [[TMP13:%.*]] = bitcast <1 x i64> [[TMP10]] to <4 x i16>3472; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>3473; CHECK-NEXT: [[TMP16:%.*]] = bitcast <4 x i16> [[TMP13]] to <1 x i64>3474; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>3475; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x i16> [[TMP12]] to <1 x i64>3476; CHECK-NEXT: [[TMP17:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>3477; CHECK-NEXT: [[TMP21:%.*]] = bitcast <1 x i64> [[TMP16]] to <4 x i16>3478; CHECK-NEXT: [[TMP23:%.*]] = bitcast <1 x i64> [[TMP8]] to <4 x i16>3479; CHECK-NEXT: [[TMP24:%.*]] = shufflevector <4 x i16> [[TMP21]], <4 x i16> [[TMP23]], <4 x i32> <i32 0, i32 2, i32 4, i32 6>3480; CHECK-NEXT: [[TMP25:%.*]] = shufflevector <4 x i16> [[TMP21]], <4 x i16> [[TMP23]], <4 x i32> <i32 1, i32 3, i32 5, i32 7>3481; CHECK-NEXT: [[TMP26:%.*]] = or <4 x i16> [[TMP24]], [[TMP25]]3482; CHECK-NEXT: [[TMP27:%.*]] = bitcast <4 x i16> [[TMP26]] to i643483; CHECK-NEXT: [[_MSPROP:%.*]] = bitcast i64 [[TMP27]] to <1 x i64>3484; CHECK-NEXT: [[TMP18:%.*]] = tail call <1 x i64> @llvm.x86.ssse3.phsub.w(<1 x i64> [[TMP2]], <1 x i64> [[TMP17]]) #[[ATTR5]]3485; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>3486; CHECK-NEXT: [[TMP19:%.*]] = bitcast <1 x i64> [[TMP18]] to <4 x i16>3487; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>3488; CHECK-NEXT: [[TMP14:%.*]] = bitcast <4 x i16> [[TMP19]] to <1 x i64>3489; CHECK-NEXT: [[TMP7:%.*]] = extractelement <1 x i64> [[TMP6]], i32 03490; CHECK-NEXT: [[TMP15:%.*]] = extractelement <1 x i64> [[TMP14]], i32 03491; CHECK-NEXT: store i64 [[TMP7]], ptr @__msan_retval_tls, align 83492; CHECK-NEXT: ret i64 [[TMP15]]3493;3494entry:3495 %0 = bitcast <1 x i64> %b to <4 x i16>3496 %1 = bitcast <1 x i64> %a to <4 x i16>3497 %2 = bitcast <4 x i16> %1 to <1 x i64>3498 %3 = bitcast <4 x i16> %0 to <1 x i64>3499 %4 = tail call <1 x i64> @llvm.x86.ssse3.phsub.w(<1 x i64> %2, <1 x i64> %3) nounwind readnone3500 %5 = bitcast <1 x i64> %4 to <4 x i16>3501 %6 = bitcast <4 x i16> %5 to <1 x i64>3502 %7 = extractelement <1 x i64> %6, i32 03503 ret i64 %73504}3505 3506declare <1 x i64> @llvm.x86.ssse3.phadd.sw(<1 x i64>, <1 x i64>) nounwind readnone3507 3508define i64 @test3(<1 x i64> %a, <1 x i64> %b) #0 {3509; CHECK-LABEL: define i64 @test3(3510; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {3511; CHECK-NEXT: entry:3512; CHECK-NEXT: [[TMP9:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83513; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 83514; CHECK-NEXT: call void @llvm.donothing()3515; CHECK-NEXT: [[TMP12:%.*]] = bitcast <1 x i64> [[TMP9]] to <4 x i16>3516; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>3517; CHECK-NEXT: [[TMP13:%.*]] = bitcast <1 x i64> [[TMP10]] to <4 x i16>3518; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>3519; CHECK-NEXT: [[TMP16:%.*]] = bitcast <4 x i16> [[TMP13]] to <1 x i64>3520; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>3521; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x i16> [[TMP12]] to <1 x i64>3522; CHECK-NEXT: [[TMP17:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>3523; CHECK-NEXT: [[TMP21:%.*]] = bitcast <1 x i64> [[TMP16]] to <4 x i16>3524; CHECK-NEXT: [[TMP23:%.*]] = bitcast <1 x i64> [[TMP8]] to <4 x i16>3525; CHECK-NEXT: [[TMP24:%.*]] = shufflevector <4 x i16> [[TMP21]], <4 x i16> [[TMP23]], <4 x i32> <i32 0, i32 2, i32 4, i32 6>3526; CHECK-NEXT: [[TMP25:%.*]] = shufflevector <4 x i16> [[TMP21]], <4 x i16> [[TMP23]], <4 x i32> <i32 1, i32 3, i32 5, i32 7>3527; CHECK-NEXT: [[TMP26:%.*]] = or <4 x i16> [[TMP24]], [[TMP25]]3528; CHECK-NEXT: [[TMP27:%.*]] = bitcast <4 x i16> [[TMP26]] to i643529; CHECK-NEXT: [[_MSPROP:%.*]] = bitcast i64 [[TMP27]] to <1 x i64>3530; CHECK-NEXT: [[TMP18:%.*]] = tail call <1 x i64> @llvm.x86.ssse3.phadd.sw(<1 x i64> [[TMP2]], <1 x i64> [[TMP17]]) #[[ATTR5]]3531; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>3532; CHECK-NEXT: [[TMP19:%.*]] = bitcast <1 x i64> [[TMP18]] to <4 x i16>3533; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>3534; CHECK-NEXT: [[TMP14:%.*]] = bitcast <4 x i16> [[TMP19]] to <1 x i64>3535; CHECK-NEXT: [[TMP7:%.*]] = extractelement <1 x i64> [[TMP6]], i32 03536; CHECK-NEXT: [[TMP15:%.*]] = extractelement <1 x i64> [[TMP14]], i32 03537; CHECK-NEXT: store i64 [[TMP7]], ptr @__msan_retval_tls, align 83538; CHECK-NEXT: ret i64 [[TMP15]]3539;3540entry:3541 %0 = bitcast <1 x i64> %b to <4 x i16>3542 %1 = bitcast <1 x i64> %a to <4 x i16>3543 %2 = bitcast <4 x i16> %1 to <1 x i64>3544 %3 = bitcast <4 x i16> %0 to <1 x i64>3545 %4 = tail call <1 x i64> @llvm.x86.ssse3.phadd.sw(<1 x i64> %2, <1 x i64> %3) nounwind readnone3546 %5 = bitcast <1 x i64> %4 to <4 x i16>3547 %6 = bitcast <4 x i16> %5 to <1 x i64>3548 %7 = extractelement <1 x i64> %6, i32 03549 ret i64 %73550}3551 3552declare <1 x i64> @llvm.x86.ssse3.phadd.d(<1 x i64>, <1 x i64>) nounwind readnone3553 3554define i64 @test2(<1 x i64> %a, <1 x i64> %b) #0 {3555; CHECK-LABEL: define i64 @test2(3556; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {3557; CHECK-NEXT: entry:3558; CHECK-NEXT: [[TMP9:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83559; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 83560; CHECK-NEXT: call void @llvm.donothing()3561; CHECK-NEXT: [[TMP12:%.*]] = bitcast <1 x i64> [[TMP9]] to <2 x i32>3562; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <2 x i32>3563; CHECK-NEXT: [[TMP13:%.*]] = bitcast <1 x i64> [[TMP10]] to <2 x i32>3564; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>3565; CHECK-NEXT: [[TMP16:%.*]] = bitcast <2 x i32> [[TMP13]] to <1 x i64>3566; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP1]] to <1 x i64>3567; CHECK-NEXT: [[TMP8:%.*]] = bitcast <2 x i32> [[TMP12]] to <1 x i64>3568; CHECK-NEXT: [[TMP17:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>3569; CHECK-NEXT: [[TMP21:%.*]] = bitcast <1 x i64> [[TMP16]] to <2 x i32>3570; CHECK-NEXT: [[TMP23:%.*]] = bitcast <1 x i64> [[TMP8]] to <2 x i32>3571; CHECK-NEXT: [[TMP24:%.*]] = shufflevector <2 x i32> [[TMP21]], <2 x i32> [[TMP23]], <2 x i32> <i32 0, i32 2>3572; CHECK-NEXT: [[TMP25:%.*]] = shufflevector <2 x i32> [[TMP21]], <2 x i32> [[TMP23]], <2 x i32> <i32 1, i32 3>3573; CHECK-NEXT: [[TMP26:%.*]] = or <2 x i32> [[TMP24]], [[TMP25]]3574; CHECK-NEXT: [[TMP27:%.*]] = bitcast <2 x i32> [[TMP26]] to i643575; CHECK-NEXT: [[_MSPROP:%.*]] = bitcast i64 [[TMP27]] to <1 x i64>3576; CHECK-NEXT: [[TMP18:%.*]] = tail call <1 x i64> @llvm.x86.ssse3.phadd.d(<1 x i64> [[TMP2]], <1 x i64> [[TMP17]]) #[[ATTR5]]3577; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <2 x i32>3578; CHECK-NEXT: [[TMP19:%.*]] = bitcast <1 x i64> [[TMP18]] to <2 x i32>3579; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i32> [[TMP11]] to <1 x i64>3580; CHECK-NEXT: [[TMP14:%.*]] = bitcast <2 x i32> [[TMP19]] to <1 x i64>3581; CHECK-NEXT: [[TMP7:%.*]] = extractelement <1 x i64> [[TMP6]], i32 03582; CHECK-NEXT: [[TMP15:%.*]] = extractelement <1 x i64> [[TMP14]], i32 03583; CHECK-NEXT: store i64 [[TMP7]], ptr @__msan_retval_tls, align 83584; CHECK-NEXT: ret i64 [[TMP15]]3585;3586entry:3587 %0 = bitcast <1 x i64> %b to <2 x i32>3588 %1 = bitcast <1 x i64> %a to <2 x i32>3589 %2 = bitcast <2 x i32> %1 to <1 x i64>3590 %3 = bitcast <2 x i32> %0 to <1 x i64>3591 %4 = tail call <1 x i64> @llvm.x86.ssse3.phadd.d(<1 x i64> %2, <1 x i64> %3) nounwind readnone3592 %5 = bitcast <1 x i64> %4 to <2 x i32>3593 %6 = bitcast <2 x i32> %5 to <1 x i64>3594 %7 = extractelement <1 x i64> %6, i32 03595 ret i64 %73596}3597 3598define <4 x float> @test89(<4 x float> %a, <1 x i64> %b) nounwind #0 {3599; ALL-LABEL: test89:3600; ALL: # %bb.0:3601; ALL-NEXT: cvtpi2ps %mm0, %xmm03602; ALL-NEXT: ret{{[l|q]}}3603; CHECK-LABEL: define <4 x float> @test89(3604; CHECK-SAME: <4 x float> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR4:[0-9]+]] {3605; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 83606; CHECK-NEXT: [[TMP4:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83607; CHECK-NEXT: call void @llvm.donothing()3608; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP1]] to i1283609; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 03610; CHECK-NEXT: [[TMP2:%.*]] = bitcast <1 x i64> [[TMP4]] to i643611; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 03612; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3613; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]3614; CHECK: 5:3615; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3616; CHECK-NEXT: unreachable3617; CHECK: 6:3618; CHECK-NEXT: [[C:%.*]] = tail call <4 x float> @llvm.x86.sse.cvtpi2ps(<4 x float> [[A]], <1 x i64> [[B]])3619; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 83620; CHECK-NEXT: ret <4 x float> [[C]]3621;3622 %c = tail call <4 x float> @llvm.x86.sse.cvtpi2ps(<4 x float> %a, <1 x i64> %b)3623 ret <4 x float> %c3624}3625 3626declare <4 x float> @llvm.x86.sse.cvtpi2ps(<4 x float>, <1 x i64>) nounwind readnone3627 3628define void @test90() #0 {3629; ALL-LABEL: test90:3630; ALL: # %bb.0:3631; ALL-NEXT: emms3632; ALL-NEXT: ret{{[l|q]}}3633; CHECK-LABEL: define void @test90(3634; CHECK-SAME: ) #[[ATTR1]] {3635; CHECK-NEXT: call void @llvm.donothing()3636; CHECK-NEXT: call void @llvm.x86.mmx.emms()3637; CHECK-NEXT: ret void3638;3639 call void @llvm.x86.mmx.emms()3640 ret void3641}3642 3643declare void @llvm.x86.mmx.emms()3644 3645define <1 x i64> @test_mm_insert_pi16(<1 x i64> %a.coerce, i32 %d) nounwind #0 {3646; CHECK-LABEL: define <1 x i64> @test_mm_insert_pi16(3647; CHECK-SAME: <1 x i64> [[A_COERCE:%.*]], i32 [[D:%.*]]) #[[ATTR4]] {3648; CHECK-NEXT: entry:3649; CHECK-NEXT: [[TMP3:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 83650; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83651; CHECK-NEXT: call void @llvm.donothing()3652; CHECK-NEXT: [[TMP7:%.*]] = bitcast <1 x i64> [[TMP3]] to i643653; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP7]], 03654; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i32 [[TMP6]], 03655; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3656; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]3657; CHECK: 3:3658; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3659; CHECK-NEXT: unreachable3660; CHECK: 4:3661; CHECK-NEXT: [[TMP9:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pinsr.w(<1 x i64> [[A_COERCE]], i32 [[D]], i32 2)3662; CHECK-NEXT: store <1 x i64> zeroinitializer, ptr @__msan_retval_tls, align 83663; CHECK-NEXT: ret <1 x i64> [[TMP9]]3664;3665entry:3666 %1 = tail call <1 x i64> @llvm.x86.mmx.pinsr.w(<1 x i64> %a.coerce, i32 %d, i32 2)3667 ret <1 x i64> %13668}3669 3670declare <1 x i64> @llvm.x86.mmx.pinsr.w(<1 x i64>, i32, i32 immarg)3671 3672define i32 @test_mm_extract_pi16(<1 x i64> %a.coerce) nounwind #0 {3673; CHECK-LABEL: define i32 @test_mm_extract_pi16(3674; CHECK-SAME: <1 x i64> [[A_COERCE:%.*]]) #[[ATTR4]] {3675; CHECK-NEXT: entry:3676; CHECK-NEXT: [[TMP2:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 83677; CHECK-NEXT: call void @llvm.donothing()3678; CHECK-NEXT: [[TMP5:%.*]] = bitcast <1 x i64> [[TMP2]] to i643679; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP5]], 03680; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP4:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]3681; CHECK: 2:3682; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3683; CHECK-NEXT: unreachable3684; CHECK: 3:3685; CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.x86.mmx.pextr.w(<1 x i64> [[A_COERCE]], i32 2)3686; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 83687; CHECK-NEXT: ret i32 [[TMP1]]3688;3689entry:3690 %1 = tail call i32 @llvm.x86.mmx.pextr.w(<1 x i64> %a.coerce, i32 2)3691 ret i32 %13692}3693 3694declare i32 @llvm.x86.mmx.pextr.w(<1 x i64>, i32 immarg)3695 3696attributes #0 = { sanitize_memory }3697;.3698; CHECK: [[PROF1]] = !{!"branch_weights", i32 1, i32 1048575}3699;.3700