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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt %s -S -passes=msan 2>&1 | FileCheck %s3;4; Handled strictly:5; - i32 @llvm.x86.sse2.movmsk.pd(<2 x double> %a0)6; - i32 @llvm.x86.sse2.pmovmskb.128(<16 x i8> %a0)7; - void @llvm.x86.sse2.pause()8; - void @llvm.x86.sse2.lfence()9; - void @llvm.x86.sse2.mfence()10; - void @llvm.x86.sse2.clflush(ptr %p)11 12target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"13target triple = "x86_64-unknown-linux-gnu"14 15define <2 x double> @test_x86_sse2_cmp_pd(<2 x double> %a0, <2 x double> %a1) #0 {16; CHECK-LABEL: @test_x86_sse2_cmp_pd(17; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 818; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 819; CHECK-NEXT: call void @llvm.donothing()20; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]]21; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <2 x i64> [[TMP3]], zeroinitializer22; CHECK-NEXT: [[TMP5:%.*]] = sext <2 x i1> [[TMP4]] to <2 x i64>23; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.sse2.cmp.pd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]], i8 7)24; CHECK-NEXT: store <2 x i64> [[TMP5]], ptr @__msan_retval_tls, align 825; CHECK-NEXT: ret <2 x double> [[RES]]26;27 %res = call <2 x double> @llvm.x86.sse2.cmp.pd(<2 x double> %a0, <2 x double> %a1, i8 7) ; <<2 x double>> [#uses=1]28 ret <2 x double> %res29}30declare <2 x double> @llvm.x86.sse2.cmp.pd(<2 x double>, <2 x double>, i8) nounwind readnone31 32 33define <2 x double> @test_x86_sse2_cmp_sd(<2 x double> %a0, <2 x double> %a1) #0 {34; CHECK-LABEL: @test_x86_sse2_cmp_sd(35; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 836; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 837; CHECK-NEXT: call void @llvm.donothing()38; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]]39; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i64 040; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 041; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i12842; CHECK-NEXT: [[TMP7:%.*]] = bitcast i128 [[TMP6]] to <2 x i64>43; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]], i8 7)44; CHECK-NEXT: store <2 x i64> [[TMP7]], ptr @__msan_retval_tls, align 845; CHECK-NEXT: ret <2 x double> [[RES]]46;47 %res = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %a0, <2 x double> %a1, i8 7) ; <<2 x double>> [#uses=1]48 ret <2 x double> %res49}50declare <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double>, <2 x double>, i8) nounwind readnone51 52 53define i32 @test_x86_sse2_comieq_sd(<2 x double> %a0, <2 x double> %a1) #0 {54; CHECK-LABEL: @test_x86_sse2_comieq_sd(55; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 856; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 857; CHECK-NEXT: call void @llvm.donothing()58; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]]59; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i64 060; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 061; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i3262; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.comieq.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]])63; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 864; CHECK-NEXT: ret i32 [[RES]]65;66 %res = call i32 @llvm.x86.sse2.comieq.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]67 ret i32 %res68}69declare i32 @llvm.x86.sse2.comieq.sd(<2 x double>, <2 x double>) nounwind readnone70 71 72define i32 @test_x86_sse2_comige_sd(<2 x double> %a0, <2 x double> %a1) #0 {73; CHECK-LABEL: @test_x86_sse2_comige_sd(74; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 875; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 876; CHECK-NEXT: call void @llvm.donothing()77; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]]78; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i64 079; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 080; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i3281; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.comige.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]])82; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 883; CHECK-NEXT: ret i32 [[RES]]84;85 %res = call i32 @llvm.x86.sse2.comige.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]86 ret i32 %res87}88declare i32 @llvm.x86.sse2.comige.sd(<2 x double>, <2 x double>) nounwind readnone89 90 91define i32 @test_x86_sse2_comigt_sd(<2 x double> %a0, <2 x double> %a1) #0 {92; CHECK-LABEL: @test_x86_sse2_comigt_sd(93; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 894; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 895; CHECK-NEXT: call void @llvm.donothing()96; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]]97; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i64 098; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 099; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i32100; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.comigt.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]])101; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8102; CHECK-NEXT: ret i32 [[RES]]103;104 %res = call i32 @llvm.x86.sse2.comigt.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]105 ret i32 %res106}107declare i32 @llvm.x86.sse2.comigt.sd(<2 x double>, <2 x double>) nounwind readnone108 109 110define i32 @test_x86_sse2_comile_sd(<2 x double> %a0, <2 x double> %a1) #0 {111; CHECK-LABEL: @test_x86_sse2_comile_sd(112; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8113; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8114; CHECK-NEXT: call void @llvm.donothing()115; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]]116; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i64 0117; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 0118; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i32119; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.comile.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]])120; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8121; CHECK-NEXT: ret i32 [[RES]]122;123 %res = call i32 @llvm.x86.sse2.comile.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]124 ret i32 %res125}126declare i32 @llvm.x86.sse2.comile.sd(<2 x double>, <2 x double>) nounwind readnone127 128 129define i32 @test_x86_sse2_comilt_sd(<2 x double> %a0, <2 x double> %a1) #0 {130; CHECK-LABEL: @test_x86_sse2_comilt_sd(131; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8132; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8133; CHECK-NEXT: call void @llvm.donothing()134; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]]135; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i64 0136; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 0137; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i32138; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.comilt.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]])139; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8140; CHECK-NEXT: ret i32 [[RES]]141;142 %res = call i32 @llvm.x86.sse2.comilt.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]143 ret i32 %res144}145declare i32 @llvm.x86.sse2.comilt.sd(<2 x double>, <2 x double>) nounwind readnone146 147 148define i32 @test_x86_sse2_comineq_sd(<2 x double> %a0, <2 x double> %a1) #0 {149; CHECK-LABEL: @test_x86_sse2_comineq_sd(150; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8151; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8152; CHECK-NEXT: call void @llvm.donothing()153; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]]154; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i64 0155; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 0156; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i32157; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.comineq.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]])158; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8159; CHECK-NEXT: ret i32 [[RES]]160;161 %res = call i32 @llvm.x86.sse2.comineq.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]162 ret i32 %res163}164declare i32 @llvm.x86.sse2.comineq.sd(<2 x double>, <2 x double>) nounwind readnone165 166 167define <4 x i32> @test_x86_sse2_cvtpd2dq(<2 x double> %a0) #0 {168; CHECK-LABEL: @test_x86_sse2_cvtpd2dq(169; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8170; CHECK-NEXT: call void @llvm.donothing()171; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i64> [[TMP1]], zeroinitializer172; CHECK-NEXT: [[TMP3:%.*]] = sext <2 x i1> [[TMP2]] to <2 x i32>173; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i32> [[TMP3]], <2 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>174; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double> [[A0:%.*]])175; CHECK-NEXT: store <4 x i32> [[TMP4]], ptr @__msan_retval_tls, align 8176; CHECK-NEXT: ret <4 x i32> [[RES]]177;178 %res = call <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double> %a0) ; <<4 x i32>> [#uses=1]179 ret <4 x i32> %res180}181declare <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double>) nounwind readnone182 183 184define <2 x i64> @test_mm_cvtpd_epi32_zext(<2 x double> %a0) nounwind #0 {185; CHECK-LABEL: @test_mm_cvtpd_epi32_zext(186; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8187; CHECK-NEXT: call void @llvm.donothing()188; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i64> [[TMP1]], zeroinitializer189; CHECK-NEXT: [[TMP3:%.*]] = sext <2 x i1> [[TMP2]] to <2 x i32>190; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i32> [[TMP3]], <2 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>191; CHECK-NEXT: [[CVT:%.*]] = call <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double> [[A0:%.*]])192; CHECK-NEXT: [[RES:%.*]] = shufflevector <4 x i32> [[TMP4]], <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>193; CHECK-NEXT: [[RES1:%.*]] = shufflevector <4 x i32> [[CVT]], <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>194; CHECK-NEXT: [[BC:%.*]] = bitcast <4 x i32> [[RES]] to <2 x i64>195; CHECK-NEXT: [[BC1:%.*]] = bitcast <4 x i32> [[RES1]] to <2 x i64>196; CHECK-NEXT: store <2 x i64> [[BC]], ptr @__msan_retval_tls, align 8197; CHECK-NEXT: ret <2 x i64> [[BC1]]198;199 %cvt = call <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double> %a0)200 %res = shufflevector <4 x i32> %cvt, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>201 %bc = bitcast <4 x i32> %res to <2 x i64>202 ret <2 x i64> %bc203}204 205 206define <2 x i64> @test_mm_cvtpd_epi32_zext_load(ptr %p0) nounwind #0 {207; CHECK-LABEL: @test_mm_cvtpd_epi32_zext_load(208; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8209; CHECK-NEXT: call void @llvm.donothing()210; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0211; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1:![0-9]+]]212; CHECK: 2:213; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5:[0-9]+]]214; CHECK-NEXT: unreachable215; CHECK: 3:216; CHECK-NEXT: [[A0:%.*]] = load <2 x double>, ptr [[P0:%.*]], align 16217; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P0]] to i64218; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 87960930222080219; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr220; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP6]], align 16221; CHECK-NEXT: [[TMP7:%.*]] = icmp ne <2 x i64> [[_MSLD]], zeroinitializer222; CHECK-NEXT: [[TMP8:%.*]] = sext <2 x i1> [[TMP7]] to <2 x i32>223; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <2 x i32> [[TMP8]], <2 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>224; CHECK-NEXT: [[CVT:%.*]] = call <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double> [[A0]])225; CHECK-NEXT: [[RES:%.*]] = shufflevector <4 x i32> [[TMP9]], <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>226; CHECK-NEXT: [[RES1:%.*]] = shufflevector <4 x i32> [[CVT]], <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>227; CHECK-NEXT: [[BC:%.*]] = bitcast <4 x i32> [[RES]] to <2 x i64>228; CHECK-NEXT: [[BC1:%.*]] = bitcast <4 x i32> [[RES1]] to <2 x i64>229; CHECK-NEXT: store <2 x i64> [[BC]], ptr @__msan_retval_tls, align 8230; CHECK-NEXT: ret <2 x i64> [[BC1]]231;232 %a0 = load <2 x double>, ptr %p0233 %cvt = call <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double> %a0)234 %res = shufflevector <4 x i32> %cvt, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>235 %bc = bitcast <4 x i32> %res to <2 x i64>236 ret <2 x i64> %bc237}238 239 240define <4 x float> @test_x86_sse2_cvtpd2ps(<2 x double> %a0) #0 {241; CHECK-LABEL: @test_x86_sse2_cvtpd2ps(242; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8243; CHECK-NEXT: call void @llvm.donothing()244; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i64> [[TMP1]], zeroinitializer245; CHECK-NEXT: [[TMP3:%.*]] = sext <2 x i1> [[TMP2]] to <2 x i32>246; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i32> [[TMP3]], <2 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>247; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse2.cvtpd2ps(<2 x double> [[A0:%.*]])248; CHECK-NEXT: store <4 x i32> [[TMP4]], ptr @__msan_retval_tls, align 8249; CHECK-NEXT: ret <4 x float> [[RES]]250;251 %res = call <4 x float> @llvm.x86.sse2.cvtpd2ps(<2 x double> %a0) ; <<4 x float>> [#uses=1]252 ret <4 x float> %res253}254declare <4 x float> @llvm.x86.sse2.cvtpd2ps(<2 x double>) nounwind readnone255 256define <4 x float> @test_x86_sse2_cvtpd2ps_zext(<2 x double> %a0) nounwind #0 {257; CHECK-LABEL: @test_x86_sse2_cvtpd2ps_zext(258; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8259; CHECK-NEXT: call void @llvm.donothing()260; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i64> [[TMP1]], zeroinitializer261; CHECK-NEXT: [[TMP3:%.*]] = sext <2 x i1> [[TMP2]] to <2 x i32>262; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i32> [[TMP3]], <2 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>263; CHECK-NEXT: [[CVT:%.*]] = call <4 x float> @llvm.x86.sse2.cvtpd2ps(<2 x double> [[A0:%.*]])264; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i32> [[TMP4]], <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>265; CHECK-NEXT: [[RES:%.*]] = shufflevector <4 x float> [[CVT]], <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>266; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8267; CHECK-NEXT: ret <4 x float> [[RES]]268;269 %cvt = call <4 x float> @llvm.x86.sse2.cvtpd2ps(<2 x double> %a0)270 %res = shufflevector <4 x float> %cvt, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>271 ret <4 x float> %res272}273 274define <4 x float> @test_x86_sse2_cvtpd2ps_zext_load(ptr %p0) nounwind #0 {275; CHECK-LABEL: @test_x86_sse2_cvtpd2ps_zext_load(276; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8277; CHECK-NEXT: call void @llvm.donothing()278; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0279; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]280; CHECK: 2:281; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]282; CHECK-NEXT: unreachable283; CHECK: 3:284; CHECK-NEXT: [[A0:%.*]] = load <2 x double>, ptr [[P0:%.*]], align 16285; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P0]] to i64286; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 87960930222080287; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr288; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP6]], align 16289; CHECK-NEXT: [[TMP7:%.*]] = icmp ne <2 x i64> [[_MSLD]], zeroinitializer290; CHECK-NEXT: [[TMP8:%.*]] = sext <2 x i1> [[TMP7]] to <2 x i32>291; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <2 x i32> [[TMP8]], <2 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>292; CHECK-NEXT: [[CVT:%.*]] = call <4 x float> @llvm.x86.sse2.cvtpd2ps(<2 x double> [[A0]])293; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i32> [[TMP9]], <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>294; CHECK-NEXT: [[RES:%.*]] = shufflevector <4 x float> [[CVT]], <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>295; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8296; CHECK-NEXT: ret <4 x float> [[RES]]297;298 %a0 = load <2 x double>, ptr %p0299 %cvt = call <4 x float> @llvm.x86.sse2.cvtpd2ps(<2 x double> %a0)300 %res = shufflevector <4 x float> %cvt, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>301 ret <4 x float> %res302}303 304define <4 x i32> @test_x86_sse2_cvtps2dq(<4 x float> %a0) #0 {305; CHECK-LABEL: @test_x86_sse2_cvtps2dq(306; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8307; CHECK-NEXT: call void @llvm.donothing()308; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <4 x i32> [[TMP1]], zeroinitializer309; CHECK-NEXT: [[TMP3:%.*]] = sext <4 x i1> [[TMP2]] to <4 x i32>310; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.sse2.cvtps2dq(<4 x float> [[A0:%.*]])311; CHECK-NEXT: store <4 x i32> [[TMP3]], ptr @__msan_retval_tls, align 8312; CHECK-NEXT: ret <4 x i32> [[RES]]313;314 %res = call <4 x i32> @llvm.x86.sse2.cvtps2dq(<4 x float> %a0) ; <<4 x i32>> [#uses=1]315 ret <4 x i32> %res316}317declare <4 x i32> @llvm.x86.sse2.cvtps2dq(<4 x float>) nounwind readnone318 319 320define i32 @test_x86_sse2_cvtsd2si(<2 x double> %a0) #0 {321; CHECK-LABEL: @test_x86_sse2_cvtsd2si(322; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8323; CHECK-NEXT: call void @llvm.donothing()324; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i64> [[TMP1]], i32 0325; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0326; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]327; CHECK: 3:328; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]329; CHECK-NEXT: unreachable330; CHECK: 4:331; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.cvtsd2si(<2 x double> [[A0:%.*]])332; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8333; CHECK-NEXT: ret i32 [[RES]]334;335 %res = call i32 @llvm.x86.sse2.cvtsd2si(<2 x double> %a0) ; <i32> [#uses=1]336 ret i32 %res337}338declare i32 @llvm.x86.sse2.cvtsd2si(<2 x double>) nounwind readnone339 340 341define <4 x float> @test_x86_sse2_cvtsd2ss(<4 x float> %a0, <2 x double> %a1) #0 {342; CHECK-LABEL: @test_x86_sse2_cvtsd2ss(343; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8344; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8345; CHECK-NEXT: call void @llvm.donothing()346; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i64> [[TMP1]], i32 0347; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP2]], i32 0, i32 0348; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP3]], 0349; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]350; CHECK: 5:351; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]352; CHECK-NEXT: unreachable353; CHECK: 6:354; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float> [[A0:%.*]], <2 x double> [[A1:%.*]])355; CHECK-NEXT: store <4 x i32> [[TMP4]], ptr @__msan_retval_tls, align 8356; CHECK-NEXT: ret <4 x float> [[RES]]357;358 %res = call <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float> %a0, <2 x double> %a1) ; <<4 x float>> [#uses=1]359 ret <4 x float> %res360}361declare <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float>, <2 x double>) nounwind readnone362 363 364define <4 x float> @test_x86_sse2_cvtsd2ss_load(<4 x float> %a0, ptr %p1) #0 {365; CHECK-LABEL: @test_x86_sse2_cvtsd2ss_load(366; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8367; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8368; CHECK-NEXT: call void @llvm.donothing()369; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0370; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]371; CHECK: 3:372; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]373; CHECK-NEXT: unreachable374; CHECK: 4:375; CHECK-NEXT: [[A1:%.*]] = load <2 x double>, ptr [[P1:%.*]], align 16376; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[P1]] to i64377; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 87960930222080378; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr379; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP7]], align 16380; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i64> [[_MSLD]], i32 0381; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i32> [[TMP2]], i32 0, i32 0382; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP8]], 0383; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP10:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]384; CHECK: 10:385; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]386; CHECK-NEXT: unreachable387; CHECK: 11:388; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float> [[A0:%.*]], <2 x double> [[A1]])389; CHECK-NEXT: store <4 x i32> [[TMP9]], ptr @__msan_retval_tls, align 8390; CHECK-NEXT: ret <4 x float> [[RES]]391;392 %a1 = load <2 x double>, ptr %p1393 %res = call <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float> %a0, <2 x double> %a1) ; <<4 x float>> [#uses=1]394 ret <4 x float> %res395}396 397 398define <4 x float> @test_x86_sse2_cvtsd2ss_load_optsize(<4 x float> %a0, ptr %p1) optsize #0 {399; CHECK-LABEL: @test_x86_sse2_cvtsd2ss_load_optsize(400; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8401; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8402; CHECK-NEXT: call void @llvm.donothing()403; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0404; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]405; CHECK: 3:406; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]407; CHECK-NEXT: unreachable408; CHECK: 4:409; CHECK-NEXT: [[A1:%.*]] = load <2 x double>, ptr [[P1:%.*]], align 16410; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[P1]] to i64411; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 87960930222080412; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr413; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP7]], align 16414; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i64> [[_MSLD]], i32 0415; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i32> [[TMP2]], i32 0, i32 0416; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP8]], 0417; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP10:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]418; CHECK: 10:419; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]420; CHECK-NEXT: unreachable421; CHECK: 11:422; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float> [[A0:%.*]], <2 x double> [[A1]])423; CHECK-NEXT: store <4 x i32> [[TMP9]], ptr @__msan_retval_tls, align 8424; CHECK-NEXT: ret <4 x float> [[RES]]425;426 %a1 = load <2 x double>, ptr %p1427 %res = call <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float> %a0, <2 x double> %a1) ; <<4 x float>> [#uses=1]428 ret <4 x float> %res429}430 431 432define <4 x i32> @test_x86_sse2_cvttpd2dq(<2 x double> %a0) #0 {433; CHECK-LABEL: @test_x86_sse2_cvttpd2dq(434; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8435; CHECK-NEXT: call void @llvm.donothing()436; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i64> [[TMP1]], zeroinitializer437; CHECK-NEXT: [[TMP3:%.*]] = sext <2 x i1> [[TMP2]] to <2 x i32>438; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i32> [[TMP3]], <2 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>439; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double> [[A0:%.*]])440; CHECK-NEXT: store <4 x i32> [[TMP4]], ptr @__msan_retval_tls, align 8441; CHECK-NEXT: ret <4 x i32> [[RES]]442;443 %res = call <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double> %a0) ; <<4 x i32>> [#uses=1]444 ret <4 x i32> %res445}446declare <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double>) nounwind readnone447 448 449define <2 x i64> @test_mm_cvttpd_epi32_zext(<2 x double> %a0) nounwind #0 {450; CHECK-LABEL: @test_mm_cvttpd_epi32_zext(451; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8452; CHECK-NEXT: call void @llvm.donothing()453; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i64> [[TMP1]], zeroinitializer454; CHECK-NEXT: [[TMP3:%.*]] = sext <2 x i1> [[TMP2]] to <2 x i32>455; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i32> [[TMP3]], <2 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>456; CHECK-NEXT: [[CVT:%.*]] = call <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double> [[A0:%.*]])457; CHECK-NEXT: [[RES:%.*]] = shufflevector <4 x i32> [[TMP4]], <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>458; CHECK-NEXT: [[RES1:%.*]] = shufflevector <4 x i32> [[CVT]], <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>459; CHECK-NEXT: [[BC:%.*]] = bitcast <4 x i32> [[RES]] to <2 x i64>460; CHECK-NEXT: [[BC1:%.*]] = bitcast <4 x i32> [[RES1]] to <2 x i64>461; CHECK-NEXT: store <2 x i64> [[BC]], ptr @__msan_retval_tls, align 8462; CHECK-NEXT: ret <2 x i64> [[BC1]]463;464 %cvt = call <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double> %a0)465 %res = shufflevector <4 x i32> %cvt, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>466 %bc = bitcast <4 x i32> %res to <2 x i64>467 ret <2 x i64> %bc468}469 470 471define <2 x i64> @test_mm_cvttpd_epi32_zext_load(ptr %p0) nounwind #0 {472; CHECK-LABEL: @test_mm_cvttpd_epi32_zext_load(473; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8474; CHECK-NEXT: call void @llvm.donothing()475; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0476; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]477; CHECK: 2:478; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]479; CHECK-NEXT: unreachable480; CHECK: 3:481; CHECK-NEXT: [[A0:%.*]] = load <2 x double>, ptr [[P0:%.*]], align 16482; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P0]] to i64483; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 87960930222080484; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr485; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP6]], align 16486; CHECK-NEXT: [[TMP7:%.*]] = icmp ne <2 x i64> [[_MSLD]], zeroinitializer487; CHECK-NEXT: [[TMP8:%.*]] = sext <2 x i1> [[TMP7]] to <2 x i32>488; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <2 x i32> [[TMP8]], <2 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>489; CHECK-NEXT: [[CVT:%.*]] = call <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double> [[A0]])490; CHECK-NEXT: [[RES:%.*]] = shufflevector <4 x i32> [[TMP9]], <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>491; CHECK-NEXT: [[RES1:%.*]] = shufflevector <4 x i32> [[CVT]], <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>492; CHECK-NEXT: [[BC:%.*]] = bitcast <4 x i32> [[RES]] to <2 x i64>493; CHECK-NEXT: [[BC1:%.*]] = bitcast <4 x i32> [[RES1]] to <2 x i64>494; CHECK-NEXT: store <2 x i64> [[BC]], ptr @__msan_retval_tls, align 8495; CHECK-NEXT: ret <2 x i64> [[BC1]]496;497 %a0 = load <2 x double>, ptr %p0498 %cvt = call <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double> %a0)499 %res = shufflevector <4 x i32> %cvt, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>500 %bc = bitcast <4 x i32> %res to <2 x i64>501 ret <2 x i64> %bc502}503 504 505define <4 x i32> @test_x86_sse2_cvttps2dq(<4 x float> %a0) #0 {506; CHECK-LABEL: @test_x86_sse2_cvttps2dq(507; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8508; CHECK-NEXT: call void @llvm.donothing()509; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <4 x i32> [[TMP1]], zeroinitializer510; CHECK-NEXT: [[TMP3:%.*]] = sext <4 x i1> [[TMP2]] to <4 x i32>511; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> [[A0:%.*]])512; CHECK-NEXT: store <4 x i32> [[TMP3]], ptr @__msan_retval_tls, align 8513; CHECK-NEXT: ret <4 x i32> [[RES]]514;515 %res = call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> %a0) ; <<4 x i32>> [#uses=1]516 ret <4 x i32> %res517}518declare <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float>) nounwind readnone519 520 521define i32 @test_x86_sse2_cvttsd2si(<2 x double> %a0) #0 {522; CHECK-LABEL: @test_x86_sse2_cvttsd2si(523; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8524; CHECK-NEXT: call void @llvm.donothing()525; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i64> [[TMP1]], i32 0526; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0527; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]528; CHECK: 3:529; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]530; CHECK-NEXT: unreachable531; CHECK: 4:532; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.cvttsd2si(<2 x double> [[A0:%.*]])533; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8534; CHECK-NEXT: ret i32 [[RES]]535;536 %res = call i32 @llvm.x86.sse2.cvttsd2si(<2 x double> %a0) ; <i32> [#uses=1]537 ret i32 %res538}539declare i32 @llvm.x86.sse2.cvttsd2si(<2 x double>) nounwind readnone540 541 542define <2 x double> @test_x86_sse2_max_pd(<2 x double> %a0, <2 x double> %a1) #0 {543; CHECK-LABEL: @test_x86_sse2_max_pd(544; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8545; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8546; CHECK-NEXT: call void @llvm.donothing()547; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]]548; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.sse2.max.pd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]])549; CHECK-NEXT: store <2 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 8550; CHECK-NEXT: ret <2 x double> [[RES]]551;552 %res = call <2 x double> @llvm.x86.sse2.max.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]553 ret <2 x double> %res554}555declare <2 x double> @llvm.x86.sse2.max.pd(<2 x double>, <2 x double>) nounwind readnone556 557 558define <2 x double> @test_x86_sse2_max_sd(<2 x double> %a0, <2 x double> %a1) #0 {559; CHECK-LABEL: @test_x86_sse2_max_sd(560; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8561; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8562; CHECK-NEXT: call void @llvm.donothing()563; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]]564; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> [[TMP3]], <2 x i32> <i32 2, i32 1>565; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.sse2.max.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]])566; CHECK-NEXT: store <2 x i64> [[TMP4]], ptr @__msan_retval_tls, align 8567; CHECK-NEXT: ret <2 x double> [[RES]]568;569 %res = call <2 x double> @llvm.x86.sse2.max.sd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]570 ret <2 x double> %res571}572declare <2 x double> @llvm.x86.sse2.max.sd(<2 x double>, <2 x double>) nounwind readnone573 574 575define <2 x double> @test_x86_sse2_min_pd(<2 x double> %a0, <2 x double> %a1) #0 {576; CHECK-LABEL: @test_x86_sse2_min_pd(577; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8578; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8579; CHECK-NEXT: call void @llvm.donothing()580; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]]581; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.sse2.min.pd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]])582; CHECK-NEXT: store <2 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 8583; CHECK-NEXT: ret <2 x double> [[RES]]584;585 %res = call <2 x double> @llvm.x86.sse2.min.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]586 ret <2 x double> %res587}588declare <2 x double> @llvm.x86.sse2.min.pd(<2 x double>, <2 x double>) nounwind readnone589 590 591define <2 x double> @test_x86_sse2_min_sd(<2 x double> %a0, <2 x double> %a1) #0 {592; CHECK-LABEL: @test_x86_sse2_min_sd(593; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8594; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8595; CHECK-NEXT: call void @llvm.donothing()596; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]]597; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> [[TMP3]], <2 x i32> <i32 2, i32 1>598; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.sse2.min.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]])599; CHECK-NEXT: store <2 x i64> [[TMP4]], ptr @__msan_retval_tls, align 8600; CHECK-NEXT: ret <2 x double> [[RES]]601;602 %res = call <2 x double> @llvm.x86.sse2.min.sd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]603 ret <2 x double> %res604}605declare <2 x double> @llvm.x86.sse2.min.sd(<2 x double>, <2 x double>) nounwind readnone606 607 608define i32 @test_x86_sse2_movmsk_pd(<2 x double> %a0) #0 {609; CHECK-LABEL: @test_x86_sse2_movmsk_pd(610; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8611; CHECK-NEXT: call void @llvm.donothing()612; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to i128613; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 0614; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]615; CHECK: 3:616; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]617; CHECK-NEXT: unreachable618; CHECK: 4:619; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.movmsk.pd(<2 x double> [[A0:%.*]])620; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8621; CHECK-NEXT: ret i32 [[RES]]622;623 %res = call i32 @llvm.x86.sse2.movmsk.pd(<2 x double> %a0) ; <i32> [#uses=1]624 ret i32 %res625}626declare i32 @llvm.x86.sse2.movmsk.pd(<2 x double>) nounwind readnone627 628 629define <8 x i16> @test_x86_sse2_packssdw_128(<4 x i32> %a0, <4 x i32> %a1) #0 {630; CHECK-LABEL: @test_x86_sse2_packssdw_128(631; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8632; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8633; CHECK-NEXT: call void @llvm.donothing()634; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <4 x i32> [[TMP1]], zeroinitializer635; CHECK-NEXT: [[TMP4:%.*]] = sext <4 x i1> [[TMP3]] to <4 x i32>636; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <4 x i32> [[TMP2]], zeroinitializer637; CHECK-NEXT: [[TMP6:%.*]] = sext <4 x i1> [[TMP5]] to <4 x i32>638; CHECK-NEXT: [[_MSPROP_VECTOR_PACK:%.*]] = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> [[TMP4]], <4 x i32> [[TMP6]])639; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> [[A0:%.*]], <4 x i32> [[A1:%.*]])640; CHECK-NEXT: store <8 x i16> [[_MSPROP_VECTOR_PACK]], ptr @__msan_retval_tls, align 8641; CHECK-NEXT: ret <8 x i16> [[RES]]642;643 %res = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> %a0, <4 x i32> %a1) ; <<8 x i16>> [#uses=1]644 ret <8 x i16> %res645}646declare <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32>, <4 x i32>) nounwind readnone647 648 649define <8 x i16> @test_x86_sse2_packssdw_128_fold() #0 {650; CHECK-LABEL: @test_x86_sse2_packssdw_128_fold(651; CHECK-NEXT: call void @llvm.donothing()652; CHECK-NEXT: [[_MSPROP_VECTOR_PACK:%.*]] = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> zeroinitializer, <4 x i32> zeroinitializer)653; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> zeroinitializer, <4 x i32> <i32 65535, i32 65536, i32 -1, i32 -131072>)654; CHECK-NEXT: store <8 x i16> [[_MSPROP_VECTOR_PACK]], ptr @__msan_retval_tls, align 8655; CHECK-NEXT: ret <8 x i16> [[RES]]656;657 %res = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> zeroinitializer, <4 x i32> <i32 65535, i32 65536, i32 -1, i32 -131072>)658 ret <8 x i16> %res659}660 661 662define <16 x i8> @test_x86_sse2_packsswb_128(<8 x i16> %a0, <8 x i16> %a1) #0 {663; CHECK-LABEL: @test_x86_sse2_packsswb_128(664; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8665; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8666; CHECK-NEXT: call void @llvm.donothing()667; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <8 x i16> [[TMP1]], zeroinitializer668; CHECK-NEXT: [[TMP4:%.*]] = sext <8 x i1> [[TMP3]] to <8 x i16>669; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <8 x i16> [[TMP2]], zeroinitializer670; CHECK-NEXT: [[TMP6:%.*]] = sext <8 x i1> [[TMP5]] to <8 x i16>671; CHECK-NEXT: [[_MSPROP_VECTOR_PACK:%.*]] = call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> [[TMP4]], <8 x i16> [[TMP6]])672; CHECK-NEXT: [[RES:%.*]] = call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> [[A0:%.*]], <8 x i16> [[A1:%.*]])673; CHECK-NEXT: store <16 x i8> [[_MSPROP_VECTOR_PACK]], ptr @__msan_retval_tls, align 8674; CHECK-NEXT: ret <16 x i8> [[RES]]675;676 %res = call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> %a0, <8 x i16> %a1) ; <<16 x i8>> [#uses=1]677 ret <16 x i8> %res678}679declare <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16>, <8 x i16>) nounwind readnone680 681 682define <16 x i8> @test_x86_sse2_packsswb_128_fold() #0 {683; CHECK-LABEL: @test_x86_sse2_packsswb_128_fold(684; CHECK-NEXT: call void @llvm.donothing()685; CHECK-NEXT: [[_MSPROP_VECTOR_PACK:%.*]] = call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> zeroinitializer, <8 x i16> zeroinitializer)686; CHECK-NEXT: [[RES:%.*]] = call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> <i16 0, i16 255, i16 256, i16 -1, i16 -1, i16 -255, i16 -256, i16 -32678>, <8 x i16> zeroinitializer)687; CHECK-NEXT: store <16 x i8> [[_MSPROP_VECTOR_PACK]], ptr @__msan_retval_tls, align 8688; CHECK-NEXT: ret <16 x i8> [[RES]]689;690 %res = call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> <i16 0, i16 255, i16 256, i16 65535, i16 -1, i16 -255, i16 -256, i16 -32678>, <8 x i16> zeroinitializer)691 ret <16 x i8> %res692}693 694 695define <16 x i8> @test_x86_sse2_packuswb_128(<8 x i16> %a0, <8 x i16> %a1) #0 {696; CHECK-LABEL: @test_x86_sse2_packuswb_128(697; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8698; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8699; CHECK-NEXT: call void @llvm.donothing()700; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <8 x i16> [[TMP1]], zeroinitializer701; CHECK-NEXT: [[TMP4:%.*]] = sext <8 x i1> [[TMP3]] to <8 x i16>702; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <8 x i16> [[TMP2]], zeroinitializer703; CHECK-NEXT: [[TMP6:%.*]] = sext <8 x i1> [[TMP5]] to <8 x i16>704; CHECK-NEXT: [[_MSPROP_VECTOR_PACK:%.*]] = call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> [[TMP4]], <8 x i16> [[TMP6]])705; CHECK-NEXT: [[RES:%.*]] = call <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16> [[A0:%.*]], <8 x i16> [[A1:%.*]])706; CHECK-NEXT: store <16 x i8> [[_MSPROP_VECTOR_PACK]], ptr @__msan_retval_tls, align 8707; CHECK-NEXT: ret <16 x i8> [[RES]]708;709 %res = call <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16> %a0, <8 x i16> %a1) ; <<16 x i8>> [#uses=1]710 ret <16 x i8> %res711}712declare <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16>, <8 x i16>) nounwind readnone713 714 715define <16 x i8> @test_x86_sse2_packuswb_128_fold() #0 {716; CHECK-LABEL: @test_x86_sse2_packuswb_128_fold(717; CHECK-NEXT: call void @llvm.donothing()718; CHECK-NEXT: [[_MSPROP_VECTOR_PACK:%.*]] = call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> zeroinitializer, <8 x i16> zeroinitializer)719; CHECK-NEXT: [[RES:%.*]] = call <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16> <i16 0, i16 255, i16 256, i16 -1, i16 -1, i16 -255, i16 -256, i16 -32678>, <8 x i16> zeroinitializer)720; CHECK-NEXT: store <16 x i8> [[_MSPROP_VECTOR_PACK]], ptr @__msan_retval_tls, align 8721; CHECK-NEXT: ret <16 x i8> [[RES]]722;723 %res = call <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16> <i16 0, i16 255, i16 256, i16 65535, i16 -1, i16 -255, i16 -256, i16 -32678>, <8 x i16> zeroinitializer)724 ret <16 x i8> %res725}726 727 728define <16 x i8> @test_x86_sse2_pavg_b(<16 x i8> %a0, <16 x i8> %a1) #0 {729; CHECK-LABEL: @test_x86_sse2_pavg_b(730; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @__msan_param_tls, align 8731; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8732; CHECK-NEXT: call void @llvm.donothing()733; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i8> [[TMP1]], [[TMP2]]734; CHECK-NEXT: [[RES:%.*]] = call <16 x i8> @llvm.x86.sse2.pavg.b(<16 x i8> [[A0:%.*]], <16 x i8> [[A1:%.*]])735; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 8736; CHECK-NEXT: ret <16 x i8> [[RES]]737;738 %res = call <16 x i8> @llvm.x86.sse2.pavg.b(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1]739 ret <16 x i8> %res740}741declare <16 x i8> @llvm.x86.sse2.pavg.b(<16 x i8>, <16 x i8>) nounwind readnone742 743 744define <8 x i16> @test_x86_sse2_pavg_w(<8 x i16> %a0, <8 x i16> %a1) #0 {745; CHECK-LABEL: @test_x86_sse2_pavg_w(746; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8747; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8748; CHECK-NEXT: call void @llvm.donothing()749; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP1]], [[TMP2]]750; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.x86.sse2.pavg.w(<8 x i16> [[A0:%.*]], <8 x i16> [[A1:%.*]])751; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8752; CHECK-NEXT: ret <8 x i16> [[RES]]753;754 %res = call <8 x i16> @llvm.x86.sse2.pavg.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]755 ret <8 x i16> %res756}757declare <8 x i16> @llvm.x86.sse2.pavg.w(<8 x i16>, <8 x i16>) nounwind readnone758 759 760define <4 x i32> @test_x86_sse2_pmadd_wd(<8 x i16> %a0, <8 x i16> %a1) #0 {761; CHECK-LABEL: @test_x86_sse2_pmadd_wd(762; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8763; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8764; CHECK-NEXT: call void @llvm.donothing()765; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <8 x i16> [[TMP1]], zeroinitializer766; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <8 x i16> [[TMP2]], zeroinitializer767; CHECK-NEXT: [[TMP12:%.*]] = icmp ne <8 x i16> [[A0:%.*]], zeroinitializer768; CHECK-NEXT: [[TMP13:%.*]] = icmp ne <8 x i16> [[A1:%.*]], zeroinitializer769; CHECK-NEXT: [[TMP11:%.*]] = and <8 x i1> [[TMP4]], [[TMP5]]770; CHECK-NEXT: [[TMP14:%.*]] = and <8 x i1> [[TMP12]], [[TMP5]]771; CHECK-NEXT: [[TMP15:%.*]] = and <8 x i1> [[TMP4]], [[TMP13]]772; CHECK-NEXT: [[TMP16:%.*]] = or <8 x i1> [[TMP11]], [[TMP14]]773; CHECK-NEXT: [[TMP17:%.*]] = or <8 x i1> [[TMP16]], [[TMP15]]774; CHECK-NEXT: [[TMP7:%.*]] = sext <8 x i1> [[TMP17]] to <8 x i16>775; CHECK-NEXT: [[TMP18:%.*]] = bitcast <8 x i16> [[TMP7]] to <4 x i32>776; CHECK-NEXT: [[TMP19:%.*]] = icmp ne <4 x i32> [[TMP18]], zeroinitializer777; CHECK-NEXT: [[TMP6:%.*]] = sext <4 x i1> [[TMP19]] to <4 x i32>778; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16> [[A0]], <8 x i16> [[A1]])779; CHECK-NEXT: store <4 x i32> [[TMP6]], ptr @__msan_retval_tls, align 8780; CHECK-NEXT: ret <4 x i32> [[RES]]781;782 %res = call <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16> %a0, <8 x i16> %a1) ; <<4 x i32>> [#uses=1]783 ret <4 x i32> %res784}785declare <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16>, <8 x i16>) nounwind readnone786 787 788define i32 @test_x86_sse2_pmovmskb_128(<16 x i8> %a0) #0 {789; CHECK-LABEL: @test_x86_sse2_pmovmskb_128(790; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @__msan_param_tls, align 8791; CHECK-NEXT: call void @llvm.donothing()792; CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to i128793; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 0794; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]795; CHECK: 3:796; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]797; CHECK-NEXT: unreachable798; CHECK: 4:799; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.pmovmskb.128(<16 x i8> [[A0:%.*]])800; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8801; CHECK-NEXT: ret i32 [[RES]]802;803 %res = call i32 @llvm.x86.sse2.pmovmskb.128(<16 x i8> %a0) ; <i32> [#uses=1]804 ret i32 %res805}806declare i32 @llvm.x86.sse2.pmovmskb.128(<16 x i8>) nounwind readnone807 808 809define <8 x i16> @test_x86_sse2_pmulh_w(<8 x i16> %a0, <8 x i16> %a1) #0 {810; CHECK-LABEL: @test_x86_sse2_pmulh_w(811; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8812; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8813; CHECK-NEXT: call void @llvm.donothing()814; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP1]], [[TMP2]]815; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16> [[A0:%.*]], <8 x i16> [[A1:%.*]])816; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8817; CHECK-NEXT: ret <8 x i16> [[RES]]818;819 %res = call <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]820 ret <8 x i16> %res821}822declare <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16>, <8 x i16>) nounwind readnone823 824 825define <8 x i16> @test_x86_sse2_pmulhu_w(<8 x i16> %a0, <8 x i16> %a1) #0 {826; CHECK-LABEL: @test_x86_sse2_pmulhu_w(827; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8828; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8829; CHECK-NEXT: call void @llvm.donothing()830; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP1]], [[TMP2]]831; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16> [[A0:%.*]], <8 x i16> [[A1:%.*]])832; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8833; CHECK-NEXT: ret <8 x i16> [[RES]]834;835 %res = call <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]836 ret <8 x i16> %res837}838declare <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16>, <8 x i16>) nounwind readnone839 840 841define <2 x i64> @test_x86_sse2_psad_bw(<16 x i8> %a0, <16 x i8> %a1) #0 {842; CHECK-LABEL: @test_x86_sse2_psad_bw(843; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @__msan_param_tls, align 8844; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8845; CHECK-NEXT: call void @llvm.donothing()846; CHECK-NEXT: [[TMP3:%.*]] = or <16 x i8> [[TMP1]], [[TMP2]]847; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP3]] to <2 x i64>848; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <2 x i64> [[TMP4]], zeroinitializer849; CHECK-NEXT: [[TMP6:%.*]] = sext <2 x i1> [[TMP5]] to <2 x i64>850; CHECK-NEXT: [[TMP7:%.*]] = lshr <2 x i64> [[TMP6]], splat (i64 48)851; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8> [[A0:%.*]], <16 x i8> [[A1:%.*]])852; CHECK-NEXT: store <2 x i64> [[TMP7]], ptr @__msan_retval_tls, align 8853; CHECK-NEXT: ret <2 x i64> [[RES]]854;855 %res = call <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8> %a0, <16 x i8> %a1) ; <<2 x i64>> [#uses=1]856 ret <2 x i64> %res857}858declare <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8>, <16 x i8>) nounwind readnone859 860 861define <4 x i32> @test_x86_sse2_psll_d(<4 x i32> %a0, <4 x i32> %a1) #0 {862; CHECK-LABEL: @test_x86_sse2_psll_d(863; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8864; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8865; CHECK-NEXT: call void @llvm.donothing()866; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP2]] to i128867; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i64868; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 0869; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i128870; CHECK-NEXT: [[TMP7:%.*]] = bitcast i128 [[TMP6]] to <4 x i32>871; CHECK-NEXT: [[TMP8:%.*]] = call <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32> [[TMP1]], <4 x i32> [[A1:%.*]])872; CHECK-NEXT: [[TMP9:%.*]] = or <4 x i32> [[TMP8]], [[TMP7]]873; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32> [[A0:%.*]], <4 x i32> [[A1]])874; CHECK-NEXT: store <4 x i32> [[TMP9]], ptr @__msan_retval_tls, align 8875; CHECK-NEXT: ret <4 x i32> [[RES]]876;877 %res = call <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]878 ret <4 x i32> %res879}880declare <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32>, <4 x i32>) nounwind readnone881 882 883define <2 x i64> @test_x86_sse2_psll_q(<2 x i64> %a0, <2 x i64> %a1) #0 {884; CHECK-LABEL: @test_x86_sse2_psll_q(885; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8886; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8887; CHECK-NEXT: call void @llvm.donothing()888; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP2]] to i128889; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i64890; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 0891; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i128892; CHECK-NEXT: [[TMP7:%.*]] = bitcast i128 [[TMP6]] to <2 x i64>893; CHECK-NEXT: [[TMP8:%.*]] = call <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64> [[TMP1]], <2 x i64> [[A1:%.*]])894; CHECK-NEXT: [[TMP9:%.*]] = or <2 x i64> [[TMP8]], [[TMP7]]895; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64> [[A0:%.*]], <2 x i64> [[A1]])896; CHECK-NEXT: store <2 x i64> [[TMP9]], ptr @__msan_retval_tls, align 8897; CHECK-NEXT: ret <2 x i64> [[RES]]898;899 %res = call <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1]900 ret <2 x i64> %res901}902declare <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64>, <2 x i64>) nounwind readnone903 904 905define <8 x i16> @test_x86_sse2_psll_w(<8 x i16> %a0, <8 x i16> %a1) #0 {906; CHECK-LABEL: @test_x86_sse2_psll_w(907; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8908; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8909; CHECK-NEXT: call void @llvm.donothing()910; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP2]] to i128911; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i64912; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 0913; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i128914; CHECK-NEXT: [[TMP7:%.*]] = bitcast i128 [[TMP6]] to <8 x i16>915; CHECK-NEXT: [[TMP8:%.*]] = call <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16> [[TMP1]], <8 x i16> [[A1:%.*]])916; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i16> [[TMP8]], [[TMP7]]917; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16> [[A0:%.*]], <8 x i16> [[A1]])918; CHECK-NEXT: store <8 x i16> [[TMP9]], ptr @__msan_retval_tls, align 8919; CHECK-NEXT: ret <8 x i16> [[RES]]920;921 %res = call <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]922 ret <8 x i16> %res923}924declare <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16>, <8 x i16>) nounwind readnone925 926 927define <4 x i32> @test_x86_sse2_pslli_d(<4 x i32> %a0) #0 {928; CHECK-LABEL: @test_x86_sse2_pslli_d(929; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8930; CHECK-NEXT: call void @llvm.donothing()931; CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> [[TMP1]], i32 7)932; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP2]], zeroinitializer933; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> [[A0:%.*]], i32 7)934; CHECK-NEXT: store <4 x i32> [[TMP3]], ptr @__msan_retval_tls, align 8935; CHECK-NEXT: ret <4 x i32> [[RES]]936;937 %res = call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> %a0, i32 7) ; <<4 x i32>> [#uses=1]938 ret <4 x i32> %res939}940declare <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32>, i32) nounwind readnone941 942 943define <2 x i64> @test_x86_sse2_pslli_q(<2 x i64> %a0) #0 {944; CHECK-LABEL: @test_x86_sse2_pslli_q(945; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8946; CHECK-NEXT: call void @llvm.donothing()947; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64> [[TMP1]], i32 7)948; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP2]], zeroinitializer949; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64> [[A0:%.*]], i32 7)950; CHECK-NEXT: store <2 x i64> [[TMP3]], ptr @__msan_retval_tls, align 8951; CHECK-NEXT: ret <2 x i64> [[RES]]952;953 %res = call <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64> %a0, i32 7) ; <<2 x i64>> [#uses=1]954 ret <2 x i64> %res955}956declare <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64>, i32) nounwind readnone957 958 959define <8 x i16> @test_x86_sse2_pslli_w(<8 x i16> %a0) #0 {960; CHECK-LABEL: @test_x86_sse2_pslli_w(961; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8962; CHECK-NEXT: call void @llvm.donothing()963; CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16> [[TMP1]], i32 7)964; CHECK-NEXT: [[TMP3:%.*]] = or <8 x i16> [[TMP2]], zeroinitializer965; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16> [[A0:%.*]], i32 7)966; CHECK-NEXT: store <8 x i16> [[TMP3]], ptr @__msan_retval_tls, align 8967; CHECK-NEXT: ret <8 x i16> [[RES]]968;969 %res = call <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16> %a0, i32 7) ; <<8 x i16>> [#uses=1]970 ret <8 x i16> %res971}972declare <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16>, i32) nounwind readnone973 974 975define <4 x i32> @test_x86_sse2_psra_d(<4 x i32> %a0, <4 x i32> %a1) #0 {976; CHECK-LABEL: @test_x86_sse2_psra_d(977; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8978; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8979; CHECK-NEXT: call void @llvm.donothing()980; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP2]] to i128981; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i64982; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 0983; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i128984; CHECK-NEXT: [[TMP7:%.*]] = bitcast i128 [[TMP6]] to <4 x i32>985; CHECK-NEXT: [[TMP8:%.*]] = call <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32> [[TMP1]], <4 x i32> [[A1:%.*]])986; CHECK-NEXT: [[TMP9:%.*]] = or <4 x i32> [[TMP8]], [[TMP7]]987; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32> [[A0:%.*]], <4 x i32> [[A1]])988; CHECK-NEXT: store <4 x i32> [[TMP9]], ptr @__msan_retval_tls, align 8989; CHECK-NEXT: ret <4 x i32> [[RES]]990;991 %res = call <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]992 ret <4 x i32> %res993}994declare <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32>, <4 x i32>) nounwind readnone995 996 997define <8 x i16> @test_x86_sse2_psra_w(<8 x i16> %a0, <8 x i16> %a1) #0 {998; CHECK-LABEL: @test_x86_sse2_psra_w(999; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81000; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81001; CHECK-NEXT: call void @llvm.donothing()1002; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP2]] to i1281003; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i641004; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 01005; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i1281006; CHECK-NEXT: [[TMP7:%.*]] = bitcast i128 [[TMP6]] to <8 x i16>1007; CHECK-NEXT: [[TMP8:%.*]] = call <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16> [[TMP1]], <8 x i16> [[A1:%.*]])1008; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i16> [[TMP8]], [[TMP7]]1009; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16> [[A0:%.*]], <8 x i16> [[A1]])1010; CHECK-NEXT: store <8 x i16> [[TMP9]], ptr @__msan_retval_tls, align 81011; CHECK-NEXT: ret <8 x i16> [[RES]]1012;1013 %res = call <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]1014 ret <8 x i16> %res1015}1016declare <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16>, <8 x i16>) nounwind readnone1017 1018 1019define <4 x i32> @test_x86_sse2_psrai_d(<4 x i32> %a0) #0 {1020; CHECK-LABEL: @test_x86_sse2_psrai_d(1021; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 81022; CHECK-NEXT: call void @llvm.donothing()1023; CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> [[TMP1]], i32 7)1024; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP2]], zeroinitializer1025; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> [[A0:%.*]], i32 7)1026; CHECK-NEXT: store <4 x i32> [[TMP3]], ptr @__msan_retval_tls, align 81027; CHECK-NEXT: ret <4 x i32> [[RES]]1028;1029 %res = call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> %a0, i32 7) ; <<4 x i32>> [#uses=1]1030 ret <4 x i32> %res1031}1032declare <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32>, i32) nounwind readnone1033 1034 1035define <8 x i16> @test_x86_sse2_psrai_w(<8 x i16> %a0) #0 {1036; CHECK-LABEL: @test_x86_sse2_psrai_w(1037; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81038; CHECK-NEXT: call void @llvm.donothing()1039; CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> [[TMP1]], i32 7)1040; CHECK-NEXT: [[TMP3:%.*]] = or <8 x i16> [[TMP2]], zeroinitializer1041; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> [[A0:%.*]], i32 7)1042; CHECK-NEXT: store <8 x i16> [[TMP3]], ptr @__msan_retval_tls, align 81043; CHECK-NEXT: ret <8 x i16> [[RES]]1044;1045 %res = call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> %a0, i32 7) ; <<8 x i16>> [#uses=1]1046 ret <8 x i16> %res1047}1048declare <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16>, i32) nounwind readnone1049 1050 1051define <4 x i32> @test_x86_sse2_psrl_d(<4 x i32> %a0, <4 x i32> %a1) #0 {1052; CHECK-LABEL: @test_x86_sse2_psrl_d(1053; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 81054; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81055; CHECK-NEXT: call void @llvm.donothing()1056; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP2]] to i1281057; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i641058; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 01059; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i1281060; CHECK-NEXT: [[TMP7:%.*]] = bitcast i128 [[TMP6]] to <4 x i32>1061; CHECK-NEXT: [[TMP8:%.*]] = call <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32> [[TMP1]], <4 x i32> [[A1:%.*]])1062; CHECK-NEXT: [[TMP9:%.*]] = or <4 x i32> [[TMP8]], [[TMP7]]1063; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32> [[A0:%.*]], <4 x i32> [[A1]])1064; CHECK-NEXT: store <4 x i32> [[TMP9]], ptr @__msan_retval_tls, align 81065; CHECK-NEXT: ret <4 x i32> [[RES]]1066;1067 %res = call <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]1068 ret <4 x i32> %res1069}1070declare <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32>, <4 x i32>) nounwind readnone1071 1072 1073define <2 x i64> @test_x86_sse2_psrl_q(<2 x i64> %a0, <2 x i64> %a1) #0 {1074; CHECK-LABEL: @test_x86_sse2_psrl_q(1075; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 81076; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81077; CHECK-NEXT: call void @llvm.donothing()1078; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP2]] to i1281079; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i641080; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 01081; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i1281082; CHECK-NEXT: [[TMP7:%.*]] = bitcast i128 [[TMP6]] to <2 x i64>1083; CHECK-NEXT: [[TMP8:%.*]] = call <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64> [[TMP1]], <2 x i64> [[A1:%.*]])1084; CHECK-NEXT: [[TMP9:%.*]] = or <2 x i64> [[TMP8]], [[TMP7]]1085; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64> [[A0:%.*]], <2 x i64> [[A1]])1086; CHECK-NEXT: store <2 x i64> [[TMP9]], ptr @__msan_retval_tls, align 81087; CHECK-NEXT: ret <2 x i64> [[RES]]1088;1089 %res = call <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1]1090 ret <2 x i64> %res1091}1092declare <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64>, <2 x i64>) nounwind readnone1093 1094 1095define <8 x i16> @test_x86_sse2_psrl_w(<8 x i16> %a0, <8 x i16> %a1) #0 {1096; CHECK-LABEL: @test_x86_sse2_psrl_w(1097; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81098; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81099; CHECK-NEXT: call void @llvm.donothing()1100; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP2]] to i1281101; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i641102; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 01103; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i1281104; CHECK-NEXT: [[TMP7:%.*]] = bitcast i128 [[TMP6]] to <8 x i16>1105; CHECK-NEXT: [[TMP8:%.*]] = call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> [[TMP1]], <8 x i16> [[A1:%.*]])1106; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i16> [[TMP8]], [[TMP7]]1107; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> [[A0:%.*]], <8 x i16> [[A1]])1108; CHECK-NEXT: store <8 x i16> [[TMP9]], ptr @__msan_retval_tls, align 81109; CHECK-NEXT: ret <8 x i16> [[RES]]1110;1111 %res = call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]1112 ret <8 x i16> %res1113}1114declare <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16>, <8 x i16>) nounwind readnone1115 1116 1117define <8 x i16> @test_x86_sse2_psrl_w_load(<8 x i16> %a0, ptr %p) #0 {1118; CHECK-LABEL: @test_x86_sse2_psrl_w_load(1119; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81120; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81121; CHECK-NEXT: call void @llvm.donothing()1122; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01123; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]1124; CHECK: 3:1125; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1126; CHECK-NEXT: unreachable1127; CHECK: 4:1128; CHECK-NEXT: [[A1:%.*]] = load <8 x i16>, ptr [[P:%.*]], align 161129; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[P]] to i641130; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 879609302220801131; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1132; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP7]], align 161133; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i16> [[_MSLD]] to i1281134; CHECK-NEXT: [[TMP9:%.*]] = trunc i128 [[TMP8]] to i641135; CHECK-NEXT: [[TMP10:%.*]] = icmp ne i64 [[TMP9]], 01136; CHECK-NEXT: [[TMP11:%.*]] = sext i1 [[TMP10]] to i1281137; CHECK-NEXT: [[TMP12:%.*]] = bitcast i128 [[TMP11]] to <8 x i16>1138; CHECK-NEXT: [[TMP13:%.*]] = call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> [[TMP2]], <8 x i16> [[A1]])1139; CHECK-NEXT: [[TMP14:%.*]] = or <8 x i16> [[TMP13]], [[TMP12]]1140; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> [[A0:%.*]], <8 x i16> [[A1]])1141; CHECK-NEXT: store <8 x i16> [[TMP14]], ptr @__msan_retval_tls, align 81142; CHECK-NEXT: ret <8 x i16> [[RES]]1143;1144 %a1 = load <8 x i16>, ptr %p1145 %res = call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]1146 ret <8 x i16> %res1147}1148 1149 1150define <4 x i32> @test_x86_sse2_psrli_d(<4 x i32> %a0) #0 {1151; CHECK-LABEL: @test_x86_sse2_psrli_d(1152; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 81153; CHECK-NEXT: call void @llvm.donothing()1154; CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> [[TMP1]], i32 7)1155; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP2]], zeroinitializer1156; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> [[A0:%.*]], i32 7)1157; CHECK-NEXT: store <4 x i32> [[TMP3]], ptr @__msan_retval_tls, align 81158; CHECK-NEXT: ret <4 x i32> [[RES]]1159;1160 %res = call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> %a0, i32 7) ; <<4 x i32>> [#uses=1]1161 ret <4 x i32> %res1162}1163declare <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32>, i32) nounwind readnone1164 1165 1166define <2 x i64> @test_x86_sse2_psrli_q(<2 x i64> %a0) #0 {1167; CHECK-LABEL: @test_x86_sse2_psrli_q(1168; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 81169; CHECK-NEXT: call void @llvm.donothing()1170; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64> [[TMP1]], i32 7)1171; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP2]], zeroinitializer1172; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64> [[A0:%.*]], i32 7)1173; CHECK-NEXT: store <2 x i64> [[TMP3]], ptr @__msan_retval_tls, align 81174; CHECK-NEXT: ret <2 x i64> [[RES]]1175;1176 %res = call <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64> %a0, i32 7) ; <<2 x i64>> [#uses=1]1177 ret <2 x i64> %res1178}1179declare <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64>, i32) nounwind readnone1180 1181 1182define <8 x i16> @test_x86_sse2_psrli_w(<8 x i16> %a0) #0 {1183; CHECK-LABEL: @test_x86_sse2_psrli_w(1184; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81185; CHECK-NEXT: call void @llvm.donothing()1186; CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> [[TMP1]], i32 7)1187; CHECK-NEXT: [[TMP3:%.*]] = or <8 x i16> [[TMP2]], zeroinitializer1188; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> [[A0:%.*]], i32 7)1189; CHECK-NEXT: store <8 x i16> [[TMP3]], ptr @__msan_retval_tls, align 81190; CHECK-NEXT: ret <8 x i16> [[RES]]1191;1192 %res = call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> %a0, i32 7) ; <<8 x i16>> [#uses=1]1193 ret <8 x i16> %res1194}1195declare <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16>, i32) nounwind readnone1196 1197 1198define i32 @test_x86_sse2_ucomieq_sd(<2 x double> %a0, <2 x double> %a1) #0 {1199; CHECK-LABEL: @test_x86_sse2_ucomieq_sd(1200; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 81201; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81202; CHECK-NEXT: call void @llvm.donothing()1203; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]]1204; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i64 01205; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 01206; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i321207; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.ucomieq.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]])1208; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 81209; CHECK-NEXT: ret i32 [[RES]]1210;1211 %res = call i32 @llvm.x86.sse2.ucomieq.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]1212 ret i32 %res1213}1214declare i32 @llvm.x86.sse2.ucomieq.sd(<2 x double>, <2 x double>) nounwind readnone1215 1216 1217define i32 @test_x86_sse2_ucomige_sd(<2 x double> %a0, <2 x double> %a1) #0 {1218; CHECK-LABEL: @test_x86_sse2_ucomige_sd(1219; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 81220; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81221; CHECK-NEXT: call void @llvm.donothing()1222; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]]1223; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i64 01224; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 01225; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i321226; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.ucomige.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]])1227; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 81228; CHECK-NEXT: ret i32 [[RES]]1229;1230 %res = call i32 @llvm.x86.sse2.ucomige.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]1231 ret i32 %res1232}1233declare i32 @llvm.x86.sse2.ucomige.sd(<2 x double>, <2 x double>) nounwind readnone1234 1235 1236define i32 @test_x86_sse2_ucomigt_sd(<2 x double> %a0, <2 x double> %a1) #0 {1237; CHECK-LABEL: @test_x86_sse2_ucomigt_sd(1238; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 81239; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81240; CHECK-NEXT: call void @llvm.donothing()1241; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]]1242; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i64 01243; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 01244; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i321245; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.ucomigt.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]])1246; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 81247; CHECK-NEXT: ret i32 [[RES]]1248;1249 %res = call i32 @llvm.x86.sse2.ucomigt.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]1250 ret i32 %res1251}1252declare i32 @llvm.x86.sse2.ucomigt.sd(<2 x double>, <2 x double>) nounwind readnone1253 1254 1255define i32 @test_x86_sse2_ucomile_sd(<2 x double> %a0, <2 x double> %a1) #0 {1256; CHECK-LABEL: @test_x86_sse2_ucomile_sd(1257; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 81258; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81259; CHECK-NEXT: call void @llvm.donothing()1260; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]]1261; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i64 01262; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 01263; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i321264; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.ucomile.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]])1265; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 81266; CHECK-NEXT: ret i32 [[RES]]1267;1268 %res = call i32 @llvm.x86.sse2.ucomile.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]1269 ret i32 %res1270}1271declare i32 @llvm.x86.sse2.ucomile.sd(<2 x double>, <2 x double>) nounwind readnone1272 1273 1274define i32 @test_x86_sse2_ucomilt_sd(<2 x double> %a0, <2 x double> %a1) #0 {1275; CHECK-LABEL: @test_x86_sse2_ucomilt_sd(1276; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 81277; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81278; CHECK-NEXT: call void @llvm.donothing()1279; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]]1280; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i64 01281; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 01282; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i321283; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.ucomilt.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]])1284; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 81285; CHECK-NEXT: ret i32 [[RES]]1286;1287 %res = call i32 @llvm.x86.sse2.ucomilt.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]1288 ret i32 %res1289}1290declare i32 @llvm.x86.sse2.ucomilt.sd(<2 x double>, <2 x double>) nounwind readnone1291 1292 1293define i32 @test_x86_sse2_ucomineq_sd(<2 x double> %a0, <2 x double> %a1) #0 {1294; CHECK-LABEL: @test_x86_sse2_ucomineq_sd(1295; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 81296; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81297; CHECK-NEXT: call void @llvm.donothing()1298; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]]1299; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i64 01300; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 01301; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i321302; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.ucomineq.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]])1303; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 81304; CHECK-NEXT: ret i32 [[RES]]1305;1306 %res = call i32 @llvm.x86.sse2.ucomineq.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]1307 ret i32 %res1308}1309declare i32 @llvm.x86.sse2.ucomineq.sd(<2 x double>, <2 x double>) nounwind readnone1310 1311define void @test_x86_sse2_pause() #0 {1312; CHECK-LABEL: @test_x86_sse2_pause(1313; CHECK-NEXT: call void @llvm.donothing()1314; CHECK-NEXT: tail call void @llvm.x86.sse2.pause()1315; CHECK-NEXT: ret void1316;1317 tail call void @llvm.x86.sse2.pause()1318 ret void1319}1320declare void @llvm.x86.sse2.pause() nounwind1321 1322define void @lfence() nounwind #0 {1323; CHECK-LABEL: @lfence(1324; CHECK-NEXT: call void @llvm.donothing()1325; CHECK-NEXT: tail call void @llvm.x86.sse2.lfence()1326; CHECK-NEXT: ret void1327;1328 tail call void @llvm.x86.sse2.lfence()1329 ret void1330}1331declare void @llvm.x86.sse2.lfence() nounwind1332 1333define void @mfence() nounwind #0 {1334; CHECK-LABEL: @mfence(1335; CHECK-NEXT: call void @llvm.donothing()1336; CHECK-NEXT: tail call void @llvm.x86.sse2.mfence()1337; CHECK-NEXT: ret void1338;1339 tail call void @llvm.x86.sse2.mfence()1340 ret void1341}1342declare void @llvm.x86.sse2.mfence() nounwind1343 1344define void @clflush(ptr %p) nounwind #0 {1345; CHECK-LABEL: @clflush(1346; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81347; CHECK-NEXT: call void @llvm.donothing()1348; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01349; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]1350; CHECK: 2:1351; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1352; CHECK-NEXT: unreachable1353; CHECK: 3:1354; CHECK-NEXT: tail call void @llvm.x86.sse2.clflush(ptr [[P:%.*]])1355; CHECK-NEXT: ret void1356;1357 tail call void @llvm.x86.sse2.clflush(ptr %p)1358 ret void1359}1360declare void @llvm.x86.sse2.clflush(ptr) nounwind1361 1362attributes #0 = { sanitize_memory }1363