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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt %s -S -msan-check-access-address=0 -passes=msan 2>&1 | FileCheck %s3; RUN: opt %s -S -msan-check-access-address=0 -msan-track-origins=2 -passes=msan 2>&1 | FileCheck %s --check-prefixes=CHECK,ORIGIN4 5target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"6target triple = "x86_64-unknown-linux-gnu"7 8define <4 x i64> @test_mm256_abs_epi8(<4 x i64> %a) local_unnamed_addr #0 {9; ORIGIN-LABEL: @test_mm256_abs_epi8(10; ORIGIN-NEXT: entry:11; ORIGIN-NEXT: [[TMP0:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 812; ORIGIN-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_origin_tls, align 413; ORIGIN-NEXT: call void @llvm.donothing()14; ORIGIN-NEXT: [[TMP2:%.*]] = bitcast <4 x i64> [[TMP0]] to <32 x i8>15; ORIGIN-NEXT: [[TMP3:%.*]] = bitcast <4 x i64> [[A:%.*]] to <32 x i8>16; ORIGIN-NEXT: [[TMP4:%.*]] = icmp eq <32 x i8> [[TMP3]], splat (i8 -128)17; ORIGIN-NEXT: [[TMP5:%.*]] = select <32 x i1> [[TMP4]], <32 x i8> splat (i8 -1), <32 x i8> [[TMP2]]18; ORIGIN-NEXT: [[TMP6:%.*]] = select i1 false, <32 x i8> [[TMP5]], <32 x i8> [[TMP2]]19; ORIGIN-NEXT: [[TMP7:%.*]] = tail call <32 x i8> @llvm.abs.v32i8(<32 x i8> [[TMP3]], i1 false)20; ORIGIN-NEXT: [[TMP8:%.*]] = bitcast <32 x i8> [[TMP6]] to <4 x i64>21; ORIGIN-NEXT: [[TMP9:%.*]] = bitcast <32 x i8> [[TMP7]] to <4 x i64>22; ORIGIN-NEXT: store <4 x i64> [[TMP8]], ptr @__msan_retval_tls, align 823; ORIGIN-NEXT: store i32 [[TMP1]], ptr @__msan_retval_origin_tls, align 424; ORIGIN-NEXT: ret <4 x i64> [[TMP9]]25;26entry:27 %0 = bitcast <4 x i64> %a to <32 x i8>28 %1 = tail call <32 x i8> @llvm.abs.v32i8(<32 x i8> %0, i1 false)29 %2 = bitcast <32 x i8> %1 to <4 x i64>30 ret <4 x i64> %231}32 33define <4 x i64> @test_mm256_abs_epi16(<4 x i64> %a) local_unnamed_addr #0 {34; ORIGIN-LABEL: @test_mm256_abs_epi16(35; ORIGIN-NEXT: entry:36; ORIGIN-NEXT: [[TMP0:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 837; ORIGIN-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_origin_tls, align 438; ORIGIN-NEXT: call void @llvm.donothing()39; ORIGIN-NEXT: [[TMP2:%.*]] = bitcast <4 x i64> [[TMP0]] to <16 x i16>40; ORIGIN-NEXT: [[TMP3:%.*]] = bitcast <4 x i64> [[A:%.*]] to <16 x i16>41; ORIGIN-NEXT: [[TMP4:%.*]] = icmp eq <16 x i16> [[TMP3]], splat (i16 -32768)42; ORIGIN-NEXT: [[TMP5:%.*]] = select <16 x i1> [[TMP4]], <16 x i16> splat (i16 -1), <16 x i16> [[TMP2]]43; ORIGIN-NEXT: [[TMP6:%.*]] = select i1 false, <16 x i16> [[TMP5]], <16 x i16> [[TMP2]]44; ORIGIN-NEXT: [[TMP7:%.*]] = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> [[TMP3]], i1 false)45; ORIGIN-NEXT: [[TMP8:%.*]] = bitcast <16 x i16> [[TMP6]] to <4 x i64>46; ORIGIN-NEXT: [[TMP9:%.*]] = bitcast <16 x i16> [[TMP7]] to <4 x i64>47; ORIGIN-NEXT: store <4 x i64> [[TMP8]], ptr @__msan_retval_tls, align 848; ORIGIN-NEXT: store i32 [[TMP1]], ptr @__msan_retval_origin_tls, align 449; ORIGIN-NEXT: ret <4 x i64> [[TMP9]]50;51entry:52 %0 = bitcast <4 x i64> %a to <16 x i16>53 %1 = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> %0, i1 false)54 %2 = bitcast <16 x i16> %1 to <4 x i64>55 ret <4 x i64> %256}57 58define <4 x i64> @test_mm256_abs_epi32(<4 x i64> %a) local_unnamed_addr #0 {59; ORIGIN-LABEL: @test_mm256_abs_epi32(60; ORIGIN-NEXT: entry:61; ORIGIN-NEXT: [[TMP0:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 862; ORIGIN-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_origin_tls, align 463; ORIGIN-NEXT: call void @llvm.donothing()64; ORIGIN-NEXT: [[TMP2:%.*]] = bitcast <4 x i64> [[TMP0]] to <8 x i32>65; ORIGIN-NEXT: [[TMP3:%.*]] = bitcast <4 x i64> [[A:%.*]] to <8 x i32>66; ORIGIN-NEXT: [[TMP4:%.*]] = icmp eq <8 x i32> [[TMP3]], splat (i32 -2147483648)67; ORIGIN-NEXT: [[TMP5:%.*]] = select <8 x i1> [[TMP4]], <8 x i32> splat (i32 -1), <8 x i32> [[TMP2]]68; ORIGIN-NEXT: [[TMP6:%.*]] = select i1 false, <8 x i32> [[TMP5]], <8 x i32> [[TMP2]]69; ORIGIN-NEXT: [[TMP7:%.*]] = tail call <8 x i32> @llvm.abs.v8i32(<8 x i32> [[TMP3]], i1 false)70; ORIGIN-NEXT: [[TMP8:%.*]] = bitcast <8 x i32> [[TMP6]] to <4 x i64>71; ORIGIN-NEXT: [[TMP9:%.*]] = bitcast <8 x i32> [[TMP7]] to <4 x i64>72; ORIGIN-NEXT: store <4 x i64> [[TMP8]], ptr @__msan_retval_tls, align 873; ORIGIN-NEXT: store i32 [[TMP1]], ptr @__msan_retval_origin_tls, align 474; ORIGIN-NEXT: ret <4 x i64> [[TMP9]]75;76entry:77 %0 = bitcast <4 x i64> %a to <8 x i32>78 %1 = tail call <8 x i32> @llvm.abs.v8i32(<8 x i32> %0, i1 false)79 %2 = bitcast <8 x i32> %1 to <4 x i64>80 ret <4 x i64> %281}82 83define <4 x double> @test_fabs(<4 x double> %a) local_unnamed_addr #0 {84; CHECK-LABEL: @test_fabs(85; CHECK-NEXT: entry:86; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 887; ORIGIN-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_origin_tls, align 488; CHECK: call void @llvm.donothing()89; CHECK-NEXT: [[TMP2:%.*]] = tail call <4 x double> @llvm.fabs.v4f64(<4 x double> [[A:%.*]])90; CHECK-NEXT: store <4 x i64> [[TMP0]], ptr @__msan_retval_tls, align 891; ORIGIN-NEXT: store i32 [[TMP1]], ptr @__msan_retval_origin_tls, align 492; CHECK: ret <4 x double> [[TMP2]]93;94entry:95 %0 = tail call <4 x double> @llvm.fabs.v4f64(<4 x double> %a)96 ret <4 x double> %097}98 99declare <32 x i8> @llvm.abs.v32i8(<32 x i8>, i1 immarg) #1100declare <16 x i16> @llvm.abs.v16i16(<16 x i16>, i1 immarg) #1101declare <8 x i32> @llvm.abs.v8i32(<8 x i32>, i1 immarg) #1102declare <4 x double> @llvm.fabs.v4f64(<4 x double>) #1103 104attributes #0 = { nounwind readnone sanitize_memory }105attributes #1 = { nounwind readnone speculatable willreturn }106 107!llvm.module.flags = !{!0}108!llvm.ident = !{!1}109 110!0 = !{i32 1, !"wchar_size", i32 4}111!1 = !{!"clang version 12.0.0"}112