187 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 62; RUN: opt < %s -msan-check-access-address=0 -S -passes=msan 2>&1 | FileCheck %s3; REQUIRES: x86-registered-target4 5target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"6target triple = "x86_64-unknown-linux-gnu"7 8declare i32 @llvm.x86.bmi.bzhi.32(i32, i32)9declare i32 @llvm.x86.bmi.bextr.32(i32, i32)10declare i32 @llvm.x86.bmi.pdep.32(i32, i32)11declare i32 @llvm.x86.bmi.pext.32(i32, i32)12 13declare i64 @llvm.x86.bmi.bzhi.64(i64, i64)14declare i64 @llvm.x86.bmi.bextr.64(i64, i64)15declare i64 @llvm.x86.bmi.pdep.64(i64, i64)16declare i64 @llvm.x86.bmi.pext.64(i64, i64)17 18define i32 @Test_bzhi_32(i32 %a, i32 %b) sanitize_memory {19; CHECK-LABEL: define i32 @Test_bzhi_32(20; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1:[0-9]+]] {21; CHECK-NEXT: [[ENTRY:.*:]]22; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 823; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 824; CHECK-NEXT: call void @llvm.donothing()25; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP0]], 026; CHECK-NEXT: [[TMP3:%.*]] = sext i1 [[TMP2]] to i3227; CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.x86.bmi.bzhi.32(i32 [[TMP1]], i32 [[B]])28; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP3]], [[TMP4]]29; CHECK-NEXT: [[C:%.*]] = tail call i32 @llvm.x86.bmi.bzhi.32(i32 [[A]], i32 [[B]])30; CHECK-NEXT: store i32 [[TMP5]], ptr @__msan_retval_tls, align 831; CHECK-NEXT: ret i32 [[C]]32;33entry:34 %c = tail call i32 @llvm.x86.bmi.bzhi.32(i32 %a, i32 %b)35 ret i32 %c36}37 38 39define i64 @Test_bzhi_64(i64 %a, i64 %b) sanitize_memory {40; CHECK-LABEL: define i64 @Test_bzhi_64(41; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {42; CHECK-NEXT: [[ENTRY:.*:]]43; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 844; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 845; CHECK-NEXT: call void @llvm.donothing()46; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[TMP0]], 047; CHECK-NEXT: [[TMP3:%.*]] = sext i1 [[TMP2]] to i6448; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.x86.bmi.bzhi.64(i64 [[TMP1]], i64 [[B]])49; CHECK-NEXT: [[TMP5:%.*]] = or i64 [[TMP3]], [[TMP4]]50; CHECK-NEXT: [[C:%.*]] = tail call i64 @llvm.x86.bmi.bzhi.64(i64 [[A]], i64 [[B]])51; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 852; CHECK-NEXT: ret i64 [[C]]53;54entry:55 %c = tail call i64 @llvm.x86.bmi.bzhi.64(i64 %a, i64 %b)56 ret i64 %c57}58 59 60 61define i32 @Test_bextr_32(i32 %a, i32 %b) sanitize_memory {62; CHECK-LABEL: define i32 @Test_bextr_32(63; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] {64; CHECK-NEXT: [[ENTRY:.*:]]65; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 866; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 867; CHECK-NEXT: call void @llvm.donothing()68; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP0]], 069; CHECK-NEXT: [[TMP3:%.*]] = sext i1 [[TMP2]] to i3270; CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.x86.bmi.bextr.32(i32 [[TMP1]], i32 [[B]])71; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP3]], [[TMP4]]72; CHECK-NEXT: [[C:%.*]] = tail call i32 @llvm.x86.bmi.bextr.32(i32 [[A]], i32 [[B]])73; CHECK-NEXT: store i32 [[TMP5]], ptr @__msan_retval_tls, align 874; CHECK-NEXT: ret i32 [[C]]75;76entry:77 %c = tail call i32 @llvm.x86.bmi.bextr.32(i32 %a, i32 %b)78 ret i32 %c79}80 81 82define i64 @Test_bextr_64(i64 %a, i64 %b) sanitize_memory {83; CHECK-LABEL: define i64 @Test_bextr_64(84; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {85; CHECK-NEXT: [[ENTRY:.*:]]86; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 887; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 888; CHECK-NEXT: call void @llvm.donothing()89; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[TMP0]], 090; CHECK-NEXT: [[TMP3:%.*]] = sext i1 [[TMP2]] to i6491; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.x86.bmi.bextr.64(i64 [[TMP1]], i64 [[B]])92; CHECK-NEXT: [[TMP5:%.*]] = or i64 [[TMP3]], [[TMP4]]93; CHECK-NEXT: [[C:%.*]] = tail call i64 @llvm.x86.bmi.bextr.64(i64 [[A]], i64 [[B]])94; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 895; CHECK-NEXT: ret i64 [[C]]96;97entry:98 %c = tail call i64 @llvm.x86.bmi.bextr.64(i64 %a, i64 %b)99 ret i64 %c100}101 102 103 104define i32 @Test_pdep_32(i32 %a, i32 %b) sanitize_memory {105; CHECK-LABEL: define i32 @Test_pdep_32(106; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] {107; CHECK-NEXT: [[ENTRY:.*:]]108; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8109; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8110; CHECK-NEXT: call void @llvm.donothing()111; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP0]], 0112; CHECK-NEXT: [[TMP3:%.*]] = sext i1 [[TMP2]] to i32113; CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.x86.bmi.pdep.32(i32 [[TMP1]], i32 [[B]])114; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP3]], [[TMP4]]115; CHECK-NEXT: [[C:%.*]] = tail call i32 @llvm.x86.bmi.pdep.32(i32 [[A]], i32 [[B]])116; CHECK-NEXT: store i32 [[TMP5]], ptr @__msan_retval_tls, align 8117; CHECK-NEXT: ret i32 [[C]]118;119entry:120 %c = tail call i32 @llvm.x86.bmi.pdep.32(i32 %a, i32 %b)121 ret i32 %c122}123 124 125define i64 @Test_pdep_64(i64 %a, i64 %b) sanitize_memory {126; CHECK-LABEL: define i64 @Test_pdep_64(127; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {128; CHECK-NEXT: [[ENTRY:.*:]]129; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8130; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8131; CHECK-NEXT: call void @llvm.donothing()132; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[TMP0]], 0133; CHECK-NEXT: [[TMP3:%.*]] = sext i1 [[TMP2]] to i64134; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.x86.bmi.pdep.64(i64 [[TMP1]], i64 [[B]])135; CHECK-NEXT: [[TMP5:%.*]] = or i64 [[TMP3]], [[TMP4]]136; CHECK-NEXT: [[C:%.*]] = tail call i64 @llvm.x86.bmi.pdep.64(i64 [[A]], i64 [[B]])137; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 8138; CHECK-NEXT: ret i64 [[C]]139;140entry:141 %c = tail call i64 @llvm.x86.bmi.pdep.64(i64 %a, i64 %b)142 ret i64 %c143}144 145 146define i32 @Test_pext_32(i32 %a, i32 %b) sanitize_memory {147; CHECK-LABEL: define i32 @Test_pext_32(148; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] {149; CHECK-NEXT: [[ENTRY:.*:]]150; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8151; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8152; CHECK-NEXT: call void @llvm.donothing()153; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP0]], 0154; CHECK-NEXT: [[TMP3:%.*]] = sext i1 [[TMP2]] to i32155; CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.x86.bmi.pext.32(i32 [[TMP1]], i32 [[B]])156; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP3]], [[TMP4]]157; CHECK-NEXT: [[C:%.*]] = tail call i32 @llvm.x86.bmi.pext.32(i32 [[A]], i32 [[B]])158; CHECK-NEXT: store i32 [[TMP5]], ptr @__msan_retval_tls, align 8159; CHECK-NEXT: ret i32 [[C]]160;161entry:162 %c = tail call i32 @llvm.x86.bmi.pext.32(i32 %a, i32 %b)163 ret i32 %c164}165 166 167define i64 @Test_pext_64(i64 %a, i64 %b) sanitize_memory {168; CHECK-LABEL: define i64 @Test_pext_64(169; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {170; CHECK-NEXT: [[ENTRY:.*:]]171; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8172; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8173; CHECK-NEXT: call void @llvm.donothing()174; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[TMP0]], 0175; CHECK-NEXT: [[TMP3:%.*]] = sext i1 [[TMP2]] to i64176; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.x86.bmi.pext.64(i64 [[TMP1]], i64 [[B]])177; CHECK-NEXT: [[TMP5:%.*]] = or i64 [[TMP3]], [[TMP4]]178; CHECK-NEXT: [[C:%.*]] = tail call i64 @llvm.x86.bmi.pext.64(i64 [[A]], i64 [[B]])179; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 8180; CHECK-NEXT: ret i64 [[C]]181;182entry:183 %c = tail call i64 @llvm.x86.bmi.pext.64(i64 %a, i64 %b)184 ret i64 %c185}186 187