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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt < %s -passes=msan -S | FileCheck %s3;4; Forked from llvm/test/CodeGen/Generic/expand-experimental-reductions.ll5 6target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"7target triple = "x86_64-unknown-linux-gnu"8 9declare i64 @llvm.vector.reduce.add.v2i64(<2 x i64>)10declare i64 @llvm.vector.reduce.mul.v2i64(<2 x i64>)11declare i64 @llvm.vector.reduce.and.v2i64(<2 x i64>)12declare i64 @llvm.vector.reduce.or.v2i64(<2 x i64>)13declare i64 @llvm.vector.reduce.xor.v2i64(<2 x i64>)14 15declare float @llvm.vector.reduce.fadd.f32.v4f32(float, <4 x float>)16declare float @llvm.vector.reduce.fmul.f32.v4f32(float, <4 x float>)17 18declare i64 @llvm.vector.reduce.smax.v2i64(<2 x i64>)19declare i64 @llvm.vector.reduce.smin.v2i64(<2 x i64>)20declare i64 @llvm.vector.reduce.umax.v2i64(<2 x i64>)21declare i64 @llvm.vector.reduce.umin.v2i64(<2 x i64>)22 23declare double @llvm.vector.reduce.fmax.v2f64(<2 x double>)24declare double @llvm.vector.reduce.fmin.v2f64(<2 x double>)25 26declare i8 @llvm.vector.reduce.and.i8.v3i8(<3 x i8>)27 28define i64 @add_i64(<2 x i64> %vec) #0 {29; CHECK-LABEL: define i64 @add_i64(30; CHECK-SAME: <2 x i64> [[VEC:%.*]]) #[[ATTR1:[0-9]+]] {31; CHECK-NEXT: [[ENTRY:.*:]]32; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 833; CHECK-NEXT: call void @llvm.donothing()34; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> [[TMP0]])35; CHECK-NEXT: [[R:%.*]] = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> [[VEC]])36; CHECK-NEXT: store i64 [[TMP1]], ptr @__msan_retval_tls, align 837; CHECK-NEXT: ret i64 [[R]]38;39entry:40 %r = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %vec)41 ret i64 %r42}43 44define i64 @mul_i64(<2 x i64> %vec) #0 {45; CHECK-LABEL: define i64 @mul_i64(46; CHECK-SAME: <2 x i64> [[VEC:%.*]]) #[[ATTR1]] {47; CHECK-NEXT: [[ENTRY:.*:]]48; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 849; CHECK-NEXT: call void @llvm.donothing()50; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> [[TMP0]])51; CHECK-NEXT: [[R:%.*]] = call i64 @llvm.vector.reduce.mul.v2i64(<2 x i64> [[VEC]])52; CHECK-NEXT: store i64 [[TMP1]], ptr @__msan_retval_tls, align 853; CHECK-NEXT: ret i64 [[R]]54;55entry:56 %r = call i64 @llvm.vector.reduce.mul.v2i64(<2 x i64> %vec)57 ret i64 %r58}59 60define i64 @and_i64(<2 x i64> %vec) #0 {61; CHECK-LABEL: define i64 @and_i64(62; CHECK-SAME: <2 x i64> [[VEC:%.*]]) #[[ATTR1]] {63; CHECK-NEXT: [[ENTRY:.*:]]64; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 865; CHECK-NEXT: call void @llvm.donothing()66; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i64> [[VEC]], [[TMP0]]67; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.vector.reduce.and.v2i64(<2 x i64> [[TMP1]])68; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> [[TMP0]])69; CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP2]], [[TMP3]]70; CHECK-NEXT: [[R:%.*]] = call i64 @llvm.vector.reduce.and.v2i64(<2 x i64> [[VEC]])71; CHECK-NEXT: store i64 [[TMP4]], ptr @__msan_retval_tls, align 872; CHECK-NEXT: ret i64 [[R]]73;74entry:75 %r = call i64 @llvm.vector.reduce.and.v2i64(<2 x i64> %vec)76 ret i64 %r77}78 79define i64 @or_i64(<2 x i64> %vec) #0 {80; CHECK-LABEL: define i64 @or_i64(81; CHECK-SAME: <2 x i64> [[VEC:%.*]]) #[[ATTR1]] {82; CHECK-NEXT: [[ENTRY:.*:]]83; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 884; CHECK-NEXT: call void @llvm.donothing()85; CHECK-NEXT: [[TMP1:%.*]] = xor <2 x i64> [[VEC]], splat (i64 -1)86; CHECK-NEXT: [[TMP2:%.*]] = or <2 x i64> [[TMP1]], [[TMP0]]87; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vector.reduce.and.v2i64(<2 x i64> [[TMP2]])88; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> [[TMP0]])89; CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP3]], [[TMP4]]90; CHECK-NEXT: [[R:%.*]] = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> [[VEC]])91; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 892; CHECK-NEXT: ret i64 [[R]]93;94entry:95 %r = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> %vec)96 ret i64 %r97}98 99define i64 @xor_i64(<2 x i64> %vec) #0 {100; CHECK-LABEL: define i64 @xor_i64(101; CHECK-SAME: <2 x i64> [[VEC:%.*]]) #[[ATTR1]] {102; CHECK-NEXT: [[ENTRY:.*:]]103; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8104; CHECK-NEXT: call void @llvm.donothing()105; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> [[TMP0]])106; CHECK-NEXT: [[R:%.*]] = call i64 @llvm.vector.reduce.xor.v2i64(<2 x i64> [[VEC]])107; CHECK-NEXT: store i64 [[TMP1]], ptr @__msan_retval_tls, align 8108; CHECK-NEXT: ret i64 [[R]]109;110entry:111 %r = call i64 @llvm.vector.reduce.xor.v2i64(<2 x i64> %vec)112 ret i64 %r113}114 115define float @fadd_f32(<4 x float> %vec) #0 {116; CHECK-LABEL: define float @fadd_f32(117; CHECK-SAME: <4 x float> [[VEC:%.*]]) #[[ATTR1]] {118; CHECK-NEXT: [[ENTRY:.*:]]119; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8120; CHECK-NEXT: call void @llvm.donothing()121; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[TMP0]])122; CHECK-NEXT: [[TMP2:%.*]] = or i32 0, [[TMP1]]123; CHECK-NEXT: [[R:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float 0.000000e+00, <4 x float> [[VEC]])124; CHECK-NEXT: store i32 [[TMP2]], ptr @__msan_retval_tls, align 8125; CHECK-NEXT: ret float [[R]]126;127entry:128 %r = call fast float @llvm.vector.reduce.fadd.f32.v4f32(float 0.0, <4 x float> %vec)129 ret float %r130}131 132define float @fadd_f32_accum(float %accum, <4 x float> %vec) #0 {133; CHECK-LABEL: define float @fadd_f32_accum(134; CHECK-SAME: float [[ACCUM:%.*]], <4 x float> [[VEC:%.*]]) #[[ATTR1]] {135; CHECK-NEXT: [[ENTRY:.*:]]136; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @__msan_param_tls, align 8137; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8138; CHECK-NEXT: call void @llvm.donothing()139; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[TMP1]])140; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP0]], [[TMP2]]141; CHECK-NEXT: [[R:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float [[ACCUM]], <4 x float> [[VEC]])142; CHECK-NEXT: store i32 [[TMP3]], ptr @__msan_retval_tls, align 8143; CHECK-NEXT: ret float [[R]]144;145entry:146 %r = call fast float @llvm.vector.reduce.fadd.f32.v4f32(float %accum, <4 x float> %vec)147 ret float %r148}149 150define float @fadd_f32_strict(float %param, <4 x float> %vec) #0 {151; CHECK-LABEL: define float @fadd_f32_strict(152; CHECK-SAME: float [[PARAM:%.*]], <4 x float> [[VEC:%.*]]) #[[ATTR1]] {153; CHECK-NEXT: [[ENTRY:.*:]]154; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr @__msan_param_tls, align 8155; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8156; CHECK-NEXT: call void @llvm.donothing()157; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[TMP0]])158; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP3]], [[TMP1]]159; CHECK-NEXT: [[R:%.*]] = call float @llvm.vector.reduce.fadd.v4f32(float [[PARAM]], <4 x float> [[VEC]])160; CHECK-NEXT: store i32 [[TMP2]], ptr @__msan_retval_tls, align 8161; CHECK-NEXT: ret float [[R]]162;163entry:164 %r = call float @llvm.vector.reduce.fadd.f32.v4f32(float %param, <4 x float> %vec)165 ret float %r166}167 168define float @fadd_f32_strict_accum(float %accum, <4 x float> %vec) #0 {169; CHECK-LABEL: define float @fadd_f32_strict_accum(170; CHECK-SAME: float [[ACCUM:%.*]], <4 x float> [[VEC:%.*]]) #[[ATTR1]] {171; CHECK-NEXT: [[ENTRY:.*:]]172; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @__msan_param_tls, align 8173; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8174; CHECK-NEXT: call void @llvm.donothing()175; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[TMP1]])176; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP0]], [[TMP2]]177; CHECK-NEXT: [[R:%.*]] = call float @llvm.vector.reduce.fadd.v4f32(float [[ACCUM]], <4 x float> [[VEC]])178; CHECK-NEXT: store i32 [[TMP3]], ptr @__msan_retval_tls, align 8179; CHECK-NEXT: ret float [[R]]180;181entry:182 %r = call float @llvm.vector.reduce.fadd.f32.v4f32(float %accum, <4 x float> %vec)183 ret float %r184}185 186define float @fmul_f32(<4 x float> %vec) #0 {187; CHECK-LABEL: define float @fmul_f32(188; CHECK-SAME: <4 x float> [[VEC:%.*]]) #[[ATTR1]] {189; CHECK-NEXT: [[ENTRY:.*:]]190; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8191; CHECK-NEXT: call void @llvm.donothing()192; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[TMP0]])193; CHECK-NEXT: [[TMP2:%.*]] = or i32 0, [[TMP1]]194; CHECK-NEXT: [[R:%.*]] = call fast float @llvm.vector.reduce.fmul.v4f32(float 1.000000e+00, <4 x float> [[VEC]])195; CHECK-NEXT: store i32 [[TMP2]], ptr @__msan_retval_tls, align 8196; CHECK-NEXT: ret float [[R]]197;198entry:199 %r = call fast float @llvm.vector.reduce.fmul.f32.v4f32(float 1.0, <4 x float> %vec)200 ret float %r201}202 203define float @fmul_f32_accum(float %accum, <4 x float> %vec) #0 {204; CHECK-LABEL: define float @fmul_f32_accum(205; CHECK-SAME: float [[ACCUM:%.*]], <4 x float> [[VEC:%.*]]) #[[ATTR1]] {206; CHECK-NEXT: [[ENTRY:.*:]]207; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @__msan_param_tls, align 8208; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8209; CHECK-NEXT: call void @llvm.donothing()210; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[TMP1]])211; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP0]], [[TMP2]]212; CHECK-NEXT: [[R:%.*]] = call fast float @llvm.vector.reduce.fmul.v4f32(float [[ACCUM]], <4 x float> [[VEC]])213; CHECK-NEXT: store i32 [[TMP3]], ptr @__msan_retval_tls, align 8214; CHECK-NEXT: ret float [[R]]215;216entry:217 %r = call fast float @llvm.vector.reduce.fmul.f32.v4f32(float %accum, <4 x float> %vec)218 ret float %r219}220 221define float @fmul_f32_strict(float %param, <4 x float> %vec) #0 {222; CHECK-LABEL: define float @fmul_f32_strict(223; CHECK-SAME: float [[PARAM:%.*]], <4 x float> [[VEC:%.*]]) #[[ATTR1]] {224; CHECK-NEXT: [[ENTRY:.*:]]225; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr @__msan_param_tls, align 8226; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8227; CHECK-NEXT: call void @llvm.donothing()228; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[TMP0]])229; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP3]], [[TMP1]]230; CHECK-NEXT: [[R:%.*]] = call float @llvm.vector.reduce.fmul.v4f32(float [[PARAM]], <4 x float> [[VEC]])231; CHECK-NEXT: store i32 [[TMP2]], ptr @__msan_retval_tls, align 8232; CHECK-NEXT: ret float [[R]]233;234entry:235 %r = call float @llvm.vector.reduce.fmul.f32.v4f32(float %param, <4 x float> %vec)236 ret float %r237}238 239define float @fmul_f32_strict_accum(float %accum, <4 x float> %vec) #0 {240; CHECK-LABEL: define float @fmul_f32_strict_accum(241; CHECK-SAME: float [[ACCUM:%.*]], <4 x float> [[VEC:%.*]]) #[[ATTR1]] {242; CHECK-NEXT: [[ENTRY:.*:]]243; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @__msan_param_tls, align 8244; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8245; CHECK-NEXT: call void @llvm.donothing()246; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[TMP1]])247; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP0]], [[TMP2]]248; CHECK-NEXT: [[R:%.*]] = call float @llvm.vector.reduce.fmul.v4f32(float [[ACCUM]], <4 x float> [[VEC]])249; CHECK-NEXT: store i32 [[TMP3]], ptr @__msan_retval_tls, align 8250; CHECK-NEXT: ret float [[R]]251;252entry:253 %r = call float @llvm.vector.reduce.fmul.f32.v4f32(float %accum, <4 x float> %vec)254 ret float %r255}256 257define i64 @smax_i64(<2 x i64> %vec) #0 {258; CHECK-LABEL: define i64 @smax_i64(259; CHECK-SAME: <2 x i64> [[VEC:%.*]]) #[[ATTR1]] {260; CHECK-NEXT: [[ENTRY:.*:]]261; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8262; CHECK-NEXT: call void @llvm.donothing()263; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> [[TMP0]])264; CHECK-NEXT: [[R:%.*]] = call i64 @llvm.vector.reduce.smax.v2i64(<2 x i64> [[VEC]])265; CHECK-NEXT: store i64 [[TMP1]], ptr @__msan_retval_tls, align 8266; CHECK-NEXT: ret i64 [[R]]267;268entry:269 %r = call i64 @llvm.vector.reduce.smax.v2i64(<2 x i64> %vec)270 ret i64 %r271}272 273define i64 @smin_i64(<2 x i64> %vec) #0 {274; CHECK-LABEL: define i64 @smin_i64(275; CHECK-SAME: <2 x i64> [[VEC:%.*]]) #[[ATTR1]] {276; CHECK-NEXT: [[ENTRY:.*:]]277; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8278; CHECK-NEXT: call void @llvm.donothing()279; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> [[TMP0]])280; CHECK-NEXT: [[R:%.*]] = call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> [[VEC]])281; CHECK-NEXT: store i64 [[TMP1]], ptr @__msan_retval_tls, align 8282; CHECK-NEXT: ret i64 [[R]]283;284entry:285 %r = call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> %vec)286 ret i64 %r287}288 289define i64 @umax_i64(<2 x i64> %vec) #0 {290; CHECK-LABEL: define i64 @umax_i64(291; CHECK-SAME: <2 x i64> [[VEC:%.*]]) #[[ATTR1]] {292; CHECK-NEXT: [[ENTRY:.*:]]293; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8294; CHECK-NEXT: call void @llvm.donothing()295; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> [[TMP0]])296; CHECK-NEXT: [[R:%.*]] = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> [[VEC]])297; CHECK-NEXT: store i64 [[TMP1]], ptr @__msan_retval_tls, align 8298; CHECK-NEXT: ret i64 [[R]]299;300entry:301 %r = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> %vec)302 ret i64 %r303}304 305define i64 @umin_i64(<2 x i64> %vec) #0 {306; CHECK-LABEL: define i64 @umin_i64(307; CHECK-SAME: <2 x i64> [[VEC:%.*]]) #[[ATTR1]] {308; CHECK-NEXT: [[ENTRY:.*:]]309; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8310; CHECK-NEXT: call void @llvm.donothing()311; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> [[TMP0]])312; CHECK-NEXT: [[R:%.*]] = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> [[VEC]])313; CHECK-NEXT: store i64 [[TMP1]], ptr @__msan_retval_tls, align 8314; CHECK-NEXT: ret i64 [[R]]315;316entry:317 %r = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> %vec)318 ret i64 %r319}320 321 322define double @fmax_f64(<2 x double> %vec) #0 {323; CHECK-LABEL: define double @fmax_f64(324; CHECK-SAME: <2 x double> [[VEC:%.*]]) #[[ATTR1]] {325; CHECK-NEXT: [[ENTRY:.*:]]326; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8327; CHECK-NEXT: call void @llvm.donothing()328; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> [[TMP0]])329; CHECK-NEXT: [[R:%.*]] = call double @llvm.vector.reduce.fmax.v2f64(<2 x double> [[VEC]])330; CHECK-NEXT: store i64 [[TMP1]], ptr @__msan_retval_tls, align 8331; CHECK-NEXT: ret double [[R]]332;333entry:334 %r = call double @llvm.vector.reduce.fmax.v2f64(<2 x double> %vec)335 ret double %r336}337 338 339define double @fmin_f64(<2 x double> %vec) #0 {340; CHECK-LABEL: define double @fmin_f64(341; CHECK-SAME: <2 x double> [[VEC:%.*]]) #[[ATTR1]] {342; CHECK-NEXT: [[ENTRY:.*:]]343; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8344; CHECK-NEXT: call void @llvm.donothing()345; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> [[TMP0]])346; CHECK-NEXT: [[R:%.*]] = call double @llvm.vector.reduce.fmin.v2f64(<2 x double> [[VEC]])347; CHECK-NEXT: store i64 [[TMP1]], ptr @__msan_retval_tls, align 8348; CHECK-NEXT: ret double [[R]]349;350entry:351 %r = call double @llvm.vector.reduce.fmin.v2f64(<2 x double> %vec)352 ret double %r353}354 355 356define i8 @test_v3i8(<3 x i8> %a) nounwind #0 {357; CHECK-LABEL: define i8 @test_v3i8(358; CHECK-SAME: <3 x i8> [[A:%.*]]) #[[ATTR2:[0-9]+]] {359; CHECK-NEXT: [[ENTRY:.*:]]360; CHECK-NEXT: [[TMP0:%.*]] = load <3 x i8>, ptr @__msan_param_tls, align 8361; CHECK-NEXT: call void @llvm.donothing()362; CHECK-NEXT: [[TMP1:%.*]] = or <3 x i8> [[A]], [[TMP0]]363; CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.vector.reduce.and.v3i8(<3 x i8> [[TMP1]])364; CHECK-NEXT: [[TMP3:%.*]] = call i8 @llvm.vector.reduce.or.v3i8(<3 x i8> [[TMP0]])365; CHECK-NEXT: [[TMP4:%.*]] = and i8 [[TMP2]], [[TMP3]]366; CHECK-NEXT: [[B:%.*]] = call i8 @llvm.vector.reduce.and.v3i8(<3 x i8> [[A]])367; CHECK-NEXT: store i8 [[TMP4]], ptr @__msan_retval_tls, align 8368; CHECK-NEXT: ret i8 [[B]]369;370entry:371 %b = call i8 @llvm.vector.reduce.and.i8.v3i8(<3 x i8> %a)372 ret i8 %b373}374 375attributes #0 = { sanitize_memory }376