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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 42; RUN: opt %s -S -passes=msan 2>&1 | FileCheck %s3;4; Handled strictly:5; - i32 @llvm.x86.mmx.pmovmskb(<1 x i64> %mmx_var.i) #26; - void @llvm.x86.mmx.maskmovq(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i, ptr %p) #27; - <2 x double> @llvm.x86.sse.cvtpi2pd(<1 x i64> %4) #58; - <1 x i64> @llvm.x86.sse.cvttpd2pi(<2 x double> %a) #59; - <1 x i64> @llvm.x86.sse.cvtpd2pi(<2 x double> %a) #510; - <1 x i64> @llvm.x86.mmx.palignr.b(<1 x i64> %mmx_var, <1 x i64> %mmx_var1, i8 16)11; - <4 x float> @llvm.x86.sse.cvtpi2ps(<4 x float> %a, <1 x i64> %b)12; - void @llvm.x86.mmx.emms()13; - <1 x i64> @llvm.x86.mmx.pinsr.w(<1 x i64> %a.coerce, i32 %d, i32 2)14; - i32 @llvm.x86.mmx.pextr.w(<1 x i64> %a.coerce, i32 2)15 16target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"17target triple = "i386-unknown-linux-gnu"18 19declare <1 x i64> @llvm.x86.ssse3.phadd.w(<1 x i64>, <1 x i64>) nounwind readnone20 21define i64 @test1(<1 x i64> %a, <1 x i64> %b) #0 {22; CHECK-LABEL: define i64 @test1(23; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1:[0-9]+]] {24; CHECK-NEXT: entry:25; CHECK-NEXT: [[TMP9:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 826; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 827; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 828; CHECK-NEXT: call void @llvm.donothing()29; CHECK-NEXT: [[TMP12:%.*]] = bitcast <1 x i64> [[TMP9]] to <4 x i16>30; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>31; CHECK-NEXT: [[TMP13:%.*]] = bitcast <1 x i64> [[TMP10]] to <4 x i16>32; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>33; CHECK-NEXT: [[TMP16:%.*]] = bitcast <4 x i16> [[TMP13]] to <1 x i64>34; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>35; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x i16> [[TMP12]] to <1 x i64>36; CHECK-NEXT: [[TMP17:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>37; CHECK-NEXT: [[TMP21:%.*]] = bitcast <1 x i64> [[TMP16]] to <4 x i16>38; CHECK-NEXT: [[TMP23:%.*]] = bitcast <1 x i64> [[TMP8]] to <4 x i16>39; CHECK-NEXT: [[TMP24:%.*]] = shufflevector <4 x i16> [[TMP21]], <4 x i16> [[TMP23]], <4 x i32> <i32 0, i32 2, i32 4, i32 6>40; CHECK-NEXT: [[TMP25:%.*]] = shufflevector <4 x i16> [[TMP21]], <4 x i16> [[TMP23]], <4 x i32> <i32 1, i32 3, i32 5, i32 7>41; CHECK-NEXT: [[TMP26:%.*]] = or <4 x i16> [[TMP24]], [[TMP25]]42; CHECK-NEXT: [[TMP27:%.*]] = bitcast <4 x i16> [[TMP26]] to i6443; CHECK-NEXT: [[_MSPROP:%.*]] = bitcast i64 [[TMP27]] to <1 x i64>44; CHECK-NEXT: [[TMP18:%.*]] = tail call <1 x i64> @llvm.x86.ssse3.phadd.w(<1 x i64> [[TMP2]], <1 x i64> [[TMP17]]) #[[ATTR5:[0-9]+]]45; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>46; CHECK-NEXT: [[TMP19:%.*]] = bitcast <1 x i64> [[TMP18]] to <4 x i16>47; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>48; CHECK-NEXT: [[TMP14:%.*]] = bitcast <4 x i16> [[TMP19]] to <1 x i64>49; CHECK-NEXT: [[TMP7:%.*]] = extractelement <1 x i64> [[TMP6]], i32 050; CHECK-NEXT: [[TMP15:%.*]] = extractelement <1 x i64> [[TMP14]], i32 051; CHECK-NEXT: store i64 [[TMP7]], ptr @__msan_retval_tls, align 852; CHECK-NEXT: ret i64 [[TMP15]]53;54entry:55 %0 = bitcast <1 x i64> %b to <4 x i16>56 %1 = bitcast <1 x i64> %a to <4 x i16>57 %2 = bitcast <4 x i16> %1 to <1 x i64>58 %3 = bitcast <4 x i16> %0 to <1 x i64>59 %4 = tail call <1 x i64> @llvm.x86.ssse3.phadd.w(<1 x i64> %2, <1 x i64> %3) nounwind readnone60 %5 = bitcast <1 x i64> %4 to <4 x i16>61 %6 = bitcast <4 x i16> %5 to <1 x i64>62 %7 = extractelement <1 x i64> %6, i32 063 ret i64 %764}65 66declare <1 x i64> @llvm.x86.mmx.pcmpgt.d(<1 x i64>, <1 x i64>) nounwind readnone67 68define i64 @test88(<1 x i64> %a, <1 x i64> %b) #0 {69; CHECK-LABEL: define i64 @test88(70; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {71; CHECK-NEXT: entry:72; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 873; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 874; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 875; CHECK-NEXT: call void @llvm.donothing()76; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <2 x i32>77; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <2 x i32>78; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <2 x i32>79; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>80; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i32> [[TMP14]] to <1 x i64>81; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <2 x i32> [[TMP1]] to <1 x i64>82; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i32> [[TMP11]] to <1 x i64>83; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>84; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]85; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pcmpgt.d(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2:[0-9]+]]86; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <2 x i32>87; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <2 x i32>88; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP9]] to <1 x i64>89; CHECK-NEXT: [[TMP12:%.*]] = bitcast <2 x i32> [[TMP16]] to <1 x i64>90; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 091; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 092; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 893; CHECK-NEXT: ret i64 [[TMP13]]94;95entry:96 %0 = bitcast <1 x i64> %b to <2 x i32>97 %1 = bitcast <1 x i64> %a to <2 x i32>98 %mmx_var.i = bitcast <2 x i32> %1 to <1 x i64>99 %mmx_var1.i = bitcast <2 x i32> %0 to <1 x i64>100 %2 = tail call <1 x i64> @llvm.x86.mmx.pcmpgt.d(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind101 %3 = bitcast <1 x i64> %2 to <2 x i32>102 %4 = bitcast <2 x i32> %3 to <1 x i64>103 %5 = extractelement <1 x i64> %4, i32 0104 ret i64 %5105}106 107declare <1 x i64> @llvm.x86.mmx.pcmpgt.w(<1 x i64>, <1 x i64>) nounwind readnone108 109define i64 @test87(<1 x i64> %a, <1 x i64> %b) #0 {110; CHECK-LABEL: define i64 @test87(111; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {112; CHECK-NEXT: entry:113; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8114; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8115; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8116; CHECK-NEXT: call void @llvm.donothing()117; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <4 x i16>118; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>119; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <4 x i16>120; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>121; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP14]] to <1 x i64>122; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>123; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>124; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>125; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]126; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pcmpgt.w(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]127; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>128; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <4 x i16>129; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP9]] to <1 x i64>130; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i16> [[TMP16]] to <1 x i64>131; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 0132; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 0133; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 8134; CHECK-NEXT: ret i64 [[TMP13]]135;136entry:137 %0 = bitcast <1 x i64> %b to <4 x i16>138 %1 = bitcast <1 x i64> %a to <4 x i16>139 %mmx_var.i = bitcast <4 x i16> %1 to <1 x i64>140 %mmx_var1.i = bitcast <4 x i16> %0 to <1 x i64>141 %2 = tail call <1 x i64> @llvm.x86.mmx.pcmpgt.w(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind142 %3 = bitcast <1 x i64> %2 to <4 x i16>143 %4 = bitcast <4 x i16> %3 to <1 x i64>144 %5 = extractelement <1 x i64> %4, i32 0145 ret i64 %5146}147 148declare <1 x i64> @llvm.x86.mmx.pcmpgt.b(<1 x i64>, <1 x i64>) nounwind readnone149 150define i64 @test86(<1 x i64> %a, <1 x i64> %b) #0 {151; CHECK-LABEL: define i64 @test86(152; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {153; CHECK-NEXT: entry:154; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8155; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8156; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8157; CHECK-NEXT: call void @llvm.donothing()158; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <8 x i8>159; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>160; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <8 x i8>161; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>162; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP14]] to <1 x i64>163; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>164; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP11]] to <1 x i64>165; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>166; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]167; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pcmpgt.b(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]168; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <8 x i8>169; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <8 x i8>170; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP9]] to <1 x i64>171; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x i8> [[TMP16]] to <1 x i64>172; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 0173; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 0174; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 8175; CHECK-NEXT: ret i64 [[TMP13]]176;177entry:178 %0 = bitcast <1 x i64> %b to <8 x i8>179 %1 = bitcast <1 x i64> %a to <8 x i8>180 %mmx_var.i = bitcast <8 x i8> %1 to <1 x i64>181 %mmx_var1.i = bitcast <8 x i8> %0 to <1 x i64>182 %2 = tail call <1 x i64> @llvm.x86.mmx.pcmpgt.b(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind183 %3 = bitcast <1 x i64> %2 to <8 x i8>184 %4 = bitcast <8 x i8> %3 to <1 x i64>185 %5 = extractelement <1 x i64> %4, i32 0186 ret i64 %5187}188 189declare <1 x i64> @llvm.x86.mmx.pcmpeq.d(<1 x i64>, <1 x i64>) nounwind readnone190 191define i64 @test85(<1 x i64> %a, <1 x i64> %b) #0 {192; CHECK-LABEL: define i64 @test85(193; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {194; CHECK-NEXT: entry:195; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8196; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8197; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8198; CHECK-NEXT: call void @llvm.donothing()199; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <2 x i32>200; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <2 x i32>201; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <2 x i32>202; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>203; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i32> [[TMP14]] to <1 x i64>204; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <2 x i32> [[TMP1]] to <1 x i64>205; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i32> [[TMP11]] to <1 x i64>206; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>207; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]208; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pcmpeq.d(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]209; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <2 x i32>210; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <2 x i32>211; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP9]] to <1 x i64>212; CHECK-NEXT: [[TMP12:%.*]] = bitcast <2 x i32> [[TMP16]] to <1 x i64>213; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 0214; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 0215; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 8216; CHECK-NEXT: ret i64 [[TMP13]]217;218entry:219 %0 = bitcast <1 x i64> %b to <2 x i32>220 %1 = bitcast <1 x i64> %a to <2 x i32>221 %mmx_var.i = bitcast <2 x i32> %1 to <1 x i64>222 %mmx_var1.i = bitcast <2 x i32> %0 to <1 x i64>223 %2 = tail call <1 x i64> @llvm.x86.mmx.pcmpeq.d(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind224 %3 = bitcast <1 x i64> %2 to <2 x i32>225 %4 = bitcast <2 x i32> %3 to <1 x i64>226 %5 = extractelement <1 x i64> %4, i32 0227 ret i64 %5228}229 230declare <1 x i64> @llvm.x86.mmx.pcmpeq.w(<1 x i64>, <1 x i64>) nounwind readnone231 232define i64 @test84(<1 x i64> %a, <1 x i64> %b) #0 {233; CHECK-LABEL: define i64 @test84(234; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {235; CHECK-NEXT: entry:236; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8237; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8238; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8239; CHECK-NEXT: call void @llvm.donothing()240; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <4 x i16>241; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>242; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <4 x i16>243; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>244; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP14]] to <1 x i64>245; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>246; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>247; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>248; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]249; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pcmpeq.w(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]250; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>251; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <4 x i16>252; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP9]] to <1 x i64>253; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i16> [[TMP16]] to <1 x i64>254; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 0255; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 0256; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 8257; CHECK-NEXT: ret i64 [[TMP13]]258;259entry:260 %0 = bitcast <1 x i64> %b to <4 x i16>261 %1 = bitcast <1 x i64> %a to <4 x i16>262 %mmx_var.i = bitcast <4 x i16> %1 to <1 x i64>263 %mmx_var1.i = bitcast <4 x i16> %0 to <1 x i64>264 %2 = tail call <1 x i64> @llvm.x86.mmx.pcmpeq.w(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind265 %3 = bitcast <1 x i64> %2 to <4 x i16>266 %4 = bitcast <4 x i16> %3 to <1 x i64>267 %5 = extractelement <1 x i64> %4, i32 0268 ret i64 %5269}270 271declare <1 x i64> @llvm.x86.mmx.pcmpeq.b(<1 x i64>, <1 x i64>) nounwind readnone272 273define i64 @test83(<1 x i64> %a, <1 x i64> %b) #0 {274; CHECK-LABEL: define i64 @test83(275; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {276; CHECK-NEXT: entry:277; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8278; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8279; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8280; CHECK-NEXT: call void @llvm.donothing()281; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <8 x i8>282; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>283; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <8 x i8>284; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>285; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP14]] to <1 x i64>286; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>287; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP11]] to <1 x i64>288; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>289; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]290; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pcmpeq.b(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]291; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <8 x i8>292; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <8 x i8>293; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP9]] to <1 x i64>294; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x i8> [[TMP16]] to <1 x i64>295; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 0296; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 0297; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 8298; CHECK-NEXT: ret i64 [[TMP13]]299;300entry:301 %0 = bitcast <1 x i64> %b to <8 x i8>302 %1 = bitcast <1 x i64> %a to <8 x i8>303 %mmx_var.i = bitcast <8 x i8> %1 to <1 x i64>304 %mmx_var1.i = bitcast <8 x i8> %0 to <1 x i64>305 %2 = tail call <1 x i64> @llvm.x86.mmx.pcmpeq.b(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind306 %3 = bitcast <1 x i64> %2 to <8 x i8>307 %4 = bitcast <8 x i8> %3 to <1 x i64>308 %5 = extractelement <1 x i64> %4, i32 0309 ret i64 %5310}311 312declare <1 x i64> @llvm.x86.mmx.punpckldq(<1 x i64>, <1 x i64>) nounwind readnone313 314define i64 @test82(<1 x i64> %a, <1 x i64> %b) #0 {315; CHECK-LABEL: define i64 @test82(316; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {317; CHECK-NEXT: entry:318; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8319; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8320; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8321; CHECK-NEXT: call void @llvm.donothing()322; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <2 x i32>323; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <2 x i32>324; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <2 x i32>325; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>326; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i32> [[TMP14]] to <1 x i64>327; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <2 x i32> [[TMP1]] to <1 x i64>328; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i32> [[TMP11]] to <1 x i64>329; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>330; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]331; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.punpckldq(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]332; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <2 x i32>333; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <2 x i32>334; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP9]] to <1 x i64>335; CHECK-NEXT: [[TMP12:%.*]] = bitcast <2 x i32> [[TMP16]] to <1 x i64>336; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 0337; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 0338; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 8339; CHECK-NEXT: ret i64 [[TMP13]]340;341entry:342 %0 = bitcast <1 x i64> %b to <2 x i32>343 %1 = bitcast <1 x i64> %a to <2 x i32>344 %mmx_var.i = bitcast <2 x i32> %1 to <1 x i64>345 %mmx_var1.i = bitcast <2 x i32> %0 to <1 x i64>346 %2 = tail call <1 x i64> @llvm.x86.mmx.punpckldq(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind347 %3 = bitcast <1 x i64> %2 to <2 x i32>348 %4 = bitcast <2 x i32> %3 to <1 x i64>349 %5 = extractelement <1 x i64> %4, i32 0350 ret i64 %5351}352 353declare <1 x i64> @llvm.x86.mmx.punpcklwd(<1 x i64>, <1 x i64>) nounwind readnone354 355define i64 @test81(<1 x i64> %a, <1 x i64> %b) #0 {356; CHECK-LABEL: define i64 @test81(357; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {358; CHECK-NEXT: entry:359; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8360; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8361; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8362; CHECK-NEXT: call void @llvm.donothing()363; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <4 x i16>364; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>365; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <4 x i16>366; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>367; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP14]] to <1 x i64>368; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>369; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>370; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>371; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]372; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.punpcklwd(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]373; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>374; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <4 x i16>375; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP9]] to <1 x i64>376; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i16> [[TMP16]] to <1 x i64>377; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 0378; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 0379; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 8380; CHECK-NEXT: ret i64 [[TMP13]]381;382entry:383 %0 = bitcast <1 x i64> %b to <4 x i16>384 %1 = bitcast <1 x i64> %a to <4 x i16>385 %mmx_var.i = bitcast <4 x i16> %1 to <1 x i64>386 %mmx_var1.i = bitcast <4 x i16> %0 to <1 x i64>387 %2 = tail call <1 x i64> @llvm.x86.mmx.punpcklwd(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind388 %3 = bitcast <1 x i64> %2 to <4 x i16>389 %4 = bitcast <4 x i16> %3 to <1 x i64>390 %5 = extractelement <1 x i64> %4, i32 0391 ret i64 %5392}393 394declare <1 x i64> @llvm.x86.mmx.punpcklbw(<1 x i64>, <1 x i64>) nounwind readnone395 396define i64 @test80(<1 x i64> %a, <1 x i64> %b) #0 {397; CHECK-LABEL: define i64 @test80(398; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {399; CHECK-NEXT: entry:400; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8401; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8402; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8403; CHECK-NEXT: call void @llvm.donothing()404; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <8 x i8>405; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>406; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <8 x i8>407; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>408; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP14]] to <1 x i64>409; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>410; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP11]] to <1 x i64>411; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>412; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]413; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.punpcklbw(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]414; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <8 x i8>415; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <8 x i8>416; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP9]] to <1 x i64>417; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x i8> [[TMP16]] to <1 x i64>418; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 0419; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 0420; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 8421; CHECK-NEXT: ret i64 [[TMP13]]422;423entry:424 %0 = bitcast <1 x i64> %b to <8 x i8>425 %1 = bitcast <1 x i64> %a to <8 x i8>426 %mmx_var.i = bitcast <8 x i8> %1 to <1 x i64>427 %mmx_var1.i = bitcast <8 x i8> %0 to <1 x i64>428 %2 = tail call <1 x i64> @llvm.x86.mmx.punpcklbw(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind429 %3 = bitcast <1 x i64> %2 to <8 x i8>430 %4 = bitcast <8 x i8> %3 to <1 x i64>431 %5 = extractelement <1 x i64> %4, i32 0432 ret i64 %5433}434 435declare <1 x i64> @llvm.x86.mmx.punpckhdq(<1 x i64>, <1 x i64>) nounwind readnone436 437define i64 @test79(<1 x i64> %a, <1 x i64> %b) #0 {438; CHECK-LABEL: define i64 @test79(439; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {440; CHECK-NEXT: entry:441; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8442; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8443; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8444; CHECK-NEXT: call void @llvm.donothing()445; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <2 x i32>446; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <2 x i32>447; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <2 x i32>448; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>449; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i32> [[TMP14]] to <1 x i64>450; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <2 x i32> [[TMP1]] to <1 x i64>451; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i32> [[TMP11]] to <1 x i64>452; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>453; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]454; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.punpckhdq(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]455; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <2 x i32>456; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <2 x i32>457; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP9]] to <1 x i64>458; CHECK-NEXT: [[TMP12:%.*]] = bitcast <2 x i32> [[TMP16]] to <1 x i64>459; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 0460; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 0461; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 8462; CHECK-NEXT: ret i64 [[TMP13]]463;464entry:465 %0 = bitcast <1 x i64> %b to <2 x i32>466 %1 = bitcast <1 x i64> %a to <2 x i32>467 %mmx_var.i = bitcast <2 x i32> %1 to <1 x i64>468 %mmx_var1.i = bitcast <2 x i32> %0 to <1 x i64>469 %2 = tail call <1 x i64> @llvm.x86.mmx.punpckhdq(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind470 %3 = bitcast <1 x i64> %2 to <2 x i32>471 %4 = bitcast <2 x i32> %3 to <1 x i64>472 %5 = extractelement <1 x i64> %4, i32 0473 ret i64 %5474}475 476declare <1 x i64> @llvm.x86.mmx.punpckhwd(<1 x i64>, <1 x i64>) nounwind readnone477 478define i64 @test78(<1 x i64> %a, <1 x i64> %b) #0 {479; CHECK-LABEL: define i64 @test78(480; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {481; CHECK-NEXT: entry:482; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8483; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8484; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8485; CHECK-NEXT: call void @llvm.donothing()486; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <4 x i16>487; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>488; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <4 x i16>489; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>490; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP14]] to <1 x i64>491; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>492; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>493; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>494; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]495; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.punpckhwd(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]496; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>497; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <4 x i16>498; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP9]] to <1 x i64>499; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i16> [[TMP16]] to <1 x i64>500; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 0501; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 0502; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 8503; CHECK-NEXT: ret i64 [[TMP13]]504;505entry:506 %0 = bitcast <1 x i64> %b to <4 x i16>507 %1 = bitcast <1 x i64> %a to <4 x i16>508 %mmx_var.i = bitcast <4 x i16> %1 to <1 x i64>509 %mmx_var1.i = bitcast <4 x i16> %0 to <1 x i64>510 %2 = tail call <1 x i64> @llvm.x86.mmx.punpckhwd(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind511 %3 = bitcast <1 x i64> %2 to <4 x i16>512 %4 = bitcast <4 x i16> %3 to <1 x i64>513 %5 = extractelement <1 x i64> %4, i32 0514 ret i64 %5515}516 517declare <1 x i64> @llvm.x86.mmx.punpckhbw(<1 x i64>, <1 x i64>) nounwind readnone518 519define i64 @test77(<1 x i64> %a, <1 x i64> %b) #0 {520; CHECK-LABEL: define i64 @test77(521; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {522; CHECK-NEXT: entry:523; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8524; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8525; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8526; CHECK-NEXT: call void @llvm.donothing()527; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <8 x i8>528; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>529; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <8 x i8>530; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>531; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP14]] to <1 x i64>532; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>533; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP11]] to <1 x i64>534; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>535; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]536; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.punpckhbw(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]537; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <8 x i8>538; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <8 x i8>539; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP9]] to <1 x i64>540; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x i8> [[TMP16]] to <1 x i64>541; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 0542; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 0543; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 8544; CHECK-NEXT: ret i64 [[TMP13]]545;546entry:547 %0 = bitcast <1 x i64> %b to <8 x i8>548 %1 = bitcast <1 x i64> %a to <8 x i8>549 %mmx_var.i = bitcast <8 x i8> %1 to <1 x i64>550 %mmx_var1.i = bitcast <8 x i8> %0 to <1 x i64>551 %2 = tail call <1 x i64> @llvm.x86.mmx.punpckhbw(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind552 %3 = bitcast <1 x i64> %2 to <8 x i8>553 %4 = bitcast <8 x i8> %3 to <1 x i64>554 %5 = extractelement <1 x i64> %4, i32 0555 ret i64 %5556}557 558declare <1 x i64> @llvm.x86.mmx.packuswb(<1 x i64>, <1 x i64>) nounwind readnone559 560define i64 @test76(<1 x i64> %a, <1 x i64> %b) #0 {561; CHECK-LABEL: define i64 @test76(562; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {563; CHECK-NEXT: entry:564; CHECK-NEXT: [[TMP16:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8565; CHECK-NEXT: [[TMP17:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8566; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8567; CHECK-NEXT: call void @llvm.donothing()568; CHECK-NEXT: [[TMP19:%.*]] = bitcast <1 x i64> [[TMP16]] to <4 x i16>569; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>570; CHECK-NEXT: [[TMP20:%.*]] = bitcast <1 x i64> [[TMP17]] to <4 x i16>571; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>572; CHECK-NEXT: [[TMP23:%.*]] = bitcast <4 x i16> [[TMP20]] to <1 x i64>573; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>574; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[TMP19]] to <1 x i64>575; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>576; CHECK-NEXT: [[TMP8:%.*]] = bitcast <1 x i64> [[TMP23]] to <4 x i16>577; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[TMP7]] to <4 x i16>578; CHECK-NEXT: [[TMP10:%.*]] = icmp ne <4 x i16> [[TMP8]], zeroinitializer579; CHECK-NEXT: [[TMP11:%.*]] = sext <4 x i1> [[TMP10]] to <4 x i16>580; CHECK-NEXT: [[TMP12:%.*]] = icmp ne <4 x i16> [[TMP9]], zeroinitializer581; CHECK-NEXT: [[TMP13:%.*]] = sext <4 x i1> [[TMP12]] to <4 x i16>582; CHECK-NEXT: [[TMP14:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>583; CHECK-NEXT: [[TMP15:%.*]] = bitcast <4 x i16> [[TMP13]] to <1 x i64>584; CHECK-NEXT: [[_MSPROP_VECTOR_PACK:%.*]] = call <1 x i64> @llvm.x86.mmx.packsswb(<1 x i64> [[TMP14]], <1 x i64> [[TMP15]])585; CHECK-NEXT: [[TMP24:%.*]] = tail call <1 x i64> @llvm.x86.mmx.packuswb(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]586; CHECK-NEXT: [[TMP18:%.*]] = bitcast <1 x i64> [[_MSPROP_VECTOR_PACK]] to <8 x i8>587; CHECK-NEXT: [[TMP4:%.*]] = bitcast <1 x i64> [[TMP24]] to <8 x i8>588; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP18]] to <1 x i64>589; CHECK-NEXT: [[TMP21:%.*]] = bitcast <8 x i8> [[TMP4]] to <1 x i64>590; CHECK-NEXT: [[TMP6:%.*]] = extractelement <1 x i64> [[TMP5]], i32 0591; CHECK-NEXT: [[TMP22:%.*]] = extractelement <1 x i64> [[TMP21]], i32 0592; CHECK-NEXT: store i64 [[TMP6]], ptr @__msan_retval_tls, align 8593; CHECK-NEXT: ret i64 [[TMP22]]594;595entry:596 %0 = bitcast <1 x i64> %b to <4 x i16>597 %1 = bitcast <1 x i64> %a to <4 x i16>598 %mmx_var.i = bitcast <4 x i16> %1 to <1 x i64>599 %mmx_var1.i = bitcast <4 x i16> %0 to <1 x i64>600 %2 = tail call <1 x i64> @llvm.x86.mmx.packuswb(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind601 %3 = bitcast <1 x i64> %2 to <8 x i8>602 %4 = bitcast <8 x i8> %3 to <1 x i64>603 %5 = extractelement <1 x i64> %4, i32 0604 ret i64 %5605}606 607declare <1 x i64> @llvm.x86.mmx.packssdw(<1 x i64>, <1 x i64>) nounwind readnone608 609define i64 @test75(<1 x i64> %a, <1 x i64> %b) #0 {610; CHECK-LABEL: define i64 @test75(611; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {612; CHECK-NEXT: entry:613; CHECK-NEXT: [[TMP16:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8614; CHECK-NEXT: [[TMP17:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8615; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8616; CHECK-NEXT: call void @llvm.donothing()617; CHECK-NEXT: [[TMP19:%.*]] = bitcast <1 x i64> [[TMP16]] to <2 x i32>618; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <2 x i32>619; CHECK-NEXT: [[TMP20:%.*]] = bitcast <1 x i64> [[TMP17]] to <2 x i32>620; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>621; CHECK-NEXT: [[TMP23:%.*]] = bitcast <2 x i32> [[TMP20]] to <1 x i64>622; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <2 x i32> [[TMP1]] to <1 x i64>623; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i32> [[TMP19]] to <1 x i64>624; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>625; CHECK-NEXT: [[TMP8:%.*]] = bitcast <1 x i64> [[TMP23]] to <2 x i32>626; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[TMP7]] to <2 x i32>627; CHECK-NEXT: [[TMP10:%.*]] = icmp ne <2 x i32> [[TMP8]], zeroinitializer628; CHECK-NEXT: [[TMP11:%.*]] = sext <2 x i1> [[TMP10]] to <2 x i32>629; CHECK-NEXT: [[TMP12:%.*]] = icmp ne <2 x i32> [[TMP9]], zeroinitializer630; CHECK-NEXT: [[TMP13:%.*]] = sext <2 x i1> [[TMP12]] to <2 x i32>631; CHECK-NEXT: [[TMP14:%.*]] = bitcast <2 x i32> [[TMP11]] to <1 x i64>632; CHECK-NEXT: [[TMP15:%.*]] = bitcast <2 x i32> [[TMP13]] to <1 x i64>633; CHECK-NEXT: [[_MSPROP_VECTOR_PACK:%.*]] = call <1 x i64> @llvm.x86.mmx.packssdw(<1 x i64> [[TMP14]], <1 x i64> [[TMP15]])634; CHECK-NEXT: [[TMP24:%.*]] = tail call <1 x i64> @llvm.x86.mmx.packssdw(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]635; CHECK-NEXT: [[TMP18:%.*]] = bitcast <1 x i64> [[_MSPROP_VECTOR_PACK]] to <4 x i16>636; CHECK-NEXT: [[TMP4:%.*]] = bitcast <1 x i64> [[TMP24]] to <4 x i16>637; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i16> [[TMP18]] to <1 x i64>638; CHECK-NEXT: [[TMP21:%.*]] = bitcast <4 x i16> [[TMP4]] to <1 x i64>639; CHECK-NEXT: [[TMP6:%.*]] = extractelement <1 x i64> [[TMP5]], i32 0640; CHECK-NEXT: [[TMP22:%.*]] = extractelement <1 x i64> [[TMP21]], i32 0641; CHECK-NEXT: store i64 [[TMP6]], ptr @__msan_retval_tls, align 8642; CHECK-NEXT: ret i64 [[TMP22]]643;644entry:645 %0 = bitcast <1 x i64> %b to <2 x i32>646 %1 = bitcast <1 x i64> %a to <2 x i32>647 %mmx_var.i = bitcast <2 x i32> %1 to <1 x i64>648 %mmx_var1.i = bitcast <2 x i32> %0 to <1 x i64>649 %2 = tail call <1 x i64> @llvm.x86.mmx.packssdw(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind650 %3 = bitcast <1 x i64> %2 to <4 x i16>651 %4 = bitcast <4 x i16> %3 to <1 x i64>652 %5 = extractelement <1 x i64> %4, i32 0653 ret i64 %5654}655 656declare <1 x i64> @llvm.x86.mmx.packsswb(<1 x i64>, <1 x i64>) nounwind readnone657 658define i64 @test74(<1 x i64> %a, <1 x i64> %b) #0 {659; CHECK-LABEL: define i64 @test74(660; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {661; CHECK-NEXT: entry:662; CHECK-NEXT: [[TMP16:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8663; CHECK-NEXT: [[TMP17:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8664; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8665; CHECK-NEXT: call void @llvm.donothing()666; CHECK-NEXT: [[TMP19:%.*]] = bitcast <1 x i64> [[TMP16]] to <4 x i16>667; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>668; CHECK-NEXT: [[TMP20:%.*]] = bitcast <1 x i64> [[TMP17]] to <4 x i16>669; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>670; CHECK-NEXT: [[TMP23:%.*]] = bitcast <4 x i16> [[TMP20]] to <1 x i64>671; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>672; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[TMP19]] to <1 x i64>673; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>674; CHECK-NEXT: [[TMP8:%.*]] = bitcast <1 x i64> [[TMP23]] to <4 x i16>675; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[TMP7]] to <4 x i16>676; CHECK-NEXT: [[TMP10:%.*]] = icmp ne <4 x i16> [[TMP8]], zeroinitializer677; CHECK-NEXT: [[TMP11:%.*]] = sext <4 x i1> [[TMP10]] to <4 x i16>678; CHECK-NEXT: [[TMP12:%.*]] = icmp ne <4 x i16> [[TMP9]], zeroinitializer679; CHECK-NEXT: [[TMP13:%.*]] = sext <4 x i1> [[TMP12]] to <4 x i16>680; CHECK-NEXT: [[TMP14:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>681; CHECK-NEXT: [[TMP15:%.*]] = bitcast <4 x i16> [[TMP13]] to <1 x i64>682; CHECK-NEXT: [[_MSPROP_VECTOR_PACK:%.*]] = call <1 x i64> @llvm.x86.mmx.packsswb(<1 x i64> [[TMP14]], <1 x i64> [[TMP15]])683; CHECK-NEXT: [[TMP24:%.*]] = tail call <1 x i64> @llvm.x86.mmx.packsswb(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]684; CHECK-NEXT: [[TMP18:%.*]] = bitcast <1 x i64> [[_MSPROP_VECTOR_PACK]] to <8 x i8>685; CHECK-NEXT: [[TMP4:%.*]] = bitcast <1 x i64> [[TMP24]] to <8 x i8>686; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP18]] to <1 x i64>687; CHECK-NEXT: [[TMP21:%.*]] = bitcast <8 x i8> [[TMP4]] to <1 x i64>688; CHECK-NEXT: [[TMP6:%.*]] = extractelement <1 x i64> [[TMP5]], i32 0689; CHECK-NEXT: [[TMP22:%.*]] = extractelement <1 x i64> [[TMP21]], i32 0690; CHECK-NEXT: store i64 [[TMP6]], ptr @__msan_retval_tls, align 8691; CHECK-NEXT: ret i64 [[TMP22]]692;693entry:694 %0 = bitcast <1 x i64> %b to <4 x i16>695 %1 = bitcast <1 x i64> %a to <4 x i16>696 %mmx_var.i = bitcast <4 x i16> %1 to <1 x i64>697 %mmx_var1.i = bitcast <4 x i16> %0 to <1 x i64>698 %2 = tail call <1 x i64> @llvm.x86.mmx.packsswb(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind699 %3 = bitcast <1 x i64> %2 to <8 x i8>700 %4 = bitcast <8 x i8> %3 to <1 x i64>701 %5 = extractelement <1 x i64> %4, i32 0702 ret i64 %5703}704 705declare <1 x i64> @llvm.x86.mmx.psrai.d(<1 x i64>, i32) nounwind readnone706 707define i64 @test73(<1 x i64> %a) #0 {708; CHECK-LABEL: define i64 @test73(709; CHECK-SAME: <1 x i64> [[A:%.*]]) #[[ATTR1]] {710; CHECK-NEXT: entry:711; CHECK-NEXT: [[TMP7:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8712; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8713; CHECK-NEXT: call void @llvm.donothing()714; CHECK-NEXT: [[TMP8:%.*]] = bitcast <1 x i64> [[TMP7]] to <2 x i32>715; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>716; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP8]] to <1 x i64>717; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>718; CHECK-NEXT: [[TMP2:%.*]] = call <1 x i64> @llvm.x86.mmx.psrai.d(<1 x i64> [[TMP1]], i32 3)719; CHECK-NEXT: [[TMP11:%.*]] = or <1 x i64> [[TMP2]], zeroinitializer720; CHECK-NEXT: [[TMP9:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psrai.d(<1 x i64> [[MMX_VAR_I]], i32 3) #[[ATTR2]]721; CHECK-NEXT: [[TMP10:%.*]] = bitcast <1 x i64> [[TMP11]] to <2 x i32>722; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP9]] to <2 x i32>723; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i32> [[TMP10]] to <1 x i64>724; CHECK-NEXT: [[TMP12:%.*]] = bitcast <2 x i32> [[TMP14]] to <1 x i64>725; CHECK-NEXT: [[TMP6:%.*]] = extractelement <1 x i64> [[TMP5]], i32 0726; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 0727; CHECK-NEXT: store i64 [[TMP6]], ptr @__msan_retval_tls, align 8728; CHECK-NEXT: ret i64 [[TMP13]]729;730entry:731 %0 = bitcast <1 x i64> %a to <2 x i32>732 %mmx_var.i = bitcast <2 x i32> %0 to <1 x i64>733 %1 = tail call <1 x i64> @llvm.x86.mmx.psrai.d(<1 x i64> %mmx_var.i, i32 3) nounwind734 %2 = bitcast <1 x i64> %1 to <2 x i32>735 %3 = bitcast <2 x i32> %2 to <1 x i64>736 %4 = extractelement <1 x i64> %3, i32 0737 ret i64 %4738}739 740declare <1 x i64> @llvm.x86.mmx.psrai.w(<1 x i64>, i32) nounwind readnone741 742define i64 @test72(<1 x i64> %a) #0 {743; CHECK-LABEL: define i64 @test72(744; CHECK-SAME: <1 x i64> [[A:%.*]]) #[[ATTR1]] {745; CHECK-NEXT: entry:746; CHECK-NEXT: [[TMP7:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8747; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8748; CHECK-NEXT: call void @llvm.donothing()749; CHECK-NEXT: [[TMP8:%.*]] = bitcast <1 x i64> [[TMP7]] to <4 x i16>750; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>751; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP8]] to <1 x i64>752; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>753; CHECK-NEXT: [[TMP2:%.*]] = call <1 x i64> @llvm.x86.mmx.psrai.w(<1 x i64> [[TMP1]], i32 3)754; CHECK-NEXT: [[TMP11:%.*]] = or <1 x i64> [[TMP2]], zeroinitializer755; CHECK-NEXT: [[TMP9:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psrai.w(<1 x i64> [[MMX_VAR_I]], i32 3) #[[ATTR2]]756; CHECK-NEXT: [[TMP10:%.*]] = bitcast <1 x i64> [[TMP11]] to <4 x i16>757; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP9]] to <4 x i16>758; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i16> [[TMP10]] to <1 x i64>759; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i16> [[TMP14]] to <1 x i64>760; CHECK-NEXT: [[TMP6:%.*]] = extractelement <1 x i64> [[TMP5]], i32 0761; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 0762; CHECK-NEXT: store i64 [[TMP6]], ptr @__msan_retval_tls, align 8763; CHECK-NEXT: ret i64 [[TMP13]]764;765entry:766 %0 = bitcast <1 x i64> %a to <4 x i16>767 %mmx_var.i = bitcast <4 x i16> %0 to <1 x i64>768 %1 = tail call <1 x i64> @llvm.x86.mmx.psrai.w(<1 x i64> %mmx_var.i, i32 3) nounwind769 %2 = bitcast <1 x i64> %1 to <4 x i16>770 %3 = bitcast <4 x i16> %2 to <1 x i64>771 %4 = extractelement <1 x i64> %3, i32 0772 ret i64 %4773}774 775define i64 @test72_2(<1 x i64> %a) #0 {776; CHECK-LABEL: define i64 @test72_2(777; CHECK-SAME: <1 x i64> [[A:%.*]]) #[[ATTR1]] {778; CHECK-NEXT: entry:779; CHECK-NEXT: [[TMP7:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8780; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8781; CHECK-NEXT: call void @llvm.donothing()782; CHECK-NEXT: [[TMP8:%.*]] = bitcast <1 x i64> [[TMP7]] to <4 x i16>783; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>784; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP8]] to <1 x i64>785; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>786; CHECK-NEXT: [[TMP2:%.*]] = call <1 x i64> @llvm.x86.mmx.psrai.w(<1 x i64> [[TMP1]], i32 0)787; CHECK-NEXT: [[TMP11:%.*]] = or <1 x i64> [[TMP2]], zeroinitializer788; CHECK-NEXT: [[TMP9:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psrai.w(<1 x i64> [[MMX_VAR_I]], i32 0) #[[ATTR2]]789; CHECK-NEXT: [[TMP10:%.*]] = bitcast <1 x i64> [[TMP11]] to <4 x i16>790; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP9]] to <4 x i16>791; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i16> [[TMP10]] to <1 x i64>792; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i16> [[TMP14]] to <1 x i64>793; CHECK-NEXT: [[TMP6:%.*]] = extractelement <1 x i64> [[TMP5]], i32 0794; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 0795; CHECK-NEXT: store i64 [[TMP6]], ptr @__msan_retval_tls, align 8796; CHECK-NEXT: ret i64 [[TMP13]]797;798entry:799 %0 = bitcast <1 x i64> %a to <4 x i16>800 %mmx_var.i = bitcast <4 x i16> %0 to <1 x i64>801 %1 = tail call <1 x i64> @llvm.x86.mmx.psrai.w(<1 x i64> %mmx_var.i, i32 0) nounwind802 %2 = bitcast <1 x i64> %1 to <4 x i16>803 %3 = bitcast <4 x i16> %2 to <1 x i64>804 %4 = extractelement <1 x i64> %3, i32 0805 ret i64 %4806}807 808declare <1 x i64> @llvm.x86.mmx.psrli.q(<1 x i64>, i32) nounwind readnone809 810define i64 @test71(<1 x i64> %a) #0 {811; CHECK-LABEL: define i64 @test71(812; CHECK-SAME: <1 x i64> [[A:%.*]]) #[[ATTR1]] {813; CHECK-NEXT: entry:814; CHECK-NEXT: [[TMP5:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8815; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8816; CHECK-NEXT: call void @llvm.donothing()817; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <1 x i64> [[TMP5]], i32 0818; CHECK-NEXT: [[TMP0:%.*]] = extractelement <1 x i64> [[A]], i32 0819; CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[_MSPROP]] to <1 x i64>820; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast i64 [[TMP0]] to <1 x i64>821; CHECK-NEXT: [[TMP3:%.*]] = call <1 x i64> @llvm.x86.mmx.psrli.q(<1 x i64> [[TMP2]], i32 3)822; CHECK-NEXT: [[TMP6:%.*]] = or <1 x i64> [[TMP3]], zeroinitializer823; CHECK-NEXT: [[TMP8:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psrli.q(<1 x i64> [[MMX_VAR_I]], i32 3) #[[ATTR2]]824; CHECK-NEXT: [[TMP7:%.*]] = bitcast <1 x i64> [[TMP6]] to i64825; CHECK-NEXT: [[TMP4:%.*]] = bitcast <1 x i64> [[TMP8]] to i64826; CHECK-NEXT: store i64 [[TMP7]], ptr @__msan_retval_tls, align 8827; CHECK-NEXT: ret i64 [[TMP4]]828;829entry:830 %0 = extractelement <1 x i64> %a, i32 0831 %mmx_var.i = bitcast i64 %0 to <1 x i64>832 %1 = tail call <1 x i64> @llvm.x86.mmx.psrli.q(<1 x i64> %mmx_var.i, i32 3) nounwind833 %2 = bitcast <1 x i64> %1 to i64834 ret i64 %2835}836 837declare <1 x i64> @llvm.x86.mmx.psrli.d(<1 x i64>, i32) nounwind readnone838 839define i64 @test70(<1 x i64> %a) #0 {840; CHECK-LABEL: define i64 @test70(841; CHECK-SAME: <1 x i64> [[A:%.*]]) #[[ATTR1]] {842; CHECK-NEXT: entry:843; CHECK-NEXT: [[TMP7:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8844; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8845; CHECK-NEXT: call void @llvm.donothing()846; CHECK-NEXT: [[TMP8:%.*]] = bitcast <1 x i64> [[TMP7]] to <2 x i32>847; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>848; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP8]] to <1 x i64>849; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>850; CHECK-NEXT: [[TMP2:%.*]] = call <1 x i64> @llvm.x86.mmx.psrli.d(<1 x i64> [[TMP1]], i32 3)851; CHECK-NEXT: [[TMP11:%.*]] = or <1 x i64> [[TMP2]], zeroinitializer852; CHECK-NEXT: [[TMP9:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psrli.d(<1 x i64> [[MMX_VAR_I]], i32 3) #[[ATTR2]]853; CHECK-NEXT: [[TMP10:%.*]] = bitcast <1 x i64> [[TMP11]] to <2 x i32>854; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP9]] to <2 x i32>855; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i32> [[TMP10]] to <1 x i64>856; CHECK-NEXT: [[TMP12:%.*]] = bitcast <2 x i32> [[TMP14]] to <1 x i64>857; CHECK-NEXT: [[TMP6:%.*]] = extractelement <1 x i64> [[TMP5]], i32 0858; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 0859; CHECK-NEXT: store i64 [[TMP6]], ptr @__msan_retval_tls, align 8860; CHECK-NEXT: ret i64 [[TMP13]]861;862entry:863 %0 = bitcast <1 x i64> %a to <2 x i32>864 %mmx_var.i = bitcast <2 x i32> %0 to <1 x i64>865 %1 = tail call <1 x i64> @llvm.x86.mmx.psrli.d(<1 x i64> %mmx_var.i, i32 3) nounwind866 %2 = bitcast <1 x i64> %1 to <2 x i32>867 %3 = bitcast <2 x i32> %2 to <1 x i64>868 %4 = extractelement <1 x i64> %3, i32 0869 ret i64 %4870}871 872define i64 @test70_2(<1 x i64> %a) #0 {873; CHECK-LABEL: define i64 @test70_2(874; CHECK-SAME: <1 x i64> [[A:%.*]]) #[[ATTR1]] {875; CHECK-NEXT: entry:876; CHECK-NEXT: [[TMP7:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8877; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8878; CHECK-NEXT: call void @llvm.donothing()879; CHECK-NEXT: [[TMP8:%.*]] = bitcast <1 x i64> [[TMP7]] to <2 x i32>880; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>881; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP8]] to <1 x i64>882; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>883; CHECK-NEXT: [[TMP2:%.*]] = call <1 x i64> @llvm.x86.mmx.psrli.d(<1 x i64> [[TMP1]], i32 0)884; CHECK-NEXT: [[TMP11:%.*]] = or <1 x i64> [[TMP2]], zeroinitializer885; CHECK-NEXT: [[TMP9:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psrli.d(<1 x i64> [[MMX_VAR_I]], i32 0) #[[ATTR2]]886; CHECK-NEXT: [[TMP10:%.*]] = bitcast <1 x i64> [[TMP11]] to <2 x i32>887; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP9]] to <2 x i32>888; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i32> [[TMP10]] to <1 x i64>889; CHECK-NEXT: [[TMP12:%.*]] = bitcast <2 x i32> [[TMP14]] to <1 x i64>890; CHECK-NEXT: [[TMP6:%.*]] = extractelement <1 x i64> [[TMP5]], i32 0891; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 0892; CHECK-NEXT: store i64 [[TMP6]], ptr @__msan_retval_tls, align 8893; CHECK-NEXT: ret i64 [[TMP13]]894;895entry:896 %0 = bitcast <1 x i64> %a to <2 x i32>897 %mmx_var.i = bitcast <2 x i32> %0 to <1 x i64>898 %1 = tail call <1 x i64> @llvm.x86.mmx.psrli.d(<1 x i64> %mmx_var.i, i32 0) nounwind899 %2 = bitcast <1 x i64> %1 to <2 x i32>900 %3 = bitcast <2 x i32> %2 to <1 x i64>901 %4 = extractelement <1 x i64> %3, i32 0902 ret i64 %4903}904 905declare <1 x i64> @llvm.x86.mmx.psrli.w(<1 x i64>, i32) nounwind readnone906 907define i64 @test69(<1 x i64> %a) #0 {908; CHECK-LABEL: define i64 @test69(909; CHECK-SAME: <1 x i64> [[A:%.*]]) #[[ATTR1]] {910; CHECK-NEXT: entry:911; CHECK-NEXT: [[TMP7:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8912; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8913; CHECK-NEXT: call void @llvm.donothing()914; CHECK-NEXT: [[TMP8:%.*]] = bitcast <1 x i64> [[TMP7]] to <4 x i16>915; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>916; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP8]] to <1 x i64>917; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>918; CHECK-NEXT: [[TMP2:%.*]] = call <1 x i64> @llvm.x86.mmx.psrli.w(<1 x i64> [[TMP1]], i32 3)919; CHECK-NEXT: [[TMP11:%.*]] = or <1 x i64> [[TMP2]], zeroinitializer920; CHECK-NEXT: [[TMP9:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psrli.w(<1 x i64> [[MMX_VAR_I]], i32 3) #[[ATTR2]]921; CHECK-NEXT: [[TMP10:%.*]] = bitcast <1 x i64> [[TMP11]] to <4 x i16>922; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP9]] to <4 x i16>923; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i16> [[TMP10]] to <1 x i64>924; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i16> [[TMP14]] to <1 x i64>925; CHECK-NEXT: [[TMP6:%.*]] = extractelement <1 x i64> [[TMP5]], i32 0926; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 0927; CHECK-NEXT: store i64 [[TMP6]], ptr @__msan_retval_tls, align 8928; CHECK-NEXT: ret i64 [[TMP13]]929;930entry:931 %0 = bitcast <1 x i64> %a to <4 x i16>932 %mmx_var.i = bitcast <4 x i16> %0 to <1 x i64>933 %1 = tail call <1 x i64> @llvm.x86.mmx.psrli.w(<1 x i64> %mmx_var.i, i32 3) nounwind934 %2 = bitcast <1 x i64> %1 to <4 x i16>935 %3 = bitcast <4 x i16> %2 to <1 x i64>936 %4 = extractelement <1 x i64> %3, i32 0937 ret i64 %4938}939 940declare <1 x i64> @llvm.x86.mmx.pslli.q(<1 x i64>, i32) nounwind readnone941 942define i64 @test68(<1 x i64> %a) #0 {943; CHECK-LABEL: define i64 @test68(944; CHECK-SAME: <1 x i64> [[A:%.*]]) #[[ATTR1]] {945; CHECK-NEXT: entry:946; CHECK-NEXT: [[TMP5:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8947; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8948; CHECK-NEXT: call void @llvm.donothing()949; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <1 x i64> [[TMP5]], i32 0950; CHECK-NEXT: [[TMP0:%.*]] = extractelement <1 x i64> [[A]], i32 0951; CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[_MSPROP]] to <1 x i64>952; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast i64 [[TMP0]] to <1 x i64>953; CHECK-NEXT: [[TMP3:%.*]] = call <1 x i64> @llvm.x86.mmx.pslli.q(<1 x i64> [[TMP2]], i32 3)954; CHECK-NEXT: [[TMP6:%.*]] = or <1 x i64> [[TMP3]], zeroinitializer955; CHECK-NEXT: [[TMP8:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pslli.q(<1 x i64> [[MMX_VAR_I]], i32 3) #[[ATTR2]]956; CHECK-NEXT: [[TMP7:%.*]] = bitcast <1 x i64> [[TMP6]] to i64957; CHECK-NEXT: [[TMP4:%.*]] = bitcast <1 x i64> [[TMP8]] to i64958; CHECK-NEXT: store i64 [[TMP7]], ptr @__msan_retval_tls, align 8959; CHECK-NEXT: ret i64 [[TMP4]]960;961entry:962 %0 = extractelement <1 x i64> %a, i32 0963 %mmx_var.i = bitcast i64 %0 to <1 x i64>964 %1 = tail call <1 x i64> @llvm.x86.mmx.pslli.q(<1 x i64> %mmx_var.i, i32 3) nounwind965 %2 = bitcast <1 x i64> %1 to i64966 ret i64 %2967}968 969declare <1 x i64> @llvm.x86.mmx.pslli.d(<1 x i64>, i32) nounwind readnone970 971define i64 @test67(<1 x i64> %a) #0 {972; CHECK-LABEL: define i64 @test67(973; CHECK-SAME: <1 x i64> [[A:%.*]]) #[[ATTR1]] {974; CHECK-NEXT: entry:975; CHECK-NEXT: [[TMP7:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8976; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8977; CHECK-NEXT: call void @llvm.donothing()978; CHECK-NEXT: [[TMP8:%.*]] = bitcast <1 x i64> [[TMP7]] to <2 x i32>979; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>980; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP8]] to <1 x i64>981; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>982; CHECK-NEXT: [[TMP2:%.*]] = call <1 x i64> @llvm.x86.mmx.pslli.d(<1 x i64> [[TMP1]], i32 3)983; CHECK-NEXT: [[TMP11:%.*]] = or <1 x i64> [[TMP2]], zeroinitializer984; CHECK-NEXT: [[TMP9:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pslli.d(<1 x i64> [[MMX_VAR_I]], i32 3) #[[ATTR2]]985; CHECK-NEXT: [[TMP10:%.*]] = bitcast <1 x i64> [[TMP11]] to <2 x i32>986; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP9]] to <2 x i32>987; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i32> [[TMP10]] to <1 x i64>988; CHECK-NEXT: [[TMP12:%.*]] = bitcast <2 x i32> [[TMP14]] to <1 x i64>989; CHECK-NEXT: [[TMP6:%.*]] = extractelement <1 x i64> [[TMP5]], i32 0990; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 0991; CHECK-NEXT: store i64 [[TMP6]], ptr @__msan_retval_tls, align 8992; CHECK-NEXT: ret i64 [[TMP13]]993;994entry:995 %0 = bitcast <1 x i64> %a to <2 x i32>996 %mmx_var.i = bitcast <2 x i32> %0 to <1 x i64>997 %1 = tail call <1 x i64> @llvm.x86.mmx.pslli.d(<1 x i64> %mmx_var.i, i32 3) nounwind998 %2 = bitcast <1 x i64> %1 to <2 x i32>999 %3 = bitcast <2 x i32> %2 to <1 x i64>1000 %4 = extractelement <1 x i64> %3, i32 01001 ret i64 %41002}1003 1004declare <1 x i64> @llvm.x86.mmx.pslli.w(<1 x i64>, i32) nounwind readnone1005 1006define i64 @test66(<1 x i64> %a) #0 {1007; CHECK-LABEL: define i64 @test66(1008; CHECK-SAME: <1 x i64> [[A:%.*]]) #[[ATTR1]] {1009; CHECK-NEXT: entry:1010; CHECK-NEXT: [[TMP7:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81011; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 81012; CHECK-NEXT: call void @llvm.donothing()1013; CHECK-NEXT: [[TMP8:%.*]] = bitcast <1 x i64> [[TMP7]] to <4 x i16>1014; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>1015; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP8]] to <1 x i64>1016; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>1017; CHECK-NEXT: [[TMP2:%.*]] = call <1 x i64> @llvm.x86.mmx.pslli.w(<1 x i64> [[TMP1]], i32 3)1018; CHECK-NEXT: [[TMP11:%.*]] = or <1 x i64> [[TMP2]], zeroinitializer1019; CHECK-NEXT: [[TMP9:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pslli.w(<1 x i64> [[MMX_VAR_I]], i32 3) #[[ATTR2]]1020; CHECK-NEXT: [[TMP10:%.*]] = bitcast <1 x i64> [[TMP11]] to <4 x i16>1021; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP9]] to <4 x i16>1022; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i16> [[TMP10]] to <1 x i64>1023; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i16> [[TMP14]] to <1 x i64>1024; CHECK-NEXT: [[TMP6:%.*]] = extractelement <1 x i64> [[TMP5]], i32 01025; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 01026; CHECK-NEXT: store i64 [[TMP6]], ptr @__msan_retval_tls, align 81027; CHECK-NEXT: ret i64 [[TMP13]]1028;1029entry:1030 %0 = bitcast <1 x i64> %a to <4 x i16>1031 %mmx_var.i = bitcast <4 x i16> %0 to <1 x i64>1032 %1 = tail call <1 x i64> @llvm.x86.mmx.pslli.w(<1 x i64> %mmx_var.i, i32 3) nounwind1033 %2 = bitcast <1 x i64> %1 to <4 x i16>1034 %3 = bitcast <4 x i16> %2 to <1 x i64>1035 %4 = extractelement <1 x i64> %3, i32 01036 ret i64 %41037}1038 1039define i64 @test66_2(<1 x i64> %a) #0 {1040; CHECK-LABEL: define i64 @test66_2(1041; CHECK-SAME: <1 x i64> [[A:%.*]]) #[[ATTR1]] {1042; CHECK-NEXT: entry:1043; CHECK-NEXT: [[TMP7:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81044; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 81045; CHECK-NEXT: call void @llvm.donothing()1046; CHECK-NEXT: [[TMP8:%.*]] = bitcast <1 x i64> [[TMP7]] to <4 x i16>1047; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>1048; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP8]] to <1 x i64>1049; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>1050; CHECK-NEXT: [[TMP2:%.*]] = call <1 x i64> @llvm.x86.mmx.pslli.w(<1 x i64> [[TMP1]], i32 0)1051; CHECK-NEXT: [[TMP11:%.*]] = or <1 x i64> [[TMP2]], zeroinitializer1052; CHECK-NEXT: [[TMP9:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pslli.w(<1 x i64> [[MMX_VAR_I]], i32 0) #[[ATTR2]]1053; CHECK-NEXT: [[TMP10:%.*]] = bitcast <1 x i64> [[TMP11]] to <4 x i16>1054; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP9]] to <4 x i16>1055; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i16> [[TMP10]] to <1 x i64>1056; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i16> [[TMP14]] to <1 x i64>1057; CHECK-NEXT: [[TMP6:%.*]] = extractelement <1 x i64> [[TMP5]], i32 01058; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 01059; CHECK-NEXT: store i64 [[TMP6]], ptr @__msan_retval_tls, align 81060; CHECK-NEXT: ret i64 [[TMP13]]1061;1062entry:1063 %0 = bitcast <1 x i64> %a to <4 x i16>1064 %mmx_var.i = bitcast <4 x i16> %0 to <1 x i64>1065 %1 = tail call <1 x i64> @llvm.x86.mmx.pslli.w(<1 x i64> %mmx_var.i, i32 0) nounwind1066 %2 = bitcast <1 x i64> %1 to <4 x i16>1067 %3 = bitcast <4 x i16> %2 to <1 x i64>1068 %4 = extractelement <1 x i64> %3, i32 01069 ret i64 %41070}1071 1072declare <1 x i64> @llvm.x86.mmx.psra.d(<1 x i64>, <1 x i64>) nounwind readnone1073 1074define i64 @test65(<1 x i64> %a, <1 x i64> %b) #0 {1075; CHECK-LABEL: define i64 @test65(1076; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {1077; CHECK-NEXT: entry:1078; CHECK-NEXT: [[TMP9:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81079; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81080; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 81081; CHECK-NEXT: call void @llvm.donothing()1082; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP9]] to <2 x i32>1083; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>1084; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP11]] to <1 x i64>1085; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>1086; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <1 x i64> [[TMP10]], i32 01087; CHECK-NEXT: [[TMP1:%.*]] = extractelement <1 x i64> [[B]], i32 01088; CHECK-NEXT: [[TMP8:%.*]] = bitcast i64 [[_MSPROP]] to <1 x i64>1089; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast i64 [[TMP1]] to <1 x i64>1090; CHECK-NEXT: [[TMP15:%.*]] = bitcast <1 x i64> [[TMP8]] to i641091; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[TMP15]], 01092; CHECK-NEXT: [[TMP14:%.*]] = sext i1 [[TMP13]] to i641093; CHECK-NEXT: [[TMP19:%.*]] = bitcast i64 [[TMP14]] to <1 x i64>1094; CHECK-NEXT: [[TMP20:%.*]] = call <1 x i64> @llvm.x86.mmx.psra.d(<1 x i64> [[TMP4]], <1 x i64> [[MMX_VAR1_I]])1095; CHECK-NEXT: [[TMP12:%.*]] = or <1 x i64> [[TMP20]], [[TMP19]]1096; CHECK-NEXT: [[TMP21:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psra.d(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]1097; CHECK-NEXT: [[TMP18:%.*]] = bitcast <1 x i64> [[TMP12]] to <2 x i32>1098; CHECK-NEXT: [[TMP5:%.*]] = bitcast <1 x i64> [[TMP21]] to <2 x i32>1099; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i32> [[TMP18]] to <1 x i64>1100; CHECK-NEXT: [[TMP16:%.*]] = bitcast <2 x i32> [[TMP5]] to <1 x i64>1101; CHECK-NEXT: [[TMP7:%.*]] = extractelement <1 x i64> [[TMP6]], i32 01102; CHECK-NEXT: [[TMP17:%.*]] = extractelement <1 x i64> [[TMP16]], i32 01103; CHECK-NEXT: store i64 [[TMP7]], ptr @__msan_retval_tls, align 81104; CHECK-NEXT: ret i64 [[TMP17]]1105;1106entry:1107 %0 = bitcast <1 x i64> %a to <2 x i32>1108 %mmx_var.i = bitcast <2 x i32> %0 to <1 x i64>1109 %1 = extractelement <1 x i64> %b, i32 01110 %mmx_var1.i = bitcast i64 %1 to <1 x i64>1111 %2 = tail call <1 x i64> @llvm.x86.mmx.psra.d(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind1112 %3 = bitcast <1 x i64> %2 to <2 x i32>1113 %4 = bitcast <2 x i32> %3 to <1 x i64>1114 %5 = extractelement <1 x i64> %4, i32 01115 ret i64 %51116}1117 1118declare <1 x i64> @llvm.x86.mmx.psra.w(<1 x i64>, <1 x i64>) nounwind readnone1119 1120define i64 @test64(<1 x i64> %a, <1 x i64> %b) #0 {1121; CHECK-LABEL: define i64 @test64(1122; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {1123; CHECK-NEXT: entry:1124; CHECK-NEXT: [[TMP9:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81125; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81126; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 81127; CHECK-NEXT: call void @llvm.donothing()1128; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP9]] to <4 x i16>1129; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>1130; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>1131; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>1132; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <1 x i64> [[TMP10]], i32 01133; CHECK-NEXT: [[TMP1:%.*]] = extractelement <1 x i64> [[B]], i32 01134; CHECK-NEXT: [[TMP8:%.*]] = bitcast i64 [[_MSPROP]] to <1 x i64>1135; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast i64 [[TMP1]] to <1 x i64>1136; CHECK-NEXT: [[TMP15:%.*]] = bitcast <1 x i64> [[TMP8]] to i641137; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[TMP15]], 01138; CHECK-NEXT: [[TMP14:%.*]] = sext i1 [[TMP13]] to i641139; CHECK-NEXT: [[TMP19:%.*]] = bitcast i64 [[TMP14]] to <1 x i64>1140; CHECK-NEXT: [[TMP20:%.*]] = call <1 x i64> @llvm.x86.mmx.psra.w(<1 x i64> [[TMP4]], <1 x i64> [[MMX_VAR1_I]])1141; CHECK-NEXT: [[TMP12:%.*]] = or <1 x i64> [[TMP20]], [[TMP19]]1142; CHECK-NEXT: [[TMP21:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psra.w(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]1143; CHECK-NEXT: [[TMP18:%.*]] = bitcast <1 x i64> [[TMP12]] to <4 x i16>1144; CHECK-NEXT: [[TMP5:%.*]] = bitcast <1 x i64> [[TMP21]] to <4 x i16>1145; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP18]] to <1 x i64>1146; CHECK-NEXT: [[TMP16:%.*]] = bitcast <4 x i16> [[TMP5]] to <1 x i64>1147; CHECK-NEXT: [[TMP7:%.*]] = extractelement <1 x i64> [[TMP6]], i32 01148; CHECK-NEXT: [[TMP17:%.*]] = extractelement <1 x i64> [[TMP16]], i32 01149; CHECK-NEXT: store i64 [[TMP7]], ptr @__msan_retval_tls, align 81150; CHECK-NEXT: ret i64 [[TMP17]]1151;1152entry:1153 %0 = bitcast <1 x i64> %a to <4 x i16>1154 %mmx_var.i = bitcast <4 x i16> %0 to <1 x i64>1155 %1 = extractelement <1 x i64> %b, i32 01156 %mmx_var1.i = bitcast i64 %1 to <1 x i64>1157 %2 = tail call <1 x i64> @llvm.x86.mmx.psra.w(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind1158 %3 = bitcast <1 x i64> %2 to <4 x i16>1159 %4 = bitcast <4 x i16> %3 to <1 x i64>1160 %5 = extractelement <1 x i64> %4, i32 01161 ret i64 %51162}1163 1164declare <1 x i64> @llvm.x86.mmx.psrl.q(<1 x i64>, <1 x i64>) nounwind readnone1165 1166define i64 @test63(<1 x i64> %a, <1 x i64> %b) #0 {1167; CHECK-LABEL: define i64 @test63(1168; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {1169; CHECK-NEXT: entry:1170; CHECK-NEXT: [[TMP7:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81171; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81172; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 81173; CHECK-NEXT: call void @llvm.donothing()1174; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <1 x i64> [[TMP7]], i32 01175; CHECK-NEXT: [[TMP0:%.*]] = extractelement <1 x i64> [[A]], i32 01176; CHECK-NEXT: [[TMP3:%.*]] = bitcast i64 [[_MSPROP]] to <1 x i64>1177; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast i64 [[TMP0]] to <1 x i64>1178; CHECK-NEXT: [[_MSPROP1:%.*]] = extractelement <1 x i64> [[TMP8]], i32 01179; CHECK-NEXT: [[TMP1:%.*]] = extractelement <1 x i64> [[B]], i32 01180; CHECK-NEXT: [[TMP13:%.*]] = bitcast i64 [[_MSPROP1]] to <1 x i64>1181; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast i64 [[TMP1]] to <1 x i64>1182; CHECK-NEXT: [[TMP6:%.*]] = bitcast <1 x i64> [[TMP13]] to i641183; CHECK-NEXT: [[TMP9:%.*]] = icmp ne i64 [[TMP6]], 01184; CHECK-NEXT: [[TMP10:%.*]] = sext i1 [[TMP9]] to i641185; CHECK-NEXT: [[TMP14:%.*]] = bitcast i64 [[TMP10]] to <1 x i64>1186; CHECK-NEXT: [[TMP15:%.*]] = call <1 x i64> @llvm.x86.mmx.psrl.q(<1 x i64> [[TMP3]], <1 x i64> [[MMX_VAR1_I]])1187; CHECK-NEXT: [[TMP16:%.*]] = or <1 x i64> [[TMP15]], [[TMP14]]1188; CHECK-NEXT: [[TMP12:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psrl.q(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]1189; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP16]] to i641190; CHECK-NEXT: [[TMP5:%.*]] = bitcast <1 x i64> [[TMP12]] to i641191; CHECK-NEXT: store i64 [[TMP11]], ptr @__msan_retval_tls, align 81192; CHECK-NEXT: ret i64 [[TMP5]]1193;1194entry:1195 %0 = extractelement <1 x i64> %a, i32 01196 %mmx_var.i = bitcast i64 %0 to <1 x i64>1197 %1 = extractelement <1 x i64> %b, i32 01198 %mmx_var1.i = bitcast i64 %1 to <1 x i64>1199 %2 = tail call <1 x i64> @llvm.x86.mmx.psrl.q(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind1200 %3 = bitcast <1 x i64> %2 to i641201 ret i64 %31202}1203 1204declare <1 x i64> @llvm.x86.mmx.psrl.d(<1 x i64>, <1 x i64>) nounwind readnone1205 1206define i64 @test62(<1 x i64> %a, <1 x i64> %b) #0 {1207; CHECK-LABEL: define i64 @test62(1208; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {1209; CHECK-NEXT: entry:1210; CHECK-NEXT: [[TMP9:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81211; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81212; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 81213; CHECK-NEXT: call void @llvm.donothing()1214; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP9]] to <2 x i32>1215; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>1216; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP11]] to <1 x i64>1217; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>1218; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <1 x i64> [[TMP10]], i32 01219; CHECK-NEXT: [[TMP1:%.*]] = extractelement <1 x i64> [[B]], i32 01220; CHECK-NEXT: [[TMP8:%.*]] = bitcast i64 [[_MSPROP]] to <1 x i64>1221; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast i64 [[TMP1]] to <1 x i64>1222; CHECK-NEXT: [[TMP15:%.*]] = bitcast <1 x i64> [[TMP8]] to i641223; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[TMP15]], 01224; CHECK-NEXT: [[TMP14:%.*]] = sext i1 [[TMP13]] to i641225; CHECK-NEXT: [[TMP19:%.*]] = bitcast i64 [[TMP14]] to <1 x i64>1226; CHECK-NEXT: [[TMP20:%.*]] = call <1 x i64> @llvm.x86.mmx.psrl.d(<1 x i64> [[TMP4]], <1 x i64> [[MMX_VAR1_I]])1227; CHECK-NEXT: [[TMP12:%.*]] = or <1 x i64> [[TMP20]], [[TMP19]]1228; CHECK-NEXT: [[TMP21:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psrl.d(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]1229; CHECK-NEXT: [[TMP18:%.*]] = bitcast <1 x i64> [[TMP12]] to <2 x i32>1230; CHECK-NEXT: [[TMP5:%.*]] = bitcast <1 x i64> [[TMP21]] to <2 x i32>1231; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i32> [[TMP18]] to <1 x i64>1232; CHECK-NEXT: [[TMP16:%.*]] = bitcast <2 x i32> [[TMP5]] to <1 x i64>1233; CHECK-NEXT: [[TMP7:%.*]] = extractelement <1 x i64> [[TMP6]], i32 01234; CHECK-NEXT: [[TMP17:%.*]] = extractelement <1 x i64> [[TMP16]], i32 01235; CHECK-NEXT: store i64 [[TMP7]], ptr @__msan_retval_tls, align 81236; CHECK-NEXT: ret i64 [[TMP17]]1237;1238entry:1239 %0 = bitcast <1 x i64> %a to <2 x i32>1240 %mmx_var.i = bitcast <2 x i32> %0 to <1 x i64>1241 %1 = extractelement <1 x i64> %b, i32 01242 %mmx_var1.i = bitcast i64 %1 to <1 x i64>1243 %2 = tail call <1 x i64> @llvm.x86.mmx.psrl.d(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind1244 %3 = bitcast <1 x i64> %2 to <2 x i32>1245 %4 = bitcast <2 x i32> %3 to <1 x i64>1246 %5 = extractelement <1 x i64> %4, i32 01247 ret i64 %51248}1249 1250declare <1 x i64> @llvm.x86.mmx.psrl.w(<1 x i64>, <1 x i64>) nounwind readnone1251 1252define i64 @test61(<1 x i64> %a, <1 x i64> %b) #0 {1253; CHECK-LABEL: define i64 @test61(1254; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {1255; CHECK-NEXT: entry:1256; CHECK-NEXT: [[TMP9:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81257; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81258; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 81259; CHECK-NEXT: call void @llvm.donothing()1260; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP9]] to <4 x i16>1261; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>1262; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>1263; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>1264; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <1 x i64> [[TMP10]], i32 01265; CHECK-NEXT: [[TMP1:%.*]] = extractelement <1 x i64> [[B]], i32 01266; CHECK-NEXT: [[TMP8:%.*]] = bitcast i64 [[_MSPROP]] to <1 x i64>1267; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast i64 [[TMP1]] to <1 x i64>1268; CHECK-NEXT: [[TMP15:%.*]] = bitcast <1 x i64> [[TMP8]] to i641269; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[TMP15]], 01270; CHECK-NEXT: [[TMP14:%.*]] = sext i1 [[TMP13]] to i641271; CHECK-NEXT: [[TMP19:%.*]] = bitcast i64 [[TMP14]] to <1 x i64>1272; CHECK-NEXT: [[TMP20:%.*]] = call <1 x i64> @llvm.x86.mmx.psrl.w(<1 x i64> [[TMP4]], <1 x i64> [[MMX_VAR1_I]])1273; CHECK-NEXT: [[TMP12:%.*]] = or <1 x i64> [[TMP20]], [[TMP19]]1274; CHECK-NEXT: [[TMP21:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psrl.w(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]1275; CHECK-NEXT: [[TMP18:%.*]] = bitcast <1 x i64> [[TMP12]] to <4 x i16>1276; CHECK-NEXT: [[TMP5:%.*]] = bitcast <1 x i64> [[TMP21]] to <4 x i16>1277; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP18]] to <1 x i64>1278; CHECK-NEXT: [[TMP16:%.*]] = bitcast <4 x i16> [[TMP5]] to <1 x i64>1279; CHECK-NEXT: [[TMP7:%.*]] = extractelement <1 x i64> [[TMP6]], i32 01280; CHECK-NEXT: [[TMP17:%.*]] = extractelement <1 x i64> [[TMP16]], i32 01281; CHECK-NEXT: store i64 [[TMP7]], ptr @__msan_retval_tls, align 81282; CHECK-NEXT: ret i64 [[TMP17]]1283;1284entry:1285 %0 = bitcast <1 x i64> %a to <4 x i16>1286 %mmx_var.i = bitcast <4 x i16> %0 to <1 x i64>1287 %1 = extractelement <1 x i64> %b, i32 01288 %mmx_var1.i = bitcast i64 %1 to <1 x i64>1289 %2 = tail call <1 x i64> @llvm.x86.mmx.psrl.w(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind1290 %3 = bitcast <1 x i64> %2 to <4 x i16>1291 %4 = bitcast <4 x i16> %3 to <1 x i64>1292 %5 = extractelement <1 x i64> %4, i32 01293 ret i64 %51294}1295 1296declare <1 x i64> @llvm.x86.mmx.psll.q(<1 x i64>, <1 x i64>) nounwind readnone1297 1298define i64 @test60(<1 x i64> %a, <1 x i64> %b) #0 {1299; CHECK-LABEL: define i64 @test60(1300; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {1301; CHECK-NEXT: entry:1302; CHECK-NEXT: [[TMP7:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81303; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81304; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 81305; CHECK-NEXT: call void @llvm.donothing()1306; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <1 x i64> [[TMP7]], i32 01307; CHECK-NEXT: [[TMP0:%.*]] = extractelement <1 x i64> [[A]], i32 01308; CHECK-NEXT: [[TMP3:%.*]] = bitcast i64 [[_MSPROP]] to <1 x i64>1309; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast i64 [[TMP0]] to <1 x i64>1310; CHECK-NEXT: [[_MSPROP1:%.*]] = extractelement <1 x i64> [[TMP8]], i32 01311; CHECK-NEXT: [[TMP1:%.*]] = extractelement <1 x i64> [[B]], i32 01312; CHECK-NEXT: [[TMP13:%.*]] = bitcast i64 [[_MSPROP1]] to <1 x i64>1313; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast i64 [[TMP1]] to <1 x i64>1314; CHECK-NEXT: [[TMP6:%.*]] = bitcast <1 x i64> [[TMP13]] to i641315; CHECK-NEXT: [[TMP9:%.*]] = icmp ne i64 [[TMP6]], 01316; CHECK-NEXT: [[TMP10:%.*]] = sext i1 [[TMP9]] to i641317; CHECK-NEXT: [[TMP14:%.*]] = bitcast i64 [[TMP10]] to <1 x i64>1318; CHECK-NEXT: [[TMP15:%.*]] = call <1 x i64> @llvm.x86.mmx.psll.q(<1 x i64> [[TMP3]], <1 x i64> [[MMX_VAR1_I]])1319; CHECK-NEXT: [[TMP16:%.*]] = or <1 x i64> [[TMP15]], [[TMP14]]1320; CHECK-NEXT: [[TMP12:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psll.q(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]1321; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP16]] to i641322; CHECK-NEXT: [[TMP5:%.*]] = bitcast <1 x i64> [[TMP12]] to i641323; CHECK-NEXT: store i64 [[TMP11]], ptr @__msan_retval_tls, align 81324; CHECK-NEXT: ret i64 [[TMP5]]1325;1326entry:1327 %0 = extractelement <1 x i64> %a, i32 01328 %mmx_var.i = bitcast i64 %0 to <1 x i64>1329 %1 = extractelement <1 x i64> %b, i32 01330 %mmx_var1.i = bitcast i64 %1 to <1 x i64>1331 %2 = tail call <1 x i64> @llvm.x86.mmx.psll.q(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind1332 %3 = bitcast <1 x i64> %2 to i641333 ret i64 %31334}1335 1336declare <1 x i64> @llvm.x86.mmx.psll.d(<1 x i64>, <1 x i64>) nounwind readnone1337 1338define i64 @test59(<1 x i64> %a, <1 x i64> %b) #0 {1339; CHECK-LABEL: define i64 @test59(1340; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {1341; CHECK-NEXT: entry:1342; CHECK-NEXT: [[TMP9:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81343; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81344; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 81345; CHECK-NEXT: call void @llvm.donothing()1346; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP9]] to <2 x i32>1347; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>1348; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP11]] to <1 x i64>1349; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>1350; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <1 x i64> [[TMP10]], i32 01351; CHECK-NEXT: [[TMP1:%.*]] = extractelement <1 x i64> [[B]], i32 01352; CHECK-NEXT: [[TMP8:%.*]] = bitcast i64 [[_MSPROP]] to <1 x i64>1353; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast i64 [[TMP1]] to <1 x i64>1354; CHECK-NEXT: [[TMP15:%.*]] = bitcast <1 x i64> [[TMP8]] to i641355; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[TMP15]], 01356; CHECK-NEXT: [[TMP14:%.*]] = sext i1 [[TMP13]] to i641357; CHECK-NEXT: [[TMP19:%.*]] = bitcast i64 [[TMP14]] to <1 x i64>1358; CHECK-NEXT: [[TMP20:%.*]] = call <1 x i64> @llvm.x86.mmx.psll.d(<1 x i64> [[TMP4]], <1 x i64> [[MMX_VAR1_I]])1359; CHECK-NEXT: [[TMP12:%.*]] = or <1 x i64> [[TMP20]], [[TMP19]]1360; CHECK-NEXT: [[TMP21:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psll.d(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]1361; CHECK-NEXT: [[TMP18:%.*]] = bitcast <1 x i64> [[TMP12]] to <2 x i32>1362; CHECK-NEXT: [[TMP5:%.*]] = bitcast <1 x i64> [[TMP21]] to <2 x i32>1363; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i32> [[TMP18]] to <1 x i64>1364; CHECK-NEXT: [[TMP16:%.*]] = bitcast <2 x i32> [[TMP5]] to <1 x i64>1365; CHECK-NEXT: [[TMP7:%.*]] = extractelement <1 x i64> [[TMP6]], i32 01366; CHECK-NEXT: [[TMP17:%.*]] = extractelement <1 x i64> [[TMP16]], i32 01367; CHECK-NEXT: store i64 [[TMP7]], ptr @__msan_retval_tls, align 81368; CHECK-NEXT: ret i64 [[TMP17]]1369;1370entry:1371 %0 = bitcast <1 x i64> %a to <2 x i32>1372 %mmx_var.i = bitcast <2 x i32> %0 to <1 x i64>1373 %1 = extractelement <1 x i64> %b, i32 01374 %mmx_var1.i = bitcast i64 %1 to <1 x i64>1375 %2 = tail call <1 x i64> @llvm.x86.mmx.psll.d(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind1376 %3 = bitcast <1 x i64> %2 to <2 x i32>1377 %4 = bitcast <2 x i32> %3 to <1 x i64>1378 %5 = extractelement <1 x i64> %4, i32 01379 ret i64 %51380}1381 1382declare <1 x i64> @llvm.x86.mmx.psll.w(<1 x i64>, <1 x i64>) nounwind readnone1383 1384define i64 @test58(<1 x i64> %a, <1 x i64> %b) #0 {1385; CHECK-LABEL: define i64 @test58(1386; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {1387; CHECK-NEXT: entry:1388; CHECK-NEXT: [[TMP9:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81389; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81390; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 81391; CHECK-NEXT: call void @llvm.donothing()1392; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP9]] to <4 x i16>1393; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>1394; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>1395; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>1396; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <1 x i64> [[TMP10]], i32 01397; CHECK-NEXT: [[TMP1:%.*]] = extractelement <1 x i64> [[B]], i32 01398; CHECK-NEXT: [[TMP8:%.*]] = bitcast i64 [[_MSPROP]] to <1 x i64>1399; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast i64 [[TMP1]] to <1 x i64>1400; CHECK-NEXT: [[TMP15:%.*]] = bitcast <1 x i64> [[TMP8]] to i641401; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[TMP15]], 01402; CHECK-NEXT: [[TMP14:%.*]] = sext i1 [[TMP13]] to i641403; CHECK-NEXT: [[TMP19:%.*]] = bitcast i64 [[TMP14]] to <1 x i64>1404; CHECK-NEXT: [[TMP20:%.*]] = call <1 x i64> @llvm.x86.mmx.psll.w(<1 x i64> [[TMP4]], <1 x i64> [[MMX_VAR1_I]])1405; CHECK-NEXT: [[TMP12:%.*]] = or <1 x i64> [[TMP20]], [[TMP19]]1406; CHECK-NEXT: [[TMP21:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psll.w(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]1407; CHECK-NEXT: [[TMP18:%.*]] = bitcast <1 x i64> [[TMP12]] to <4 x i16>1408; CHECK-NEXT: [[TMP5:%.*]] = bitcast <1 x i64> [[TMP21]] to <4 x i16>1409; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP18]] to <1 x i64>1410; CHECK-NEXT: [[TMP16:%.*]] = bitcast <4 x i16> [[TMP5]] to <1 x i64>1411; CHECK-NEXT: [[TMP7:%.*]] = extractelement <1 x i64> [[TMP6]], i32 01412; CHECK-NEXT: [[TMP17:%.*]] = extractelement <1 x i64> [[TMP16]], i32 01413; CHECK-NEXT: store i64 [[TMP7]], ptr @__msan_retval_tls, align 81414; CHECK-NEXT: ret i64 [[TMP17]]1415;1416entry:1417 %0 = bitcast <1 x i64> %a to <4 x i16>1418 %mmx_var.i = bitcast <4 x i16> %0 to <1 x i64>1419 %1 = extractelement <1 x i64> %b, i32 01420 %mmx_var1.i = bitcast i64 %1 to <1 x i64>1421 %2 = tail call <1 x i64> @llvm.x86.mmx.psll.w(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind1422 %3 = bitcast <1 x i64> %2 to <4 x i16>1423 %4 = bitcast <4 x i16> %3 to <1 x i64>1424 %5 = extractelement <1 x i64> %4, i32 01425 ret i64 %51426}1427 1428declare <1 x i64> @llvm.x86.mmx.pxor(<1 x i64>, <1 x i64>) nounwind readnone1429 1430define i64 @test56(<1 x i64> %a, <1 x i64> %b) #0 {1431; CHECK-LABEL: define i64 @test56(1432; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {1433; CHECK-NEXT: entry:1434; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81435; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81436; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 81437; CHECK-NEXT: call void @llvm.donothing()1438; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <2 x i32>1439; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <2 x i32>1440; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <2 x i32>1441; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>1442; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i32> [[TMP14]] to <1 x i64>1443; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <2 x i32> [[TMP1]] to <1 x i64>1444; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i32> [[TMP11]] to <1 x i64>1445; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>1446; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]1447; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pxor(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]1448; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <2 x i32>1449; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <2 x i32>1450; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP9]] to <1 x i64>1451; CHECK-NEXT: [[TMP12:%.*]] = bitcast <2 x i32> [[TMP16]] to <1 x i64>1452; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 01453; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 01454; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 81455; CHECK-NEXT: ret i64 [[TMP13]]1456;1457entry:1458 %0 = bitcast <1 x i64> %b to <2 x i32>1459 %1 = bitcast <1 x i64> %a to <2 x i32>1460 %mmx_var.i = bitcast <2 x i32> %1 to <1 x i64>1461 %mmx_var1.i = bitcast <2 x i32> %0 to <1 x i64>1462 %2 = tail call <1 x i64> @llvm.x86.mmx.pxor(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind1463 %3 = bitcast <1 x i64> %2 to <2 x i32>1464 %4 = bitcast <2 x i32> %3 to <1 x i64>1465 %5 = extractelement <1 x i64> %4, i32 01466 ret i64 %51467}1468 1469declare <1 x i64> @llvm.x86.mmx.por(<1 x i64>, <1 x i64>) nounwind readnone1470 1471define i64 @test55(<1 x i64> %a, <1 x i64> %b) #0 {1472; CHECK-LABEL: define i64 @test55(1473; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {1474; CHECK-NEXT: entry:1475; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81476; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81477; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 81478; CHECK-NEXT: call void @llvm.donothing()1479; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <2 x i32>1480; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <2 x i32>1481; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <2 x i32>1482; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>1483; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i32> [[TMP14]] to <1 x i64>1484; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <2 x i32> [[TMP1]] to <1 x i64>1485; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i32> [[TMP11]] to <1 x i64>1486; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>1487; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]1488; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.por(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]1489; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <2 x i32>1490; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <2 x i32>1491; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP9]] to <1 x i64>1492; CHECK-NEXT: [[TMP12:%.*]] = bitcast <2 x i32> [[TMP16]] to <1 x i64>1493; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 01494; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 01495; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 81496; CHECK-NEXT: ret i64 [[TMP13]]1497;1498entry:1499 %0 = bitcast <1 x i64> %b to <2 x i32>1500 %1 = bitcast <1 x i64> %a to <2 x i32>1501 %mmx_var.i = bitcast <2 x i32> %1 to <1 x i64>1502 %mmx_var1.i = bitcast <2 x i32> %0 to <1 x i64>1503 %2 = tail call <1 x i64> @llvm.x86.mmx.por(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind1504 %3 = bitcast <1 x i64> %2 to <2 x i32>1505 %4 = bitcast <2 x i32> %3 to <1 x i64>1506 %5 = extractelement <1 x i64> %4, i32 01507 ret i64 %51508}1509 1510declare <1 x i64> @llvm.x86.mmx.pandn(<1 x i64>, <1 x i64>) nounwind readnone1511 1512define i64 @test54(<1 x i64> %a, <1 x i64> %b) #0 {1513; CHECK-LABEL: define i64 @test54(1514; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {1515; CHECK-NEXT: entry:1516; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81517; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81518; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 81519; CHECK-NEXT: call void @llvm.donothing()1520; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <2 x i32>1521; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <2 x i32>1522; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <2 x i32>1523; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>1524; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i32> [[TMP14]] to <1 x i64>1525; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <2 x i32> [[TMP1]] to <1 x i64>1526; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i32> [[TMP11]] to <1 x i64>1527; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>1528; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]1529; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pandn(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]1530; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <2 x i32>1531; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <2 x i32>1532; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP9]] to <1 x i64>1533; CHECK-NEXT: [[TMP12:%.*]] = bitcast <2 x i32> [[TMP16]] to <1 x i64>1534; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 01535; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 01536; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 81537; CHECK-NEXT: ret i64 [[TMP13]]1538;1539entry:1540 %0 = bitcast <1 x i64> %b to <2 x i32>1541 %1 = bitcast <1 x i64> %a to <2 x i32>1542 %mmx_var.i = bitcast <2 x i32> %1 to <1 x i64>1543 %mmx_var1.i = bitcast <2 x i32> %0 to <1 x i64>1544 %2 = tail call <1 x i64> @llvm.x86.mmx.pandn(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind1545 %3 = bitcast <1 x i64> %2 to <2 x i32>1546 %4 = bitcast <2 x i32> %3 to <1 x i64>1547 %5 = extractelement <1 x i64> %4, i32 01548 ret i64 %51549}1550 1551declare <1 x i64> @llvm.x86.mmx.pand(<1 x i64>, <1 x i64>) nounwind readnone1552 1553define i64 @test53(<1 x i64> %a, <1 x i64> %b) #0 {1554; CHECK-LABEL: define i64 @test53(1555; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {1556; CHECK-NEXT: entry:1557; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81558; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81559; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 81560; CHECK-NEXT: call void @llvm.donothing()1561; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <2 x i32>1562; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <2 x i32>1563; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <2 x i32>1564; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>1565; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i32> [[TMP14]] to <1 x i64>1566; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <2 x i32> [[TMP1]] to <1 x i64>1567; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i32> [[TMP11]] to <1 x i64>1568; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>1569; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]1570; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pand(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]1571; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <2 x i32>1572; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <2 x i32>1573; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP9]] to <1 x i64>1574; CHECK-NEXT: [[TMP12:%.*]] = bitcast <2 x i32> [[TMP16]] to <1 x i64>1575; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 01576; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 01577; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 81578; CHECK-NEXT: ret i64 [[TMP13]]1579;1580entry:1581 %0 = bitcast <1 x i64> %b to <2 x i32>1582 %1 = bitcast <1 x i64> %a to <2 x i32>1583 %mmx_var.i = bitcast <2 x i32> %1 to <1 x i64>1584 %mmx_var1.i = bitcast <2 x i32> %0 to <1 x i64>1585 %2 = tail call <1 x i64> @llvm.x86.mmx.pand(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind1586 %3 = bitcast <1 x i64> %2 to <2 x i32>1587 %4 = bitcast <2 x i32> %3 to <1 x i64>1588 %5 = extractelement <1 x i64> %4, i32 01589 ret i64 %51590}1591 1592declare <1 x i64> @llvm.x86.mmx.pmull.w(<1 x i64>, <1 x i64>) nounwind readnone1593 1594define i64 @test52(<1 x i64> %a, <1 x i64> %b) #0 {1595; CHECK-LABEL: define i64 @test52(1596; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {1597; CHECK-NEXT: entry:1598; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81599; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81600; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 81601; CHECK-NEXT: call void @llvm.donothing()1602; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <4 x i16>1603; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>1604; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <4 x i16>1605; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>1606; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP14]] to <1 x i64>1607; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>1608; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>1609; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>1610; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]1611; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pmull.w(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]1612; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>1613; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <4 x i16>1614; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP9]] to <1 x i64>1615; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i16> [[TMP16]] to <1 x i64>1616; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 01617; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 01618; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 81619; CHECK-NEXT: ret i64 [[TMP13]]1620;1621entry:1622 %0 = bitcast <1 x i64> %b to <4 x i16>1623 %1 = bitcast <1 x i64> %a to <4 x i16>1624 %mmx_var.i = bitcast <4 x i16> %1 to <1 x i64>1625 %mmx_var1.i = bitcast <4 x i16> %0 to <1 x i64>1626 %2 = tail call <1 x i64> @llvm.x86.mmx.pmull.w(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind1627 %3 = bitcast <1 x i64> %2 to <4 x i16>1628 %4 = bitcast <4 x i16> %3 to <1 x i64>1629 %5 = extractelement <1 x i64> %4, i32 01630 ret i64 %51631}1632 1633define i64 @test51(<1 x i64> %a, <1 x i64> %b) #0 {1634; CHECK-LABEL: define i64 @test51(1635; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {1636; CHECK-NEXT: entry:1637; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81638; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81639; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 81640; CHECK-NEXT: call void @llvm.donothing()1641; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <4 x i16>1642; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>1643; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <4 x i16>1644; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>1645; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP14]] to <1 x i64>1646; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>1647; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>1648; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>1649; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]1650; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pmull.w(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]1651; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>1652; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <4 x i16>1653; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP9]] to <1 x i64>1654; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i16> [[TMP16]] to <1 x i64>1655; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 01656; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 01657; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 81658; CHECK-NEXT: ret i64 [[TMP13]]1659;1660entry:1661 %0 = bitcast <1 x i64> %b to <4 x i16>1662 %1 = bitcast <1 x i64> %a to <4 x i16>1663 %mmx_var.i = bitcast <4 x i16> %1 to <1 x i64>1664 %mmx_var1.i = bitcast <4 x i16> %0 to <1 x i64>1665 %2 = tail call <1 x i64> @llvm.x86.mmx.pmull.w(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind1666 %3 = bitcast <1 x i64> %2 to <4 x i16>1667 %4 = bitcast <4 x i16> %3 to <1 x i64>1668 %5 = extractelement <1 x i64> %4, i32 01669 ret i64 %51670}1671 1672declare <1 x i64> @llvm.x86.mmx.pmulh.w(<1 x i64>, <1 x i64>) nounwind readnone1673 1674define i64 @test50(<1 x i64> %a, <1 x i64> %b) #0 {1675; CHECK-LABEL: define i64 @test50(1676; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {1677; CHECK-NEXT: entry:1678; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81679; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81680; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 81681; CHECK-NEXT: call void @llvm.donothing()1682; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <4 x i16>1683; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>1684; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <4 x i16>1685; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>1686; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP14]] to <1 x i64>1687; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>1688; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>1689; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>1690; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]1691; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pmulh.w(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]1692; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>1693; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <4 x i16>1694; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP9]] to <1 x i64>1695; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i16> [[TMP16]] to <1 x i64>1696; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 01697; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 01698; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 81699; CHECK-NEXT: ret i64 [[TMP13]]1700;1701entry:1702 %0 = bitcast <1 x i64> %b to <4 x i16>1703 %1 = bitcast <1 x i64> %a to <4 x i16>1704 %mmx_var.i = bitcast <4 x i16> %1 to <1 x i64>1705 %mmx_var1.i = bitcast <4 x i16> %0 to <1 x i64>1706 %2 = tail call <1 x i64> @llvm.x86.mmx.pmulh.w(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind1707 %3 = bitcast <1 x i64> %2 to <4 x i16>1708 %4 = bitcast <4 x i16> %3 to <1 x i64>1709 %5 = extractelement <1 x i64> %4, i32 01710 ret i64 %51711}1712 1713declare <1 x i64> @llvm.x86.mmx.pmadd.wd(<1 x i64>, <1 x i64>) nounwind readnone1714 1715define i64 @test49(<1 x i64> %a, <1 x i64> %b) #0 {1716; CHECK-LABEL: define i64 @test49(1717; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {1718; CHECK-NEXT: entry:1719; CHECK-NEXT: [[TMP13:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81720; CHECK-NEXT: [[TMP15:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81721; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 81722; CHECK-NEXT: call void @llvm.donothing()1723; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP13]] to <4 x i16>1724; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>1725; CHECK-NEXT: [[TMP19:%.*]] = bitcast <1 x i64> [[TMP15]] to <4 x i16>1726; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>1727; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP19]] to <1 x i64>1728; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>1729; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[TMP16]] to <1 x i64>1730; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>1731; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[MMX_VAR_I]] to <4 x i16>1732; CHECK-NEXT: [[TMP10:%.*]] = bitcast <1 x i64> [[MMX_VAR1_I]] to <4 x i16>1733; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP6]] to <4 x i16>1734; CHECK-NEXT: [[TMP22:%.*]] = bitcast <1 x i64> [[TMP7]] to <4 x i16>1735; CHECK-NEXT: [[TMP30:%.*]] = icmp ne <4 x i16> [[TMP11]], zeroinitializer1736; CHECK-NEXT: [[TMP31:%.*]] = icmp ne <4 x i16> [[TMP22]], zeroinitializer1737; CHECK-NEXT: [[TMP23:%.*]] = icmp ne <4 x i16> [[TMP9]], zeroinitializer1738; CHECK-NEXT: [[TMP33:%.*]] = icmp ne <4 x i16> [[TMP10]], zeroinitializer1739; CHECK-NEXT: [[TMP32:%.*]] = and <4 x i1> [[TMP30]], [[TMP31]]1740; CHECK-NEXT: [[TMP36:%.*]] = and <4 x i1> [[TMP23]], [[TMP31]]1741; CHECK-NEXT: [[TMP37:%.*]] = and <4 x i1> [[TMP30]], [[TMP33]]1742; CHECK-NEXT: [[TMP38:%.*]] = or <4 x i1> [[TMP32]], [[TMP36]]1743; CHECK-NEXT: [[TMP39:%.*]] = or <4 x i1> [[TMP38]], [[TMP37]]1744; CHECK-NEXT: [[TMP24:%.*]] = sext <4 x i1> [[TMP39]] to <4 x i16>1745; CHECK-NEXT: [[TMP25:%.*]] = bitcast <4 x i16> [[TMP24]] to <2 x i32>1746; CHECK-NEXT: [[TMP26:%.*]] = icmp ne <2 x i32> [[TMP25]], zeroinitializer1747; CHECK-NEXT: [[TMP28:%.*]] = sext <2 x i1> [[TMP26]] to <2 x i32>1748; CHECK-NEXT: [[TMP29:%.*]] = bitcast <2 x i32> [[TMP28]] to i641749; CHECK-NEXT: [[TMP14:%.*]] = bitcast i64 [[TMP29]] to <1 x i64>1750; CHECK-NEXT: [[TMP34:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pmadd.wd(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]1751; CHECK-NEXT: [[TMP20:%.*]] = bitcast <1 x i64> [[TMP14]] to <2 x i32>1752; CHECK-NEXT: [[TMP35:%.*]] = bitcast <1 x i64> [[TMP34]] to <2 x i32>1753; CHECK-NEXT: [[TMP17:%.*]] = bitcast <2 x i32> [[TMP20]] to <1 x i64>1754; CHECK-NEXT: [[TMP21:%.*]] = bitcast <2 x i32> [[TMP35]] to <1 x i64>1755; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP17]], i32 01756; CHECK-NEXT: [[TMP18:%.*]] = extractelement <1 x i64> [[TMP21]], i32 01757; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 81758; CHECK-NEXT: ret i64 [[TMP18]]1759;1760entry:1761 %0 = bitcast <1 x i64> %b to <4 x i16>1762 %1 = bitcast <1 x i64> %a to <4 x i16>1763 %mmx_var.i = bitcast <4 x i16> %1 to <1 x i64>1764 %mmx_var1.i = bitcast <4 x i16> %0 to <1 x i64>1765 %2 = tail call <1 x i64> @llvm.x86.mmx.pmadd.wd(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind1766 %3 = bitcast <1 x i64> %2 to <2 x i32>1767 %4 = bitcast <2 x i32> %3 to <1 x i64>1768 %5 = extractelement <1 x i64> %4, i32 01769 ret i64 %51770}1771 1772declare <1 x i64> @llvm.x86.mmx.psubus.w(<1 x i64>, <1 x i64>) nounwind readnone1773 1774define i64 @test48(<1 x i64> %a, <1 x i64> %b) #0 {1775; CHECK-LABEL: define i64 @test48(1776; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {1777; CHECK-NEXT: entry:1778; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81779; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81780; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 81781; CHECK-NEXT: call void @llvm.donothing()1782; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <4 x i16>1783; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>1784; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <4 x i16>1785; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>1786; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP14]] to <1 x i64>1787; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>1788; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>1789; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>1790; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]1791; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psubus.w(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]1792; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>1793; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <4 x i16>1794; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP9]] to <1 x i64>1795; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i16> [[TMP16]] to <1 x i64>1796; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 01797; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 01798; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 81799; CHECK-NEXT: ret i64 [[TMP13]]1800;1801entry:1802 %0 = bitcast <1 x i64> %b to <4 x i16>1803 %1 = bitcast <1 x i64> %a to <4 x i16>1804 %mmx_var.i = bitcast <4 x i16> %1 to <1 x i64>1805 %mmx_var1.i = bitcast <4 x i16> %0 to <1 x i64>1806 %2 = tail call <1 x i64> @llvm.x86.mmx.psubus.w(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind1807 %3 = bitcast <1 x i64> %2 to <4 x i16>1808 %4 = bitcast <4 x i16> %3 to <1 x i64>1809 %5 = extractelement <1 x i64> %4, i32 01810 ret i64 %51811}1812 1813declare <1 x i64> @llvm.x86.mmx.psubus.b(<1 x i64>, <1 x i64>) nounwind readnone1814 1815define i64 @test47(<1 x i64> %a, <1 x i64> %b) #0 {1816; CHECK-LABEL: define i64 @test47(1817; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {1818; CHECK-NEXT: entry:1819; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81820; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81821; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 81822; CHECK-NEXT: call void @llvm.donothing()1823; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <8 x i8>1824; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>1825; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <8 x i8>1826; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>1827; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP14]] to <1 x i64>1828; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>1829; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP11]] to <1 x i64>1830; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>1831; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]1832; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psubus.b(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]1833; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <8 x i8>1834; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <8 x i8>1835; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP9]] to <1 x i64>1836; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x i8> [[TMP16]] to <1 x i64>1837; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 01838; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 01839; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 81840; CHECK-NEXT: ret i64 [[TMP13]]1841;1842entry:1843 %0 = bitcast <1 x i64> %b to <8 x i8>1844 %1 = bitcast <1 x i64> %a to <8 x i8>1845 %mmx_var.i = bitcast <8 x i8> %1 to <1 x i64>1846 %mmx_var1.i = bitcast <8 x i8> %0 to <1 x i64>1847 %2 = tail call <1 x i64> @llvm.x86.mmx.psubus.b(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind1848 %3 = bitcast <1 x i64> %2 to <8 x i8>1849 %4 = bitcast <8 x i8> %3 to <1 x i64>1850 %5 = extractelement <1 x i64> %4, i32 01851 ret i64 %51852}1853 1854declare <1 x i64> @llvm.x86.mmx.psubs.w(<1 x i64>, <1 x i64>) nounwind readnone1855 1856define i64 @test46(<1 x i64> %a, <1 x i64> %b) #0 {1857; CHECK-LABEL: define i64 @test46(1858; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {1859; CHECK-NEXT: entry:1860; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81861; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81862; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 81863; CHECK-NEXT: call void @llvm.donothing()1864; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <4 x i16>1865; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>1866; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <4 x i16>1867; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>1868; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP14]] to <1 x i64>1869; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>1870; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>1871; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>1872; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]1873; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psubs.w(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]1874; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>1875; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <4 x i16>1876; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP9]] to <1 x i64>1877; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i16> [[TMP16]] to <1 x i64>1878; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 01879; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 01880; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 81881; CHECK-NEXT: ret i64 [[TMP13]]1882;1883entry:1884 %0 = bitcast <1 x i64> %b to <4 x i16>1885 %1 = bitcast <1 x i64> %a to <4 x i16>1886 %mmx_var.i = bitcast <4 x i16> %1 to <1 x i64>1887 %mmx_var1.i = bitcast <4 x i16> %0 to <1 x i64>1888 %2 = tail call <1 x i64> @llvm.x86.mmx.psubs.w(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind1889 %3 = bitcast <1 x i64> %2 to <4 x i16>1890 %4 = bitcast <4 x i16> %3 to <1 x i64>1891 %5 = extractelement <1 x i64> %4, i32 01892 ret i64 %51893}1894 1895declare <1 x i64> @llvm.x86.mmx.psubs.b(<1 x i64>, <1 x i64>) nounwind readnone1896 1897define i64 @test45(<1 x i64> %a, <1 x i64> %b) #0 {1898; CHECK-LABEL: define i64 @test45(1899; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {1900; CHECK-NEXT: entry:1901; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81902; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81903; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 81904; CHECK-NEXT: call void @llvm.donothing()1905; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <8 x i8>1906; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>1907; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <8 x i8>1908; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>1909; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP14]] to <1 x i64>1910; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>1911; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP11]] to <1 x i64>1912; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>1913; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]1914; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psubs.b(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]1915; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <8 x i8>1916; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <8 x i8>1917; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP9]] to <1 x i64>1918; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x i8> [[TMP16]] to <1 x i64>1919; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 01920; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 01921; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 81922; CHECK-NEXT: ret i64 [[TMP13]]1923;1924entry:1925 %0 = bitcast <1 x i64> %b to <8 x i8>1926 %1 = bitcast <1 x i64> %a to <8 x i8>1927 %mmx_var.i = bitcast <8 x i8> %1 to <1 x i64>1928 %mmx_var1.i = bitcast <8 x i8> %0 to <1 x i64>1929 %2 = tail call <1 x i64> @llvm.x86.mmx.psubs.b(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind1930 %3 = bitcast <1 x i64> %2 to <8 x i8>1931 %4 = bitcast <8 x i8> %3 to <1 x i64>1932 %5 = extractelement <1 x i64> %4, i32 01933 ret i64 %51934}1935 1936define i64 @test44(<1 x i64> %a, <1 x i64> %b) #0 {1937; CHECK-LABEL: define i64 @test44(1938; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {1939; CHECK-NEXT: entry:1940; CHECK-NEXT: [[TMP4:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81941; CHECK-NEXT: [[TMP5:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81942; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 81943; CHECK-NEXT: call void @llvm.donothing()1944; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <1 x i64> [[TMP4]], i32 01945; CHECK-NEXT: [[TMP0:%.*]] = extractelement <1 x i64> [[A]], i32 01946; CHECK-NEXT: [[TMP7:%.*]] = bitcast i64 [[_MSPROP]] to <1 x i64>1947; CHECK-NEXT: [[MMX_VAR:%.*]] = bitcast i64 [[TMP0]] to <1 x i64>1948; CHECK-NEXT: [[_MSPROP1:%.*]] = extractelement <1 x i64> [[TMP5]], i32 01949; CHECK-NEXT: [[TMP1:%.*]] = extractelement <1 x i64> [[B]], i32 01950; CHECK-NEXT: [[TMP8:%.*]] = bitcast i64 [[_MSPROP1]] to <1 x i64>1951; CHECK-NEXT: [[MMX_VAR1:%.*]] = bitcast i64 [[TMP1]] to <1 x i64>1952; CHECK-NEXT: [[_MSPROP3:%.*]] = or <1 x i64> [[TMP7]], [[TMP8]]1953; CHECK-NEXT: [[TMP6:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psub.q(<1 x i64> [[MMX_VAR]], <1 x i64> [[MMX_VAR1]])1954; CHECK-NEXT: [[_MSPROP2:%.*]] = bitcast <1 x i64> [[_MSPROP3]] to i641955; CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[TMP6]] to i641956; CHECK-NEXT: store i64 [[_MSPROP2]], ptr @__msan_retval_tls, align 81957; CHECK-NEXT: ret i64 [[TMP3]]1958;1959entry:1960 %0 = extractelement <1 x i64> %a, i32 01961 %mmx_var = bitcast i64 %0 to <1 x i64>1962 %1 = extractelement <1 x i64> %b, i32 01963 %mmx_var1 = bitcast i64 %1 to <1 x i64>1964 %2 = tail call <1 x i64> @llvm.x86.mmx.psub.q(<1 x i64> %mmx_var, <1 x i64> %mmx_var1)1965 %3 = bitcast <1 x i64> %2 to i641966 ret i64 %31967}1968 1969declare <1 x i64> @llvm.x86.mmx.psub.q(<1 x i64>, <1 x i64>) nounwind readnone1970 1971declare <1 x i64> @llvm.x86.mmx.psub.d(<1 x i64>, <1 x i64>) nounwind readnone1972 1973define i64 @test43(<1 x i64> %a, <1 x i64> %b) #0 {1974; CHECK-LABEL: define i64 @test43(1975; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {1976; CHECK-NEXT: entry:1977; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81978; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 81979; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 81980; CHECK-NEXT: call void @llvm.donothing()1981; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <2 x i32>1982; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <2 x i32>1983; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <2 x i32>1984; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>1985; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i32> [[TMP14]] to <1 x i64>1986; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <2 x i32> [[TMP1]] to <1 x i64>1987; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i32> [[TMP11]] to <1 x i64>1988; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>1989; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]1990; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psub.d(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]1991; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <2 x i32>1992; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <2 x i32>1993; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP9]] to <1 x i64>1994; CHECK-NEXT: [[TMP12:%.*]] = bitcast <2 x i32> [[TMP16]] to <1 x i64>1995; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 01996; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 01997; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 81998; CHECK-NEXT: ret i64 [[TMP13]]1999;2000entry:2001 %0 = bitcast <1 x i64> %b to <2 x i32>2002 %1 = bitcast <1 x i64> %a to <2 x i32>2003 %mmx_var.i = bitcast <2 x i32> %1 to <1 x i64>2004 %mmx_var1.i = bitcast <2 x i32> %0 to <1 x i64>2005 %2 = tail call <1 x i64> @llvm.x86.mmx.psub.d(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind2006 %3 = bitcast <1 x i64> %2 to <2 x i32>2007 %4 = bitcast <2 x i32> %3 to <1 x i64>2008 %5 = extractelement <1 x i64> %4, i32 02009 ret i64 %52010}2011 2012declare <1 x i64> @llvm.x86.mmx.psub.w(<1 x i64>, <1 x i64>) nounwind readnone2013 2014define i64 @test42(<1 x i64> %a, <1 x i64> %b) #0 {2015; CHECK-LABEL: define i64 @test42(2016; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {2017; CHECK-NEXT: entry:2018; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82019; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82020; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 82021; CHECK-NEXT: call void @llvm.donothing()2022; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <4 x i16>2023; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>2024; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <4 x i16>2025; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>2026; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP14]] to <1 x i64>2027; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>2028; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>2029; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>2030; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]2031; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psub.w(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]2032; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>2033; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <4 x i16>2034; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP9]] to <1 x i64>2035; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i16> [[TMP16]] to <1 x i64>2036; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 02037; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 02038; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 82039; CHECK-NEXT: ret i64 [[TMP13]]2040;2041entry:2042 %0 = bitcast <1 x i64> %b to <4 x i16>2043 %1 = bitcast <1 x i64> %a to <4 x i16>2044 %mmx_var.i = bitcast <4 x i16> %1 to <1 x i64>2045 %mmx_var1.i = bitcast <4 x i16> %0 to <1 x i64>2046 %2 = tail call <1 x i64> @llvm.x86.mmx.psub.w(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind2047 %3 = bitcast <1 x i64> %2 to <4 x i16>2048 %4 = bitcast <4 x i16> %3 to <1 x i64>2049 %5 = extractelement <1 x i64> %4, i32 02050 ret i64 %52051}2052 2053declare <1 x i64> @llvm.x86.mmx.psub.b(<1 x i64>, <1 x i64>) nounwind readnone2054 2055define i64 @test41(<1 x i64> %a, <1 x i64> %b) #0 {2056; CHECK-LABEL: define i64 @test41(2057; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {2058; CHECK-NEXT: entry:2059; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82060; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82061; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 82062; CHECK-NEXT: call void @llvm.donothing()2063; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <8 x i8>2064; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>2065; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <8 x i8>2066; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>2067; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP14]] to <1 x i64>2068; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>2069; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP11]] to <1 x i64>2070; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>2071; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]2072; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psub.b(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]2073; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <8 x i8>2074; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <8 x i8>2075; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP9]] to <1 x i64>2076; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x i8> [[TMP16]] to <1 x i64>2077; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 02078; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 02079; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 82080; CHECK-NEXT: ret i64 [[TMP13]]2081;2082entry:2083 %0 = bitcast <1 x i64> %b to <8 x i8>2084 %1 = bitcast <1 x i64> %a to <8 x i8>2085 %mmx_var.i = bitcast <8 x i8> %1 to <1 x i64>2086 %mmx_var1.i = bitcast <8 x i8> %0 to <1 x i64>2087 %2 = tail call <1 x i64> @llvm.x86.mmx.psub.b(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind2088 %3 = bitcast <1 x i64> %2 to <8 x i8>2089 %4 = bitcast <8 x i8> %3 to <1 x i64>2090 %5 = extractelement <1 x i64> %4, i32 02091 ret i64 %52092}2093 2094declare <1 x i64> @llvm.x86.mmx.paddus.w(<1 x i64>, <1 x i64>) nounwind readnone2095 2096define i64 @test40(<1 x i64> %a, <1 x i64> %b) #0 {2097; CHECK-LABEL: define i64 @test40(2098; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {2099; CHECK-NEXT: entry:2100; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82101; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82102; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 82103; CHECK-NEXT: call void @llvm.donothing()2104; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <4 x i16>2105; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>2106; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <4 x i16>2107; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>2108; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP14]] to <1 x i64>2109; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>2110; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>2111; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>2112; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]2113; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.paddus.w(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]2114; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>2115; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <4 x i16>2116; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP9]] to <1 x i64>2117; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i16> [[TMP16]] to <1 x i64>2118; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 02119; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 02120; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 82121; CHECK-NEXT: ret i64 [[TMP13]]2122;2123entry:2124 %0 = bitcast <1 x i64> %b to <4 x i16>2125 %1 = bitcast <1 x i64> %a to <4 x i16>2126 %mmx_var.i = bitcast <4 x i16> %1 to <1 x i64>2127 %mmx_var1.i = bitcast <4 x i16> %0 to <1 x i64>2128 %2 = tail call <1 x i64> @llvm.x86.mmx.paddus.w(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind2129 %3 = bitcast <1 x i64> %2 to <4 x i16>2130 %4 = bitcast <4 x i16> %3 to <1 x i64>2131 %5 = extractelement <1 x i64> %4, i32 02132 ret i64 %52133}2134 2135declare <1 x i64> @llvm.x86.mmx.paddus.b(<1 x i64>, <1 x i64>) nounwind readnone2136 2137define i64 @test39(<1 x i64> %a, <1 x i64> %b) #0 {2138; CHECK-LABEL: define i64 @test39(2139; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {2140; CHECK-NEXT: entry:2141; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82142; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82143; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 82144; CHECK-NEXT: call void @llvm.donothing()2145; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <8 x i8>2146; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>2147; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <8 x i8>2148; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>2149; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP14]] to <1 x i64>2150; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>2151; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP11]] to <1 x i64>2152; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>2153; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]2154; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.paddus.b(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]2155; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <8 x i8>2156; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <8 x i8>2157; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP9]] to <1 x i64>2158; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x i8> [[TMP16]] to <1 x i64>2159; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 02160; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 02161; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 82162; CHECK-NEXT: ret i64 [[TMP13]]2163;2164entry:2165 %0 = bitcast <1 x i64> %b to <8 x i8>2166 %1 = bitcast <1 x i64> %a to <8 x i8>2167 %mmx_var.i = bitcast <8 x i8> %1 to <1 x i64>2168 %mmx_var1.i = bitcast <8 x i8> %0 to <1 x i64>2169 %2 = tail call <1 x i64> @llvm.x86.mmx.paddus.b(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind2170 %3 = bitcast <1 x i64> %2 to <8 x i8>2171 %4 = bitcast <8 x i8> %3 to <1 x i64>2172 %5 = extractelement <1 x i64> %4, i32 02173 ret i64 %52174}2175 2176declare <1 x i64> @llvm.x86.mmx.padds.w(<1 x i64>, <1 x i64>) nounwind readnone2177 2178define i64 @test38(<1 x i64> %a, <1 x i64> %b) #0 {2179; CHECK-LABEL: define i64 @test38(2180; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {2181; CHECK-NEXT: entry:2182; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82183; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82184; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 82185; CHECK-NEXT: call void @llvm.donothing()2186; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <4 x i16>2187; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>2188; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <4 x i16>2189; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>2190; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP14]] to <1 x i64>2191; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>2192; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>2193; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>2194; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]2195; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.padds.w(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]2196; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>2197; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <4 x i16>2198; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP9]] to <1 x i64>2199; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i16> [[TMP16]] to <1 x i64>2200; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 02201; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 02202; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 82203; CHECK-NEXT: ret i64 [[TMP13]]2204;2205entry:2206 %0 = bitcast <1 x i64> %b to <4 x i16>2207 %1 = bitcast <1 x i64> %a to <4 x i16>2208 %mmx_var.i = bitcast <4 x i16> %1 to <1 x i64>2209 %mmx_var1.i = bitcast <4 x i16> %0 to <1 x i64>2210 %2 = tail call <1 x i64> @llvm.x86.mmx.padds.w(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind2211 %3 = bitcast <1 x i64> %2 to <4 x i16>2212 %4 = bitcast <4 x i16> %3 to <1 x i64>2213 %5 = extractelement <1 x i64> %4, i32 02214 ret i64 %52215}2216 2217declare <1 x i64> @llvm.x86.mmx.padds.b(<1 x i64>, <1 x i64>) nounwind readnone2218 2219define i64 @test37(<1 x i64> %a, <1 x i64> %b) #0 {2220; CHECK-LABEL: define i64 @test37(2221; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {2222; CHECK-NEXT: entry:2223; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82224; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82225; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 82226; CHECK-NEXT: call void @llvm.donothing()2227; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <8 x i8>2228; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>2229; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <8 x i8>2230; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>2231; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP14]] to <1 x i64>2232; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>2233; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP11]] to <1 x i64>2234; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>2235; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]2236; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.padds.b(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]2237; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <8 x i8>2238; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <8 x i8>2239; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP9]] to <1 x i64>2240; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x i8> [[TMP16]] to <1 x i64>2241; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 02242; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 02243; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 82244; CHECK-NEXT: ret i64 [[TMP13]]2245;2246entry:2247 %0 = bitcast <1 x i64> %b to <8 x i8>2248 %1 = bitcast <1 x i64> %a to <8 x i8>2249 %mmx_var.i = bitcast <8 x i8> %1 to <1 x i64>2250 %mmx_var1.i = bitcast <8 x i8> %0 to <1 x i64>2251 %2 = tail call <1 x i64> @llvm.x86.mmx.padds.b(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind2252 %3 = bitcast <1 x i64> %2 to <8 x i8>2253 %4 = bitcast <8 x i8> %3 to <1 x i64>2254 %5 = extractelement <1 x i64> %4, i32 02255 ret i64 %52256}2257 2258declare <1 x i64> @llvm.x86.mmx.padd.q(<1 x i64>, <1 x i64>) nounwind readnone2259 2260define i64 @test36(<1 x i64> %a, <1 x i64> %b) #0 {2261; CHECK-LABEL: define i64 @test36(2262; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {2263; CHECK-NEXT: entry:2264; CHECK-NEXT: [[TMP4:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82265; CHECK-NEXT: [[TMP5:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82266; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 82267; CHECK-NEXT: call void @llvm.donothing()2268; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <1 x i64> [[TMP4]], i32 02269; CHECK-NEXT: [[TMP0:%.*]] = extractelement <1 x i64> [[A]], i32 02270; CHECK-NEXT: [[TMP7:%.*]] = bitcast i64 [[_MSPROP]] to <1 x i64>2271; CHECK-NEXT: [[MMX_VAR:%.*]] = bitcast i64 [[TMP0]] to <1 x i64>2272; CHECK-NEXT: [[_MSPROP1:%.*]] = extractelement <1 x i64> [[TMP5]], i32 02273; CHECK-NEXT: [[TMP1:%.*]] = extractelement <1 x i64> [[B]], i32 02274; CHECK-NEXT: [[TMP8:%.*]] = bitcast i64 [[_MSPROP1]] to <1 x i64>2275; CHECK-NEXT: [[MMX_VAR1:%.*]] = bitcast i64 [[TMP1]] to <1 x i64>2276; CHECK-NEXT: [[_MSPROP3:%.*]] = or <1 x i64> [[TMP7]], [[TMP8]]2277; CHECK-NEXT: [[TMP6:%.*]] = tail call <1 x i64> @llvm.x86.mmx.padd.q(<1 x i64> [[MMX_VAR]], <1 x i64> [[MMX_VAR1]])2278; CHECK-NEXT: [[_MSPROP2:%.*]] = bitcast <1 x i64> [[_MSPROP3]] to i642279; CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[TMP6]] to i642280; CHECK-NEXT: store i64 [[_MSPROP2]], ptr @__msan_retval_tls, align 82281; CHECK-NEXT: ret i64 [[TMP3]]2282;2283entry:2284 %0 = extractelement <1 x i64> %a, i32 02285 %mmx_var = bitcast i64 %0 to <1 x i64>2286 %1 = extractelement <1 x i64> %b, i32 02287 %mmx_var1 = bitcast i64 %1 to <1 x i64>2288 %2 = tail call <1 x i64> @llvm.x86.mmx.padd.q(<1 x i64> %mmx_var, <1 x i64> %mmx_var1)2289 %3 = bitcast <1 x i64> %2 to i642290 ret i64 %32291}2292 2293declare <1 x i64> @llvm.x86.mmx.padd.d(<1 x i64>, <1 x i64>) nounwind readnone2294 2295define i64 @test35(<1 x i64> %a, <1 x i64> %b) #0 {2296; CHECK-LABEL: define i64 @test35(2297; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {2298; CHECK-NEXT: entry:2299; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82300; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82301; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 82302; CHECK-NEXT: call void @llvm.donothing()2303; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <2 x i32>2304; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <2 x i32>2305; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <2 x i32>2306; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>2307; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i32> [[TMP14]] to <1 x i64>2308; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <2 x i32> [[TMP1]] to <1 x i64>2309; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i32> [[TMP11]] to <1 x i64>2310; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>2311; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]2312; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.padd.d(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]2313; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <2 x i32>2314; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <2 x i32>2315; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP9]] to <1 x i64>2316; CHECK-NEXT: [[TMP12:%.*]] = bitcast <2 x i32> [[TMP16]] to <1 x i64>2317; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 02318; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 02319; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 82320; CHECK-NEXT: ret i64 [[TMP13]]2321;2322entry:2323 %0 = bitcast <1 x i64> %b to <2 x i32>2324 %1 = bitcast <1 x i64> %a to <2 x i32>2325 %mmx_var.i = bitcast <2 x i32> %1 to <1 x i64>2326 %mmx_var1.i = bitcast <2 x i32> %0 to <1 x i64>2327 %2 = tail call <1 x i64> @llvm.x86.mmx.padd.d(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind2328 %3 = bitcast <1 x i64> %2 to <2 x i32>2329 %4 = bitcast <2 x i32> %3 to <1 x i64>2330 %5 = extractelement <1 x i64> %4, i32 02331 ret i64 %52332}2333 2334declare <1 x i64> @llvm.x86.mmx.padd.w(<1 x i64>, <1 x i64>) nounwind readnone2335 2336define i64 @test34(<1 x i64> %a, <1 x i64> %b) #0 {2337; CHECK-LABEL: define i64 @test34(2338; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {2339; CHECK-NEXT: entry:2340; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82341; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82342; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 82343; CHECK-NEXT: call void @llvm.donothing()2344; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <4 x i16>2345; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>2346; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <4 x i16>2347; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>2348; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP14]] to <1 x i64>2349; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>2350; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>2351; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>2352; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]2353; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.padd.w(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]2354; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>2355; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <4 x i16>2356; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP9]] to <1 x i64>2357; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i16> [[TMP16]] to <1 x i64>2358; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 02359; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 02360; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 82361; CHECK-NEXT: ret i64 [[TMP13]]2362;2363entry:2364 %0 = bitcast <1 x i64> %b to <4 x i16>2365 %1 = bitcast <1 x i64> %a to <4 x i16>2366 %mmx_var.i = bitcast <4 x i16> %1 to <1 x i64>2367 %mmx_var1.i = bitcast <4 x i16> %0 to <1 x i64>2368 %2 = tail call <1 x i64> @llvm.x86.mmx.padd.w(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind2369 %3 = bitcast <1 x i64> %2 to <4 x i16>2370 %4 = bitcast <4 x i16> %3 to <1 x i64>2371 %5 = extractelement <1 x i64> %4, i32 02372 ret i64 %52373}2374 2375declare <1 x i64> @llvm.x86.mmx.padd.b(<1 x i64>, <1 x i64>) nounwind readnone2376 2377define i64 @test33(<1 x i64> %a, <1 x i64> %b) #0 {2378; CHECK-LABEL: define i64 @test33(2379; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {2380; CHECK-NEXT: entry:2381; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82382; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82383; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 82384; CHECK-NEXT: call void @llvm.donothing()2385; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <8 x i8>2386; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>2387; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <8 x i8>2388; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>2389; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP14]] to <1 x i64>2390; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>2391; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP11]] to <1 x i64>2392; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>2393; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]2394; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.padd.b(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]2395; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <8 x i8>2396; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <8 x i8>2397; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP9]] to <1 x i64>2398; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x i8> [[TMP16]] to <1 x i64>2399; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 02400; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 02401; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 82402; CHECK-NEXT: ret i64 [[TMP13]]2403;2404entry:2405 %0 = bitcast <1 x i64> %b to <8 x i8>2406 %1 = bitcast <1 x i64> %a to <8 x i8>2407 %mmx_var.i = bitcast <8 x i8> %1 to <1 x i64>2408 %mmx_var1.i = bitcast <8 x i8> %0 to <1 x i64>2409 %2 = tail call <1 x i64> @llvm.x86.mmx.padd.b(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind2410 %3 = bitcast <1 x i64> %2 to <8 x i8>2411 %4 = bitcast <8 x i8> %3 to <1 x i64>2412 %5 = extractelement <1 x i64> %4, i32 02413 ret i64 %52414}2415 2416declare <1 x i64> @llvm.x86.mmx.psad.bw(<1 x i64>, <1 x i64>) nounwind readnone2417 2418define i64 @test32(<1 x i64> %a, <1 x i64> %b) #0 {2419; CHECK-LABEL: define i64 @test32(2420; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {2421; CHECK-NEXT: entry:2422; CHECK-NEXT: [[TMP5:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82423; CHECK-NEXT: [[TMP12:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82424; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 82425; CHECK-NEXT: call void @llvm.donothing()2426; CHECK-NEXT: [[TMP13:%.*]] = bitcast <1 x i64> [[TMP5]] to <8 x i8>2427; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>2428; CHECK-NEXT: [[TMP4:%.*]] = bitcast <1 x i64> [[TMP12]] to <8 x i8>2429; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>2430; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP4]] to <1 x i64>2431; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>2432; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP13]] to <1 x i64>2433; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>2434; CHECK-NEXT: [[TMP16:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]2435; CHECK-NEXT: [[TMP8:%.*]] = bitcast <1 x i64> [[TMP16]] to i642436; CHECK-NEXT: [[TMP9:%.*]] = icmp ne i64 [[TMP8]], 02437; CHECK-NEXT: [[TMP10:%.*]] = sext i1 [[TMP9]] to i642438; CHECK-NEXT: [[TMP11:%.*]] = lshr i64 [[TMP10]], 482439; CHECK-NEXT: [[TMP17:%.*]] = bitcast i64 [[TMP11]] to <1 x i64>2440; CHECK-NEXT: [[TMP14:%.*]] = tail call <1 x i64> @llvm.x86.mmx.psad.bw(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]2441; CHECK-NEXT: [[TMP15:%.*]] = bitcast <1 x i64> [[TMP17]] to i642442; CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[TMP14]] to i642443; CHECK-NEXT: store i64 [[TMP15]], ptr @__msan_retval_tls, align 82444; CHECK-NEXT: ret i64 [[TMP3]]2445;2446entry:2447 %0 = bitcast <1 x i64> %b to <8 x i8>2448 %1 = bitcast <1 x i64> %a to <8 x i8>2449 %mmx_var.i = bitcast <8 x i8> %1 to <1 x i64>2450 %mmx_var1.i = bitcast <8 x i8> %0 to <1 x i64>2451 %2 = tail call <1 x i64> @llvm.x86.mmx.psad.bw(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind2452 %3 = bitcast <1 x i64> %2 to i642453 ret i64 %32454}2455 2456declare <1 x i64> @llvm.x86.mmx.pmins.w(<1 x i64>, <1 x i64>) nounwind readnone2457 2458define i64 @test31(<1 x i64> %a, <1 x i64> %b) #0 {2459; CHECK-LABEL: define i64 @test31(2460; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {2461; CHECK-NEXT: entry:2462; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82463; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82464; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 82465; CHECK-NEXT: call void @llvm.donothing()2466; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <4 x i16>2467; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>2468; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <4 x i16>2469; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>2470; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP14]] to <1 x i64>2471; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>2472; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>2473; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>2474; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]2475; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pmins.w(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]2476; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>2477; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <4 x i16>2478; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP9]] to <1 x i64>2479; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i16> [[TMP16]] to <1 x i64>2480; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 02481; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 02482; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 82483; CHECK-NEXT: ret i64 [[TMP13]]2484;2485entry:2486 %0 = bitcast <1 x i64> %b to <4 x i16>2487 %1 = bitcast <1 x i64> %a to <4 x i16>2488 %mmx_var.i = bitcast <4 x i16> %1 to <1 x i64>2489 %mmx_var1.i = bitcast <4 x i16> %0 to <1 x i64>2490 %2 = tail call <1 x i64> @llvm.x86.mmx.pmins.w(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind2491 %3 = bitcast <1 x i64> %2 to <4 x i16>2492 %4 = bitcast <4 x i16> %3 to <1 x i64>2493 %5 = extractelement <1 x i64> %4, i32 02494 ret i64 %52495}2496 2497declare <1 x i64> @llvm.x86.mmx.pminu.b(<1 x i64>, <1 x i64>) nounwind readnone2498 2499define i64 @test30(<1 x i64> %a, <1 x i64> %b) #0 {2500; CHECK-LABEL: define i64 @test30(2501; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {2502; CHECK-NEXT: entry:2503; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82504; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82505; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 82506; CHECK-NEXT: call void @llvm.donothing()2507; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <8 x i8>2508; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>2509; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <8 x i8>2510; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>2511; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP14]] to <1 x i64>2512; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>2513; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP11]] to <1 x i64>2514; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>2515; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]2516; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pminu.b(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]2517; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <8 x i8>2518; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <8 x i8>2519; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP9]] to <1 x i64>2520; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x i8> [[TMP16]] to <1 x i64>2521; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 02522; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 02523; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 82524; CHECK-NEXT: ret i64 [[TMP13]]2525;2526entry:2527 %0 = bitcast <1 x i64> %b to <8 x i8>2528 %1 = bitcast <1 x i64> %a to <8 x i8>2529 %mmx_var.i = bitcast <8 x i8> %1 to <1 x i64>2530 %mmx_var1.i = bitcast <8 x i8> %0 to <1 x i64>2531 %2 = tail call <1 x i64> @llvm.x86.mmx.pminu.b(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind2532 %3 = bitcast <1 x i64> %2 to <8 x i8>2533 %4 = bitcast <8 x i8> %3 to <1 x i64>2534 %5 = extractelement <1 x i64> %4, i32 02535 ret i64 %52536}2537 2538declare <1 x i64> @llvm.x86.mmx.pmaxs.w(<1 x i64>, <1 x i64>) nounwind readnone2539 2540define i64 @test29(<1 x i64> %a, <1 x i64> %b) #0 {2541; CHECK-LABEL: define i64 @test29(2542; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {2543; CHECK-NEXT: entry:2544; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82545; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82546; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 82547; CHECK-NEXT: call void @llvm.donothing()2548; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <4 x i16>2549; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>2550; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <4 x i16>2551; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>2552; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP14]] to <1 x i64>2553; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>2554; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>2555; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>2556; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]2557; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pmaxs.w(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]2558; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>2559; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <4 x i16>2560; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP9]] to <1 x i64>2561; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i16> [[TMP16]] to <1 x i64>2562; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 02563; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 02564; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 82565; CHECK-NEXT: ret i64 [[TMP13]]2566;2567entry:2568 %0 = bitcast <1 x i64> %b to <4 x i16>2569 %1 = bitcast <1 x i64> %a to <4 x i16>2570 %mmx_var.i = bitcast <4 x i16> %1 to <1 x i64>2571 %mmx_var1.i = bitcast <4 x i16> %0 to <1 x i64>2572 %2 = tail call <1 x i64> @llvm.x86.mmx.pmaxs.w(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind2573 %3 = bitcast <1 x i64> %2 to <4 x i16>2574 %4 = bitcast <4 x i16> %3 to <1 x i64>2575 %5 = extractelement <1 x i64> %4, i32 02576 ret i64 %52577}2578 2579declare <1 x i64> @llvm.x86.mmx.pmaxu.b(<1 x i64>, <1 x i64>) nounwind readnone2580 2581define i64 @test28(<1 x i64> %a, <1 x i64> %b) #0 {2582; CHECK-LABEL: define i64 @test28(2583; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {2584; CHECK-NEXT: entry:2585; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82586; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82587; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 82588; CHECK-NEXT: call void @llvm.donothing()2589; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <8 x i8>2590; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>2591; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <8 x i8>2592; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>2593; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP14]] to <1 x i64>2594; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>2595; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP11]] to <1 x i64>2596; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>2597; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]2598; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pmaxu.b(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]2599; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <8 x i8>2600; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <8 x i8>2601; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP9]] to <1 x i64>2602; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x i8> [[TMP16]] to <1 x i64>2603; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 02604; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 02605; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 82606; CHECK-NEXT: ret i64 [[TMP13]]2607;2608entry:2609 %0 = bitcast <1 x i64> %b to <8 x i8>2610 %1 = bitcast <1 x i64> %a to <8 x i8>2611 %mmx_var.i = bitcast <8 x i8> %1 to <1 x i64>2612 %mmx_var1.i = bitcast <8 x i8> %0 to <1 x i64>2613 %2 = tail call <1 x i64> @llvm.x86.mmx.pmaxu.b(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind2614 %3 = bitcast <1 x i64> %2 to <8 x i8>2615 %4 = bitcast <8 x i8> %3 to <1 x i64>2616 %5 = extractelement <1 x i64> %4, i32 02617 ret i64 %52618}2619 2620declare <1 x i64> @llvm.x86.mmx.pavg.w(<1 x i64>, <1 x i64>) nounwind readnone2621 2622define i64 @test27(<1 x i64> %a, <1 x i64> %b) #0 {2623; CHECK-LABEL: define i64 @test27(2624; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {2625; CHECK-NEXT: entry:2626; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82627; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82628; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 82629; CHECK-NEXT: call void @llvm.donothing()2630; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <4 x i16>2631; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>2632; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <4 x i16>2633; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>2634; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP14]] to <1 x i64>2635; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>2636; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>2637; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>2638; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]2639; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pavg.w(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]2640; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>2641; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <4 x i16>2642; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP9]] to <1 x i64>2643; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i16> [[TMP16]] to <1 x i64>2644; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 02645; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 02646; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 82647; CHECK-NEXT: ret i64 [[TMP13]]2648;2649entry:2650 %0 = bitcast <1 x i64> %b to <4 x i16>2651 %1 = bitcast <1 x i64> %a to <4 x i16>2652 %mmx_var.i = bitcast <4 x i16> %1 to <1 x i64>2653 %mmx_var1.i = bitcast <4 x i16> %0 to <1 x i64>2654 %2 = tail call <1 x i64> @llvm.x86.mmx.pavg.w(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind2655 %3 = bitcast <1 x i64> %2 to <4 x i16>2656 %4 = bitcast <4 x i16> %3 to <1 x i64>2657 %5 = extractelement <1 x i64> %4, i32 02658 ret i64 %52659}2660 2661declare <1 x i64> @llvm.x86.mmx.pavg.b(<1 x i64>, <1 x i64>) nounwind readnone2662 2663define i64 @test26(<1 x i64> %a, <1 x i64> %b) #0 {2664; CHECK-LABEL: define i64 @test26(2665; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {2666; CHECK-NEXT: entry:2667; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82668; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82669; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 82670; CHECK-NEXT: call void @llvm.donothing()2671; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <8 x i8>2672; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>2673; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <8 x i8>2674; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>2675; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP14]] to <1 x i64>2676; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>2677; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP11]] to <1 x i64>2678; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>2679; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]2680; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pavg.b(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]2681; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <8 x i8>2682; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <8 x i8>2683; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP9]] to <1 x i64>2684; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x i8> [[TMP16]] to <1 x i64>2685; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 02686; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 02687; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 82688; CHECK-NEXT: ret i64 [[TMP13]]2689;2690entry:2691 %0 = bitcast <1 x i64> %b to <8 x i8>2692 %1 = bitcast <1 x i64> %a to <8 x i8>2693 %mmx_var.i = bitcast <8 x i8> %1 to <1 x i64>2694 %mmx_var1.i = bitcast <8 x i8> %0 to <1 x i64>2695 %2 = tail call <1 x i64> @llvm.x86.mmx.pavg.b(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind2696 %3 = bitcast <1 x i64> %2 to <8 x i8>2697 %4 = bitcast <8 x i8> %3 to <1 x i64>2698 %5 = extractelement <1 x i64> %4, i32 02699 ret i64 %52700}2701 2702declare void @llvm.x86.mmx.movnt.dq(ptr, <1 x i64>) nounwind2703 2704define void @test25(ptr %p, <1 x i64> %a) nounwind optsize ssp #0 {2705; CHECK-LABEL: define void @test25(2706; CHECK-SAME: ptr [[P:%.*]], <1 x i64> [[A:%.*]]) #[[ATTR3:[0-9]+]] {2707; CHECK-NEXT: entry:2708; CHECK-NEXT: [[TMP2:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82709; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82710; CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 82711; CHECK-NEXT: call void @llvm.donothing()2712; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <1 x i64> [[TMP2]], i32 02713; CHECK-NEXT: [[TMP0:%.*]] = extractelement <1 x i64> [[A]], i32 02714; CHECK-NEXT: [[TMP3:%.*]] = bitcast i64 [[_MSPROP]] to <1 x i64>2715; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast i64 [[TMP0]] to <1 x i64>2716; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P]] to i642717; CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], -21474836492718; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr2719; CHECK-NEXT: store <1 x i64> [[TMP3]], ptr [[TMP6]], align 12720; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02721; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1:![0-9]+]]2722; CHECK: 8:2723; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6:[0-9]+]]2724; CHECK-NEXT: unreachable2725; CHECK: 9:2726; CHECK-NEXT: tail call void @llvm.x86.mmx.movnt.dq(ptr [[P]], <1 x i64> [[MMX_VAR_I]]) #[[ATTR2]]2727; CHECK-NEXT: ret void2728;2729entry:2730 %0 = extractelement <1 x i64> %a, i32 02731 %mmx_var.i = bitcast i64 %0 to <1 x i64>2732 tail call void @llvm.x86.mmx.movnt.dq(ptr %p, <1 x i64> %mmx_var.i) nounwind2733 ret void2734}2735 2736declare i32 @llvm.x86.mmx.pmovmskb(<1 x i64>) nounwind readnone2737 2738define i32 @test24(<1 x i64> %a) #0 {2739; CHECK-LABEL: define i32 @test24(2740; CHECK-SAME: <1 x i64> [[A:%.*]]) #[[ATTR1]] {2741; CHECK-NEXT: entry:2742; CHECK-NEXT: [[TMP2:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82743; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 82744; CHECK-NEXT: call void @llvm.donothing()2745; CHECK-NEXT: [[TMP6:%.*]] = bitcast <1 x i64> [[TMP2]] to <8 x i8>2746; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>2747; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP6]] to <1 x i64>2748; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>2749; CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[TMP4]] to i642750; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP3]], 02751; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP8:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]2752; CHECK: 6:2753; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]2754; CHECK-NEXT: unreachable2755; CHECK: 7:2756; CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.x86.mmx.pmovmskb(<1 x i64> [[MMX_VAR_I]]) #[[ATTR2]]2757; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 82758; CHECK-NEXT: ret i32 [[TMP1]]2759;2760entry:2761 %0 = bitcast <1 x i64> %a to <8 x i8>2762 %mmx_var.i = bitcast <8 x i8> %0 to <1 x i64>2763 %1 = tail call i32 @llvm.x86.mmx.pmovmskb(<1 x i64> %mmx_var.i) nounwind2764 ret i32 %12765}2766 2767declare void @llvm.x86.mmx.maskmovq(<1 x i64>, <1 x i64>, ptr) nounwind2768 2769define void @test23(<1 x i64> %d, <1 x i64> %n, ptr %p) nounwind optsize ssp #0 {2770; CHECK-LABEL: define void @test23(2771; CHECK-SAME: <1 x i64> [[D:%.*]], <1 x i64> [[N:%.*]], ptr [[P:%.*]]) #[[ATTR3]] {2772; CHECK-NEXT: entry:2773; CHECK-NEXT: [[TMP4:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82774; CHECK-NEXT: [[TMP6:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82775; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 82776; CHECK-NEXT: [[TMP11:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 82777; CHECK-NEXT: call void @llvm.donothing()2778; CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[TMP4]] to <8 x i8>2779; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[N]] to <8 x i8>2780; CHECK-NEXT: [[TMP5:%.*]] = bitcast <1 x i64> [[TMP6]] to <8 x i8>2781; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[D]] to <8 x i8>2782; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i8> [[TMP5]] to <1 x i64>2783; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>2784; CHECK-NEXT: [[TMP10:%.*]] = bitcast <8 x i8> [[TMP3]] to <1 x i64>2785; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>2786; CHECK-NEXT: [[TMP7:%.*]] = bitcast <1 x i64> [[TMP9]] to i642787; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP7]], 02788; CHECK-NEXT: [[TMP8:%.*]] = bitcast <1 x i64> [[TMP10]] to i642789; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP8]], 02790; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]2791; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 02792; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]]2793; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP12:%.*]], label [[TMP13:%.*]], !prof [[PROF1]]2794; CHECK: 12:2795; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]2796; CHECK-NEXT: unreachable2797; CHECK: 13:2798; CHECK-NEXT: tail call void @llvm.x86.mmx.maskmovq(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]], ptr [[P]]) #[[ATTR2]]2799; CHECK-NEXT: ret void2800;2801entry:2802 %0 = bitcast <1 x i64> %n to <8 x i8>2803 %1 = bitcast <1 x i64> %d to <8 x i8>2804 %mmx_var.i = bitcast <8 x i8> %1 to <1 x i64>2805 %mmx_var1.i = bitcast <8 x i8> %0 to <1 x i64>2806 tail call void @llvm.x86.mmx.maskmovq(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i, ptr %p) nounwind2807 ret void2808}2809 2810declare <1 x i64> @llvm.x86.mmx.pmulhu.w(<1 x i64>, <1 x i64>) nounwind readnone2811 2812define i64 @test22(<1 x i64> %a, <1 x i64> %b) #0 {2813; CHECK-LABEL: define i64 @test22(2814; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {2815; CHECK-NEXT: entry:2816; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82817; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82818; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 82819; CHECK-NEXT: call void @llvm.donothing()2820; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP8]] to <4 x i16>2821; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>2822; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP10]] to <4 x i16>2823; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>2824; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP14]] to <1 x i64>2825; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>2826; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>2827; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>2828; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]2829; CHECK-NEXT: [[TMP15:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pmulhu.w(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]2830; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>2831; CHECK-NEXT: [[TMP16:%.*]] = bitcast <1 x i64> [[TMP15]] to <4 x i16>2832; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP9]] to <1 x i64>2833; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i16> [[TMP16]] to <1 x i64>2834; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 02835; CHECK-NEXT: [[TMP13:%.*]] = extractelement <1 x i64> [[TMP12]], i32 02836; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 82837; CHECK-NEXT: ret i64 [[TMP13]]2838;2839entry:2840 %0 = bitcast <1 x i64> %b to <4 x i16>2841 %1 = bitcast <1 x i64> %a to <4 x i16>2842 %mmx_var.i = bitcast <4 x i16> %1 to <1 x i64>2843 %mmx_var1.i = bitcast <4 x i16> %0 to <1 x i64>2844 %2 = tail call <1 x i64> @llvm.x86.mmx.pmulhu.w(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind2845 %3 = bitcast <1 x i64> %2 to <4 x i16>2846 %4 = bitcast <4 x i16> %3 to <1 x i64>2847 %5 = extractelement <1 x i64> %4, i32 02848 ret i64 %52849}2850 2851declare <1 x i64> @llvm.x86.sse.pshuf.w(<1 x i64>, i8) nounwind readnone2852 2853define i64 @test21(<1 x i64> %a) #0 {2854; CHECK-LABEL: define i64 @test21(2855; CHECK-SAME: <1 x i64> [[A:%.*]]) #[[ATTR1]] {2856; CHECK-NEXT: entry:2857; CHECK-NEXT: [[TMP7:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82858; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 82859; CHECK-NEXT: call void @llvm.donothing()2860; CHECK-NEXT: [[TMP8:%.*]] = bitcast <1 x i64> [[TMP7]] to <4 x i16>2861; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>2862; CHECK-NEXT: [[TMP10:%.*]] = bitcast <4 x i16> [[TMP8]] to <1 x i64>2863; CHECK-NEXT: [[TMP11:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>2864; CHECK-NEXT: [[TMP6:%.*]] = call <1 x i64> @llvm.x86.sse.pshuf.w(<1 x i64> [[TMP10]], i8 3)2865; CHECK-NEXT: [[TMP13:%.*]] = or <1 x i64> zeroinitializer, [[TMP6]]2866; CHECK-NEXT: [[TMP14:%.*]] = tail call <1 x i64> @llvm.x86.sse.pshuf.w(<1 x i64> [[TMP11]], i8 3) #[[ATTR5]]2867; CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[TMP13]] to <4 x i16>2868; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[TMP14]] to <4 x i16>2869; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP3]] to <1 x i64>2870; CHECK-NEXT: [[TMP15:%.*]] = bitcast <4 x i16> [[TMP9]] to <1 x i64>2871; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 02872; CHECK-NEXT: [[TMP12:%.*]] = extractelement <1 x i64> [[TMP15]], i32 02873; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 82874; CHECK-NEXT: ret i64 [[TMP12]]2875;2876entry:2877 %0 = bitcast <1 x i64> %a to <4 x i16>2878 %1 = bitcast <4 x i16> %0 to <1 x i64>2879 %2 = tail call <1 x i64> @llvm.x86.sse.pshuf.w(<1 x i64> %1, i8 3) nounwind readnone2880 %3 = bitcast <1 x i64> %2 to <4 x i16>2881 %4 = bitcast <4 x i16> %3 to <1 x i64>2882 %5 = extractelement <1 x i64> %4, i32 02883 ret i64 %52884}2885 2886define i32 @test21_2(<1 x i64> %a) #0 {2887; CHECK-LABEL: define i32 @test21_2(2888; CHECK-SAME: <1 x i64> [[A:%.*]]) #[[ATTR1]] {2889; CHECK-NEXT: entry:2890; CHECK-NEXT: [[TMP7:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82891; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 82892; CHECK-NEXT: call void @llvm.donothing()2893; CHECK-NEXT: [[TMP8:%.*]] = bitcast <1 x i64> [[TMP7]] to <4 x i16>2894; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>2895; CHECK-NEXT: [[TMP10:%.*]] = bitcast <4 x i16> [[TMP8]] to <1 x i64>2896; CHECK-NEXT: [[TMP11:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>2897; CHECK-NEXT: [[TMP6:%.*]] = call <1 x i64> @llvm.x86.sse.pshuf.w(<1 x i64> [[TMP10]], i8 3)2898; CHECK-NEXT: [[TMP13:%.*]] = or <1 x i64> zeroinitializer, [[TMP6]]2899; CHECK-NEXT: [[TMP14:%.*]] = tail call <1 x i64> @llvm.x86.sse.pshuf.w(<1 x i64> [[TMP11]], i8 3) #[[ATTR5]]2900; CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[TMP13]] to <4 x i16>2901; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[TMP14]] to <4 x i16>2902; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP3]] to <2 x i32>2903; CHECK-NEXT: [[TMP15:%.*]] = bitcast <4 x i16> [[TMP9]] to <2 x i32>2904; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i32> [[TMP4]], i32 02905; CHECK-NEXT: [[TMP12:%.*]] = extractelement <2 x i32> [[TMP15]], i32 02906; CHECK-NEXT: store i32 [[TMP5]], ptr @__msan_retval_tls, align 82907; CHECK-NEXT: ret i32 [[TMP12]]2908;2909entry:2910 %0 = bitcast <1 x i64> %a to <4 x i16>2911 %1 = bitcast <4 x i16> %0 to <1 x i64>2912 %2 = tail call <1 x i64> @llvm.x86.sse.pshuf.w(<1 x i64> %1, i8 3) nounwind readnone2913 %3 = bitcast <1 x i64> %2 to <4 x i16>2914 %4 = bitcast <4 x i16> %3 to <2 x i32>2915 %5 = extractelement <2 x i32> %4, i32 02916 ret i32 %52917}2918 2919declare <1 x i64> @llvm.x86.mmx.pmulu.dq(<1 x i64>, <1 x i64>) nounwind readnone2920 2921define i64 @test20(<1 x i64> %a, <1 x i64> %b) #0 {2922; CHECK-LABEL: define i64 @test20(2923; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {2924; CHECK-NEXT: entry:2925; CHECK-NEXT: [[TMP5:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82926; CHECK-NEXT: [[TMP8:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82927; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 82928; CHECK-NEXT: call void @llvm.donothing()2929; CHECK-NEXT: [[TMP9:%.*]] = bitcast <1 x i64> [[TMP5]] to <2 x i32>2930; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <2 x i32>2931; CHECK-NEXT: [[TMP4:%.*]] = bitcast <1 x i64> [[TMP8]] to <2 x i32>2932; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>2933; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i32> [[TMP4]] to <1 x i64>2934; CHECK-NEXT: [[MMX_VAR_I:%.*]] = bitcast <2 x i32> [[TMP1]] to <1 x i64>2935; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i32> [[TMP9]] to <1 x i64>2936; CHECK-NEXT: [[MMX_VAR1_I:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>2937; CHECK-NEXT: [[_MSPROP1:%.*]] = or <1 x i64> [[TMP6]], [[TMP7]]2938; CHECK-NEXT: [[TMP10:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pmulu.dq(<1 x i64> [[MMX_VAR_I]], <1 x i64> [[MMX_VAR1_I]]) #[[ATTR2]]2939; CHECK-NEXT: [[_MSPROP:%.*]] = bitcast <1 x i64> [[_MSPROP1]] to i642940; CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[TMP10]] to i642941; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 82942; CHECK-NEXT: ret i64 [[TMP3]]2943;2944entry:2945 %0 = bitcast <1 x i64> %b to <2 x i32>2946 %1 = bitcast <1 x i64> %a to <2 x i32>2947 %mmx_var.i = bitcast <2 x i32> %1 to <1 x i64>2948 %mmx_var1.i = bitcast <2 x i32> %0 to <1 x i64>2949 %2 = tail call <1 x i64> @llvm.x86.mmx.pmulu.dq(<1 x i64> %mmx_var.i, <1 x i64> %mmx_var1.i) nounwind2950 %3 = bitcast <1 x i64> %2 to i642951 ret i64 %32952}2953 2954declare <2 x double> @llvm.x86.sse.cvtpi2pd(<1 x i64>) nounwind readnone2955 2956define <2 x double> @test19(<1 x i64> %a) #0 {2957; CHECK-LABEL: define <2 x double> @test19(2958; CHECK-SAME: <1 x i64> [[A:%.*]]) #[[ATTR1]] {2959; CHECK-NEXT: entry:2960; CHECK-NEXT: [[TMP4:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 82961; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 82962; CHECK-NEXT: call void @llvm.donothing()2963; CHECK-NEXT: [[TMP7:%.*]] = bitcast <1 x i64> [[TMP4]] to <2 x i32>2964; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>2965; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i32> [[TMP7]] to <1 x i64>2966; CHECK-NEXT: [[TMP8:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>2967; CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[TMP5]] to i642968; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP3]], 02969; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP9:%.*]], label [[TMP10:%.*]], !prof [[PROF1]]2970; CHECK: 7:2971; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]2972; CHECK-NEXT: unreachable2973; CHECK: 8:2974; CHECK-NEXT: [[TMP2:%.*]] = tail call <2 x double> @llvm.x86.sse.cvtpi2pd(<1 x i64> [[TMP8]]) #[[ATTR5]]2975; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 82976; CHECK-NEXT: ret <2 x double> [[TMP2]]2977;2978entry:2979 %0 = bitcast <1 x i64> %a to <2 x i32>2980 %1 = bitcast <2 x i32> %0 to <1 x i64>2981 %2 = tail call <2 x double> @llvm.x86.sse.cvtpi2pd(<1 x i64> %1) nounwind readnone2982 ret <2 x double> %22983}2984 2985declare <1 x i64> @llvm.x86.sse.cvttpd2pi(<2 x double>) nounwind readnone2986 2987define i64 @test18(<2 x double> %a) #0 {2988; CHECK-LABEL: define i64 @test18(2989; CHECK-SAME: <2 x double> [[A:%.*]]) #[[ATTR1]] {2990; CHECK-NEXT: entry:2991; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 82992; CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 82993; CHECK-NEXT: call void @llvm.donothing()2994; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to i1282995; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 02996; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP7:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]2997; CHECK: 3:2998; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]2999; CHECK-NEXT: unreachable3000; CHECK: 4:3001; CHECK-NEXT: [[TMP8:%.*]] = tail call <1 x i64> @llvm.x86.sse.cvttpd2pi(<2 x double> [[A]]) #[[ATTR5]]3002; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[TMP8]] to <2 x i32>3003; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP1]] to <1 x i64>3004; CHECK-NEXT: [[TMP3:%.*]] = extractelement <1 x i64> [[TMP2]], i32 03005; CHECK-NEXT: store i64 0, ptr @__msan_retval_tls, align 83006; CHECK-NEXT: ret i64 [[TMP3]]3007;3008entry:3009 %0 = tail call <1 x i64> @llvm.x86.sse.cvttpd2pi(<2 x double> %a) nounwind readnone3010 %1 = bitcast <1 x i64> %0 to <2 x i32>3011 %2 = bitcast <2 x i32> %1 to <1 x i64>3012 %3 = extractelement <1 x i64> %2, i32 03013 ret i64 %33014}3015 3016declare <1 x i64> @llvm.x86.sse.cvtpd2pi(<2 x double>) nounwind readnone3017 3018define i64 @test17(<2 x double> %a) #0 {3019; CHECK-LABEL: define i64 @test17(3020; CHECK-SAME: <2 x double> [[A:%.*]]) #[[ATTR1]] {3021; CHECK-NEXT: entry:3022; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 83023; CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 83024; CHECK-NEXT: call void @llvm.donothing()3025; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to i1283026; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 03027; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP7:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]3028; CHECK: 3:3029; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3030; CHECK-NEXT: unreachable3031; CHECK: 4:3032; CHECK-NEXT: [[TMP8:%.*]] = tail call <1 x i64> @llvm.x86.sse.cvtpd2pi(<2 x double> [[A]]) #[[ATTR5]]3033; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[TMP8]] to <2 x i32>3034; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP1]] to <1 x i64>3035; CHECK-NEXT: [[TMP3:%.*]] = extractelement <1 x i64> [[TMP2]], i32 03036; CHECK-NEXT: store i64 0, ptr @__msan_retval_tls, align 83037; CHECK-NEXT: ret i64 [[TMP3]]3038;3039entry:3040 %0 = tail call <1 x i64> @llvm.x86.sse.cvtpd2pi(<2 x double> %a) nounwind readnone3041 %1 = bitcast <1 x i64> %0 to <2 x i32>3042 %2 = bitcast <2 x i32> %1 to <1 x i64>3043 %3 = extractelement <1 x i64> %2, i32 03044 ret i64 %33045}3046 3047declare <1 x i64> @llvm.x86.mmx.palignr.b(<1 x i64>, <1 x i64>, i8) nounwind readnone3048 3049define i64 @test16(<1 x i64> %a, <1 x i64> %b) #0 {3050; CHECK-LABEL: define i64 @test16(3051; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {3052; CHECK-NEXT: entry:3053; CHECK-NEXT: [[TMP6:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 83054; CHECK-NEXT: [[TMP7:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83055; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 83056; CHECK-NEXT: call void @llvm.donothing()3057; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <1 x i64> [[TMP6]], i32 03058; CHECK-NEXT: [[TMP0:%.*]] = extractelement <1 x i64> [[A]], i32 03059; CHECK-NEXT: [[TMP4:%.*]] = bitcast i64 [[_MSPROP]] to <1 x i64>3060; CHECK-NEXT: [[MMX_VAR:%.*]] = bitcast i64 [[TMP0]] to <1 x i64>3061; CHECK-NEXT: [[_MSPROP1:%.*]] = extractelement <1 x i64> [[TMP7]], i32 03062; CHECK-NEXT: [[TMP1:%.*]] = extractelement <1 x i64> [[B]], i32 03063; CHECK-NEXT: [[TMP5:%.*]] = bitcast i64 [[_MSPROP1]] to <1 x i64>3064; CHECK-NEXT: [[MMX_VAR1:%.*]] = bitcast i64 [[TMP1]] to <1 x i64>3065; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP4]] to i643066; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP11]], 03067; CHECK-NEXT: [[TMP12:%.*]] = bitcast <1 x i64> [[TMP5]] to i643068; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP12]], 03069; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP2]]3070; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP9:%.*]], label [[TMP13:%.*]], !prof [[PROF1]]3071; CHECK: 9:3072; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3073; CHECK-NEXT: unreachable3074; CHECK: 10:3075; CHECK-NEXT: [[TMP10:%.*]] = tail call <1 x i64> @llvm.x86.mmx.palignr.b(<1 x i64> [[MMX_VAR]], <1 x i64> [[MMX_VAR1]], i8 16)3076; CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[TMP10]] to i643077; CHECK-NEXT: store i64 0, ptr @__msan_retval_tls, align 83078; CHECK-NEXT: ret i64 [[TMP3]]3079;3080entry:3081 %0 = extractelement <1 x i64> %a, i32 03082 %mmx_var = bitcast i64 %0 to <1 x i64>3083 %1 = extractelement <1 x i64> %b, i32 03084 %mmx_var1 = bitcast i64 %1 to <1 x i64>3085 %2 = tail call <1 x i64> @llvm.x86.mmx.palignr.b(<1 x i64> %mmx_var, <1 x i64> %mmx_var1, i8 16)3086 %3 = bitcast <1 x i64> %2 to i643087 ret i64 %33088}3089 3090declare <1 x i64> @llvm.x86.ssse3.pabs.d(<1 x i64>) nounwind readnone3091 3092define i64 @test15(<1 x i64> %a) #0 {3093; CHECK-LABEL: define i64 @test15(3094; CHECK-SAME: <1 x i64> [[A:%.*]]) #[[ATTR1]] {3095; CHECK-NEXT: entry:3096; CHECK-NEXT: [[TMP7:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 83097; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 83098; CHECK-NEXT: call void @llvm.donothing()3099; CHECK-NEXT: [[TMP8:%.*]] = bitcast <1 x i64> [[TMP7]] to <2 x i32>3100; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>3101; CHECK-NEXT: [[TMP11:%.*]] = bitcast <2 x i32> [[TMP8]] to <1 x i64>3102; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>3103; CHECK-NEXT: [[TMP12:%.*]] = tail call <1 x i64> @llvm.x86.ssse3.pabs.d(<1 x i64> [[TMP1]]) #[[ATTR5]]3104; CHECK-NEXT: [[TMP6:%.*]] = bitcast <1 x i64> [[TMP11]] to <2 x i32>3105; CHECK-NEXT: [[TMP13:%.*]] = bitcast <1 x i64> [[TMP12]] to <2 x i32>3106; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP6]] to <1 x i64>3107; CHECK-NEXT: [[TMP9:%.*]] = bitcast <2 x i32> [[TMP13]] to <1 x i64>3108; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 03109; CHECK-NEXT: [[TMP10:%.*]] = extractelement <1 x i64> [[TMP9]], i32 03110; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 83111; CHECK-NEXT: ret i64 [[TMP10]]3112;3113entry:3114 %0 = bitcast <1 x i64> %a to <2 x i32>3115 %1 = bitcast <2 x i32> %0 to <1 x i64>3116 %2 = tail call <1 x i64> @llvm.x86.ssse3.pabs.d(<1 x i64> %1) nounwind readnone3117 %3 = bitcast <1 x i64> %2 to <2 x i32>3118 %4 = bitcast <2 x i32> %3 to <1 x i64>3119 %5 = extractelement <1 x i64> %4, i32 03120 ret i64 %53121}3122 3123declare <1 x i64> @llvm.x86.ssse3.pabs.w(<1 x i64>) nounwind readnone3124 3125define i64 @test14(<1 x i64> %a) #0 {3126; CHECK-LABEL: define i64 @test14(3127; CHECK-SAME: <1 x i64> [[A:%.*]]) #[[ATTR1]] {3128; CHECK-NEXT: entry:3129; CHECK-NEXT: [[TMP7:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 83130; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 83131; CHECK-NEXT: call void @llvm.donothing()3132; CHECK-NEXT: [[TMP8:%.*]] = bitcast <1 x i64> [[TMP7]] to <4 x i16>3133; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>3134; CHECK-NEXT: [[TMP11:%.*]] = bitcast <4 x i16> [[TMP8]] to <1 x i64>3135; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>3136; CHECK-NEXT: [[TMP12:%.*]] = tail call <1 x i64> @llvm.x86.ssse3.pabs.w(<1 x i64> [[TMP1]]) #[[ATTR5]]3137; CHECK-NEXT: [[TMP6:%.*]] = bitcast <1 x i64> [[TMP11]] to <4 x i16>3138; CHECK-NEXT: [[TMP13:%.*]] = bitcast <1 x i64> [[TMP12]] to <4 x i16>3139; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP6]] to <1 x i64>3140; CHECK-NEXT: [[TMP9:%.*]] = bitcast <4 x i16> [[TMP13]] to <1 x i64>3141; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 03142; CHECK-NEXT: [[TMP10:%.*]] = extractelement <1 x i64> [[TMP9]], i32 03143; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 83144; CHECK-NEXT: ret i64 [[TMP10]]3145;3146entry:3147 %0 = bitcast <1 x i64> %a to <4 x i16>3148 %1 = bitcast <4 x i16> %0 to <1 x i64>3149 %2 = tail call <1 x i64> @llvm.x86.ssse3.pabs.w(<1 x i64> %1) nounwind readnone3150 %3 = bitcast <1 x i64> %2 to <4 x i16>3151 %4 = bitcast <4 x i16> %3 to <1 x i64>3152 %5 = extractelement <1 x i64> %4, i32 03153 ret i64 %53154}3155 3156declare <1 x i64> @llvm.x86.ssse3.pabs.b(<1 x i64>) nounwind readnone3157 3158define i64 @test13(<1 x i64> %a) #0 {3159; CHECK-LABEL: define i64 @test13(3160; CHECK-SAME: <1 x i64> [[A:%.*]]) #[[ATTR1]] {3161; CHECK-NEXT: entry:3162; CHECK-NEXT: [[TMP7:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 83163; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 83164; CHECK-NEXT: call void @llvm.donothing()3165; CHECK-NEXT: [[TMP8:%.*]] = bitcast <1 x i64> [[TMP7]] to <8 x i8>3166; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>3167; CHECK-NEXT: [[TMP11:%.*]] = bitcast <8 x i8> [[TMP8]] to <1 x i64>3168; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>3169; CHECK-NEXT: [[TMP12:%.*]] = tail call <1 x i64> @llvm.x86.ssse3.pabs.b(<1 x i64> [[TMP1]]) #[[ATTR5]]3170; CHECK-NEXT: [[TMP6:%.*]] = bitcast <1 x i64> [[TMP11]] to <8 x i8>3171; CHECK-NEXT: [[TMP13:%.*]] = bitcast <1 x i64> [[TMP12]] to <8 x i8>3172; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP6]] to <1 x i64>3173; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i8> [[TMP13]] to <1 x i64>3174; CHECK-NEXT: [[TMP5:%.*]] = extractelement <1 x i64> [[TMP4]], i32 03175; CHECK-NEXT: [[TMP10:%.*]] = extractelement <1 x i64> [[TMP9]], i32 03176; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 83177; CHECK-NEXT: ret i64 [[TMP10]]3178;3179entry:3180 %0 = bitcast <1 x i64> %a to <8 x i8>3181 %1 = bitcast <8 x i8> %0 to <1 x i64>3182 %2 = tail call <1 x i64> @llvm.x86.ssse3.pabs.b(<1 x i64> %1) nounwind readnone3183 %3 = bitcast <1 x i64> %2 to <8 x i8>3184 %4 = bitcast <8 x i8> %3 to <1 x i64>3185 %5 = extractelement <1 x i64> %4, i32 03186 ret i64 %53187}3188 3189declare <1 x i64> @llvm.x86.ssse3.psign.d(<1 x i64>, <1 x i64>) nounwind readnone3190 3191define i64 @test12(<1 x i64> %a, <1 x i64> %b) #0 {3192; CHECK-LABEL: define i64 @test12(3193; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {3194; CHECK-NEXT: entry:3195; CHECK-NEXT: [[TMP9:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83196; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 83197; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 83198; CHECK-NEXT: call void @llvm.donothing()3199; CHECK-NEXT: [[TMP12:%.*]] = bitcast <1 x i64> [[TMP9]] to <2 x i32>3200; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <2 x i32>3201; CHECK-NEXT: [[TMP13:%.*]] = bitcast <1 x i64> [[TMP10]] to <2 x i32>3202; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>3203; CHECK-NEXT: [[TMP16:%.*]] = bitcast <2 x i32> [[TMP13]] to <1 x i64>3204; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP1]] to <1 x i64>3205; CHECK-NEXT: [[TMP8:%.*]] = bitcast <2 x i32> [[TMP12]] to <1 x i64>3206; CHECK-NEXT: [[TMP17:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>3207; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP16]], [[TMP8]]3208; CHECK-NEXT: [[TMP18:%.*]] = tail call <1 x i64> @llvm.x86.ssse3.psign.d(<1 x i64> [[TMP2]], <1 x i64> [[TMP17]]) #[[ATTR5]]3209; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <2 x i32>3210; CHECK-NEXT: [[TMP19:%.*]] = bitcast <1 x i64> [[TMP18]] to <2 x i32>3211; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i32> [[TMP11]] to <1 x i64>3212; CHECK-NEXT: [[TMP14:%.*]] = bitcast <2 x i32> [[TMP19]] to <1 x i64>3213; CHECK-NEXT: [[TMP7:%.*]] = extractelement <1 x i64> [[TMP6]], i32 03214; CHECK-NEXT: [[TMP15:%.*]] = extractelement <1 x i64> [[TMP14]], i32 03215; CHECK-NEXT: store i64 [[TMP7]], ptr @__msan_retval_tls, align 83216; CHECK-NEXT: ret i64 [[TMP15]]3217;3218entry:3219 %0 = bitcast <1 x i64> %b to <2 x i32>3220 %1 = bitcast <1 x i64> %a to <2 x i32>3221 %2 = bitcast <2 x i32> %1 to <1 x i64>3222 %3 = bitcast <2 x i32> %0 to <1 x i64>3223 %4 = tail call <1 x i64> @llvm.x86.ssse3.psign.d(<1 x i64> %2, <1 x i64> %3) nounwind readnone3224 %5 = bitcast <1 x i64> %4 to <2 x i32>3225 %6 = bitcast <2 x i32> %5 to <1 x i64>3226 %7 = extractelement <1 x i64> %6, i32 03227 ret i64 %73228}3229 3230declare <1 x i64> @llvm.x86.ssse3.psign.w(<1 x i64>, <1 x i64>) nounwind readnone3231 3232define i64 @test11(<1 x i64> %a, <1 x i64> %b) #0 {3233; CHECK-LABEL: define i64 @test11(3234; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {3235; CHECK-NEXT: entry:3236; CHECK-NEXT: [[TMP9:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83237; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 83238; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 83239; CHECK-NEXT: call void @llvm.donothing()3240; CHECK-NEXT: [[TMP12:%.*]] = bitcast <1 x i64> [[TMP9]] to <4 x i16>3241; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>3242; CHECK-NEXT: [[TMP13:%.*]] = bitcast <1 x i64> [[TMP10]] to <4 x i16>3243; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>3244; CHECK-NEXT: [[TMP16:%.*]] = bitcast <4 x i16> [[TMP13]] to <1 x i64>3245; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>3246; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x i16> [[TMP12]] to <1 x i64>3247; CHECK-NEXT: [[TMP17:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>3248; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP16]], [[TMP8]]3249; CHECK-NEXT: [[TMP18:%.*]] = tail call <1 x i64> @llvm.x86.ssse3.psign.w(<1 x i64> [[TMP2]], <1 x i64> [[TMP17]]) #[[ATTR5]]3250; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>3251; CHECK-NEXT: [[TMP19:%.*]] = bitcast <1 x i64> [[TMP18]] to <4 x i16>3252; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>3253; CHECK-NEXT: [[TMP14:%.*]] = bitcast <4 x i16> [[TMP19]] to <1 x i64>3254; CHECK-NEXT: [[TMP7:%.*]] = extractelement <1 x i64> [[TMP6]], i32 03255; CHECK-NEXT: [[TMP15:%.*]] = extractelement <1 x i64> [[TMP14]], i32 03256; CHECK-NEXT: store i64 [[TMP7]], ptr @__msan_retval_tls, align 83257; CHECK-NEXT: ret i64 [[TMP15]]3258;3259entry:3260 %0 = bitcast <1 x i64> %b to <4 x i16>3261 %1 = bitcast <1 x i64> %a to <4 x i16>3262 %2 = bitcast <4 x i16> %1 to <1 x i64>3263 %3 = bitcast <4 x i16> %0 to <1 x i64>3264 %4 = tail call <1 x i64> @llvm.x86.ssse3.psign.w(<1 x i64> %2, <1 x i64> %3) nounwind readnone3265 %5 = bitcast <1 x i64> %4 to <4 x i16>3266 %6 = bitcast <4 x i16> %5 to <1 x i64>3267 %7 = extractelement <1 x i64> %6, i32 03268 ret i64 %73269}3270 3271declare <1 x i64> @llvm.x86.ssse3.psign.b(<1 x i64>, <1 x i64>) nounwind readnone3272 3273define i64 @test10(<1 x i64> %a, <1 x i64> %b) #0 {3274; CHECK-LABEL: define i64 @test10(3275; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {3276; CHECK-NEXT: entry:3277; CHECK-NEXT: [[TMP9:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83278; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 83279; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 83280; CHECK-NEXT: call void @llvm.donothing()3281; CHECK-NEXT: [[TMP12:%.*]] = bitcast <1 x i64> [[TMP9]] to <8 x i8>3282; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>3283; CHECK-NEXT: [[TMP13:%.*]] = bitcast <1 x i64> [[TMP10]] to <8 x i8>3284; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>3285; CHECK-NEXT: [[TMP16:%.*]] = bitcast <8 x i8> [[TMP13]] to <1 x i64>3286; CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>3287; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP12]] to <1 x i64>3288; CHECK-NEXT: [[TMP17:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>3289; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP16]], [[TMP8]]3290; CHECK-NEXT: [[TMP18:%.*]] = tail call <1 x i64> @llvm.x86.ssse3.psign.b(<1 x i64> [[TMP2]], <1 x i64> [[TMP17]]) #[[ATTR5]]3291; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <8 x i8>3292; CHECK-NEXT: [[TMP19:%.*]] = bitcast <1 x i64> [[TMP18]] to <8 x i8>3293; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP11]] to <1 x i64>3294; CHECK-NEXT: [[TMP14:%.*]] = bitcast <8 x i8> [[TMP19]] to <1 x i64>3295; CHECK-NEXT: [[TMP7:%.*]] = extractelement <1 x i64> [[TMP6]], i32 03296; CHECK-NEXT: [[TMP15:%.*]] = extractelement <1 x i64> [[TMP14]], i32 03297; CHECK-NEXT: store i64 [[TMP7]], ptr @__msan_retval_tls, align 83298; CHECK-NEXT: ret i64 [[TMP15]]3299;3300entry:3301 %0 = bitcast <1 x i64> %b to <8 x i8>3302 %1 = bitcast <1 x i64> %a to <8 x i8>3303 %2 = bitcast <8 x i8> %1 to <1 x i64>3304 %3 = bitcast <8 x i8> %0 to <1 x i64>3305 %4 = tail call <1 x i64> @llvm.x86.ssse3.psign.b(<1 x i64> %2, <1 x i64> %3) nounwind readnone3306 %5 = bitcast <1 x i64> %4 to <8 x i8>3307 %6 = bitcast <8 x i8> %5 to <1 x i64>3308 %7 = extractelement <1 x i64> %6, i32 03309 ret i64 %73310}3311 3312declare <1 x i64> @llvm.x86.ssse3.pshuf.b(<1 x i64>, <1 x i64>) nounwind readnone3313 3314define i64 @test9(<1 x i64> %a, <1 x i64> %b) #0 {3315; CHECK-LABEL: define i64 @test9(3316; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {3317; CHECK-NEXT: entry:3318; CHECK-NEXT: [[TMP9:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83319; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 83320; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 83321; CHECK-NEXT: call void @llvm.donothing()3322; CHECK-NEXT: [[TMP12:%.*]] = bitcast <1 x i64> [[TMP9]] to <8 x i8>3323; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>3324; CHECK-NEXT: [[TMP13:%.*]] = bitcast <1 x i64> [[TMP10]] to <8 x i8>3325; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>3326; CHECK-NEXT: [[TMP16:%.*]] = bitcast <8 x i8> [[TMP13]] to <1 x i64>3327; CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>3328; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP12]] to <1 x i64>3329; CHECK-NEXT: [[TMP17:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>3330; CHECK-NEXT: [[TMP20:%.*]] = call <1 x i64> @llvm.x86.ssse3.pshuf.b(<1 x i64> [[TMP16]], <1 x i64> [[TMP17]])3331; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP8]], [[TMP20]]3332; CHECK-NEXT: [[TMP18:%.*]] = tail call <1 x i64> @llvm.x86.ssse3.pshuf.b(<1 x i64> [[TMP2]], <1 x i64> [[TMP17]]) #[[ATTR5]]3333; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <8 x i8>3334; CHECK-NEXT: [[TMP19:%.*]] = bitcast <1 x i64> [[TMP18]] to <8 x i8>3335; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP11]] to <1 x i64>3336; CHECK-NEXT: [[TMP14:%.*]] = bitcast <8 x i8> [[TMP19]] to <1 x i64>3337; CHECK-NEXT: [[TMP7:%.*]] = extractelement <1 x i64> [[TMP6]], i32 03338; CHECK-NEXT: [[TMP15:%.*]] = extractelement <1 x i64> [[TMP14]], i32 03339; CHECK-NEXT: store i64 [[TMP7]], ptr @__msan_retval_tls, align 83340; CHECK-NEXT: ret i64 [[TMP15]]3341;3342entry:3343 %0 = bitcast <1 x i64> %b to <8 x i8>3344 %1 = bitcast <1 x i64> %a to <8 x i8>3345 %2 = bitcast <8 x i8> %1 to <1 x i64>3346 %3 = bitcast <8 x i8> %0 to <1 x i64>3347 %4 = tail call <1 x i64> @llvm.x86.ssse3.pshuf.b(<1 x i64> %2, <1 x i64> %3) nounwind readnone3348 %5 = bitcast <1 x i64> %4 to <8 x i8>3349 %6 = bitcast <8 x i8> %5 to <1 x i64>3350 %7 = extractelement <1 x i64> %6, i32 03351 ret i64 %73352}3353 3354declare <1 x i64> @llvm.x86.ssse3.pmul.hr.sw(<1 x i64>, <1 x i64>) nounwind readnone3355 3356define i64 @test8(<1 x i64> %a, <1 x i64> %b) #0 {3357; CHECK-LABEL: define i64 @test8(3358; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {3359; CHECK-NEXT: entry:3360; CHECK-NEXT: [[TMP9:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83361; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 83362; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 83363; CHECK-NEXT: call void @llvm.donothing()3364; CHECK-NEXT: [[TMP12:%.*]] = bitcast <1 x i64> [[TMP9]] to <4 x i16>3365; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>3366; CHECK-NEXT: [[TMP13:%.*]] = bitcast <1 x i64> [[TMP10]] to <4 x i16>3367; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>3368; CHECK-NEXT: [[TMP16:%.*]] = bitcast <4 x i16> [[TMP13]] to <1 x i64>3369; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>3370; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x i16> [[TMP12]] to <1 x i64>3371; CHECK-NEXT: [[TMP17:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>3372; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP16]], [[TMP8]]3373; CHECK-NEXT: [[TMP18:%.*]] = tail call <1 x i64> @llvm.x86.ssse3.pmul.hr.sw(<1 x i64> [[TMP2]], <1 x i64> [[TMP17]]) #[[ATTR5]]3374; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>3375; CHECK-NEXT: [[TMP19:%.*]] = bitcast <1 x i64> [[TMP18]] to <4 x i16>3376; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>3377; CHECK-NEXT: [[TMP14:%.*]] = bitcast <4 x i16> [[TMP19]] to <1 x i64>3378; CHECK-NEXT: [[TMP7:%.*]] = extractelement <1 x i64> [[TMP6]], i32 03379; CHECK-NEXT: [[TMP15:%.*]] = extractelement <1 x i64> [[TMP14]], i32 03380; CHECK-NEXT: store i64 [[TMP7]], ptr @__msan_retval_tls, align 83381; CHECK-NEXT: ret i64 [[TMP15]]3382;3383entry:3384 %0 = bitcast <1 x i64> %b to <4 x i16>3385 %1 = bitcast <1 x i64> %a to <4 x i16>3386 %2 = bitcast <4 x i16> %1 to <1 x i64>3387 %3 = bitcast <4 x i16> %0 to <1 x i64>3388 %4 = tail call <1 x i64> @llvm.x86.ssse3.pmul.hr.sw(<1 x i64> %2, <1 x i64> %3) nounwind readnone3389 %5 = bitcast <1 x i64> %4 to <4 x i16>3390 %6 = bitcast <4 x i16> %5 to <1 x i64>3391 %7 = extractelement <1 x i64> %6, i32 03392 ret i64 %73393}3394 3395declare <1 x i64> @llvm.x86.ssse3.pmadd.ub.sw(<1 x i64>, <1 x i64>) nounwind readnone3396 3397define i64 @test7(<1 x i64> %a, <1 x i64> %b) #0 {3398; CHECK-LABEL: define i64 @test7(3399; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {3400; CHECK-NEXT: entry:3401; CHECK-NEXT: [[TMP9:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83402; CHECK-NEXT: [[TMP15:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 83403; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 83404; CHECK-NEXT: call void @llvm.donothing()3405; CHECK-NEXT: [[TMP17:%.*]] = bitcast <1 x i64> [[TMP9]] to <8 x i8>3406; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>3407; CHECK-NEXT: [[TMP18:%.*]] = bitcast <1 x i64> [[TMP15]] to <8 x i8>3408; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>3409; CHECK-NEXT: [[TMP21:%.*]] = bitcast <8 x i8> [[TMP18]] to <1 x i64>3410; CHECK-NEXT: [[TMP22:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>3411; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP17]] to <1 x i64>3412; CHECK-NEXT: [[TMP23:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>3413; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[TMP22]] to <8 x i8>3414; CHECK-NEXT: [[TMP12:%.*]] = bitcast <1 x i64> [[TMP23]] to <8 x i8>3415; CHECK-NEXT: [[TMP13:%.*]] = bitcast <1 x i64> [[TMP21]] to <8 x i8>3416; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[TMP8]] to <8 x i8>3417; CHECK-NEXT: [[TMP33:%.*]] = icmp ne <8 x i8> [[TMP13]], zeroinitializer3418; CHECK-NEXT: [[TMP34:%.*]] = icmp ne <8 x i8> [[TMP14]], zeroinitializer3419; CHECK-NEXT: [[TMP26:%.*]] = icmp ne <8 x i8> [[TMP11]], zeroinitializer3420; CHECK-NEXT: [[TMP36:%.*]] = icmp ne <8 x i8> [[TMP12]], zeroinitializer3421; CHECK-NEXT: [[TMP35:%.*]] = and <8 x i1> [[TMP33]], [[TMP34]]3422; CHECK-NEXT: [[TMP38:%.*]] = and <8 x i1> [[TMP26]], [[TMP34]]3423; CHECK-NEXT: [[TMP39:%.*]] = and <8 x i1> [[TMP33]], [[TMP36]]3424; CHECK-NEXT: [[TMP40:%.*]] = or <8 x i1> [[TMP35]], [[TMP38]]3425; CHECK-NEXT: [[TMP41:%.*]] = or <8 x i1> [[TMP40]], [[TMP39]]3426; CHECK-NEXT: [[TMP16:%.*]] = sext <8 x i1> [[TMP41]] to <8 x i8>3427; CHECK-NEXT: [[TMP27:%.*]] = bitcast <8 x i8> [[TMP16]] to <4 x i16>3428; CHECK-NEXT: [[TMP28:%.*]] = icmp ne <4 x i16> [[TMP27]], zeroinitializer3429; CHECK-NEXT: [[TMP42:%.*]] = sext <4 x i1> [[TMP28]] to <4 x i16>3430; CHECK-NEXT: [[TMP30:%.*]] = bitcast <4 x i16> [[TMP42]] to i643431; CHECK-NEXT: [[TMP32:%.*]] = bitcast i64 [[TMP30]] to <1 x i64>3432; CHECK-NEXT: [[TMP31:%.*]] = tail call <1 x i64> @llvm.x86.ssse3.pmadd.ub.sw(<1 x i64> [[TMP22]], <1 x i64> [[TMP23]]) #[[ATTR5]]3433; CHECK-NEXT: [[TMP25:%.*]] = bitcast <1 x i64> [[TMP32]] to <8 x i8>3434; CHECK-NEXT: [[TMP37:%.*]] = bitcast <1 x i64> [[TMP31]] to <8 x i8>3435; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP25]] to <1 x i64>3436; CHECK-NEXT: [[TMP19:%.*]] = bitcast <8 x i8> [[TMP37]] to <1 x i64>3437; CHECK-NEXT: [[TMP7:%.*]] = extractelement <1 x i64> [[TMP6]], i32 03438; CHECK-NEXT: [[TMP20:%.*]] = extractelement <1 x i64> [[TMP19]], i32 03439; CHECK-NEXT: store i64 [[TMP7]], ptr @__msan_retval_tls, align 83440; CHECK-NEXT: ret i64 [[TMP20]]3441;3442entry:3443 %0 = bitcast <1 x i64> %b to <8 x i8>3444 %1 = bitcast <1 x i64> %a to <8 x i8>3445 %2 = bitcast <8 x i8> %1 to <1 x i64>3446 %3 = bitcast <8 x i8> %0 to <1 x i64>3447 %4 = tail call <1 x i64> @llvm.x86.ssse3.pmadd.ub.sw(<1 x i64> %2, <1 x i64> %3) nounwind readnone3448 %5 = bitcast <1 x i64> %4 to <8 x i8>3449 %6 = bitcast <8 x i8> %5 to <1 x i64>3450 %7 = extractelement <1 x i64> %6, i32 03451 ret i64 %73452}3453 3454declare <1 x i64> @llvm.x86.ssse3.phsub.sw(<1 x i64>, <1 x i64>) nounwind readnone3455 3456define i64 @test6(<1 x i64> %a, <1 x i64> %b) #0 {3457; CHECK-LABEL: define i64 @test6(3458; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {3459; CHECK-NEXT: entry:3460; CHECK-NEXT: [[TMP9:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83461; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 83462; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 83463; CHECK-NEXT: call void @llvm.donothing()3464; CHECK-NEXT: [[TMP12:%.*]] = bitcast <1 x i64> [[TMP9]] to <4 x i16>3465; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>3466; CHECK-NEXT: [[TMP13:%.*]] = bitcast <1 x i64> [[TMP10]] to <4 x i16>3467; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>3468; CHECK-NEXT: [[TMP16:%.*]] = bitcast <4 x i16> [[TMP13]] to <1 x i64>3469; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>3470; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x i16> [[TMP12]] to <1 x i64>3471; CHECK-NEXT: [[TMP17:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>3472; CHECK-NEXT: [[TMP21:%.*]] = bitcast <1 x i64> [[TMP16]] to <4 x i16>3473; CHECK-NEXT: [[TMP23:%.*]] = bitcast <1 x i64> [[TMP8]] to <4 x i16>3474; CHECK-NEXT: [[TMP24:%.*]] = shufflevector <4 x i16> [[TMP21]], <4 x i16> [[TMP23]], <4 x i32> <i32 0, i32 2, i32 4, i32 6>3475; CHECK-NEXT: [[TMP25:%.*]] = shufflevector <4 x i16> [[TMP21]], <4 x i16> [[TMP23]], <4 x i32> <i32 1, i32 3, i32 5, i32 7>3476; CHECK-NEXT: [[TMP26:%.*]] = or <4 x i16> [[TMP24]], [[TMP25]]3477; CHECK-NEXT: [[TMP27:%.*]] = bitcast <4 x i16> [[TMP26]] to i643478; CHECK-NEXT: [[_MSPROP:%.*]] = bitcast i64 [[TMP27]] to <1 x i64>3479; CHECK-NEXT: [[TMP18:%.*]] = tail call <1 x i64> @llvm.x86.ssse3.phsub.sw(<1 x i64> [[TMP2]], <1 x i64> [[TMP17]]) #[[ATTR5]]3480; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>3481; CHECK-NEXT: [[TMP19:%.*]] = bitcast <1 x i64> [[TMP18]] to <4 x i16>3482; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>3483; CHECK-NEXT: [[TMP14:%.*]] = bitcast <4 x i16> [[TMP19]] to <1 x i64>3484; CHECK-NEXT: [[TMP7:%.*]] = extractelement <1 x i64> [[TMP6]], i32 03485; CHECK-NEXT: [[TMP15:%.*]] = extractelement <1 x i64> [[TMP14]], i32 03486; CHECK-NEXT: store i64 [[TMP7]], ptr @__msan_retval_tls, align 83487; CHECK-NEXT: ret i64 [[TMP15]]3488;3489entry:3490 %0 = bitcast <1 x i64> %b to <4 x i16>3491 %1 = bitcast <1 x i64> %a to <4 x i16>3492 %2 = bitcast <4 x i16> %1 to <1 x i64>3493 %3 = bitcast <4 x i16> %0 to <1 x i64>3494 %4 = tail call <1 x i64> @llvm.x86.ssse3.phsub.sw(<1 x i64> %2, <1 x i64> %3) nounwind readnone3495 %5 = bitcast <1 x i64> %4 to <4 x i16>3496 %6 = bitcast <4 x i16> %5 to <1 x i64>3497 %7 = extractelement <1 x i64> %6, i32 03498 ret i64 %73499}3500 3501declare <1 x i64> @llvm.x86.ssse3.phsub.d(<1 x i64>, <1 x i64>) nounwind readnone3502 3503define i64 @test5(<1 x i64> %a, <1 x i64> %b) #0 {3504; CHECK-LABEL: define i64 @test5(3505; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {3506; CHECK-NEXT: entry:3507; CHECK-NEXT: [[TMP9:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83508; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 83509; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 83510; CHECK-NEXT: call void @llvm.donothing()3511; CHECK-NEXT: [[TMP12:%.*]] = bitcast <1 x i64> [[TMP9]] to <2 x i32>3512; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <2 x i32>3513; CHECK-NEXT: [[TMP13:%.*]] = bitcast <1 x i64> [[TMP10]] to <2 x i32>3514; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>3515; CHECK-NEXT: [[TMP16:%.*]] = bitcast <2 x i32> [[TMP13]] to <1 x i64>3516; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP1]] to <1 x i64>3517; CHECK-NEXT: [[TMP8:%.*]] = bitcast <2 x i32> [[TMP12]] to <1 x i64>3518; CHECK-NEXT: [[TMP17:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>3519; CHECK-NEXT: [[TMP21:%.*]] = bitcast <1 x i64> [[TMP16]] to <2 x i32>3520; CHECK-NEXT: [[TMP23:%.*]] = bitcast <1 x i64> [[TMP8]] to <2 x i32>3521; CHECK-NEXT: [[TMP24:%.*]] = shufflevector <2 x i32> [[TMP21]], <2 x i32> [[TMP23]], <2 x i32> <i32 0, i32 2>3522; CHECK-NEXT: [[TMP25:%.*]] = shufflevector <2 x i32> [[TMP21]], <2 x i32> [[TMP23]], <2 x i32> <i32 1, i32 3>3523; CHECK-NEXT: [[TMP26:%.*]] = or <2 x i32> [[TMP24]], [[TMP25]]3524; CHECK-NEXT: [[TMP27:%.*]] = bitcast <2 x i32> [[TMP26]] to i643525; CHECK-NEXT: [[_MSPROP:%.*]] = bitcast i64 [[TMP27]] to <1 x i64>3526; CHECK-NEXT: [[TMP18:%.*]] = tail call <1 x i64> @llvm.x86.ssse3.phsub.d(<1 x i64> [[TMP2]], <1 x i64> [[TMP17]]) #[[ATTR5]]3527; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <2 x i32>3528; CHECK-NEXT: [[TMP19:%.*]] = bitcast <1 x i64> [[TMP18]] to <2 x i32>3529; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i32> [[TMP11]] to <1 x i64>3530; CHECK-NEXT: [[TMP14:%.*]] = bitcast <2 x i32> [[TMP19]] to <1 x i64>3531; CHECK-NEXT: [[TMP7:%.*]] = extractelement <1 x i64> [[TMP6]], i32 03532; CHECK-NEXT: [[TMP15:%.*]] = extractelement <1 x i64> [[TMP14]], i32 03533; CHECK-NEXT: store i64 [[TMP7]], ptr @__msan_retval_tls, align 83534; CHECK-NEXT: ret i64 [[TMP15]]3535;3536entry:3537 %0 = bitcast <1 x i64> %b to <2 x i32>3538 %1 = bitcast <1 x i64> %a to <2 x i32>3539 %2 = bitcast <2 x i32> %1 to <1 x i64>3540 %3 = bitcast <2 x i32> %0 to <1 x i64>3541 %4 = tail call <1 x i64> @llvm.x86.ssse3.phsub.d(<1 x i64> %2, <1 x i64> %3) nounwind readnone3542 %5 = bitcast <1 x i64> %4 to <2 x i32>3543 %6 = bitcast <2 x i32> %5 to <1 x i64>3544 %7 = extractelement <1 x i64> %6, i32 03545 ret i64 %73546}3547 3548declare <1 x i64> @llvm.x86.ssse3.phsub.w(<1 x i64>, <1 x i64>) nounwind readnone3549 3550define i64 @test4(<1 x i64> %a, <1 x i64> %b) #0 {3551; CHECK-LABEL: define i64 @test4(3552; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {3553; CHECK-NEXT: entry:3554; CHECK-NEXT: [[TMP9:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83555; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 83556; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 83557; CHECK-NEXT: call void @llvm.donothing()3558; CHECK-NEXT: [[TMP12:%.*]] = bitcast <1 x i64> [[TMP9]] to <4 x i16>3559; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>3560; CHECK-NEXT: [[TMP13:%.*]] = bitcast <1 x i64> [[TMP10]] to <4 x i16>3561; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>3562; CHECK-NEXT: [[TMP16:%.*]] = bitcast <4 x i16> [[TMP13]] to <1 x i64>3563; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>3564; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x i16> [[TMP12]] to <1 x i64>3565; CHECK-NEXT: [[TMP17:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>3566; CHECK-NEXT: [[TMP21:%.*]] = bitcast <1 x i64> [[TMP16]] to <4 x i16>3567; CHECK-NEXT: [[TMP23:%.*]] = bitcast <1 x i64> [[TMP8]] to <4 x i16>3568; CHECK-NEXT: [[TMP24:%.*]] = shufflevector <4 x i16> [[TMP21]], <4 x i16> [[TMP23]], <4 x i32> <i32 0, i32 2, i32 4, i32 6>3569; CHECK-NEXT: [[TMP25:%.*]] = shufflevector <4 x i16> [[TMP21]], <4 x i16> [[TMP23]], <4 x i32> <i32 1, i32 3, i32 5, i32 7>3570; CHECK-NEXT: [[TMP26:%.*]] = or <4 x i16> [[TMP24]], [[TMP25]]3571; CHECK-NEXT: [[TMP27:%.*]] = bitcast <4 x i16> [[TMP26]] to i643572; CHECK-NEXT: [[_MSPROP:%.*]] = bitcast i64 [[TMP27]] to <1 x i64>3573; CHECK-NEXT: [[TMP18:%.*]] = tail call <1 x i64> @llvm.x86.ssse3.phsub.w(<1 x i64> [[TMP2]], <1 x i64> [[TMP17]]) #[[ATTR5]]3574; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>3575; CHECK-NEXT: [[TMP19:%.*]] = bitcast <1 x i64> [[TMP18]] to <4 x i16>3576; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>3577; CHECK-NEXT: [[TMP14:%.*]] = bitcast <4 x i16> [[TMP19]] to <1 x i64>3578; CHECK-NEXT: [[TMP7:%.*]] = extractelement <1 x i64> [[TMP6]], i32 03579; CHECK-NEXT: [[TMP15:%.*]] = extractelement <1 x i64> [[TMP14]], i32 03580; CHECK-NEXT: store i64 [[TMP7]], ptr @__msan_retval_tls, align 83581; CHECK-NEXT: ret i64 [[TMP15]]3582;3583entry:3584 %0 = bitcast <1 x i64> %b to <4 x i16>3585 %1 = bitcast <1 x i64> %a to <4 x i16>3586 %2 = bitcast <4 x i16> %1 to <1 x i64>3587 %3 = bitcast <4 x i16> %0 to <1 x i64>3588 %4 = tail call <1 x i64> @llvm.x86.ssse3.phsub.w(<1 x i64> %2, <1 x i64> %3) nounwind readnone3589 %5 = bitcast <1 x i64> %4 to <4 x i16>3590 %6 = bitcast <4 x i16> %5 to <1 x i64>3591 %7 = extractelement <1 x i64> %6, i32 03592 ret i64 %73593}3594 3595declare <1 x i64> @llvm.x86.ssse3.phadd.sw(<1 x i64>, <1 x i64>) nounwind readnone3596 3597define i64 @test3(<1 x i64> %a, <1 x i64> %b) #0 {3598; CHECK-LABEL: define i64 @test3(3599; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {3600; CHECK-NEXT: entry:3601; CHECK-NEXT: [[TMP9:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83602; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 83603; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 83604; CHECK-NEXT: call void @llvm.donothing()3605; CHECK-NEXT: [[TMP12:%.*]] = bitcast <1 x i64> [[TMP9]] to <4 x i16>3606; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <4 x i16>3607; CHECK-NEXT: [[TMP13:%.*]] = bitcast <1 x i64> [[TMP10]] to <4 x i16>3608; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>3609; CHECK-NEXT: [[TMP16:%.*]] = bitcast <4 x i16> [[TMP13]] to <1 x i64>3610; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[TMP1]] to <1 x i64>3611; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x i16> [[TMP12]] to <1 x i64>3612; CHECK-NEXT: [[TMP17:%.*]] = bitcast <4 x i16> [[TMP0]] to <1 x i64>3613; CHECK-NEXT: [[TMP21:%.*]] = bitcast <1 x i64> [[TMP16]] to <4 x i16>3614; CHECK-NEXT: [[TMP23:%.*]] = bitcast <1 x i64> [[TMP8]] to <4 x i16>3615; CHECK-NEXT: [[TMP24:%.*]] = shufflevector <4 x i16> [[TMP21]], <4 x i16> [[TMP23]], <4 x i32> <i32 0, i32 2, i32 4, i32 6>3616; CHECK-NEXT: [[TMP25:%.*]] = shufflevector <4 x i16> [[TMP21]], <4 x i16> [[TMP23]], <4 x i32> <i32 1, i32 3, i32 5, i32 7>3617; CHECK-NEXT: [[TMP26:%.*]] = or <4 x i16> [[TMP24]], [[TMP25]]3618; CHECK-NEXT: [[TMP27:%.*]] = bitcast <4 x i16> [[TMP26]] to i643619; CHECK-NEXT: [[_MSPROP:%.*]] = bitcast i64 [[TMP27]] to <1 x i64>3620; CHECK-NEXT: [[TMP18:%.*]] = tail call <1 x i64> @llvm.x86.ssse3.phadd.sw(<1 x i64> [[TMP2]], <1 x i64> [[TMP17]]) #[[ATTR5]]3621; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>3622; CHECK-NEXT: [[TMP19:%.*]] = bitcast <1 x i64> [[TMP18]] to <4 x i16>3623; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP11]] to <1 x i64>3624; CHECK-NEXT: [[TMP14:%.*]] = bitcast <4 x i16> [[TMP19]] to <1 x i64>3625; CHECK-NEXT: [[TMP7:%.*]] = extractelement <1 x i64> [[TMP6]], i32 03626; CHECK-NEXT: [[TMP15:%.*]] = extractelement <1 x i64> [[TMP14]], i32 03627; CHECK-NEXT: store i64 [[TMP7]], ptr @__msan_retval_tls, align 83628; CHECK-NEXT: ret i64 [[TMP15]]3629;3630entry:3631 %0 = bitcast <1 x i64> %b to <4 x i16>3632 %1 = bitcast <1 x i64> %a to <4 x i16>3633 %2 = bitcast <4 x i16> %1 to <1 x i64>3634 %3 = bitcast <4 x i16> %0 to <1 x i64>3635 %4 = tail call <1 x i64> @llvm.x86.ssse3.phadd.sw(<1 x i64> %2, <1 x i64> %3) nounwind readnone3636 %5 = bitcast <1 x i64> %4 to <4 x i16>3637 %6 = bitcast <4 x i16> %5 to <1 x i64>3638 %7 = extractelement <1 x i64> %6, i32 03639 ret i64 %73640}3641 3642declare <1 x i64> @llvm.x86.ssse3.phadd.d(<1 x i64>, <1 x i64>) nounwind readnone3643 3644define i64 @test2(<1 x i64> %a, <1 x i64> %b) #0 {3645; CHECK-LABEL: define i64 @test2(3646; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR1]] {3647; CHECK-NEXT: entry:3648; CHECK-NEXT: [[TMP9:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83649; CHECK-NEXT: [[TMP10:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 83650; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 83651; CHECK-NEXT: call void @llvm.donothing()3652; CHECK-NEXT: [[TMP12:%.*]] = bitcast <1 x i64> [[TMP9]] to <2 x i32>3653; CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <2 x i32>3654; CHECK-NEXT: [[TMP13:%.*]] = bitcast <1 x i64> [[TMP10]] to <2 x i32>3655; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>3656; CHECK-NEXT: [[TMP16:%.*]] = bitcast <2 x i32> [[TMP13]] to <1 x i64>3657; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP1]] to <1 x i64>3658; CHECK-NEXT: [[TMP8:%.*]] = bitcast <2 x i32> [[TMP12]] to <1 x i64>3659; CHECK-NEXT: [[TMP17:%.*]] = bitcast <2 x i32> [[TMP0]] to <1 x i64>3660; CHECK-NEXT: [[TMP21:%.*]] = bitcast <1 x i64> [[TMP16]] to <2 x i32>3661; CHECK-NEXT: [[TMP23:%.*]] = bitcast <1 x i64> [[TMP8]] to <2 x i32>3662; CHECK-NEXT: [[TMP24:%.*]] = shufflevector <2 x i32> [[TMP21]], <2 x i32> [[TMP23]], <2 x i32> <i32 0, i32 2>3663; CHECK-NEXT: [[TMP25:%.*]] = shufflevector <2 x i32> [[TMP21]], <2 x i32> [[TMP23]], <2 x i32> <i32 1, i32 3>3664; CHECK-NEXT: [[TMP26:%.*]] = or <2 x i32> [[TMP24]], [[TMP25]]3665; CHECK-NEXT: [[TMP27:%.*]] = bitcast <2 x i32> [[TMP26]] to i643666; CHECK-NEXT: [[_MSPROP:%.*]] = bitcast i64 [[TMP27]] to <1 x i64>3667; CHECK-NEXT: [[TMP18:%.*]] = tail call <1 x i64> @llvm.x86.ssse3.phadd.d(<1 x i64> [[TMP2]], <1 x i64> [[TMP17]]) #[[ATTR5]]3668; CHECK-NEXT: [[TMP11:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <2 x i32>3669; CHECK-NEXT: [[TMP19:%.*]] = bitcast <1 x i64> [[TMP18]] to <2 x i32>3670; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i32> [[TMP11]] to <1 x i64>3671; CHECK-NEXT: [[TMP14:%.*]] = bitcast <2 x i32> [[TMP19]] to <1 x i64>3672; CHECK-NEXT: [[TMP7:%.*]] = extractelement <1 x i64> [[TMP6]], i32 03673; CHECK-NEXT: [[TMP15:%.*]] = extractelement <1 x i64> [[TMP14]], i32 03674; CHECK-NEXT: store i64 [[TMP7]], ptr @__msan_retval_tls, align 83675; CHECK-NEXT: ret i64 [[TMP15]]3676;3677entry:3678 %0 = bitcast <1 x i64> %b to <2 x i32>3679 %1 = bitcast <1 x i64> %a to <2 x i32>3680 %2 = bitcast <2 x i32> %1 to <1 x i64>3681 %3 = bitcast <2 x i32> %0 to <1 x i64>3682 %4 = tail call <1 x i64> @llvm.x86.ssse3.phadd.d(<1 x i64> %2, <1 x i64> %3) nounwind readnone3683 %5 = bitcast <1 x i64> %4 to <2 x i32>3684 %6 = bitcast <2 x i32> %5 to <1 x i64>3685 %7 = extractelement <1 x i64> %6, i32 03686 ret i64 %73687}3688 3689define <4 x float> @test89(<4 x float> %a, <1 x i64> %b) nounwind #0 {3690; ALL-LABEL: test89:3691; ALL: # %bb.0:3692; ALL-NEXT: cvtpi2ps %mm0, %xmm03693; ALL-NEXT: ret{{[l|q]}}3694; CHECK-LABEL: define <4 x float> @test89(3695; CHECK-SAME: <4 x float> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR4:[0-9]+]] {3696; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 83697; CHECK-NEXT: [[TMP4:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83698; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 83699; CHECK-NEXT: call void @llvm.donothing()3700; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP1]] to i1283701; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 03702; CHECK-NEXT: [[TMP2:%.*]] = bitcast <1 x i64> [[TMP4]] to i643703; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 03704; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3705; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]3706; CHECK: 6:3707; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3708; CHECK-NEXT: unreachable3709; CHECK: 7:3710; CHECK-NEXT: [[C:%.*]] = tail call <4 x float> @llvm.x86.sse.cvtpi2ps(<4 x float> [[A]], <1 x i64> [[B]])3711; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 83712; CHECK-NEXT: ret <4 x float> [[C]]3713;3714 %c = tail call <4 x float> @llvm.x86.sse.cvtpi2ps(<4 x float> %a, <1 x i64> %b)3715 ret <4 x float> %c3716}3717 3718declare <4 x float> @llvm.x86.sse.cvtpi2ps(<4 x float>, <1 x i64>) nounwind readnone3719 3720define void @test90() #0 {3721; ALL-LABEL: test90:3722; ALL: # %bb.0:3723; ALL-NEXT: emms3724; ALL-NEXT: ret{{[l|q]}}3725; CHECK-LABEL: define void @test90(3726; CHECK-SAME: ) #[[ATTR1]] {3727; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 83728; CHECK-NEXT: call void @llvm.donothing()3729; CHECK-NEXT: call void @llvm.x86.mmx.emms()3730; CHECK-NEXT: ret void3731;3732 call void @llvm.x86.mmx.emms()3733 ret void3734}3735 3736declare void @llvm.x86.mmx.emms()3737 3738define <1 x i64> @test_mm_insert_pi16(<1 x i64> %a.coerce, i32 %d) nounwind #0 {3739; CHECK-LABEL: define <1 x i64> @test_mm_insert_pi16(3740; CHECK-SAME: <1 x i64> [[A_COERCE:%.*]], i32 [[D:%.*]]) #[[ATTR4]] {3741; CHECK-NEXT: entry:3742; CHECK-NEXT: [[TMP3:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 83743; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83744; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 83745; CHECK-NEXT: call void @llvm.donothing()3746; CHECK-NEXT: [[TMP7:%.*]] = bitcast <1 x i64> [[TMP3]] to i643747; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP7]], 03748; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i32 [[TMP6]], 03749; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3750; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF1]]3751; CHECK: 4:3752; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3753; CHECK-NEXT: unreachable3754; CHECK: 5:3755; CHECK-NEXT: [[TMP9:%.*]] = tail call <1 x i64> @llvm.x86.mmx.pinsr.w(<1 x i64> [[A_COERCE]], i32 [[D]], i32 2)3756; CHECK-NEXT: store <1 x i64> zeroinitializer, ptr @__msan_retval_tls, align 83757; CHECK-NEXT: ret <1 x i64> [[TMP9]]3758;3759entry:3760 %1 = tail call <1 x i64> @llvm.x86.mmx.pinsr.w(<1 x i64> %a.coerce, i32 %d, i32 2)3761 ret <1 x i64> %13762}3763 3764declare <1 x i64> @llvm.x86.mmx.pinsr.w(<1 x i64>, i32, i32 immarg)3765 3766define i32 @test_mm_extract_pi16(<1 x i64> %a.coerce) nounwind #0 {3767; CHECK-LABEL: define i32 @test_mm_extract_pi16(3768; CHECK-SAME: <1 x i64> [[A_COERCE:%.*]]) #[[ATTR4]] {3769; CHECK-NEXT: entry:3770; CHECK-NEXT: [[TMP2:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 83771; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 83772; CHECK-NEXT: call void @llvm.donothing()3773; CHECK-NEXT: [[TMP5:%.*]] = bitcast <1 x i64> [[TMP2]] to i643774; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP5]], 03775; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP6:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]3776; CHECK: 3:3777; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]3778; CHECK-NEXT: unreachable3779; CHECK: 4:3780; CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.x86.mmx.pextr.w(<1 x i64> [[A_COERCE]], i32 2)3781; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 83782; CHECK-NEXT: ret i32 [[TMP1]]3783;3784entry:3785 %1 = tail call i32 @llvm.x86.mmx.pextr.w(<1 x i64> %a.coerce, i32 2)3786 ret i32 %13787}3788 3789declare i32 @llvm.x86.mmx.pextr.w(<1 x i64>, i32 immarg)3790 3791attributes #0 = { sanitize_memory }3792;.3793; CHECK: [[PROF1]] = !{!"branch_weights", i32 1, i32 1048575}3794;.3795