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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt < %s -msan-check-access-address=0 -S -passes=msan 2>&1 | FileCheck %s3; RUN: opt < %s -msan-check-access-address=0 -S -passes=msan -msan-track-origins=1 2>&1 | FileCheck -check-prefixes=ORIGINS %s4 5; REQUIRES: x86-registered-target6 7target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"8target triple = "i386-unknown-linux-gnu"9 10; Store intrinsic.11 12define void @StoreIntrinsic(ptr %p, <4 x float> %x) nounwind uwtable sanitize_memory {13; CHECK-LABEL: define void @StoreIntrinsic(14; CHECK-SAME: ptr [[P:%.*]], <4 x float> [[X:%.*]]) #[[ATTR0:[0-9]+]] {15; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 816; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 817; CHECK-NEXT: call void @llvm.donothing()18; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[P]] to i6419; CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], -214748364920; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr21; CHECK-NEXT: store <4 x i32> [[TMP1]], ptr [[TMP4]], align 122; CHECK-NEXT: store <4 x float> [[X]], ptr [[P]], align 123; CHECK-NEXT: ret void24;25; ORIGINS-LABEL: define void @StoreIntrinsic(26; ORIGINS-SAME: ptr [[P:%.*]], <4 x float> [[X:%.*]]) #[[ATTR0:[0-9]+]] {27; ORIGINS-NEXT: [[TMP10:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 828; ORIGINS-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 829; ORIGINS-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_origin_tls, i64 8), align 430; ORIGINS-NEXT: call void @llvm.donothing()31; ORIGINS-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[P]] to i6432; ORIGINS-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], -214748364933; ORIGINS-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr34; ORIGINS-NEXT: [[TMP6:%.*]] = add i64 [[TMP4]], 107374182435; ORIGINS-NEXT: [[TMP7:%.*]] = and i64 [[TMP6]], -436; ORIGINS-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr37; ORIGINS-NEXT: store <4 x i32> [[TMP1]], ptr [[TMP5]], align 138; ORIGINS-NEXT: [[TMP9:%.*]] = bitcast <4 x i32> [[TMP1]] to i12839; ORIGINS-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP9]], 040; ORIGINS-NEXT: br i1 [[_MSCMP]], label %[[BB11:.*]], label %[[BB15:.*]], !prof [[PROF1:![0-9]+]]41; ORIGINS: [[BB11]]:42; ORIGINS-NEXT: store i32 [[TMP2]], ptr [[TMP8]], align 443; ORIGINS-NEXT: [[TMP11:%.*]] = getelementptr i32, ptr [[TMP8]], i32 144; ORIGINS-NEXT: store i32 [[TMP2]], ptr [[TMP11]], align 445; ORIGINS-NEXT: [[TMP12:%.*]] = getelementptr i32, ptr [[TMP8]], i32 246; ORIGINS-NEXT: store i32 [[TMP2]], ptr [[TMP12]], align 447; ORIGINS-NEXT: [[TMP13:%.*]] = getelementptr i32, ptr [[TMP8]], i32 348; ORIGINS-NEXT: store i32 [[TMP2]], ptr [[TMP13]], align 449; ORIGINS-NEXT: br label %[[BB15]]50; ORIGINS: [[BB15]]:51; ORIGINS-NEXT: store <4 x float> [[X]], ptr [[P]], align 152; ORIGINS-NEXT: ret void53;54 call void @llvm.x86.sse.storeu.ps(ptr %p, <4 x float> %x)55 ret void56}57 58declare void @llvm.x86.sse.storeu.ps(ptr, <4 x float>) nounwind59 60 61 62; Load intrinsic.63 64define <16 x i8> @LoadIntrinsic(ptr %p) nounwind uwtable sanitize_memory {65; CHECK-LABEL: define <16 x i8> @LoadIntrinsic(66; CHECK-SAME: ptr [[P:%.*]]) #[[ATTR0]] {67; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 868; CHECK-NEXT: call void @llvm.donothing()69; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i6470; CHECK-NEXT: [[TMP2:%.*]] = and i64 [[TMP1]], -214748364971; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr72; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i8>, ptr [[TMP3]], align 173; CHECK-NEXT: [[CALL:%.*]] = call <16 x i8> @llvm.x86.sse3.ldu.dq(ptr [[P]])74; CHECK-NEXT: store <16 x i8> [[_MSLD]], ptr @__msan_retval_tls, align 875; CHECK-NEXT: ret <16 x i8> [[CALL]]76;77; ORIGINS-LABEL: define <16 x i8> @LoadIntrinsic(78; ORIGINS-SAME: ptr [[P:%.*]]) #[[ATTR0]] {79; ORIGINS-NEXT: [[TMP8:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 880; ORIGINS-NEXT: call void @llvm.donothing()81; ORIGINS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i6482; ORIGINS-NEXT: [[TMP2:%.*]] = and i64 [[TMP1]], -214748364983; ORIGINS-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr84; ORIGINS-NEXT: [[TMP4:%.*]] = add i64 [[TMP2]], 107374182485; ORIGINS-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], -486; ORIGINS-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr87; ORIGINS-NEXT: [[_MSLD:%.*]] = load <16 x i8>, ptr [[TMP3]], align 188; ORIGINS-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 489; ORIGINS-NEXT: [[CALL:%.*]] = call <16 x i8> @llvm.x86.sse3.ldu.dq(ptr [[P]])90; ORIGINS-NEXT: store <16 x i8> [[_MSLD]], ptr @__msan_retval_tls, align 891; ORIGINS-NEXT: store i32 [[TMP7]], ptr @__msan_retval_origin_tls, align 492; ORIGINS-NEXT: ret <16 x i8> [[CALL]]93;94 %call = call <16 x i8> @llvm.x86.sse3.ldu.dq(ptr %p)95 ret <16 x i8> %call96}97 98declare <16 x i8> @llvm.x86.sse3.ldu.dq(ptr %p) nounwind99 100 101 102; Simple NoMem intrinsic103; Check that shadow is OR'ed, and origin is Select'ed104; And no shadow checks!105 106define <8 x i16> @Pmulhuw128(<8 x i16> %a, <8 x i16> %b) nounwind uwtable sanitize_memory {107; CHECK-LABEL: define <8 x i16> @Pmulhuw128(108; CHECK-SAME: <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]]) #[[ATTR0]] {109; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8110; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8111; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8112; CHECK-NEXT: call void @llvm.donothing()113; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP1]], [[TMP2]]114; CHECK-NEXT: [[CALL:%.*]] = call <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16> [[A]], <8 x i16> [[B]])115; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8116; CHECK-NEXT: ret <8 x i16> [[CALL]]117;118; ORIGINS-LABEL: define <8 x i16> @Pmulhuw128(119; ORIGINS-SAME: <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]]) #[[ATTR0]] {120; ORIGINS-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8121; ORIGINS-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4122; ORIGINS-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8123; ORIGINS-NEXT: [[TMP4:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_origin_tls, i64 16), align 4124; ORIGINS-NEXT: [[TMP8:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8125; ORIGINS-NEXT: call void @llvm.donothing()126; ORIGINS-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP1]], [[TMP3]]127; ORIGINS-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP3]] to i128128; ORIGINS-NEXT: [[TMP6:%.*]] = icmp ne i128 [[TMP5]], 0129; ORIGINS-NEXT: [[TMP7:%.*]] = select i1 [[TMP6]], i32 [[TMP4]], i32 [[TMP2]]130; ORIGINS-NEXT: [[CALL:%.*]] = call <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16> [[A]], <8 x i16> [[B]])131; ORIGINS-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8132; ORIGINS-NEXT: store i32 [[TMP7]], ptr @__msan_retval_origin_tls, align 4133; ORIGINS-NEXT: ret <8 x i16> [[CALL]]134;135 %call = call <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16> %a, <8 x i16> %b)136 ret <8 x i16> %call137}138 139declare <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16> %a, <8 x i16> %b) nounwind140;.141; ORIGINS: [[PROF1]] = !{!"branch_weights", i32 1, i32 1048575}142;.143