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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt %s -S -passes=msan 2>&1 | FileCheck %s3 4target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"5target triple = "i386-unknown-linux-gnu"6 7define <4 x float> @test_x86_sse_cmp_ps(<4 x float> %a0, <4 x float> %a1) #0 {8; CHECK-LABEL: @test_x86_sse_cmp_ps(9; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 810; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 811; CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 812; CHECK-NEXT: call void @llvm.donothing()13; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]]14; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <4 x i32> [[TMP3]], zeroinitializer15; CHECK-NEXT: [[TMP5:%.*]] = sext <4 x i1> [[TMP4]] to <4 x i32>16; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse.cmp.ps(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], i8 7)17; CHECK-NEXT: store <4 x i32> [[TMP5]], ptr @__msan_retval_tls, align 818; CHECK-NEXT: ret <4 x float> [[RES]]19;20 %res = call <4 x float> @llvm.x86.sse.cmp.ps(<4 x float> %a0, <4 x float> %a1, i8 7) ; <<4 x float>> [#uses=1]21 ret <4 x float> %res22}23declare <4 x float> @llvm.x86.sse.cmp.ps(<4 x float>, <4 x float>, i8) nounwind readnone24 25 26define <4 x float> @test_x86_sse_cmp_ss(<4 x float> %a0, <4 x float> %a1) #0 {27; CHECK-LABEL: @test_x86_sse_cmp_ss(28; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 829; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 830; CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 831; CHECK-NEXT: call void @llvm.donothing()32; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]]33; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[TMP3]], i64 034; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 035; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i12836; CHECK-NEXT: [[TMP7:%.*]] = bitcast i128 [[TMP6]] to <4 x i32>37; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], i8 7)38; CHECK-NEXT: store <4 x i32> [[TMP7]], ptr @__msan_retval_tls, align 839; CHECK-NEXT: ret <4 x float> [[RES]]40;41 %res = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %a0, <4 x float> %a1, i8 7) ; <<4 x float>> [#uses=1]42 ret <4 x float> %res43}44declare <4 x float> @llvm.x86.sse.cmp.ss(<4 x float>, <4 x float>, i8) nounwind readnone45 46 47define i32 @test_x86_sse_comieq_ss(<4 x float> %a0, <4 x float> %a1) #0 {48; CHECK-LABEL: @test_x86_sse_comieq_ss(49; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 850; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 851; CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 852; CHECK-NEXT: call void @llvm.donothing()53; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]]54; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[TMP3]], i64 055; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 056; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i3257; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse.comieq.ss(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]])58; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 859; CHECK-NEXT: ret i32 [[RES]]60;61 %res = call i32 @llvm.x86.sse.comieq.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]62 ret i32 %res63}64declare i32 @llvm.x86.sse.comieq.ss(<4 x float>, <4 x float>) nounwind readnone65 66 67define i32 @test_x86_sse_comige_ss(<4 x float> %a0, <4 x float> %a1) #0 {68; CHECK-LABEL: @test_x86_sse_comige_ss(69; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 870; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 871; CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 872; CHECK-NEXT: call void @llvm.donothing()73; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]]74; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[TMP3]], i64 075; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 076; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i3277; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse.comige.ss(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]])78; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 879; CHECK-NEXT: ret i32 [[RES]]80;81 %res = call i32 @llvm.x86.sse.comige.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]82 ret i32 %res83}84declare i32 @llvm.x86.sse.comige.ss(<4 x float>, <4 x float>) nounwind readnone85 86 87define i32 @test_x86_sse_comigt_ss(<4 x float> %a0, <4 x float> %a1) #0 {88; CHECK-LABEL: @test_x86_sse_comigt_ss(89; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 890; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 891; CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 892; CHECK-NEXT: call void @llvm.donothing()93; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]]94; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[TMP3]], i64 095; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 096; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i3297; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse.comigt.ss(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]])98; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 899; CHECK-NEXT: ret i32 [[RES]]100;101 %res = call i32 @llvm.x86.sse.comigt.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]102 ret i32 %res103}104declare i32 @llvm.x86.sse.comigt.ss(<4 x float>, <4 x float>) nounwind readnone105 106 107define i32 @test_x86_sse_comile_ss(<4 x float> %a0, <4 x float> %a1) #0 {108; CHECK-LABEL: @test_x86_sse_comile_ss(109; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8110; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8111; CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8112; CHECK-NEXT: call void @llvm.donothing()113; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]]114; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[TMP3]], i64 0115; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0116; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i32117; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse.comile.ss(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]])118; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8119; CHECK-NEXT: ret i32 [[RES]]120;121 %res = call i32 @llvm.x86.sse.comile.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]122 ret i32 %res123}124declare i32 @llvm.x86.sse.comile.ss(<4 x float>, <4 x float>) nounwind readnone125 126 127define i32 @test_x86_sse_comilt_ss(<4 x float> %a0, <4 x float> %a1) #0 {128; CHECK-LABEL: @test_x86_sse_comilt_ss(129; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8130; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8131; CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8132; CHECK-NEXT: call void @llvm.donothing()133; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]]134; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[TMP3]], i64 0135; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0136; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i32137; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse.comilt.ss(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]])138; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8139; CHECK-NEXT: ret i32 [[RES]]140;141 %res = call i32 @llvm.x86.sse.comilt.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]142 ret i32 %res143}144declare i32 @llvm.x86.sse.comilt.ss(<4 x float>, <4 x float>) nounwind readnone145 146 147define i32 @test_x86_sse_comineq_ss(<4 x float> %a0, <4 x float> %a1) #0 {148; CHECK-LABEL: @test_x86_sse_comineq_ss(149; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8150; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8151; CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8152; CHECK-NEXT: call void @llvm.donothing()153; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]]154; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[TMP3]], i64 0155; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0156; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i32157; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse.comineq.ss(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]])158; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8159; CHECK-NEXT: ret i32 [[RES]]160;161 %res = call i32 @llvm.x86.sse.comineq.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]162 ret i32 %res163}164declare i32 @llvm.x86.sse.comineq.ss(<4 x float>, <4 x float>) nounwind readnone165 166 167define i32 @test_x86_sse_cvtss2si(<4 x float> %a0) #0 {168; CHECK-LABEL: @test_x86_sse_cvtss2si(169; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8170; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8171; CHECK-NEXT: call void @llvm.donothing()172; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[TMP1]], i32 0173; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP2]], 0174; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP6:%.*]], label [[TMP5:%.*]], !prof [[PROF1:![0-9]+]]175; CHECK: 4:176; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4:[0-9]+]]177; CHECK-NEXT: unreachable178; CHECK: 5:179; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse.cvtss2si(<4 x float> [[A0:%.*]])180; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8181; CHECK-NEXT: ret i32 [[RES]]182;183 %res = call i32 @llvm.x86.sse.cvtss2si(<4 x float> %a0) ; <i32> [#uses=1]184 ret i32 %res185}186declare i32 @llvm.x86.sse.cvtss2si(<4 x float>) nounwind readnone187 188 189define i32 @test_x86_sse_cvttss2si(<4 x float> %a0) #0 {190; CHECK-LABEL: @test_x86_sse_cvttss2si(191; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8192; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8193; CHECK-NEXT: call void @llvm.donothing()194; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[TMP1]], i32 0195; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP2]], 0196; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP6:%.*]], label [[TMP5:%.*]], !prof [[PROF1]]197; CHECK: 4:198; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]199; CHECK-NEXT: unreachable200; CHECK: 5:201; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse.cvttss2si(<4 x float> [[A0:%.*]])202; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8203; CHECK-NEXT: ret i32 [[RES]]204;205 %res = call i32 @llvm.x86.sse.cvttss2si(<4 x float> %a0) ; <i32> [#uses=1]206 ret i32 %res207}208declare i32 @llvm.x86.sse.cvttss2si(<4 x float>) nounwind readnone209 210 211define void @test_x86_sse_ldmxcsr(ptr %a0) #0 {212; CHECK-LABEL: @test_x86_sse_ldmxcsr(213; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8214; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8215; CHECK-NEXT: call void @llvm.donothing()216; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[A0:%.*]] to i64217; CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], -2147483649218; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr219; CHECK-NEXT: [[_LDMXCSR:%.*]] = load i32, ptr [[TMP4]], align 1220; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0221; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i32 [[_LDMXCSR]], 0222; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]223; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]224; CHECK: 6:225; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]226; CHECK-NEXT: unreachable227; CHECK: 7:228; CHECK-NEXT: call void @llvm.x86.sse.ldmxcsr(ptr [[A0]])229; CHECK-NEXT: ret void230;231 call void @llvm.x86.sse.ldmxcsr(ptr %a0)232 ret void233}234declare void @llvm.x86.sse.ldmxcsr(ptr) nounwind235 236 237 238define <4 x float> @test_x86_sse_max_ps(<4 x float> %a0, <4 x float> %a1) #0 {239; CHECK-LABEL: @test_x86_sse_max_ps(240; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8241; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8242; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8243; CHECK-NEXT: call void @llvm.donothing()244; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]]245; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse.max.ps(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]])246; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8247; CHECK-NEXT: ret <4 x float> [[RES]]248;249 %res = call <4 x float> @llvm.x86.sse.max.ps(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]250 ret <4 x float> %res251}252declare <4 x float> @llvm.x86.sse.max.ps(<4 x float>, <4 x float>) nounwind readnone253 254 255define <4 x float> @test_x86_sse_max_ss(<4 x float> %a0, <4 x float> %a1) #0 {256; CHECK-LABEL: @test_x86_sse_max_ss(257; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8258; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8259; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8260; CHECK-NEXT: call void @llvm.donothing()261; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]]262; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> [[TMP3]], <4 x i32> <i32 4, i32 1, i32 2, i32 3>263; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse.max.ss(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]])264; CHECK-NEXT: store <4 x i32> [[TMP4]], ptr @__msan_retval_tls, align 8265; CHECK-NEXT: ret <4 x float> [[RES]]266;267 %res = call <4 x float> @llvm.x86.sse.max.ss(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]268 ret <4 x float> %res269}270declare <4 x float> @llvm.x86.sse.max.ss(<4 x float>, <4 x float>) nounwind readnone271 272 273define <4 x float> @test_x86_sse_min_ps(<4 x float> %a0, <4 x float> %a1) #0 {274; CHECK-LABEL: @test_x86_sse_min_ps(275; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8276; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8277; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8278; CHECK-NEXT: call void @llvm.donothing()279; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]]280; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse.min.ps(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]])281; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8282; CHECK-NEXT: ret <4 x float> [[RES]]283;284 %res = call <4 x float> @llvm.x86.sse.min.ps(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]285 ret <4 x float> %res286}287declare <4 x float> @llvm.x86.sse.min.ps(<4 x float>, <4 x float>) nounwind readnone288 289 290define <4 x float> @test_x86_sse_min_ss(<4 x float> %a0, <4 x float> %a1) #0 {291; CHECK-LABEL: @test_x86_sse_min_ss(292; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8293; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8294; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8295; CHECK-NEXT: call void @llvm.donothing()296; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]]297; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> [[TMP3]], <4 x i32> <i32 4, i32 1, i32 2, i32 3>298; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse.min.ss(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]])299; CHECK-NEXT: store <4 x i32> [[TMP4]], ptr @__msan_retval_tls, align 8300; CHECK-NEXT: ret <4 x float> [[RES]]301;302 %res = call <4 x float> @llvm.x86.sse.min.ss(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]303 ret <4 x float> %res304}305declare <4 x float> @llvm.x86.sse.min.ss(<4 x float>, <4 x float>) nounwind readnone306 307 308define i32 @test_x86_sse_movmsk_ps(<4 x float> %a0) #0 {309; CHECK-LABEL: @test_x86_sse_movmsk_ps(310; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8311; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8312; CHECK-NEXT: call void @llvm.donothing()313; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[TMP1]] to i128314; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 0315; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP6:%.*]], label [[TMP5:%.*]], !prof [[PROF1]]316; CHECK: 4:317; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]318; CHECK-NEXT: unreachable319; CHECK: 5:320; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse.movmsk.ps(<4 x float> [[A0:%.*]])321; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8322; CHECK-NEXT: ret i32 [[RES]]323;324 %res = call i32 @llvm.x86.sse.movmsk.ps(<4 x float> %a0) ; <i32> [#uses=1]325 ret i32 %res326}327declare i32 @llvm.x86.sse.movmsk.ps(<4 x float>) nounwind readnone328 329 330 331define <4 x float> @test_x86_sse_rcp_ps(<4 x float> %a0) #0 {332; CHECK-LABEL: @test_x86_sse_rcp_ps(333; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8334; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8335; CHECK-NEXT: call void @llvm.donothing()336; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse.rcp.ps(<4 x float> [[A0:%.*]])337; CHECK-NEXT: store <4 x i32> [[TMP1]], ptr @__msan_retval_tls, align 8338; CHECK-NEXT: ret <4 x float> [[RES]]339;340 %res = call <4 x float> @llvm.x86.sse.rcp.ps(<4 x float> %a0) ; <<4 x float>> [#uses=1]341 ret <4 x float> %res342}343declare <4 x float> @llvm.x86.sse.rcp.ps(<4 x float>) nounwind readnone344 345 346define <4 x float> @test_x86_sse_rcp_ss(<4 x float> %a0) #0 {347; CHECK-LABEL: @test_x86_sse_rcp_ss(348; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8349; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8350; CHECK-NEXT: call void @llvm.donothing()351; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> [[A0:%.*]])352; CHECK-NEXT: store <4 x i32> [[TMP1]], ptr @__msan_retval_tls, align 8353; CHECK-NEXT: ret <4 x float> [[RES]]354;355 %res = call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> %a0) ; <<4 x float>> [#uses=1]356 ret <4 x float> %res357}358declare <4 x float> @llvm.x86.sse.rcp.ss(<4 x float>) nounwind readnone359 360 361define <4 x float> @test_x86_sse_rsqrt_ps(<4 x float> %a0) #0 {362; CHECK-LABEL: @test_x86_sse_rsqrt_ps(363; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8364; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8365; CHECK-NEXT: call void @llvm.donothing()366; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse.rsqrt.ps(<4 x float> [[A0:%.*]])367; CHECK-NEXT: store <4 x i32> [[TMP1]], ptr @__msan_retval_tls, align 8368; CHECK-NEXT: ret <4 x float> [[RES]]369;370 %res = call <4 x float> @llvm.x86.sse.rsqrt.ps(<4 x float> %a0) ; <<4 x float>> [#uses=1]371 ret <4 x float> %res372}373declare <4 x float> @llvm.x86.sse.rsqrt.ps(<4 x float>) nounwind readnone374 375 376define <4 x float> @test_x86_sse_rsqrt_ss(<4 x float> %a0) #0 {377; CHECK-LABEL: @test_x86_sse_rsqrt_ss(378; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8379; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8380; CHECK-NEXT: call void @llvm.donothing()381; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float> [[A0:%.*]])382; CHECK-NEXT: store <4 x i32> [[TMP1]], ptr @__msan_retval_tls, align 8383; CHECK-NEXT: ret <4 x float> [[RES]]384;385 %res = call <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float> %a0) ; <<4 x float>> [#uses=1]386 ret <4 x float> %res387}388declare <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float>) nounwind readnone389 390 391define void @test_x86_sse_stmxcsr(ptr %a0) #0 {392; CHECK-LABEL: @test_x86_sse_stmxcsr(393; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8394; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8395; CHECK-NEXT: call void @llvm.donothing()396; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[A0:%.*]] to i64397; CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], -2147483649398; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr399; CHECK-NEXT: store i32 0, ptr [[TMP4]], align 4400; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0401; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]402; CHECK: 6:403; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]404; CHECK-NEXT: unreachable405; CHECK: 7:406; CHECK-NEXT: call void @llvm.x86.sse.stmxcsr(ptr [[A0]])407; CHECK-NEXT: ret void408;409 call void @llvm.x86.sse.stmxcsr(ptr %a0)410 ret void411}412declare void @llvm.x86.sse.stmxcsr(ptr) nounwind413 414 415define i32 @test_x86_sse_ucomieq_ss(<4 x float> %a0, <4 x float> %a1) #0 {416; CHECK-LABEL: @test_x86_sse_ucomieq_ss(417; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8418; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8419; CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8420; CHECK-NEXT: call void @llvm.donothing()421; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]]422; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[TMP3]], i64 0423; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0424; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i32425; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse.ucomieq.ss(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]])426; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8427; CHECK-NEXT: ret i32 [[RES]]428;429 %res = call i32 @llvm.x86.sse.ucomieq.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]430 ret i32 %res431}432declare i32 @llvm.x86.sse.ucomieq.ss(<4 x float>, <4 x float>) nounwind readnone433 434 435define i32 @test_x86_sse_ucomige_ss(<4 x float> %a0, <4 x float> %a1) #0 {436; CHECK-LABEL: @test_x86_sse_ucomige_ss(437; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8438; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8439; CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8440; CHECK-NEXT: call void @llvm.donothing()441; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]]442; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[TMP3]], i64 0443; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0444; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i32445; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse.ucomige.ss(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]])446; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8447; CHECK-NEXT: ret i32 [[RES]]448;449 %res = call i32 @llvm.x86.sse.ucomige.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]450 ret i32 %res451}452declare i32 @llvm.x86.sse.ucomige.ss(<4 x float>, <4 x float>) nounwind readnone453 454 455define i32 @test_x86_sse_ucomigt_ss(<4 x float> %a0, <4 x float> %a1) #0 {456; CHECK-LABEL: @test_x86_sse_ucomigt_ss(457; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8458; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8459; CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8460; CHECK-NEXT: call void @llvm.donothing()461; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]]462; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[TMP3]], i64 0463; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0464; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i32465; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse.ucomigt.ss(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]])466; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8467; CHECK-NEXT: ret i32 [[RES]]468;469 %res = call i32 @llvm.x86.sse.ucomigt.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]470 ret i32 %res471}472declare i32 @llvm.x86.sse.ucomigt.ss(<4 x float>, <4 x float>) nounwind readnone473 474 475define i32 @test_x86_sse_ucomile_ss(<4 x float> %a0, <4 x float> %a1) #0 {476; CHECK-LABEL: @test_x86_sse_ucomile_ss(477; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8478; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8479; CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8480; CHECK-NEXT: call void @llvm.donothing()481; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]]482; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[TMP3]], i64 0483; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0484; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i32485; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse.ucomile.ss(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]])486; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8487; CHECK-NEXT: ret i32 [[RES]]488;489 %res = call i32 @llvm.x86.sse.ucomile.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]490 ret i32 %res491}492declare i32 @llvm.x86.sse.ucomile.ss(<4 x float>, <4 x float>) nounwind readnone493 494 495define i32 @test_x86_sse_ucomilt_ss(<4 x float> %a0, <4 x float> %a1) #0 {496; CHECK-LABEL: @test_x86_sse_ucomilt_ss(497; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8498; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8499; CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8500; CHECK-NEXT: call void @llvm.donothing()501; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]]502; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[TMP3]], i64 0503; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0504; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i32505; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse.ucomilt.ss(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]])506; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8507; CHECK-NEXT: ret i32 [[RES]]508;509 %res = call i32 @llvm.x86.sse.ucomilt.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]510 ret i32 %res511}512declare i32 @llvm.x86.sse.ucomilt.ss(<4 x float>, <4 x float>) nounwind readnone513 514 515define i32 @test_x86_sse_ucomineq_ss(<4 x float> %a0, <4 x float> %a1) #0 {516; CHECK-LABEL: @test_x86_sse_ucomineq_ss(517; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8518; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8519; CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8520; CHECK-NEXT: call void @llvm.donothing()521; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]]522; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[TMP3]], i64 0523; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0524; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i32525; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse.ucomineq.ss(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]])526; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8527; CHECK-NEXT: ret i32 [[RES]]528;529 %res = call i32 @llvm.x86.sse.ucomineq.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]530 ret i32 %res531}532declare i32 @llvm.x86.sse.ucomineq.ss(<4 x float>, <4 x float>) nounwind readnone533 534 535define void @sfence() nounwind {536; CHECK-LABEL: @sfence(537; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8538; CHECK-NEXT: call void @llvm.donothing()539; CHECK-NEXT: tail call void @llvm.x86.sse.sfence()540; CHECK-NEXT: ret void541;542 tail call void @llvm.x86.sse.sfence()543 ret void544}545declare void @llvm.x86.sse.sfence() nounwind546 547attributes #0 = { sanitize_memory }548