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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt %s -S -passes=msan 2>&1 | FileCheck %s3;4; Handled strictly:5; - i32 @llvm.x86.sse2.movmsk.pd(<2 x double> %a0)6; - i32 @llvm.x86.sse2.pmovmskb.128(<16 x i8> %a0)7; - void @llvm.x86.sse2.pause()8; - void @llvm.x86.sse2.lfence()9; - void @llvm.x86.sse2.mfence()10; - void @llvm.x86.sse2.clflush(ptr %p)11 12target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"13target triple = "i386-unknown-linux-gnu"14 15define <2 x double> @test_x86_sse2_cmp_pd(<2 x double> %a0, <2 x double> %a1) #0 {16; CHECK-LABEL: @test_x86_sse2_cmp_pd(17; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 818; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 819; CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 820; CHECK-NEXT: call void @llvm.donothing()21; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]]22; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <2 x i64> [[TMP3]], zeroinitializer23; CHECK-NEXT: [[TMP5:%.*]] = sext <2 x i1> [[TMP4]] to <2 x i64>24; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.sse2.cmp.pd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]], i8 7)25; CHECK-NEXT: store <2 x i64> [[TMP5]], ptr @__msan_retval_tls, align 826; CHECK-NEXT: ret <2 x double> [[RES]]27;28 %res = call <2 x double> @llvm.x86.sse2.cmp.pd(<2 x double> %a0, <2 x double> %a1, i8 7) ; <<2 x double>> [#uses=1]29 ret <2 x double> %res30}31declare <2 x double> @llvm.x86.sse2.cmp.pd(<2 x double>, <2 x double>, i8) nounwind readnone32 33 34define <2 x double> @test_x86_sse2_cmp_sd(<2 x double> %a0, <2 x double> %a1) #0 {35; CHECK-LABEL: @test_x86_sse2_cmp_sd(36; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 837; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 838; CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 839; CHECK-NEXT: call void @llvm.donothing()40; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]]41; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i64 042; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 043; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i12844; CHECK-NEXT: [[TMP7:%.*]] = bitcast i128 [[TMP6]] to <2 x i64>45; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]], i8 7)46; CHECK-NEXT: store <2 x i64> [[TMP7]], ptr @__msan_retval_tls, align 847; CHECK-NEXT: ret <2 x double> [[RES]]48;49 %res = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %a0, <2 x double> %a1, i8 7) ; <<2 x double>> [#uses=1]50 ret <2 x double> %res51}52declare <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double>, <2 x double>, i8) nounwind readnone53 54 55define i32 @test_x86_sse2_comieq_sd(<2 x double> %a0, <2 x double> %a1) #0 {56; CHECK-LABEL: @test_x86_sse2_comieq_sd(57; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 858; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 859; CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 860; CHECK-NEXT: call void @llvm.donothing()61; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]]62; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i64 063; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 064; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i3265; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.comieq.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]])66; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 867; CHECK-NEXT: ret i32 [[RES]]68;69 %res = call i32 @llvm.x86.sse2.comieq.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]70 ret i32 %res71}72declare i32 @llvm.x86.sse2.comieq.sd(<2 x double>, <2 x double>) nounwind readnone73 74 75define i32 @test_x86_sse2_comige_sd(<2 x double> %a0, <2 x double> %a1) #0 {76; CHECK-LABEL: @test_x86_sse2_comige_sd(77; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 878; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 879; CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 880; CHECK-NEXT: call void @llvm.donothing()81; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]]82; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i64 083; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 084; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i3285; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.comige.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]])86; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 887; CHECK-NEXT: ret i32 [[RES]]88;89 %res = call i32 @llvm.x86.sse2.comige.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]90 ret i32 %res91}92declare i32 @llvm.x86.sse2.comige.sd(<2 x double>, <2 x double>) nounwind readnone93 94 95define i32 @test_x86_sse2_comigt_sd(<2 x double> %a0, <2 x double> %a1) #0 {96; CHECK-LABEL: @test_x86_sse2_comigt_sd(97; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 898; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 899; CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8100; CHECK-NEXT: call void @llvm.donothing()101; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]]102; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i64 0103; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 0104; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i32105; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.comigt.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]])106; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8107; CHECK-NEXT: ret i32 [[RES]]108;109 %res = call i32 @llvm.x86.sse2.comigt.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]110 ret i32 %res111}112declare i32 @llvm.x86.sse2.comigt.sd(<2 x double>, <2 x double>) nounwind readnone113 114 115define i32 @test_x86_sse2_comile_sd(<2 x double> %a0, <2 x double> %a1) #0 {116; CHECK-LABEL: @test_x86_sse2_comile_sd(117; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8118; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8119; CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8120; CHECK-NEXT: call void @llvm.donothing()121; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]]122; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i64 0123; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 0124; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i32125; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.comile.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]])126; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8127; CHECK-NEXT: ret i32 [[RES]]128;129 %res = call i32 @llvm.x86.sse2.comile.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]130 ret i32 %res131}132declare i32 @llvm.x86.sse2.comile.sd(<2 x double>, <2 x double>) nounwind readnone133 134 135define i32 @test_x86_sse2_comilt_sd(<2 x double> %a0, <2 x double> %a1) #0 {136; CHECK-LABEL: @test_x86_sse2_comilt_sd(137; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8138; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8139; CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8140; CHECK-NEXT: call void @llvm.donothing()141; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]]142; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i64 0143; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 0144; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i32145; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.comilt.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]])146; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8147; CHECK-NEXT: ret i32 [[RES]]148;149 %res = call i32 @llvm.x86.sse2.comilt.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]150 ret i32 %res151}152declare i32 @llvm.x86.sse2.comilt.sd(<2 x double>, <2 x double>) nounwind readnone153 154 155define i32 @test_x86_sse2_comineq_sd(<2 x double> %a0, <2 x double> %a1) #0 {156; CHECK-LABEL: @test_x86_sse2_comineq_sd(157; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8158; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8159; CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8160; CHECK-NEXT: call void @llvm.donothing()161; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]]162; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i64 0163; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 0164; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i32165; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.comineq.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]])166; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8167; CHECK-NEXT: ret i32 [[RES]]168;169 %res = call i32 @llvm.x86.sse2.comineq.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]170 ret i32 %res171}172declare i32 @llvm.x86.sse2.comineq.sd(<2 x double>, <2 x double>) nounwind readnone173 174 175define <4 x i32> @test_x86_sse2_cvtpd2dq(<2 x double> %a0) #0 {176; CHECK-LABEL: @test_x86_sse2_cvtpd2dq(177; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8178; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8179; CHECK-NEXT: call void @llvm.donothing()180; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <2 x i64> [[TMP1]], zeroinitializer181; CHECK-NEXT: [[TMP6:%.*]] = sext <2 x i1> [[TMP3]] to <2 x i32>182; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x i32> [[TMP6]], <2 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>183; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double> [[A0:%.*]])184; CHECK-NEXT: store <4 x i32> [[TMP5]], ptr @__msan_retval_tls, align 8185; CHECK-NEXT: ret <4 x i32> [[RES]]186;187 %res = call <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double> %a0) ; <<4 x i32>> [#uses=1]188 ret <4 x i32> %res189}190declare <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double>) nounwind readnone191 192 193define <2 x i64> @test_mm_cvtpd_epi32_zext(<2 x double> %a0) nounwind #0 {194; CHECK-LABEL: @test_mm_cvtpd_epi32_zext(195; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8196; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8197; CHECK-NEXT: call void @llvm.donothing()198; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <2 x i64> [[TMP1]], zeroinitializer199; CHECK-NEXT: [[TMP6:%.*]] = sext <2 x i1> [[TMP3]] to <2 x i32>200; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x i32> [[TMP6]], <2 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>201; CHECK-NEXT: [[CVT:%.*]] = call <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double> [[A0:%.*]])202; CHECK-NEXT: [[RES:%.*]] = shufflevector <4 x i32> [[TMP5]], <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>203; CHECK-NEXT: [[RES1:%.*]] = shufflevector <4 x i32> [[CVT]], <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>204; CHECK-NEXT: [[BC:%.*]] = bitcast <4 x i32> [[RES]] to <2 x i64>205; CHECK-NEXT: [[BC1:%.*]] = bitcast <4 x i32> [[RES1]] to <2 x i64>206; CHECK-NEXT: store <2 x i64> [[BC]], ptr @__msan_retval_tls, align 8207; CHECK-NEXT: ret <2 x i64> [[BC1]]208;209 %cvt = call <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double> %a0)210 %res = shufflevector <4 x i32> %cvt, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>211 %bc = bitcast <4 x i32> %res to <2 x i64>212 ret <2 x i64> %bc213}214 215 216define <2 x i64> @test_mm_cvtpd_epi32_zext_load(ptr %p0) nounwind #0 {217; CHECK-LABEL: @test_mm_cvtpd_epi32_zext_load(218; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8219; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8220; CHECK-NEXT: call void @llvm.donothing()221; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0222; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP7:%.*]], !prof [[PROF1:![0-9]+]]223; CHECK: 3:224; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5:[0-9]+]]225; CHECK-NEXT: unreachable226; CHECK: 4:227; CHECK-NEXT: [[A0:%.*]] = load <2 x double>, ptr [[P0:%.*]], align 16228; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P0]] to i64229; CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], -2147483649230; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr231; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP6]], align 16232; CHECK-NEXT: [[TMP8:%.*]] = icmp ne <2 x i64> [[_MSLD]], zeroinitializer233; CHECK-NEXT: [[TMP9:%.*]] = sext <2 x i1> [[TMP8]] to <2 x i32>234; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <2 x i32> [[TMP9]], <2 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>235; CHECK-NEXT: [[CVT:%.*]] = call <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double> [[A0]])236; CHECK-NEXT: [[RES:%.*]] = shufflevector <4 x i32> [[TMP10]], <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>237; CHECK-NEXT: [[RES1:%.*]] = shufflevector <4 x i32> [[CVT]], <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>238; CHECK-NEXT: [[BC:%.*]] = bitcast <4 x i32> [[RES]] to <2 x i64>239; CHECK-NEXT: [[BC1:%.*]] = bitcast <4 x i32> [[RES1]] to <2 x i64>240; CHECK-NEXT: store <2 x i64> [[BC]], ptr @__msan_retval_tls, align 8241; CHECK-NEXT: ret <2 x i64> [[BC1]]242;243 %a0 = load <2 x double>, ptr %p0244 %cvt = call <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double> %a0)245 %res = shufflevector <4 x i32> %cvt, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>246 %bc = bitcast <4 x i32> %res to <2 x i64>247 ret <2 x i64> %bc248}249 250 251define <4 x float> @test_x86_sse2_cvtpd2ps(<2 x double> %a0) #0 {252; CHECK-LABEL: @test_x86_sse2_cvtpd2ps(253; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8254; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8255; CHECK-NEXT: call void @llvm.donothing()256; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <2 x i64> [[TMP1]], zeroinitializer257; CHECK-NEXT: [[TMP6:%.*]] = sext <2 x i1> [[TMP3]] to <2 x i32>258; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x i32> [[TMP6]], <2 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>259; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse2.cvtpd2ps(<2 x double> [[A0:%.*]])260; CHECK-NEXT: store <4 x i32> [[TMP5]], ptr @__msan_retval_tls, align 8261; CHECK-NEXT: ret <4 x float> [[RES]]262;263 %res = call <4 x float> @llvm.x86.sse2.cvtpd2ps(<2 x double> %a0) ; <<4 x float>> [#uses=1]264 ret <4 x float> %res265}266declare <4 x float> @llvm.x86.sse2.cvtpd2ps(<2 x double>) nounwind readnone267 268define <4 x float> @test_x86_sse2_cvtpd2ps_zext(<2 x double> %a0) nounwind #0 {269; CHECK-LABEL: @test_x86_sse2_cvtpd2ps_zext(270; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8271; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8272; CHECK-NEXT: call void @llvm.donothing()273; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <2 x i64> [[TMP1]], zeroinitializer274; CHECK-NEXT: [[TMP6:%.*]] = sext <2 x i1> [[TMP3]] to <2 x i32>275; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x i32> [[TMP6]], <2 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>276; CHECK-NEXT: [[CVT:%.*]] = call <4 x float> @llvm.x86.sse2.cvtpd2ps(<2 x double> [[A0:%.*]])277; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i32> [[TMP5]], <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>278; CHECK-NEXT: [[RES:%.*]] = shufflevector <4 x float> [[CVT]], <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>279; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8280; CHECK-NEXT: ret <4 x float> [[RES]]281;282 %cvt = call <4 x float> @llvm.x86.sse2.cvtpd2ps(<2 x double> %a0)283 %res = shufflevector <4 x float> %cvt, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>284 ret <4 x float> %res285}286 287define <4 x float> @test_x86_sse2_cvtpd2ps_zext_load(ptr %p0) nounwind #0 {288; CHECK-LABEL: @test_x86_sse2_cvtpd2ps_zext_load(289; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8290; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8291; CHECK-NEXT: call void @llvm.donothing()292; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0293; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]294; CHECK: 3:295; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]296; CHECK-NEXT: unreachable297; CHECK: 4:298; CHECK-NEXT: [[A0:%.*]] = load <2 x double>, ptr [[P0:%.*]], align 16299; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P0]] to i64300; CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], -2147483649301; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr302; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP6]], align 16303; CHECK-NEXT: [[TMP8:%.*]] = icmp ne <2 x i64> [[_MSLD]], zeroinitializer304; CHECK-NEXT: [[TMP9:%.*]] = sext <2 x i1> [[TMP8]] to <2 x i32>305; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <2 x i32> [[TMP9]], <2 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>306; CHECK-NEXT: [[CVT:%.*]] = call <4 x float> @llvm.x86.sse2.cvtpd2ps(<2 x double> [[A0]])307; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i32> [[TMP10]], <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>308; CHECK-NEXT: [[RES:%.*]] = shufflevector <4 x float> [[CVT]], <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>309; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8310; CHECK-NEXT: ret <4 x float> [[RES]]311;312 %a0 = load <2 x double>, ptr %p0313 %cvt = call <4 x float> @llvm.x86.sse2.cvtpd2ps(<2 x double> %a0)314 %res = shufflevector <4 x float> %cvt, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>315 ret <4 x float> %res316}317 318define <4 x i32> @test_x86_sse2_cvtps2dq(<4 x float> %a0) #0 {319; CHECK-LABEL: @test_x86_sse2_cvtps2dq(320; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8321; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8322; CHECK-NEXT: call void @llvm.donothing()323; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <4 x i32> [[TMP1]], zeroinitializer324; CHECK-NEXT: [[TMP5:%.*]] = sext <4 x i1> [[TMP3]] to <4 x i32>325; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.sse2.cvtps2dq(<4 x float> [[A0:%.*]])326; CHECK-NEXT: store <4 x i32> [[TMP5]], ptr @__msan_retval_tls, align 8327; CHECK-NEXT: ret <4 x i32> [[RES]]328;329 %res = call <4 x i32> @llvm.x86.sse2.cvtps2dq(<4 x float> %a0) ; <<4 x i32>> [#uses=1]330 ret <4 x i32> %res331}332declare <4 x i32> @llvm.x86.sse2.cvtps2dq(<4 x float>) nounwind readnone333 334 335define i32 @test_x86_sse2_cvtsd2si(<2 x double> %a0) #0 {336; CHECK-LABEL: @test_x86_sse2_cvtsd2si(337; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8338; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8339; CHECK-NEXT: call void @llvm.donothing()340; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i64> [[TMP1]], i32 0341; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0342; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP6:%.*]], label [[TMP5:%.*]], !prof [[PROF1]]343; CHECK: 4:344; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]345; CHECK-NEXT: unreachable346; CHECK: 5:347; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.cvtsd2si(<2 x double> [[A0:%.*]])348; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8349; CHECK-NEXT: ret i32 [[RES]]350;351 %res = call i32 @llvm.x86.sse2.cvtsd2si(<2 x double> %a0) ; <i32> [#uses=1]352 ret i32 %res353}354declare i32 @llvm.x86.sse2.cvtsd2si(<2 x double>) nounwind readnone355 356 357define <4 x float> @test_x86_sse2_cvtsd2ss(<4 x float> %a0, <2 x double> %a1) #0 {358; CHECK-LABEL: @test_x86_sse2_cvtsd2ss(359; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8360; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8361; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8362; CHECK-NEXT: call void @llvm.donothing()363; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i64> [[TMP1]], i32 0364; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP2]], i32 0, i32 0365; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP3]], 0366; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]367; CHECK: 6:368; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]369; CHECK-NEXT: unreachable370; CHECK: 7:371; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float> [[A0:%.*]], <2 x double> [[A1:%.*]])372; CHECK-NEXT: store <4 x i32> [[TMP4]], ptr @__msan_retval_tls, align 8373; CHECK-NEXT: ret <4 x float> [[RES]]374;375 %res = call <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float> %a0, <2 x double> %a1) ; <<4 x float>> [#uses=1]376 ret <4 x float> %res377}378declare <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float>, <2 x double>) nounwind readnone379 380 381define <4 x float> @test_x86_sse2_cvtsd2ss_load(<4 x float> %a0, ptr %p1) #0 {382; CHECK-LABEL: @test_x86_sse2_cvtsd2ss_load(383; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8384; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8385; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8386; CHECK-NEXT: call void @llvm.donothing()387; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0388; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP4:%.*]], label [[TMP10:%.*]], !prof [[PROF1]]389; CHECK: 4:390; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]391; CHECK-NEXT: unreachable392; CHECK: 5:393; CHECK-NEXT: [[A1:%.*]] = load <2 x double>, ptr [[P1:%.*]], align 16394; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[P1]] to i64395; CHECK-NEXT: [[TMP6:%.*]] = and i64 [[TMP5]], -2147483649396; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr397; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP7]], align 16398; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i64> [[_MSLD]], i32 0399; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i32> [[TMP2]], i32 0, i32 0400; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP8]], 0401; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP11:%.*]], label [[TMP12:%.*]], !prof [[PROF1]]402; CHECK: 11:403; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]404; CHECK-NEXT: unreachable405; CHECK: 12:406; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float> [[A0:%.*]], <2 x double> [[A1]])407; CHECK-NEXT: store <4 x i32> [[TMP9]], ptr @__msan_retval_tls, align 8408; CHECK-NEXT: ret <4 x float> [[RES]]409;410 %a1 = load <2 x double>, ptr %p1411 %res = call <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float> %a0, <2 x double> %a1) ; <<4 x float>> [#uses=1]412 ret <4 x float> %res413}414 415 416define <4 x float> @test_x86_sse2_cvtsd2ss_load_optsize(<4 x float> %a0, ptr %p1) optsize #0 {417; CHECK-LABEL: @test_x86_sse2_cvtsd2ss_load_optsize(418; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8419; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8420; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8421; CHECK-NEXT: call void @llvm.donothing()422; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0423; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP4:%.*]], label [[TMP10:%.*]], !prof [[PROF1]]424; CHECK: 4:425; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]426; CHECK-NEXT: unreachable427; CHECK: 5:428; CHECK-NEXT: [[A1:%.*]] = load <2 x double>, ptr [[P1:%.*]], align 16429; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[P1]] to i64430; CHECK-NEXT: [[TMP6:%.*]] = and i64 [[TMP5]], -2147483649431; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr432; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP7]], align 16433; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i64> [[_MSLD]], i32 0434; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i32> [[TMP2]], i32 0, i32 0435; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP8]], 0436; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP11:%.*]], label [[TMP12:%.*]], !prof [[PROF1]]437; CHECK: 11:438; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]439; CHECK-NEXT: unreachable440; CHECK: 12:441; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float> [[A0:%.*]], <2 x double> [[A1]])442; CHECK-NEXT: store <4 x i32> [[TMP9]], ptr @__msan_retval_tls, align 8443; CHECK-NEXT: ret <4 x float> [[RES]]444;445 %a1 = load <2 x double>, ptr %p1446 %res = call <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float> %a0, <2 x double> %a1) ; <<4 x float>> [#uses=1]447 ret <4 x float> %res448}449 450 451define <4 x i32> @test_x86_sse2_cvttpd2dq(<2 x double> %a0) #0 {452; CHECK-LABEL: @test_x86_sse2_cvttpd2dq(453; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8454; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8455; CHECK-NEXT: call void @llvm.donothing()456; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <2 x i64> [[TMP1]], zeroinitializer457; CHECK-NEXT: [[TMP6:%.*]] = sext <2 x i1> [[TMP3]] to <2 x i32>458; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x i32> [[TMP6]], <2 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>459; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double> [[A0:%.*]])460; CHECK-NEXT: store <4 x i32> [[TMP5]], ptr @__msan_retval_tls, align 8461; CHECK-NEXT: ret <4 x i32> [[RES]]462;463 %res = call <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double> %a0) ; <<4 x i32>> [#uses=1]464 ret <4 x i32> %res465}466declare <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double>) nounwind readnone467 468 469define <2 x i64> @test_mm_cvttpd_epi32_zext(<2 x double> %a0) nounwind #0 {470; CHECK-LABEL: @test_mm_cvttpd_epi32_zext(471; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8472; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8473; CHECK-NEXT: call void @llvm.donothing()474; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <2 x i64> [[TMP1]], zeroinitializer475; CHECK-NEXT: [[TMP6:%.*]] = sext <2 x i1> [[TMP3]] to <2 x i32>476; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x i32> [[TMP6]], <2 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>477; CHECK-NEXT: [[CVT:%.*]] = call <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double> [[A0:%.*]])478; CHECK-NEXT: [[RES:%.*]] = shufflevector <4 x i32> [[TMP5]], <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>479; CHECK-NEXT: [[RES1:%.*]] = shufflevector <4 x i32> [[CVT]], <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>480; CHECK-NEXT: [[BC:%.*]] = bitcast <4 x i32> [[RES]] to <2 x i64>481; CHECK-NEXT: [[BC1:%.*]] = bitcast <4 x i32> [[RES1]] to <2 x i64>482; CHECK-NEXT: store <2 x i64> [[BC]], ptr @__msan_retval_tls, align 8483; CHECK-NEXT: ret <2 x i64> [[BC1]]484;485 %cvt = call <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double> %a0)486 %res = shufflevector <4 x i32> %cvt, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>487 %bc = bitcast <4 x i32> %res to <2 x i64>488 ret <2 x i64> %bc489}490 491 492define <2 x i64> @test_mm_cvttpd_epi32_zext_load(ptr %p0) nounwind #0 {493; CHECK-LABEL: @test_mm_cvttpd_epi32_zext_load(494; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8495; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8496; CHECK-NEXT: call void @llvm.donothing()497; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0498; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP7:%.*]], !prof [[PROF1]]499; CHECK: 3:500; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]501; CHECK-NEXT: unreachable502; CHECK: 4:503; CHECK-NEXT: [[A0:%.*]] = load <2 x double>, ptr [[P0:%.*]], align 16504; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P0]] to i64505; CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], -2147483649506; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr507; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP6]], align 16508; CHECK-NEXT: [[TMP8:%.*]] = icmp ne <2 x i64> [[_MSLD]], zeroinitializer509; CHECK-NEXT: [[TMP9:%.*]] = sext <2 x i1> [[TMP8]] to <2 x i32>510; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <2 x i32> [[TMP9]], <2 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>511; CHECK-NEXT: [[CVT:%.*]] = call <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double> [[A0]])512; CHECK-NEXT: [[RES:%.*]] = shufflevector <4 x i32> [[TMP10]], <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>513; CHECK-NEXT: [[RES1:%.*]] = shufflevector <4 x i32> [[CVT]], <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>514; CHECK-NEXT: [[BC:%.*]] = bitcast <4 x i32> [[RES]] to <2 x i64>515; CHECK-NEXT: [[BC1:%.*]] = bitcast <4 x i32> [[RES1]] to <2 x i64>516; CHECK-NEXT: store <2 x i64> [[BC]], ptr @__msan_retval_tls, align 8517; CHECK-NEXT: ret <2 x i64> [[BC1]]518;519 %a0 = load <2 x double>, ptr %p0520 %cvt = call <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double> %a0)521 %res = shufflevector <4 x i32> %cvt, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>522 %bc = bitcast <4 x i32> %res to <2 x i64>523 ret <2 x i64> %bc524}525 526 527define <4 x i32> @test_x86_sse2_cvttps2dq(<4 x float> %a0) #0 {528; CHECK-LABEL: @test_x86_sse2_cvttps2dq(529; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8530; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8531; CHECK-NEXT: call void @llvm.donothing()532; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <4 x i32> [[TMP1]], zeroinitializer533; CHECK-NEXT: [[TMP5:%.*]] = sext <4 x i1> [[TMP3]] to <4 x i32>534; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> [[A0:%.*]])535; CHECK-NEXT: store <4 x i32> [[TMP5]], ptr @__msan_retval_tls, align 8536; CHECK-NEXT: ret <4 x i32> [[RES]]537;538 %res = call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> %a0) ; <<4 x i32>> [#uses=1]539 ret <4 x i32> %res540}541declare <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float>) nounwind readnone542 543 544define i32 @test_x86_sse2_cvttsd2si(<2 x double> %a0) #0 {545; CHECK-LABEL: @test_x86_sse2_cvttsd2si(546; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8547; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8548; CHECK-NEXT: call void @llvm.donothing()549; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i64> [[TMP1]], i32 0550; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0551; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP6:%.*]], label [[TMP5:%.*]], !prof [[PROF1]]552; CHECK: 4:553; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]554; CHECK-NEXT: unreachable555; CHECK: 5:556; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.cvttsd2si(<2 x double> [[A0:%.*]])557; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8558; CHECK-NEXT: ret i32 [[RES]]559;560 %res = call i32 @llvm.x86.sse2.cvttsd2si(<2 x double> %a0) ; <i32> [#uses=1]561 ret i32 %res562}563declare i32 @llvm.x86.sse2.cvttsd2si(<2 x double>) nounwind readnone564 565 566define <2 x double> @test_x86_sse2_max_pd(<2 x double> %a0, <2 x double> %a1) #0 {567; CHECK-LABEL: @test_x86_sse2_max_pd(568; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8569; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8570; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8571; CHECK-NEXT: call void @llvm.donothing()572; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]]573; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.sse2.max.pd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]])574; CHECK-NEXT: store <2 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 8575; CHECK-NEXT: ret <2 x double> [[RES]]576;577 %res = call <2 x double> @llvm.x86.sse2.max.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]578 ret <2 x double> %res579}580declare <2 x double> @llvm.x86.sse2.max.pd(<2 x double>, <2 x double>) nounwind readnone581 582 583define <2 x double> @test_x86_sse2_max_sd(<2 x double> %a0, <2 x double> %a1) #0 {584; CHECK-LABEL: @test_x86_sse2_max_sd(585; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8586; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8587; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8588; CHECK-NEXT: call void @llvm.donothing()589; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]]590; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> [[TMP3]], <2 x i32> <i32 2, i32 1>591; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.sse2.max.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]])592; CHECK-NEXT: store <2 x i64> [[TMP4]], ptr @__msan_retval_tls, align 8593; CHECK-NEXT: ret <2 x double> [[RES]]594;595 %res = call <2 x double> @llvm.x86.sse2.max.sd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]596 ret <2 x double> %res597}598declare <2 x double> @llvm.x86.sse2.max.sd(<2 x double>, <2 x double>) nounwind readnone599 600 601define <2 x double> @test_x86_sse2_min_pd(<2 x double> %a0, <2 x double> %a1) #0 {602; CHECK-LABEL: @test_x86_sse2_min_pd(603; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8604; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8605; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8606; CHECK-NEXT: call void @llvm.donothing()607; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]]608; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.sse2.min.pd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]])609; CHECK-NEXT: store <2 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 8610; CHECK-NEXT: ret <2 x double> [[RES]]611;612 %res = call <2 x double> @llvm.x86.sse2.min.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]613 ret <2 x double> %res614}615declare <2 x double> @llvm.x86.sse2.min.pd(<2 x double>, <2 x double>) nounwind readnone616 617 618define <2 x double> @test_x86_sse2_min_sd(<2 x double> %a0, <2 x double> %a1) #0 {619; CHECK-LABEL: @test_x86_sse2_min_sd(620; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8621; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8622; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8623; CHECK-NEXT: call void @llvm.donothing()624; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]]625; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> [[TMP3]], <2 x i32> <i32 2, i32 1>626; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.sse2.min.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]])627; CHECK-NEXT: store <2 x i64> [[TMP4]], ptr @__msan_retval_tls, align 8628; CHECK-NEXT: ret <2 x double> [[RES]]629;630 %res = call <2 x double> @llvm.x86.sse2.min.sd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]631 ret <2 x double> %res632}633declare <2 x double> @llvm.x86.sse2.min.sd(<2 x double>, <2 x double>) nounwind readnone634 635 636define i32 @test_x86_sse2_movmsk_pd(<2 x double> %a0) #0 {637; CHECK-LABEL: @test_x86_sse2_movmsk_pd(638; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8639; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8640; CHECK-NEXT: call void @llvm.donothing()641; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to i128642; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 0643; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP6:%.*]], label [[TMP5:%.*]], !prof [[PROF1]]644; CHECK: 4:645; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]646; CHECK-NEXT: unreachable647; CHECK: 5:648; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.movmsk.pd(<2 x double> [[A0:%.*]])649; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8650; CHECK-NEXT: ret i32 [[RES]]651;652 %res = call i32 @llvm.x86.sse2.movmsk.pd(<2 x double> %a0) ; <i32> [#uses=1]653 ret i32 %res654}655declare i32 @llvm.x86.sse2.movmsk.pd(<2 x double>) nounwind readnone656 657 658define <8 x i16> @test_x86_sse2_packssdw_128(<4 x i32> %a0, <4 x i32> %a1) #0 {659; CHECK-LABEL: @test_x86_sse2_packssdw_128(660; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8661; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8662; CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8663; CHECK-NEXT: call void @llvm.donothing()664; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <4 x i32> [[TMP1]], zeroinitializer665; CHECK-NEXT: [[TMP4:%.*]] = sext <4 x i1> [[TMP3]] to <4 x i32>666; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <4 x i32> [[TMP2]], zeroinitializer667; CHECK-NEXT: [[TMP6:%.*]] = sext <4 x i1> [[TMP5]] to <4 x i32>668; CHECK-NEXT: [[_MSPROP_VECTOR_PACK:%.*]] = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> [[TMP4]], <4 x i32> [[TMP6]])669; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> [[A0:%.*]], <4 x i32> [[A1:%.*]])670; CHECK-NEXT: store <8 x i16> [[_MSPROP_VECTOR_PACK]], ptr @__msan_retval_tls, align 8671; CHECK-NEXT: ret <8 x i16> [[RES]]672;673 %res = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> %a0, <4 x i32> %a1) ; <<8 x i16>> [#uses=1]674 ret <8 x i16> %res675}676declare <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32>, <4 x i32>) nounwind readnone677 678 679define <8 x i16> @test_x86_sse2_packssdw_128_fold() #0 {680; CHECK-LABEL: @test_x86_sse2_packssdw_128_fold(681; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8682; CHECK-NEXT: call void @llvm.donothing()683; CHECK-NEXT: [[_MSPROP_VECTOR_PACK:%.*]] = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> zeroinitializer, <4 x i32> zeroinitializer)684; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> zeroinitializer, <4 x i32> <i32 65535, i32 65536, i32 -1, i32 -131072>)685; CHECK-NEXT: store <8 x i16> [[_MSPROP_VECTOR_PACK]], ptr @__msan_retval_tls, align 8686; CHECK-NEXT: ret <8 x i16> [[RES]]687;688 %res = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> zeroinitializer, <4 x i32> <i32 65535, i32 65536, i32 -1, i32 -131072>)689 ret <8 x i16> %res690}691 692 693define <16 x i8> @test_x86_sse2_packsswb_128(<8 x i16> %a0, <8 x i16> %a1) #0 {694; CHECK-LABEL: @test_x86_sse2_packsswb_128(695; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8696; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8697; CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8698; CHECK-NEXT: call void @llvm.donothing()699; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <8 x i16> [[TMP1]], zeroinitializer700; CHECK-NEXT: [[TMP4:%.*]] = sext <8 x i1> [[TMP3]] to <8 x i16>701; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <8 x i16> [[TMP2]], zeroinitializer702; CHECK-NEXT: [[TMP6:%.*]] = sext <8 x i1> [[TMP5]] to <8 x i16>703; CHECK-NEXT: [[_MSPROP_VECTOR_PACK:%.*]] = call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> [[TMP4]], <8 x i16> [[TMP6]])704; CHECK-NEXT: [[RES:%.*]] = call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> [[A0:%.*]], <8 x i16> [[A1:%.*]])705; CHECK-NEXT: store <16 x i8> [[_MSPROP_VECTOR_PACK]], ptr @__msan_retval_tls, align 8706; CHECK-NEXT: ret <16 x i8> [[RES]]707;708 %res = call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> %a0, <8 x i16> %a1) ; <<16 x i8>> [#uses=1]709 ret <16 x i8> %res710}711declare <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16>, <8 x i16>) nounwind readnone712 713 714define <16 x i8> @test_x86_sse2_packsswb_128_fold() #0 {715; CHECK-LABEL: @test_x86_sse2_packsswb_128_fold(716; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8717; CHECK-NEXT: call void @llvm.donothing()718; CHECK-NEXT: [[_MSPROP_VECTOR_PACK:%.*]] = call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> zeroinitializer, <8 x i16> zeroinitializer)719; CHECK-NEXT: [[RES:%.*]] = call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> <i16 0, i16 255, i16 256, i16 -1, i16 -1, i16 -255, i16 -256, i16 -32678>, <8 x i16> zeroinitializer)720; CHECK-NEXT: store <16 x i8> [[_MSPROP_VECTOR_PACK]], ptr @__msan_retval_tls, align 8721; CHECK-NEXT: ret <16 x i8> [[RES]]722;723 %res = call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> <i16 0, i16 255, i16 256, i16 65535, i16 -1, i16 -255, i16 -256, i16 -32678>, <8 x i16> zeroinitializer)724 ret <16 x i8> %res725}726 727 728define <16 x i8> @test_x86_sse2_packuswb_128(<8 x i16> %a0, <8 x i16> %a1) #0 {729; CHECK-LABEL: @test_x86_sse2_packuswb_128(730; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8731; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8732; CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8733; CHECK-NEXT: call void @llvm.donothing()734; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <8 x i16> [[TMP1]], zeroinitializer735; CHECK-NEXT: [[TMP4:%.*]] = sext <8 x i1> [[TMP3]] to <8 x i16>736; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <8 x i16> [[TMP2]], zeroinitializer737; CHECK-NEXT: [[TMP6:%.*]] = sext <8 x i1> [[TMP5]] to <8 x i16>738; CHECK-NEXT: [[_MSPROP_VECTOR_PACK:%.*]] = call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> [[TMP4]], <8 x i16> [[TMP6]])739; CHECK-NEXT: [[RES:%.*]] = call <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16> [[A0:%.*]], <8 x i16> [[A1:%.*]])740; CHECK-NEXT: store <16 x i8> [[_MSPROP_VECTOR_PACK]], ptr @__msan_retval_tls, align 8741; CHECK-NEXT: ret <16 x i8> [[RES]]742;743 %res = call <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16> %a0, <8 x i16> %a1) ; <<16 x i8>> [#uses=1]744 ret <16 x i8> %res745}746declare <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16>, <8 x i16>) nounwind readnone747 748 749define <16 x i8> @test_x86_sse2_packuswb_128_fold() #0 {750; CHECK-LABEL: @test_x86_sse2_packuswb_128_fold(751; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8752; CHECK-NEXT: call void @llvm.donothing()753; CHECK-NEXT: [[_MSPROP_VECTOR_PACK:%.*]] = call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> zeroinitializer, <8 x i16> zeroinitializer)754; CHECK-NEXT: [[RES:%.*]] = call <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16> <i16 0, i16 255, i16 256, i16 -1, i16 -1, i16 -255, i16 -256, i16 -32678>, <8 x i16> zeroinitializer)755; CHECK-NEXT: store <16 x i8> [[_MSPROP_VECTOR_PACK]], ptr @__msan_retval_tls, align 8756; CHECK-NEXT: ret <16 x i8> [[RES]]757;758 %res = call <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16> <i16 0, i16 255, i16 256, i16 65535, i16 -1, i16 -255, i16 -256, i16 -32678>, <8 x i16> zeroinitializer)759 ret <16 x i8> %res760}761 762 763define <16 x i8> @test_x86_sse2_pavg_b(<16 x i8> %a0, <16 x i8> %a1) #0 {764; CHECK-LABEL: @test_x86_sse2_pavg_b(765; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @__msan_param_tls, align 8766; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8767; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8768; CHECK-NEXT: call void @llvm.donothing()769; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i8> [[TMP1]], [[TMP2]]770; CHECK-NEXT: [[RES:%.*]] = call <16 x i8> @llvm.x86.sse2.pavg.b(<16 x i8> [[A0:%.*]], <16 x i8> [[A1:%.*]])771; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 8772; CHECK-NEXT: ret <16 x i8> [[RES]]773;774 %res = call <16 x i8> @llvm.x86.sse2.pavg.b(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1]775 ret <16 x i8> %res776}777declare <16 x i8> @llvm.x86.sse2.pavg.b(<16 x i8>, <16 x i8>) nounwind readnone778 779 780define <8 x i16> @test_x86_sse2_pavg_w(<8 x i16> %a0, <8 x i16> %a1) #0 {781; CHECK-LABEL: @test_x86_sse2_pavg_w(782; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8783; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8784; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8785; CHECK-NEXT: call void @llvm.donothing()786; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP1]], [[TMP2]]787; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.x86.sse2.pavg.w(<8 x i16> [[A0:%.*]], <8 x i16> [[A1:%.*]])788; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8789; CHECK-NEXT: ret <8 x i16> [[RES]]790;791 %res = call <8 x i16> @llvm.x86.sse2.pavg.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]792 ret <8 x i16> %res793}794declare <8 x i16> @llvm.x86.sse2.pavg.w(<8 x i16>, <8 x i16>) nounwind readnone795 796 797define <4 x i32> @test_x86_sse2_pmadd_wd(<8 x i16> %a0, <8 x i16> %a1) #0 {798; CHECK-LABEL: @test_x86_sse2_pmadd_wd(799; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8800; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8801; CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8802; CHECK-NEXT: call void @llvm.donothing()803; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <8 x i16> [[TMP1]], zeroinitializer804; CHECK-NEXT: [[TMP12:%.*]] = icmp ne <8 x i16> [[TMP2]], zeroinitializer805; CHECK-NEXT: [[TMP14:%.*]] = icmp ne <8 x i16> [[A0:%.*]], zeroinitializer806; CHECK-NEXT: [[TMP15:%.*]] = icmp ne <8 x i16> [[A1:%.*]], zeroinitializer807; CHECK-NEXT: [[TMP13:%.*]] = and <8 x i1> [[TMP5]], [[TMP12]]808; CHECK-NEXT: [[TMP16:%.*]] = and <8 x i1> [[TMP14]], [[TMP12]]809; CHECK-NEXT: [[TMP17:%.*]] = and <8 x i1> [[TMP5]], [[TMP15]]810; CHECK-NEXT: [[TMP18:%.*]] = or <8 x i1> [[TMP13]], [[TMP16]]811; CHECK-NEXT: [[TMP19:%.*]] = or <8 x i1> [[TMP18]], [[TMP17]]812; CHECK-NEXT: [[TMP8:%.*]] = sext <8 x i1> [[TMP19]] to <8 x i16>813; CHECK-NEXT: [[TMP20:%.*]] = bitcast <8 x i16> [[TMP8]] to <4 x i32>814; CHECK-NEXT: [[TMP21:%.*]] = icmp ne <4 x i32> [[TMP20]], zeroinitializer815; CHECK-NEXT: [[TMP6:%.*]] = sext <4 x i1> [[TMP21]] to <4 x i32>816; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16> [[A0]], <8 x i16> [[A1]])817; CHECK-NEXT: store <4 x i32> [[TMP6]], ptr @__msan_retval_tls, align 8818; CHECK-NEXT: ret <4 x i32> [[RES]]819;820 %res = call <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16> %a0, <8 x i16> %a1) ; <<4 x i32>> [#uses=1]821 ret <4 x i32> %res822}823declare <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16>, <8 x i16>) nounwind readnone824 825 826define i32 @test_x86_sse2_pmovmskb_128(<16 x i8> %a0) #0 {827; CHECK-LABEL: @test_x86_sse2_pmovmskb_128(828; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @__msan_param_tls, align 8829; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8830; CHECK-NEXT: call void @llvm.donothing()831; CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to i128832; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 0833; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP6:%.*]], label [[TMP5:%.*]], !prof [[PROF1]]834; CHECK: 4:835; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]836; CHECK-NEXT: unreachable837; CHECK: 5:838; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.pmovmskb.128(<16 x i8> [[A0:%.*]])839; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8840; CHECK-NEXT: ret i32 [[RES]]841;842 %res = call i32 @llvm.x86.sse2.pmovmskb.128(<16 x i8> %a0) ; <i32> [#uses=1]843 ret i32 %res844}845declare i32 @llvm.x86.sse2.pmovmskb.128(<16 x i8>) nounwind readnone846 847 848define <8 x i16> @test_x86_sse2_pmulh_w(<8 x i16> %a0, <8 x i16> %a1) #0 {849; CHECK-LABEL: @test_x86_sse2_pmulh_w(850; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8851; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8852; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8853; CHECK-NEXT: call void @llvm.donothing()854; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP1]], [[TMP2]]855; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16> [[A0:%.*]], <8 x i16> [[A1:%.*]])856; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8857; CHECK-NEXT: ret <8 x i16> [[RES]]858;859 %res = call <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]860 ret <8 x i16> %res861}862declare <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16>, <8 x i16>) nounwind readnone863 864 865define <8 x i16> @test_x86_sse2_pmulhu_w(<8 x i16> %a0, <8 x i16> %a1) #0 {866; CHECK-LABEL: @test_x86_sse2_pmulhu_w(867; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8868; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8869; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8870; CHECK-NEXT: call void @llvm.donothing()871; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP1]], [[TMP2]]872; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16> [[A0:%.*]], <8 x i16> [[A1:%.*]])873; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8874; CHECK-NEXT: ret <8 x i16> [[RES]]875;876 %res = call <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]877 ret <8 x i16> %res878}879declare <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16>, <8 x i16>) nounwind readnone880 881 882define <2 x i64> @test_x86_sse2_psad_bw(<16 x i8> %a0, <16 x i8> %a1) #0 {883; CHECK-LABEL: @test_x86_sse2_psad_bw(884; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @__msan_param_tls, align 8885; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8886; CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8887; CHECK-NEXT: call void @llvm.donothing()888; CHECK-NEXT: [[TMP3:%.*]] = or <16 x i8> [[TMP1]], [[TMP2]]889; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP3]] to <2 x i64>890; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <2 x i64> [[TMP4]], zeroinitializer891; CHECK-NEXT: [[TMP6:%.*]] = sext <2 x i1> [[TMP5]] to <2 x i64>892; CHECK-NEXT: [[TMP7:%.*]] = lshr <2 x i64> [[TMP6]], splat (i64 48)893; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8> [[A0:%.*]], <16 x i8> [[A1:%.*]])894; CHECK-NEXT: store <2 x i64> [[TMP7]], ptr @__msan_retval_tls, align 8895; CHECK-NEXT: ret <2 x i64> [[RES]]896;897 %res = call <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8> %a0, <16 x i8> %a1) ; <<2 x i64>> [#uses=1]898 ret <2 x i64> %res899}900declare <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8>, <16 x i8>) nounwind readnone901 902 903define <4 x i32> @test_x86_sse2_psll_d(<4 x i32> %a0, <4 x i32> %a1) #0 {904; CHECK-LABEL: @test_x86_sse2_psll_d(905; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8906; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8907; CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8908; CHECK-NEXT: call void @llvm.donothing()909; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP2]] to i128910; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i64911; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 0912; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i128913; CHECK-NEXT: [[TMP7:%.*]] = bitcast i128 [[TMP6]] to <4 x i32>914; CHECK-NEXT: [[TMP8:%.*]] = call <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32> [[TMP1]], <4 x i32> [[A1:%.*]])915; CHECK-NEXT: [[TMP9:%.*]] = or <4 x i32> [[TMP8]], [[TMP7]]916; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32> [[A0:%.*]], <4 x i32> [[A1]])917; CHECK-NEXT: store <4 x i32> [[TMP9]], ptr @__msan_retval_tls, align 8918; CHECK-NEXT: ret <4 x i32> [[RES]]919;920 %res = call <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]921 ret <4 x i32> %res922}923declare <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32>, <4 x i32>) nounwind readnone924 925 926define <2 x i64> @test_x86_sse2_psll_q(<2 x i64> %a0, <2 x i64> %a1) #0 {927; CHECK-LABEL: @test_x86_sse2_psll_q(928; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8929; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8930; CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8931; CHECK-NEXT: call void @llvm.donothing()932; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP2]] to i128933; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i64934; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 0935; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i128936; CHECK-NEXT: [[TMP7:%.*]] = bitcast i128 [[TMP6]] to <2 x i64>937; CHECK-NEXT: [[TMP8:%.*]] = call <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64> [[TMP1]], <2 x i64> [[A1:%.*]])938; CHECK-NEXT: [[TMP9:%.*]] = or <2 x i64> [[TMP8]], [[TMP7]]939; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64> [[A0:%.*]], <2 x i64> [[A1]])940; CHECK-NEXT: store <2 x i64> [[TMP9]], ptr @__msan_retval_tls, align 8941; CHECK-NEXT: ret <2 x i64> [[RES]]942;943 %res = call <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1]944 ret <2 x i64> %res945}946declare <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64>, <2 x i64>) nounwind readnone947 948 949define <8 x i16> @test_x86_sse2_psll_w(<8 x i16> %a0, <8 x i16> %a1) #0 {950; CHECK-LABEL: @test_x86_sse2_psll_w(951; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8952; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8953; CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8954; CHECK-NEXT: call void @llvm.donothing()955; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP2]] to i128956; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i64957; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 0958; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i128959; CHECK-NEXT: [[TMP7:%.*]] = bitcast i128 [[TMP6]] to <8 x i16>960; CHECK-NEXT: [[TMP8:%.*]] = call <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16> [[TMP1]], <8 x i16> [[A1:%.*]])961; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i16> [[TMP8]], [[TMP7]]962; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16> [[A0:%.*]], <8 x i16> [[A1]])963; CHECK-NEXT: store <8 x i16> [[TMP9]], ptr @__msan_retval_tls, align 8964; CHECK-NEXT: ret <8 x i16> [[RES]]965;966 %res = call <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]967 ret <8 x i16> %res968}969declare <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16>, <8 x i16>) nounwind readnone970 971 972define <4 x i32> @test_x86_sse2_pslli_d(<4 x i32> %a0) #0 {973; CHECK-LABEL: @test_x86_sse2_pslli_d(974; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8975; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8976; CHECK-NEXT: call void @llvm.donothing()977; CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> [[TMP1]], i32 7)978; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP2]], zeroinitializer979; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> [[A0:%.*]], i32 7)980; CHECK-NEXT: store <4 x i32> [[TMP3]], ptr @__msan_retval_tls, align 8981; CHECK-NEXT: ret <4 x i32> [[RES]]982;983 %res = call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> %a0, i32 7) ; <<4 x i32>> [#uses=1]984 ret <4 x i32> %res985}986declare <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32>, i32) nounwind readnone987 988 989define <2 x i64> @test_x86_sse2_pslli_q(<2 x i64> %a0) #0 {990; CHECK-LABEL: @test_x86_sse2_pslli_q(991; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8992; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8993; CHECK-NEXT: call void @llvm.donothing()994; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64> [[TMP1]], i32 7)995; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP2]], zeroinitializer996; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64> [[A0:%.*]], i32 7)997; CHECK-NEXT: store <2 x i64> [[TMP3]], ptr @__msan_retval_tls, align 8998; CHECK-NEXT: ret <2 x i64> [[RES]]999;1000 %res = call <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64> %a0, i32 7) ; <<2 x i64>> [#uses=1]1001 ret <2 x i64> %res1002}1003declare <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64>, i32) nounwind readnone1004 1005 1006define <8 x i16> @test_x86_sse2_pslli_w(<8 x i16> %a0) #0 {1007; CHECK-LABEL: @test_x86_sse2_pslli_w(1008; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81009; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 81010; CHECK-NEXT: call void @llvm.donothing()1011; CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16> [[TMP1]], i32 7)1012; CHECK-NEXT: [[TMP3:%.*]] = or <8 x i16> [[TMP2]], zeroinitializer1013; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16> [[A0:%.*]], i32 7)1014; CHECK-NEXT: store <8 x i16> [[TMP3]], ptr @__msan_retval_tls, align 81015; CHECK-NEXT: ret <8 x i16> [[RES]]1016;1017 %res = call <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16> %a0, i32 7) ; <<8 x i16>> [#uses=1]1018 ret <8 x i16> %res1019}1020declare <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16>, i32) nounwind readnone1021 1022 1023define <4 x i32> @test_x86_sse2_psra_d(<4 x i32> %a0, <4 x i32> %a1) #0 {1024; CHECK-LABEL: @test_x86_sse2_psra_d(1025; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 81026; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81027; CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 81028; CHECK-NEXT: call void @llvm.donothing()1029; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP2]] to i1281030; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i641031; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 01032; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i1281033; CHECK-NEXT: [[TMP7:%.*]] = bitcast i128 [[TMP6]] to <4 x i32>1034; CHECK-NEXT: [[TMP8:%.*]] = call <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32> [[TMP1]], <4 x i32> [[A1:%.*]])1035; CHECK-NEXT: [[TMP9:%.*]] = or <4 x i32> [[TMP8]], [[TMP7]]1036; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32> [[A0:%.*]], <4 x i32> [[A1]])1037; CHECK-NEXT: store <4 x i32> [[TMP9]], ptr @__msan_retval_tls, align 81038; CHECK-NEXT: ret <4 x i32> [[RES]]1039;1040 %res = call <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]1041 ret <4 x i32> %res1042}1043declare <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32>, <4 x i32>) nounwind readnone1044 1045 1046define <8 x i16> @test_x86_sse2_psra_w(<8 x i16> %a0, <8 x i16> %a1) #0 {1047; CHECK-LABEL: @test_x86_sse2_psra_w(1048; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81049; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81050; CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 81051; CHECK-NEXT: call void @llvm.donothing()1052; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP2]] to i1281053; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i641054; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 01055; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i1281056; CHECK-NEXT: [[TMP7:%.*]] = bitcast i128 [[TMP6]] to <8 x i16>1057; CHECK-NEXT: [[TMP8:%.*]] = call <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16> [[TMP1]], <8 x i16> [[A1:%.*]])1058; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i16> [[TMP8]], [[TMP7]]1059; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16> [[A0:%.*]], <8 x i16> [[A1]])1060; CHECK-NEXT: store <8 x i16> [[TMP9]], ptr @__msan_retval_tls, align 81061; CHECK-NEXT: ret <8 x i16> [[RES]]1062;1063 %res = call <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]1064 ret <8 x i16> %res1065}1066declare <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16>, <8 x i16>) nounwind readnone1067 1068 1069define <4 x i32> @test_x86_sse2_psrai_d(<4 x i32> %a0) #0 {1070; CHECK-LABEL: @test_x86_sse2_psrai_d(1071; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 81072; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 81073; CHECK-NEXT: call void @llvm.donothing()1074; CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> [[TMP1]], i32 7)1075; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP2]], zeroinitializer1076; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> [[A0:%.*]], i32 7)1077; CHECK-NEXT: store <4 x i32> [[TMP3]], ptr @__msan_retval_tls, align 81078; CHECK-NEXT: ret <4 x i32> [[RES]]1079;1080 %res = call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> %a0, i32 7) ; <<4 x i32>> [#uses=1]1081 ret <4 x i32> %res1082}1083declare <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32>, i32) nounwind readnone1084 1085 1086define <8 x i16> @test_x86_sse2_psrai_w(<8 x i16> %a0) #0 {1087; CHECK-LABEL: @test_x86_sse2_psrai_w(1088; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81089; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 81090; CHECK-NEXT: call void @llvm.donothing()1091; CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> [[TMP1]], i32 7)1092; CHECK-NEXT: [[TMP3:%.*]] = or <8 x i16> [[TMP2]], zeroinitializer1093; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> [[A0:%.*]], i32 7)1094; CHECK-NEXT: store <8 x i16> [[TMP3]], ptr @__msan_retval_tls, align 81095; CHECK-NEXT: ret <8 x i16> [[RES]]1096;1097 %res = call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> %a0, i32 7) ; <<8 x i16>> [#uses=1]1098 ret <8 x i16> %res1099}1100declare <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16>, i32) nounwind readnone1101 1102 1103define <4 x i32> @test_x86_sse2_psrl_d(<4 x i32> %a0, <4 x i32> %a1) #0 {1104; CHECK-LABEL: @test_x86_sse2_psrl_d(1105; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 81106; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81107; CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 81108; CHECK-NEXT: call void @llvm.donothing()1109; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP2]] to i1281110; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i641111; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 01112; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i1281113; CHECK-NEXT: [[TMP7:%.*]] = bitcast i128 [[TMP6]] to <4 x i32>1114; CHECK-NEXT: [[TMP8:%.*]] = call <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32> [[TMP1]], <4 x i32> [[A1:%.*]])1115; CHECK-NEXT: [[TMP9:%.*]] = or <4 x i32> [[TMP8]], [[TMP7]]1116; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32> [[A0:%.*]], <4 x i32> [[A1]])1117; CHECK-NEXT: store <4 x i32> [[TMP9]], ptr @__msan_retval_tls, align 81118; CHECK-NEXT: ret <4 x i32> [[RES]]1119;1120 %res = call <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]1121 ret <4 x i32> %res1122}1123declare <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32>, <4 x i32>) nounwind readnone1124 1125 1126define <2 x i64> @test_x86_sse2_psrl_q(<2 x i64> %a0, <2 x i64> %a1) #0 {1127; CHECK-LABEL: @test_x86_sse2_psrl_q(1128; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 81129; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81130; CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 81131; CHECK-NEXT: call void @llvm.donothing()1132; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP2]] to i1281133; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i641134; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 01135; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i1281136; CHECK-NEXT: [[TMP7:%.*]] = bitcast i128 [[TMP6]] to <2 x i64>1137; CHECK-NEXT: [[TMP8:%.*]] = call <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64> [[TMP1]], <2 x i64> [[A1:%.*]])1138; CHECK-NEXT: [[TMP9:%.*]] = or <2 x i64> [[TMP8]], [[TMP7]]1139; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64> [[A0:%.*]], <2 x i64> [[A1]])1140; CHECK-NEXT: store <2 x i64> [[TMP9]], ptr @__msan_retval_tls, align 81141; CHECK-NEXT: ret <2 x i64> [[RES]]1142;1143 %res = call <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1]1144 ret <2 x i64> %res1145}1146declare <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64>, <2 x i64>) nounwind readnone1147 1148 1149define <8 x i16> @test_x86_sse2_psrl_w(<8 x i16> %a0, <8 x i16> %a1) #0 {1150; CHECK-LABEL: @test_x86_sse2_psrl_w(1151; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81152; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81153; CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 81154; CHECK-NEXT: call void @llvm.donothing()1155; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP2]] to i1281156; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i641157; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 01158; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i1281159; CHECK-NEXT: [[TMP7:%.*]] = bitcast i128 [[TMP6]] to <8 x i16>1160; CHECK-NEXT: [[TMP8:%.*]] = call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> [[TMP1]], <8 x i16> [[A1:%.*]])1161; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i16> [[TMP8]], [[TMP7]]1162; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> [[A0:%.*]], <8 x i16> [[A1]])1163; CHECK-NEXT: store <8 x i16> [[TMP9]], ptr @__msan_retval_tls, align 81164; CHECK-NEXT: ret <8 x i16> [[RES]]1165;1166 %res = call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]1167 ret <8 x i16> %res1168}1169declare <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16>, <8 x i16>) nounwind readnone1170 1171 1172define <8 x i16> @test_x86_sse2_psrl_w_load(<8 x i16> %a0, ptr %p) #0 {1173; CHECK-LABEL: @test_x86_sse2_psrl_w_load(1174; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81175; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81176; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 81177; CHECK-NEXT: call void @llvm.donothing()1178; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01179; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP4:%.*]], label [[TMP15:%.*]], !prof [[PROF1]]1180; CHECK: 4:1181; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1182; CHECK-NEXT: unreachable1183; CHECK: 5:1184; CHECK-NEXT: [[A1:%.*]] = load <8 x i16>, ptr [[P:%.*]], align 161185; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[P]] to i641186; CHECK-NEXT: [[TMP6:%.*]] = and i64 [[TMP5]], -21474836491187; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1188; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP7]], align 161189; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i16> [[_MSLD]] to i1281190; CHECK-NEXT: [[TMP9:%.*]] = trunc i128 [[TMP8]] to i641191; CHECK-NEXT: [[TMP10:%.*]] = icmp ne i64 [[TMP9]], 01192; CHECK-NEXT: [[TMP11:%.*]] = sext i1 [[TMP10]] to i1281193; CHECK-NEXT: [[TMP12:%.*]] = bitcast i128 [[TMP11]] to <8 x i16>1194; CHECK-NEXT: [[TMP13:%.*]] = call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> [[TMP2]], <8 x i16> [[A1]])1195; CHECK-NEXT: [[TMP14:%.*]] = or <8 x i16> [[TMP13]], [[TMP12]]1196; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> [[A0:%.*]], <8 x i16> [[A1]])1197; CHECK-NEXT: store <8 x i16> [[TMP14]], ptr @__msan_retval_tls, align 81198; CHECK-NEXT: ret <8 x i16> [[RES]]1199;1200 %a1 = load <8 x i16>, ptr %p1201 %res = call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]1202 ret <8 x i16> %res1203}1204 1205 1206define <4 x i32> @test_x86_sse2_psrli_d(<4 x i32> %a0) #0 {1207; CHECK-LABEL: @test_x86_sse2_psrli_d(1208; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 81209; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 81210; CHECK-NEXT: call void @llvm.donothing()1211; CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> [[TMP1]], i32 7)1212; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP2]], zeroinitializer1213; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> [[A0:%.*]], i32 7)1214; CHECK-NEXT: store <4 x i32> [[TMP3]], ptr @__msan_retval_tls, align 81215; CHECK-NEXT: ret <4 x i32> [[RES]]1216;1217 %res = call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> %a0, i32 7) ; <<4 x i32>> [#uses=1]1218 ret <4 x i32> %res1219}1220declare <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32>, i32) nounwind readnone1221 1222 1223define <2 x i64> @test_x86_sse2_psrli_q(<2 x i64> %a0) #0 {1224; CHECK-LABEL: @test_x86_sse2_psrli_q(1225; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 81226; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 81227; CHECK-NEXT: call void @llvm.donothing()1228; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64> [[TMP1]], i32 7)1229; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP2]], zeroinitializer1230; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64> [[A0:%.*]], i32 7)1231; CHECK-NEXT: store <2 x i64> [[TMP3]], ptr @__msan_retval_tls, align 81232; CHECK-NEXT: ret <2 x i64> [[RES]]1233;1234 %res = call <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64> %a0, i32 7) ; <<2 x i64>> [#uses=1]1235 ret <2 x i64> %res1236}1237declare <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64>, i32) nounwind readnone1238 1239 1240define <8 x i16> @test_x86_sse2_psrli_w(<8 x i16> %a0) #0 {1241; CHECK-LABEL: @test_x86_sse2_psrli_w(1242; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 81243; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 81244; CHECK-NEXT: call void @llvm.donothing()1245; CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> [[TMP1]], i32 7)1246; CHECK-NEXT: [[TMP3:%.*]] = or <8 x i16> [[TMP2]], zeroinitializer1247; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> [[A0:%.*]], i32 7)1248; CHECK-NEXT: store <8 x i16> [[TMP3]], ptr @__msan_retval_tls, align 81249; CHECK-NEXT: ret <8 x i16> [[RES]]1250;1251 %res = call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> %a0, i32 7) ; <<8 x i16>> [#uses=1]1252 ret <8 x i16> %res1253}1254declare <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16>, i32) nounwind readnone1255 1256 1257define i32 @test_x86_sse2_ucomieq_sd(<2 x double> %a0, <2 x double> %a1) #0 {1258; CHECK-LABEL: @test_x86_sse2_ucomieq_sd(1259; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 81260; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81261; CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 81262; CHECK-NEXT: call void @llvm.donothing()1263; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]]1264; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i64 01265; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 01266; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i321267; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.ucomieq.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]])1268; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 81269; CHECK-NEXT: ret i32 [[RES]]1270;1271 %res = call i32 @llvm.x86.sse2.ucomieq.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]1272 ret i32 %res1273}1274declare i32 @llvm.x86.sse2.ucomieq.sd(<2 x double>, <2 x double>) nounwind readnone1275 1276 1277define i32 @test_x86_sse2_ucomige_sd(<2 x double> %a0, <2 x double> %a1) #0 {1278; CHECK-LABEL: @test_x86_sse2_ucomige_sd(1279; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 81280; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81281; CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 81282; CHECK-NEXT: call void @llvm.donothing()1283; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]]1284; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i64 01285; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 01286; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i321287; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.ucomige.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]])1288; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 81289; CHECK-NEXT: ret i32 [[RES]]1290;1291 %res = call i32 @llvm.x86.sse2.ucomige.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]1292 ret i32 %res1293}1294declare i32 @llvm.x86.sse2.ucomige.sd(<2 x double>, <2 x double>) nounwind readnone1295 1296 1297define i32 @test_x86_sse2_ucomigt_sd(<2 x double> %a0, <2 x double> %a1) #0 {1298; CHECK-LABEL: @test_x86_sse2_ucomigt_sd(1299; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 81300; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81301; CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 81302; CHECK-NEXT: call void @llvm.donothing()1303; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]]1304; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i64 01305; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 01306; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i321307; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.ucomigt.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]])1308; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 81309; CHECK-NEXT: ret i32 [[RES]]1310;1311 %res = call i32 @llvm.x86.sse2.ucomigt.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]1312 ret i32 %res1313}1314declare i32 @llvm.x86.sse2.ucomigt.sd(<2 x double>, <2 x double>) nounwind readnone1315 1316 1317define i32 @test_x86_sse2_ucomile_sd(<2 x double> %a0, <2 x double> %a1) #0 {1318; CHECK-LABEL: @test_x86_sse2_ucomile_sd(1319; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 81320; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81321; CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 81322; CHECK-NEXT: call void @llvm.donothing()1323; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]]1324; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i64 01325; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 01326; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i321327; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.ucomile.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]])1328; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 81329; CHECK-NEXT: ret i32 [[RES]]1330;1331 %res = call i32 @llvm.x86.sse2.ucomile.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]1332 ret i32 %res1333}1334declare i32 @llvm.x86.sse2.ucomile.sd(<2 x double>, <2 x double>) nounwind readnone1335 1336 1337define i32 @test_x86_sse2_ucomilt_sd(<2 x double> %a0, <2 x double> %a1) #0 {1338; CHECK-LABEL: @test_x86_sse2_ucomilt_sd(1339; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 81340; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81341; CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 81342; CHECK-NEXT: call void @llvm.donothing()1343; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]]1344; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i64 01345; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 01346; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i321347; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.ucomilt.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]])1348; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 81349; CHECK-NEXT: ret i32 [[RES]]1350;1351 %res = call i32 @llvm.x86.sse2.ucomilt.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]1352 ret i32 %res1353}1354declare i32 @llvm.x86.sse2.ucomilt.sd(<2 x double>, <2 x double>) nounwind readnone1355 1356 1357define i32 @test_x86_sse2_ucomineq_sd(<2 x double> %a0, <2 x double> %a1) #0 {1358; CHECK-LABEL: @test_x86_sse2_ucomineq_sd(1359; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 81360; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81361; CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 81362; CHECK-NEXT: call void @llvm.donothing()1363; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]]1364; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i64 01365; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 01366; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i321367; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.ucomineq.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]])1368; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 81369; CHECK-NEXT: ret i32 [[RES]]1370;1371 %res = call i32 @llvm.x86.sse2.ucomineq.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]1372 ret i32 %res1373}1374declare i32 @llvm.x86.sse2.ucomineq.sd(<2 x double>, <2 x double>) nounwind readnone1375 1376define void @test_x86_sse2_pause() #0 {1377; CHECK-LABEL: @test_x86_sse2_pause(1378; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 81379; CHECK-NEXT: call void @llvm.donothing()1380; CHECK-NEXT: tail call void @llvm.x86.sse2.pause()1381; CHECK-NEXT: ret void1382;1383 tail call void @llvm.x86.sse2.pause()1384 ret void1385}1386declare void @llvm.x86.sse2.pause() nounwind1387 1388define void @lfence() nounwind #0 {1389; CHECK-LABEL: @lfence(1390; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 81391; CHECK-NEXT: call void @llvm.donothing()1392; CHECK-NEXT: tail call void @llvm.x86.sse2.lfence()1393; CHECK-NEXT: ret void1394;1395 tail call void @llvm.x86.sse2.lfence()1396 ret void1397}1398declare void @llvm.x86.sse2.lfence() nounwind1399 1400define void @mfence() nounwind #0 {1401; CHECK-LABEL: @mfence(1402; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 81403; CHECK-NEXT: call void @llvm.donothing()1404; CHECK-NEXT: tail call void @llvm.x86.sse2.mfence()1405; CHECK-NEXT: ret void1406;1407 tail call void @llvm.x86.sse2.mfence()1408 ret void1409}1410declare void @llvm.x86.sse2.mfence() nounwind1411 1412define void @clflush(ptr %p) nounwind #0 {1413; CHECK-LABEL: @clflush(1414; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81415; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 81416; CHECK-NEXT: call void @llvm.donothing()1417; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01418; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]1419; CHECK: 3:1420; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1421; CHECK-NEXT: unreachable1422; CHECK: 4:1423; CHECK-NEXT: tail call void @llvm.x86.sse2.clflush(ptr [[P:%.*]])1424; CHECK-NEXT: ret void1425;1426 tail call void @llvm.x86.sse2.clflush(ptr %p)1427 ret void1428}1429declare void @llvm.x86.sse2.clflush(ptr) nounwind1430 1431attributes #0 = { sanitize_memory }1432