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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt < %s -msan-check-access-address=0 -S -passes=msan 2>&1 | FileCheck %s3; RUN: opt < %s -msan-check-access-address=0 -S -passes=msan -msan-track-origins=1 2>&1 | FileCheck %s --check-prefixes=ORIGIN4; RUN: opt < %s -msan-check-access-address=0 -S -passes="msan<track-origins=1>" 2>&1 | FileCheck %s --check-prefixes=ORIGIN5; RUN: opt < %s -msan-check-access-address=0 -S -passes=msan -msan-track-origins=2 2>&1 | FileCheck %s --check-prefixes=ORIGIN26 7; Test that shadow and origin are stored for variadic function params.8 9target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"10target triple = "i386-unknown-linux-gnu"11 12%struct.__va_list_tag = type { i32, i32, ptr, ptr }13 14define dso_local i32 @test(i32 %a, i32 %b, i32 %c) local_unnamed_addr {15; CHECK-LABEL: define dso_local i32 @test(16; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]]) local_unnamed_addr {17; CHECK-NEXT: [[ENTRY:.*:]]18; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 819; CHECK-NEXT: call void @llvm.donothing()20; CHECK-NEXT: store i32 0, ptr @__msan_param_tls, align 821; CHECK-NEXT: store i32 0, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 822; CHECK-NEXT: store i32 0, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 823; CHECK-NEXT: store i32 0, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 824; CHECK-NEXT: store i32 0, ptr @__msan_va_arg_tls, align 825; CHECK-NEXT: store i32 0, ptr getelementptr (i8, ptr @__msan_va_arg_tls, i64 8), align 826; CHECK-NEXT: store i32 0, ptr getelementptr (i8, ptr @__msan_va_arg_tls, i64 16), align 827; CHECK-NEXT: store i64 24, ptr @__msan_va_arg_overflow_size_tls, align 828; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 829; CHECK-NEXT: [[CALL:%.*]] = tail call i32 (i32, ...) @sum(i32 3, i32 [[A]], i32 [[B]], i32 [[C]])30; CHECK-NEXT: [[_MSRET:%.*]] = load i32, ptr @__msan_retval_tls, align 831; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 832; CHECK-NEXT: ret i32 [[CALL]]33;34; ORIGIN-LABEL: define dso_local i32 @test(35; ORIGIN-SAME: i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]]) local_unnamed_addr {36; ORIGIN-NEXT: [[ENTRY:.*:]]37; ORIGIN-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 838; ORIGIN-NEXT: call void @llvm.donothing()39; ORIGIN-NEXT: store i32 0, ptr @__msan_param_tls, align 840; ORIGIN-NEXT: store i32 0, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 841; ORIGIN-NEXT: store i32 0, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 842; ORIGIN-NEXT: store i32 0, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 843; ORIGIN-NEXT: store i32 0, ptr @__msan_va_arg_tls, align 844; ORIGIN-NEXT: store i32 0, ptr getelementptr (i8, ptr @__msan_va_arg_tls, i64 8), align 845; ORIGIN-NEXT: store i32 0, ptr getelementptr (i8, ptr @__msan_va_arg_tls, i64 16), align 846; ORIGIN-NEXT: store i64 24, ptr @__msan_va_arg_overflow_size_tls, align 847; ORIGIN-NEXT: store i32 0, ptr @__msan_retval_tls, align 848; ORIGIN-NEXT: [[CALL:%.*]] = tail call i32 (i32, ...) @sum(i32 3, i32 [[A]], i32 [[B]], i32 [[C]])49; ORIGIN-NEXT: [[_MSRET:%.*]] = load i32, ptr @__msan_retval_tls, align 850; ORIGIN-NEXT: [[TMP0:%.*]] = load i32, ptr @__msan_retval_origin_tls, align 451; ORIGIN-NEXT: store i32 0, ptr @__msan_retval_tls, align 852; ORIGIN-NEXT: store i32 0, ptr @__msan_retval_origin_tls, align 453; ORIGIN-NEXT: ret i32 [[CALL]]54;55; ORIGIN2-LABEL: define dso_local i32 @test(56; ORIGIN2-SAME: i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]]) local_unnamed_addr {57; ORIGIN2-NEXT: [[ENTRY:.*:]]58; ORIGIN2-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 859; ORIGIN2-NEXT: call void @llvm.donothing()60; ORIGIN2-NEXT: store i32 0, ptr @__msan_param_tls, align 861; ORIGIN2-NEXT: store i32 0, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 862; ORIGIN2-NEXT: store i32 0, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 863; ORIGIN2-NEXT: store i32 0, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 864; ORIGIN2-NEXT: store i32 0, ptr @__msan_va_arg_tls, align 865; ORIGIN2-NEXT: store i32 0, ptr getelementptr (i8, ptr @__msan_va_arg_tls, i64 8), align 866; ORIGIN2-NEXT: store i32 0, ptr getelementptr (i8, ptr @__msan_va_arg_tls, i64 16), align 867; ORIGIN2-NEXT: store i64 24, ptr @__msan_va_arg_overflow_size_tls, align 868; ORIGIN2-NEXT: store i32 0, ptr @__msan_retval_tls, align 869; ORIGIN2-NEXT: [[CALL:%.*]] = tail call i32 (i32, ...) @sum(i32 3, i32 [[A]], i32 [[B]], i32 [[C]])70; ORIGIN2-NEXT: [[_MSRET:%.*]] = load i32, ptr @__msan_retval_tls, align 871; ORIGIN2-NEXT: [[TMP0:%.*]] = load i32, ptr @__msan_retval_origin_tls, align 472; ORIGIN2-NEXT: store i32 0, ptr @__msan_retval_tls, align 873; ORIGIN2-NEXT: store i32 0, ptr @__msan_retval_origin_tls, align 474; ORIGIN2-NEXT: ret i32 [[CALL]]75;76entry:77 %call = tail call i32 (i32, ...) @sum(i32 3, i32 %a, i32 %b, i32 %c)78 ret i32 %call79}80 81define dso_local i32 @sum(i32 %n, ...) local_unnamed_addr #0 {82; CHECK-LABEL: define dso_local i32 @sum(83; CHECK-SAME: i32 [[N:%.*]], ...) local_unnamed_addr {84; CHECK-NEXT: [[ENTRY:.*]]:85; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 886; CHECK-NEXT: [[TMP2:%.*]] = alloca i8, i64 [[TMP1]], align 887; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP2]], i8 0, i64 [[TMP1]], i1 false)88; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP1]], i64 800)89; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP2]], ptr align 8 @__msan_va_arg_tls, i64 [[TMP3]], i1 false)90; CHECK-NEXT: call void @llvm.donothing()91; CHECK-NEXT: [[ARGS:%.*]] = alloca [1 x %struct.__va_list_tag], align 1692; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[ARGS]] to i6493; CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], -214748364994; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr95; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[TMP6]], i8 0, i64 24, i1 false)96; CHECK-NEXT: call void @llvm.lifetime.start.p0(ptr nonnull [[ARGS]])97; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[ARGS]] to i6498; CHECK-NEXT: [[TMP8:%.*]] = and i64 [[TMP7]], -214748364999; CHECK-NEXT: [[TMP9:%.*]] = inttoptr i64 [[TMP8]] to ptr100; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP9]], i8 0, i64 4, i1 false)101; CHECK-NEXT: call void @llvm.va_start.p0(ptr nonnull [[ARGS]])102; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[ARGS]] to i64103; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to ptr104; CHECK-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8105; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[TMP12]] to i64106; CHECK-NEXT: [[TMP14:%.*]] = and i64 [[TMP13]], -2147483649107; CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP14]] to ptr108; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP15]], ptr align 8 [[TMP2]], i64 [[TMP1]], i1 false)109; CHECK-NEXT: [[TMP25:%.*]] = xor i32 [[N]], -2147483648110; CHECK-NEXT: [[TMP26:%.*]] = and i32 [[TMP25]], -1111; CHECK-NEXT: [[TMP27:%.*]] = or i32 [[TMP25]], 0112; CHECK-NEXT: [[TMP28:%.*]] = icmp ugt i32 [[TMP26]], -2147483648113; CHECK-NEXT: [[TMP29:%.*]] = icmp ugt i32 [[TMP27]], -2147483648114; CHECK-NEXT: [[TMP30:%.*]] = xor i1 [[TMP28]], [[TMP29]]115; CHECK-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[N]], 0116; CHECK-NEXT: br i1 [[CMP9]], label %[[FOR_BODY_LR_PH:.*]], label %[[FOR_END:.*]]117; CHECK: [[FOR_BODY_LR_PH]]:118; CHECK-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x %struct.__va_list_tag], ptr [[ARGS]], i64 0, i64 0, i32 3119; CHECK-NEXT: [[OVERFLOW_ARG_AREA_P:%.*]] = getelementptr inbounds [1 x %struct.__va_list_tag], ptr [[ARGS]], i64 0, i64 0, i32 2120; CHECK-NEXT: [[GP_OFFSET_PRE:%.*]] = load i32, ptr [[ARGS]], align 16121; CHECK-NEXT: br label %[[FOR_BODY:.*]]122; CHECK: [[FOR_BODY]]:123; CHECK-NEXT: [[GP_OFFSET:%.*]] = phi i32 [ [[GP_OFFSET_PRE]], %[[FOR_BODY_LR_PH]] ], [ [[GP_OFFSET12:%.*]], %[[VAARG_END:.*]] ]124; CHECK-NEXT: [[SUM_011:%.*]] = phi i32 [ 0, %[[FOR_BODY_LR_PH]] ], [ [[ADD:%.*]], %[[VAARG_END]] ]125; CHECK-NEXT: [[I_010:%.*]] = phi i32 [ 0, %[[FOR_BODY_LR_PH]] ], [ [[INC:%.*]], %[[VAARG_END]] ]126; CHECK-NEXT: [[TMP32:%.*]] = and i32 [[GP_OFFSET]], -1127; CHECK-NEXT: [[TMP33:%.*]] = or i32 [[GP_OFFSET]], 0128; CHECK-NEXT: [[TMP34:%.*]] = icmp ult i32 [[TMP32]], 41129; CHECK-NEXT: [[TMP35:%.*]] = icmp ult i32 [[TMP33]], 41130; CHECK-NEXT: [[TMP36:%.*]] = xor i1 [[TMP34]], [[TMP35]]131; CHECK-NEXT: [[FITS_IN_GP:%.*]] = icmp ult i32 [[GP_OFFSET]], 41132; CHECK-NEXT: br i1 [[FITS_IN_GP]], label %[[VAARG_IN_REG:.*]], label %[[VAARG_IN_MEM:.*]]133; CHECK: [[VAARG_IN_REG]]:134; CHECK-NEXT: [[REG_SAVE_AREA:%.*]] = load ptr, ptr [[TMP31]], align 16135; CHECK-NEXT: [[TMP37:%.*]] = sext i32 [[GP_OFFSET]] to i64136; CHECK-NEXT: [[TMP38:%.*]] = getelementptr i8, ptr [[REG_SAVE_AREA]], i64 [[TMP37]]137; CHECK-NEXT: [[TMP39:%.*]] = add i32 [[GP_OFFSET]], 8138; CHECK-NEXT: [[TMP40:%.*]] = ptrtoint ptr [[ARGS]] to i64139; CHECK-NEXT: [[TMP41:%.*]] = and i64 [[TMP40]], -2147483649140; CHECK-NEXT: [[TMP42:%.*]] = inttoptr i64 [[TMP41]] to ptr141; CHECK-NEXT: store i32 0, ptr [[TMP42]], align 16142; CHECK-NEXT: store i32 [[TMP39]], ptr [[ARGS]], align 16143; CHECK-NEXT: br label %[[VAARG_END]]144; CHECK: [[VAARG_IN_MEM]]:145; CHECK-NEXT: [[OVERFLOW_ARG_AREA:%.*]] = load ptr, ptr [[OVERFLOW_ARG_AREA_P]], align 8146; CHECK-NEXT: [[OVERFLOW_ARG_AREA_NEXT:%.*]] = getelementptr i8, ptr [[OVERFLOW_ARG_AREA]], i64 8147; CHECK-NEXT: [[TMP43:%.*]] = ptrtoint ptr [[OVERFLOW_ARG_AREA_P]] to i64148; CHECK-NEXT: [[TMP44:%.*]] = and i64 [[TMP43]], -2147483649149; CHECK-NEXT: [[TMP45:%.*]] = inttoptr i64 [[TMP44]] to ptr150; CHECK-NEXT: store i64 0, ptr [[TMP45]], align 8151; CHECK-NEXT: store ptr [[OVERFLOW_ARG_AREA_NEXT]], ptr [[OVERFLOW_ARG_AREA_P]], align 8152; CHECK-NEXT: br label %[[VAARG_END]]153; CHECK: [[VAARG_END]]:154; CHECK-NEXT: [[GP_OFFSET12]] = phi i32 [ [[TMP39]], %[[VAARG_IN_REG]] ], [ [[GP_OFFSET]], %[[VAARG_IN_MEM]] ]155; CHECK-NEXT: [[VAARG_ADDR_IN:%.*]] = phi ptr [ [[TMP38]], %[[VAARG_IN_REG]] ], [ [[OVERFLOW_ARG_AREA]], %[[VAARG_IN_MEM]] ]156; CHECK-NEXT: [[TMP46:%.*]] = load i32, ptr [[VAARG_ADDR_IN]], align 4157; CHECK-NEXT: [[ADD]] = add nsw i32 [[TMP46]], [[SUM_011]]158; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[I_010]], 1159; CHECK-NEXT: [[TMP47:%.*]] = xor i32 [[INC]], [[N]]160; CHECK-NEXT: [[TMP48:%.*]] = and i32 -1, [[TMP47]]161; CHECK-NEXT: [[TMP49:%.*]] = icmp eq i32 [[TMP48]], 0162; CHECK-NEXT: [[_MSPROP_ICMP:%.*]] = and i1 false, [[TMP49]]163; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INC]], [[N]]164; CHECK-NEXT: br i1 [[EXITCOND]], label %[[FOR_END]], label %[[FOR_BODY]]165; CHECK: [[FOR_END]]:166; CHECK-NEXT: [[SUM_0_LCSSA:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[ADD]], %[[VAARG_END]] ]167; CHECK-NEXT: call void @llvm.va_end.p0(ptr nonnull [[ARGS]])168; CHECK-NEXT: call void @llvm.lifetime.end.p0(ptr nonnull [[ARGS]])169; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8170; CHECK-NEXT: ret i32 [[SUM_0_LCSSA]]171;172; ORIGIN-LABEL: define dso_local i32 @sum(173; ORIGIN-SAME: i32 [[N:%.*]], ...) local_unnamed_addr {174; ORIGIN-NEXT: [[ENTRY:.*]]:175; ORIGIN-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8176; ORIGIN-NEXT: [[TMP2:%.*]] = alloca i8, i64 [[TMP1]], align 8177; ORIGIN-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP2]], i8 0, i64 [[TMP1]], i1 false)178; ORIGIN-NEXT: [[TMP3:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP1]], i64 800)179; ORIGIN-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP2]], ptr align 8 @__msan_va_arg_tls, i64 [[TMP3]], i1 false)180; ORIGIN-NEXT: call void @llvm.donothing()181; ORIGIN-NEXT: [[ARGS:%.*]] = alloca [1 x %struct.__va_list_tag], align 16182; ORIGIN-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[ARGS]] to i64183; ORIGIN-NEXT: [[TMP6:%.*]] = and i64 [[TMP5]], -2147483649184; ORIGIN-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr185; ORIGIN-NEXT: [[TMP8:%.*]] = add i64 [[TMP6]], 1073741824186; ORIGIN-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], -4187; ORIGIN-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP9]] to ptr188; ORIGIN-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[TMP7]], i8 0, i64 24, i1 false)189; ORIGIN-NEXT: call void @llvm.lifetime.start.p0(ptr nonnull [[ARGS]])190; ORIGIN-NEXT: [[TMP23:%.*]] = ptrtoint ptr [[ARGS]] to i64191; ORIGIN-NEXT: [[TMP11:%.*]] = and i64 [[TMP23]], -2147483649192; ORIGIN-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr193; ORIGIN-NEXT: [[TMP13:%.*]] = add i64 [[TMP11]], 1073741824194; ORIGIN-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP13]] to ptr195; ORIGIN-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP12]], i8 0, i64 4, i1 false)196; ORIGIN-NEXT: call void @llvm.va_start.p0(ptr nonnull [[ARGS]])197; ORIGIN-NEXT: [[TMP15:%.*]] = ptrtoint ptr [[ARGS]] to i64198; ORIGIN-NEXT: [[TMP16:%.*]] = inttoptr i64 [[TMP15]] to ptr199; ORIGIN-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8200; ORIGIN-NEXT: [[TMP18:%.*]] = ptrtoint ptr [[TMP17]] to i64201; ORIGIN-NEXT: [[TMP19:%.*]] = and i64 [[TMP18]], -2147483649202; ORIGIN-NEXT: [[TMP20:%.*]] = inttoptr i64 [[TMP19]] to ptr203; ORIGIN-NEXT: [[TMP21:%.*]] = add i64 [[TMP19]], 1073741824204; ORIGIN-NEXT: [[TMP22:%.*]] = inttoptr i64 [[TMP21]] to ptr205; ORIGIN-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP20]], ptr align 8 [[TMP2]], i64 [[TMP1]], i1 false)206; ORIGIN-NEXT: [[TMP36:%.*]] = xor i32 [[N]], -2147483648207; ORIGIN-NEXT: [[TMP37:%.*]] = and i32 [[TMP36]], -1208; ORIGIN-NEXT: [[TMP38:%.*]] = or i32 [[TMP36]], 0209; ORIGIN-NEXT: [[TMP39:%.*]] = icmp ugt i32 [[TMP37]], -2147483648210; ORIGIN-NEXT: [[TMP40:%.*]] = icmp ugt i32 [[TMP38]], -2147483648211; ORIGIN-NEXT: [[TMP41:%.*]] = xor i1 [[TMP39]], [[TMP40]]212; ORIGIN-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[N]], 0213; ORIGIN-NEXT: br i1 [[CMP9]], label %[[FOR_BODY_LR_PH:.*]], label %[[FOR_END:.*]]214; ORIGIN: [[FOR_BODY_LR_PH]]:215; ORIGIN-NEXT: [[TMP42:%.*]] = getelementptr inbounds [1 x %struct.__va_list_tag], ptr [[ARGS]], i64 0, i64 0, i32 3216; ORIGIN-NEXT: [[OVERFLOW_ARG_AREA_P:%.*]] = getelementptr inbounds [1 x %struct.__va_list_tag], ptr [[ARGS]], i64 0, i64 0, i32 2217; ORIGIN-NEXT: [[GP_OFFSET_PRE:%.*]] = load i32, ptr [[ARGS]], align 16218; ORIGIN-NEXT: br label %[[FOR_BODY:.*]]219; ORIGIN: [[FOR_BODY]]:220; ORIGIN-NEXT: [[GP_OFFSET:%.*]] = phi i32 [ [[GP_OFFSET_PRE]], %[[FOR_BODY_LR_PH]] ], [ [[GP_OFFSET12:%.*]], %[[VAARG_END:.*]] ]221; ORIGIN-NEXT: [[SUM_011:%.*]] = phi i32 [ 0, %[[FOR_BODY_LR_PH]] ], [ [[ADD:%.*]], %[[VAARG_END]] ]222; ORIGIN-NEXT: [[I_010:%.*]] = phi i32 [ 0, %[[FOR_BODY_LR_PH]] ], [ [[INC:%.*]], %[[VAARG_END]] ]223; ORIGIN-NEXT: [[TMP43:%.*]] = and i32 [[GP_OFFSET]], -1224; ORIGIN-NEXT: [[TMP44:%.*]] = or i32 [[GP_OFFSET]], 0225; ORIGIN-NEXT: [[TMP45:%.*]] = icmp ult i32 [[TMP43]], 41226; ORIGIN-NEXT: [[TMP46:%.*]] = icmp ult i32 [[TMP44]], 41227; ORIGIN-NEXT: [[TMP47:%.*]] = xor i1 [[TMP45]], [[TMP46]]228; ORIGIN-NEXT: [[FITS_IN_GP:%.*]] = icmp ult i32 [[GP_OFFSET]], 41229; ORIGIN-NEXT: br i1 [[FITS_IN_GP]], label %[[VAARG_IN_REG:.*]], label %[[VAARG_IN_MEM:.*]]230; ORIGIN: [[VAARG_IN_REG]]:231; ORIGIN-NEXT: [[REG_SAVE_AREA:%.*]] = load ptr, ptr [[TMP42]], align 16232; ORIGIN-NEXT: [[TMP48:%.*]] = sext i32 [[GP_OFFSET]] to i64233; ORIGIN-NEXT: [[TMP49:%.*]] = getelementptr i8, ptr [[REG_SAVE_AREA]], i64 [[TMP48]]234; ORIGIN-NEXT: [[TMP50:%.*]] = add i32 [[GP_OFFSET]], 8235; ORIGIN-NEXT: [[TMP51:%.*]] = ptrtoint ptr [[ARGS]] to i64236; ORIGIN-NEXT: [[TMP52:%.*]] = and i64 [[TMP51]], -2147483649237; ORIGIN-NEXT: [[TMP53:%.*]] = inttoptr i64 [[TMP52]] to ptr238; ORIGIN-NEXT: [[TMP54:%.*]] = add i64 [[TMP52]], 1073741824239; ORIGIN-NEXT: [[TMP55:%.*]] = inttoptr i64 [[TMP54]] to ptr240; ORIGIN-NEXT: store i32 0, ptr [[TMP53]], align 16241; ORIGIN-NEXT: store i32 [[TMP50]], ptr [[ARGS]], align 16242; ORIGIN-NEXT: br label %[[VAARG_END]]243; ORIGIN: [[VAARG_IN_MEM]]:244; ORIGIN-NEXT: [[OVERFLOW_ARG_AREA:%.*]] = load ptr, ptr [[OVERFLOW_ARG_AREA_P]], align 8245; ORIGIN-NEXT: [[OVERFLOW_ARG_AREA_NEXT:%.*]] = getelementptr i8, ptr [[OVERFLOW_ARG_AREA]], i64 8246; ORIGIN-NEXT: [[TMP56:%.*]] = ptrtoint ptr [[OVERFLOW_ARG_AREA_P]] to i64247; ORIGIN-NEXT: [[TMP57:%.*]] = and i64 [[TMP56]], -2147483649248; ORIGIN-NEXT: [[TMP58:%.*]] = inttoptr i64 [[TMP57]] to ptr249; ORIGIN-NEXT: [[TMP59:%.*]] = add i64 [[TMP57]], 1073741824250; ORIGIN-NEXT: [[TMP60:%.*]] = inttoptr i64 [[TMP59]] to ptr251; ORIGIN-NEXT: store i64 0, ptr [[TMP58]], align 8252; ORIGIN-NEXT: store ptr [[OVERFLOW_ARG_AREA_NEXT]], ptr [[OVERFLOW_ARG_AREA_P]], align 8253; ORIGIN-NEXT: br label %[[VAARG_END]]254; ORIGIN: [[VAARG_END]]:255; ORIGIN-NEXT: [[GP_OFFSET12]] = phi i32 [ [[TMP50]], %[[VAARG_IN_REG]] ], [ [[GP_OFFSET]], %[[VAARG_IN_MEM]] ]256; ORIGIN-NEXT: [[VAARG_ADDR_IN:%.*]] = phi ptr [ [[TMP49]], %[[VAARG_IN_REG]] ], [ [[OVERFLOW_ARG_AREA]], %[[VAARG_IN_MEM]] ]257; ORIGIN-NEXT: [[TMP61:%.*]] = load i32, ptr [[VAARG_ADDR_IN]], align 4258; ORIGIN-NEXT: [[ADD]] = add nsw i32 [[TMP61]], [[SUM_011]]259; ORIGIN-NEXT: [[INC]] = add nuw nsw i32 [[I_010]], 1260; ORIGIN-NEXT: [[TMP62:%.*]] = xor i32 [[INC]], [[N]]261; ORIGIN-NEXT: [[TMP63:%.*]] = and i32 -1, [[TMP62]]262; ORIGIN-NEXT: [[TMP64:%.*]] = icmp eq i32 [[TMP63]], 0263; ORIGIN-NEXT: [[_MSPROP_ICMP:%.*]] = and i1 false, [[TMP64]]264; ORIGIN-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INC]], [[N]]265; ORIGIN-NEXT: br i1 [[EXITCOND]], label %[[FOR_END]], label %[[FOR_BODY]]266; ORIGIN: [[FOR_END]]:267; ORIGIN-NEXT: [[SUM_0_LCSSA:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[ADD]], %[[VAARG_END]] ]268; ORIGIN-NEXT: call void @llvm.va_end.p0(ptr nonnull [[ARGS]])269; ORIGIN-NEXT: call void @llvm.lifetime.end.p0(ptr nonnull [[ARGS]])270; ORIGIN-NEXT: store i32 0, ptr @__msan_retval_tls, align 8271; ORIGIN-NEXT: store i32 0, ptr @__msan_retval_origin_tls, align 4272; ORIGIN-NEXT: ret i32 [[SUM_0_LCSSA]]273;274; ORIGIN2-LABEL: define dso_local i32 @sum(275; ORIGIN2-SAME: i32 [[N:%.*]], ...) local_unnamed_addr {276; ORIGIN2-NEXT: [[ENTRY:.*]]:277; ORIGIN2-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8278; ORIGIN2-NEXT: [[TMP2:%.*]] = alloca i8, i64 [[TMP1]], align 8279; ORIGIN2-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP2]], i8 0, i64 [[TMP1]], i1 false)280; ORIGIN2-NEXT: [[TMP3:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP1]], i64 800)281; ORIGIN2-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP2]], ptr align 8 @__msan_va_arg_tls, i64 [[TMP3]], i1 false)282; ORIGIN2-NEXT: call void @llvm.donothing()283; ORIGIN2-NEXT: [[ARGS:%.*]] = alloca [1 x %struct.__va_list_tag], align 16284; ORIGIN2-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[ARGS]] to i64285; ORIGIN2-NEXT: [[TMP6:%.*]] = and i64 [[TMP5]], -2147483649286; ORIGIN2-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr287; ORIGIN2-NEXT: [[TMP8:%.*]] = add i64 [[TMP6]], 1073741824288; ORIGIN2-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], -4289; ORIGIN2-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP9]] to ptr290; ORIGIN2-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[TMP7]], i8 0, i64 24, i1 false)291; ORIGIN2-NEXT: call void @llvm.lifetime.start.p0(ptr nonnull [[ARGS]])292; ORIGIN2-NEXT: [[TMP23:%.*]] = ptrtoint ptr [[ARGS]] to i64293; ORIGIN2-NEXT: [[TMP11:%.*]] = and i64 [[TMP23]], -2147483649294; ORIGIN2-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr295; ORIGIN2-NEXT: [[TMP13:%.*]] = add i64 [[TMP11]], 1073741824296; ORIGIN2-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP13]] to ptr297; ORIGIN2-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP12]], i8 0, i64 4, i1 false)298; ORIGIN2-NEXT: call void @llvm.va_start.p0(ptr nonnull [[ARGS]])299; ORIGIN2-NEXT: [[TMP15:%.*]] = ptrtoint ptr [[ARGS]] to i64300; ORIGIN2-NEXT: [[TMP16:%.*]] = inttoptr i64 [[TMP15]] to ptr301; ORIGIN2-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8302; ORIGIN2-NEXT: [[TMP18:%.*]] = ptrtoint ptr [[TMP17]] to i64303; ORIGIN2-NEXT: [[TMP19:%.*]] = and i64 [[TMP18]], -2147483649304; ORIGIN2-NEXT: [[TMP20:%.*]] = inttoptr i64 [[TMP19]] to ptr305; ORIGIN2-NEXT: [[TMP21:%.*]] = add i64 [[TMP19]], 1073741824306; ORIGIN2-NEXT: [[TMP22:%.*]] = inttoptr i64 [[TMP21]] to ptr307; ORIGIN2-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP20]], ptr align 8 [[TMP2]], i64 [[TMP1]], i1 false)308; ORIGIN2-NEXT: [[TMP36:%.*]] = xor i32 [[N]], -2147483648309; ORIGIN2-NEXT: [[TMP37:%.*]] = and i32 [[TMP36]], -1310; ORIGIN2-NEXT: [[TMP38:%.*]] = or i32 [[TMP36]], 0311; ORIGIN2-NEXT: [[TMP39:%.*]] = icmp ugt i32 [[TMP37]], -2147483648312; ORIGIN2-NEXT: [[TMP40:%.*]] = icmp ugt i32 [[TMP38]], -2147483648313; ORIGIN2-NEXT: [[TMP41:%.*]] = xor i1 [[TMP39]], [[TMP40]]314; ORIGIN2-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[N]], 0315; ORIGIN2-NEXT: br i1 [[CMP9]], label %[[FOR_BODY_LR_PH:.*]], label %[[FOR_END:.*]]316; ORIGIN2: [[FOR_BODY_LR_PH]]:317; ORIGIN2-NEXT: [[TMP42:%.*]] = getelementptr inbounds [1 x %struct.__va_list_tag], ptr [[ARGS]], i64 0, i64 0, i32 3318; ORIGIN2-NEXT: [[OVERFLOW_ARG_AREA_P:%.*]] = getelementptr inbounds [1 x %struct.__va_list_tag], ptr [[ARGS]], i64 0, i64 0, i32 2319; ORIGIN2-NEXT: [[GP_OFFSET_PRE:%.*]] = load i32, ptr [[ARGS]], align 16320; ORIGIN2-NEXT: br label %[[FOR_BODY:.*]]321; ORIGIN2: [[FOR_BODY]]:322; ORIGIN2-NEXT: [[GP_OFFSET:%.*]] = phi i32 [ [[GP_OFFSET_PRE]], %[[FOR_BODY_LR_PH]] ], [ [[GP_OFFSET12:%.*]], %[[VAARG_END:.*]] ]323; ORIGIN2-NEXT: [[SUM_011:%.*]] = phi i32 [ 0, %[[FOR_BODY_LR_PH]] ], [ [[ADD:%.*]], %[[VAARG_END]] ]324; ORIGIN2-NEXT: [[I_010:%.*]] = phi i32 [ 0, %[[FOR_BODY_LR_PH]] ], [ [[INC:%.*]], %[[VAARG_END]] ]325; ORIGIN2-NEXT: [[TMP43:%.*]] = and i32 [[GP_OFFSET]], -1326; ORIGIN2-NEXT: [[TMP44:%.*]] = or i32 [[GP_OFFSET]], 0327; ORIGIN2-NEXT: [[TMP45:%.*]] = icmp ult i32 [[TMP43]], 41328; ORIGIN2-NEXT: [[TMP46:%.*]] = icmp ult i32 [[TMP44]], 41329; ORIGIN2-NEXT: [[TMP47:%.*]] = xor i1 [[TMP45]], [[TMP46]]330; ORIGIN2-NEXT: [[FITS_IN_GP:%.*]] = icmp ult i32 [[GP_OFFSET]], 41331; ORIGIN2-NEXT: br i1 [[FITS_IN_GP]], label %[[VAARG_IN_REG:.*]], label %[[VAARG_IN_MEM:.*]]332; ORIGIN2: [[VAARG_IN_REG]]:333; ORIGIN2-NEXT: [[REG_SAVE_AREA:%.*]] = load ptr, ptr [[TMP42]], align 16334; ORIGIN2-NEXT: [[TMP48:%.*]] = sext i32 [[GP_OFFSET]] to i64335; ORIGIN2-NEXT: [[TMP49:%.*]] = getelementptr i8, ptr [[REG_SAVE_AREA]], i64 [[TMP48]]336; ORIGIN2-NEXT: [[TMP50:%.*]] = add i32 [[GP_OFFSET]], 8337; ORIGIN2-NEXT: [[TMP51:%.*]] = ptrtoint ptr [[ARGS]] to i64338; ORIGIN2-NEXT: [[TMP52:%.*]] = and i64 [[TMP51]], -2147483649339; ORIGIN2-NEXT: [[TMP53:%.*]] = inttoptr i64 [[TMP52]] to ptr340; ORIGIN2-NEXT: [[TMP54:%.*]] = add i64 [[TMP52]], 1073741824341; ORIGIN2-NEXT: [[TMP55:%.*]] = inttoptr i64 [[TMP54]] to ptr342; ORIGIN2-NEXT: store i32 0, ptr [[TMP53]], align 16343; ORIGIN2-NEXT: store i32 [[TMP50]], ptr [[ARGS]], align 16344; ORIGIN2-NEXT: br label %[[VAARG_END]]345; ORIGIN2: [[VAARG_IN_MEM]]:346; ORIGIN2-NEXT: [[OVERFLOW_ARG_AREA:%.*]] = load ptr, ptr [[OVERFLOW_ARG_AREA_P]], align 8347; ORIGIN2-NEXT: [[OVERFLOW_ARG_AREA_NEXT:%.*]] = getelementptr i8, ptr [[OVERFLOW_ARG_AREA]], i64 8348; ORIGIN2-NEXT: [[TMP56:%.*]] = ptrtoint ptr [[OVERFLOW_ARG_AREA_P]] to i64349; ORIGIN2-NEXT: [[TMP57:%.*]] = and i64 [[TMP56]], -2147483649350; ORIGIN2-NEXT: [[TMP58:%.*]] = inttoptr i64 [[TMP57]] to ptr351; ORIGIN2-NEXT: [[TMP59:%.*]] = add i64 [[TMP57]], 1073741824352; ORIGIN2-NEXT: [[TMP60:%.*]] = inttoptr i64 [[TMP59]] to ptr353; ORIGIN2-NEXT: store i64 0, ptr [[TMP58]], align 8354; ORIGIN2-NEXT: store ptr [[OVERFLOW_ARG_AREA_NEXT]], ptr [[OVERFLOW_ARG_AREA_P]], align 8355; ORIGIN2-NEXT: br label %[[VAARG_END]]356; ORIGIN2: [[VAARG_END]]:357; ORIGIN2-NEXT: [[GP_OFFSET12]] = phi i32 [ [[TMP50]], %[[VAARG_IN_REG]] ], [ [[GP_OFFSET]], %[[VAARG_IN_MEM]] ]358; ORIGIN2-NEXT: [[VAARG_ADDR_IN:%.*]] = phi ptr [ [[TMP49]], %[[VAARG_IN_REG]] ], [ [[OVERFLOW_ARG_AREA]], %[[VAARG_IN_MEM]] ]359; ORIGIN2-NEXT: [[TMP61:%.*]] = load i32, ptr [[VAARG_ADDR_IN]], align 4360; ORIGIN2-NEXT: [[ADD]] = add nsw i32 [[TMP61]], [[SUM_011]]361; ORIGIN2-NEXT: [[INC]] = add nuw nsw i32 [[I_010]], 1362; ORIGIN2-NEXT: [[TMP62:%.*]] = xor i32 [[INC]], [[N]]363; ORIGIN2-NEXT: [[TMP63:%.*]] = and i32 -1, [[TMP62]]364; ORIGIN2-NEXT: [[TMP64:%.*]] = icmp eq i32 [[TMP63]], 0365; ORIGIN2-NEXT: [[_MSPROP_ICMP:%.*]] = and i1 false, [[TMP64]]366; ORIGIN2-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INC]], [[N]]367; ORIGIN2-NEXT: br i1 [[EXITCOND]], label %[[FOR_END]], label %[[FOR_BODY]]368; ORIGIN2: [[FOR_END]]:369; ORIGIN2-NEXT: [[SUM_0_LCSSA:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[ADD]], %[[VAARG_END]] ]370; ORIGIN2-NEXT: call void @llvm.va_end.p0(ptr nonnull [[ARGS]])371; ORIGIN2-NEXT: call void @llvm.lifetime.end.p0(ptr nonnull [[ARGS]])372; ORIGIN2-NEXT: store i32 0, ptr @__msan_retval_tls, align 8373; ORIGIN2-NEXT: store i32 0, ptr @__msan_retval_origin_tls, align 4374; ORIGIN2-NEXT: ret i32 [[SUM_0_LCSSA]]375;376entry:377 %args = alloca [1 x %struct.__va_list_tag], align 16378 call void @llvm.lifetime.start.p0(ptr nonnull %args) #2379 call void @llvm.va_start(ptr nonnull %args)380 %cmp9 = icmp sgt i32 %n, 0381 br i1 %cmp9, label %for.body.lr.ph, label %for.end382 383for.body.lr.ph: ; preds = %entry384 %0 = getelementptr inbounds [1 x %struct.__va_list_tag], ptr %args, i64 0, i64 0, i32 3385 %overflow_arg_area_p = getelementptr inbounds [1 x %struct.__va_list_tag], ptr %args, i64 0, i64 0, i32 2386 %gp_offset.pre = load i32, ptr %args, align 16387 br label %for.body388 389for.body: ; preds = %vaarg.end, %for.body.lr.ph390 %gp_offset = phi i32 [ %gp_offset.pre, %for.body.lr.ph ], [ %gp_offset12, %vaarg.end ]391 %sum.011 = phi i32 [ 0, %for.body.lr.ph ], [ %add, %vaarg.end ]392 %i.010 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %vaarg.end ]393 %fits_in_gp = icmp ult i32 %gp_offset, 41394 br i1 %fits_in_gp, label %vaarg.in_reg, label %vaarg.in_mem395 396vaarg.in_reg: ; preds = %for.body397 %reg_save_area = load ptr, ptr %0, align 16398 %1 = sext i32 %gp_offset to i64399 %2 = getelementptr i8, ptr %reg_save_area, i64 %1400 %3 = add i32 %gp_offset, 8401 store i32 %3, ptr %args, align 16402 br label %vaarg.end403 404vaarg.in_mem: ; preds = %for.body405 %overflow_arg_area = load ptr, ptr %overflow_arg_area_p, align 8406 %overflow_arg_area.next = getelementptr i8, ptr %overflow_arg_area, i64 8407 store ptr %overflow_arg_area.next, ptr %overflow_arg_area_p, align 8408 br label %vaarg.end409 410vaarg.end: ; preds = %vaarg.in_mem, %vaarg.in_reg411 %gp_offset12 = phi i32 [ %3, %vaarg.in_reg ], [ %gp_offset, %vaarg.in_mem ]412 %vaarg.addr.in = phi ptr [ %2, %vaarg.in_reg ], [ %overflow_arg_area, %vaarg.in_mem ]413 %4 = load i32, ptr %vaarg.addr.in, align 4414 %add = add nsw i32 %4, %sum.011415 %inc = add nuw nsw i32 %i.010, 1416 %exitcond = icmp eq i32 %inc, %n417 br i1 %exitcond, label %for.end, label %for.body418 419for.end: ; preds = %vaarg.end, %entry420 %sum.0.lcssa = phi i32 [ 0, %entry ], [ %add, %vaarg.end ]421 call void @llvm.va_end(ptr nonnull %args)422 call void @llvm.lifetime.end.p0(ptr nonnull %args) #2423 ret i32 %sum.0.lcssa424}425 426 427; Function Attrs: argmemonly nounwind428declare void @llvm.lifetime.start.p0(ptr nocapture) #1429 430; Function Attrs: nounwind431declare void @llvm.va_start(ptr) #2432 433; Function Attrs: nounwind434declare void @llvm.va_end(ptr) #2435 436; Function Attrs: argmemonly nounwind437declare void @llvm.lifetime.end.p0(ptr nocapture) #1438 439declare dso_local i80 @sum_i80(i32, ...) local_unnamed_addr440 441; Unaligned types like i80 should also work.442define dso_local i80 @test_i80(i80 %a, i80 %b, i80 %c) local_unnamed_addr {443; CHECK-LABEL: define dso_local i80 @test_i80(444; CHECK-SAME: i80 [[A:%.*]], i80 [[B:%.*]], i80 [[C:%.*]]) local_unnamed_addr {445; CHECK-NEXT: [[ENTRY:.*:]]446; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8447; CHECK-NEXT: call void @llvm.donothing()448; CHECK-NEXT: store i32 0, ptr @__msan_param_tls, align 8449; CHECK-NEXT: store i80 0, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8450; CHECK-NEXT: store i80 0, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 8451; CHECK-NEXT: store i80 0, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 8452; CHECK-NEXT: store i80 0, ptr @__msan_va_arg_tls, align 8453; CHECK-NEXT: store i80 0, ptr getelementptr (i8, ptr @__msan_va_arg_tls, i64 16), align 8454; CHECK-NEXT: store i80 0, ptr getelementptr (i8, ptr @__msan_va_arg_tls, i64 32), align 8455; CHECK-NEXT: store i64 48, ptr @__msan_va_arg_overflow_size_tls, align 8456; CHECK-NEXT: store i80 0, ptr @__msan_retval_tls, align 8457; CHECK-NEXT: [[CALL:%.*]] = tail call i80 (i32, ...) @sum_i80(i32 3, i80 [[A]], i80 [[B]], i80 [[C]])458; CHECK-NEXT: [[_MSRET:%.*]] = load i80, ptr @__msan_retval_tls, align 8459; CHECK-NEXT: store i80 0, ptr @__msan_retval_tls, align 8460; CHECK-NEXT: ret i80 [[CALL]]461;462; ORIGIN-LABEL: define dso_local i80 @test_i80(463; ORIGIN-SAME: i80 [[A:%.*]], i80 [[B:%.*]], i80 [[C:%.*]]) local_unnamed_addr {464; ORIGIN-NEXT: [[ENTRY:.*:]]465; ORIGIN-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8466; ORIGIN-NEXT: call void @llvm.donothing()467; ORIGIN-NEXT: store i32 0, ptr @__msan_param_tls, align 8468; ORIGIN-NEXT: store i80 0, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8469; ORIGIN-NEXT: store i80 0, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 8470; ORIGIN-NEXT: store i80 0, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 8471; ORIGIN-NEXT: store i80 0, ptr @__msan_va_arg_tls, align 8472; ORIGIN-NEXT: store i80 0, ptr getelementptr (i8, ptr @__msan_va_arg_tls, i64 16), align 8473; ORIGIN-NEXT: store i80 0, ptr getelementptr (i8, ptr @__msan_va_arg_tls, i64 32), align 8474; ORIGIN-NEXT: store i64 48, ptr @__msan_va_arg_overflow_size_tls, align 8475; ORIGIN-NEXT: store i80 0, ptr @__msan_retval_tls, align 8476; ORIGIN-NEXT: [[CALL:%.*]] = tail call i80 (i32, ...) @sum_i80(i32 3, i80 [[A]], i80 [[B]], i80 [[C]])477; ORIGIN-NEXT: [[_MSRET:%.*]] = load i80, ptr @__msan_retval_tls, align 8478; ORIGIN-NEXT: [[TMP0:%.*]] = load i32, ptr @__msan_retval_origin_tls, align 4479; ORIGIN-NEXT: store i80 0, ptr @__msan_retval_tls, align 8480; ORIGIN-NEXT: store i32 0, ptr @__msan_retval_origin_tls, align 4481; ORIGIN-NEXT: ret i80 [[CALL]]482;483; ORIGIN2-LABEL: define dso_local i80 @test_i80(484; ORIGIN2-SAME: i80 [[A:%.*]], i80 [[B:%.*]], i80 [[C:%.*]]) local_unnamed_addr {485; ORIGIN2-NEXT: [[ENTRY:.*:]]486; ORIGIN2-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8487; ORIGIN2-NEXT: call void @llvm.donothing()488; ORIGIN2-NEXT: store i32 0, ptr @__msan_param_tls, align 8489; ORIGIN2-NEXT: store i80 0, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8490; ORIGIN2-NEXT: store i80 0, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 8491; ORIGIN2-NEXT: store i80 0, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 8492; ORIGIN2-NEXT: store i80 0, ptr @__msan_va_arg_tls, align 8493; ORIGIN2-NEXT: store i80 0, ptr getelementptr (i8, ptr @__msan_va_arg_tls, i64 16), align 8494; ORIGIN2-NEXT: store i80 0, ptr getelementptr (i8, ptr @__msan_va_arg_tls, i64 32), align 8495; ORIGIN2-NEXT: store i64 48, ptr @__msan_va_arg_overflow_size_tls, align 8496; ORIGIN2-NEXT: store i80 0, ptr @__msan_retval_tls, align 8497; ORIGIN2-NEXT: [[CALL:%.*]] = tail call i80 (i32, ...) @sum_i80(i32 3, i80 [[A]], i80 [[B]], i80 [[C]])498; ORIGIN2-NEXT: [[_MSRET:%.*]] = load i80, ptr @__msan_retval_tls, align 8499; ORIGIN2-NEXT: [[TMP0:%.*]] = load i32, ptr @__msan_retval_origin_tls, align 4500; ORIGIN2-NEXT: store i80 0, ptr @__msan_retval_tls, align 8501; ORIGIN2-NEXT: store i32 0, ptr @__msan_retval_origin_tls, align 4502; ORIGIN2-NEXT: ret i80 [[CALL]]503;504entry:505 %call = tail call i80 (i32, ...) @sum_i80(i32 3, i80 %a, i80 %b, i80 %c)506 ret i80 %call507}508