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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -msan-check-access-address=0 -S -passes=msan 2>&1 | FileCheck %s --implicit-check-not="call void @__msan_warning"3; RUN: opt < %s -msan-check-access-address=1 -S -passes=msan 2>&1 | FileCheck %s --check-prefixes=ADDR --implicit-check-not="call void @__msan_warning"4; RUN: opt < %s -msan-check-access-address=0 -msan-track-origins=1 -S -passes=msan 2>&1 | FileCheck %s --check-prefixes=ORIGINS --implicit-check-not="call void @__msan_warning"5 6; Just don't crash.7; RUN: opt < %s -msan-check-access-address=1 -msan-track-origins=1 -S -passes=msan -msan-kernel8 9target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"10target triple = "x86_64-unknown-linux-gnu"11 12declare void @llvm.masked.store.v4i64.p0(<4 x i64>, ptr, i32, <4 x i1>)13declare <4 x double> @llvm.masked.load.v4f64.p0(ptr, i32, <4 x i1>, <4 x double>)14declare <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr>, i32, <16 x i1>, <16 x float>)15declare void @llvm.masked.scatter.v8i32.v8p0 (<8 x i32>, <8 x ptr>, i32, <8 x i1>)16declare <16 x float> @llvm.masked.expandload.v16f32(ptr, <16 x i1>, <16 x float>)17declare void @llvm.masked.compressstore.v16f32(<16 x float>, ptr, <16 x i1>)18 19define void @Store(ptr %p, <4 x i64> %v, <4 x i1> %mask) sanitize_memory {20; CHECK-LABEL: @Store(21; CHECK-NEXT: entry:22; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 823; CHECK-NEXT: call void @llvm.donothing()24; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i6425; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 8796093022208026; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr27; CHECK-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> [[TMP0]], ptr align 1 [[TMP3]], <4 x i1> [[MASK:%.*]])28; CHECK-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> [[V:%.*]], ptr align 1 [[P]], <4 x i1> [[MASK]])29; CHECK-NEXT: ret void30;31; ADDR-LABEL: @Store(32; ADDR-NEXT: entry:33; ADDR-NEXT: [[TMP0:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 834; ADDR-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 835; ADDR-NEXT: [[TMP2:%.*]] = load <4 x i1>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 836; ADDR-NEXT: call void @llvm.donothing()37; ADDR-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[P:%.*]] to i6438; ADDR-NEXT: [[TMP4:%.*]] = xor i64 [[TMP3]], 8796093022208039; ADDR-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr40; ADDR-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> [[TMP0]], ptr align 1 [[TMP5]], <4 x i1> [[MASK:%.*]])41; ADDR-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 042; ADDR-NEXT: [[TMP6:%.*]] = bitcast <4 x i1> [[TMP2]] to i443; ADDR-NEXT: [[_MSCMP1:%.*]] = icmp ne i4 [[TMP6]], 044; ADDR-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]45; ADDR-NEXT: br i1 [[_MSOR]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1:![0-9]+]]46; ADDR: 7:47; ADDR-NEXT: call void @__msan_warning_noreturn() #[[ATTR7:[0-9]+]]48; ADDR-NEXT: unreachable49; ADDR: 8:50; ADDR-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> [[V:%.*]], ptr align 1 [[P]], <4 x i1> [[MASK]])51; ADDR-NEXT: ret void52;53; ORIGINS-LABEL: @Store(54; ORIGINS-NEXT: entry:55; ORIGINS-NEXT: [[TMP0:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 856; ORIGINS-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_origin_tls, i64 8), align 457; ORIGINS-NEXT: call void @llvm.donothing()58; ORIGINS-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[P:%.*]] to i6459; ORIGINS-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 8796093022208060; ORIGINS-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr61; ORIGINS-NEXT: [[TMP5:%.*]] = add i64 [[TMP3]], 1759218604441662; ORIGINS-NEXT: [[TMP6:%.*]] = and i64 [[TMP5]], -463; ORIGINS-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr64; ORIGINS-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> [[TMP0]], ptr align 1 [[TMP4]], <4 x i1> [[MASK:%.*]])65; ORIGINS-NEXT: store i32 [[TMP1]], ptr [[TMP7]], align 466; ORIGINS-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[TMP7]], i32 167; ORIGINS-NEXT: store i32 [[TMP1]], ptr [[TMP8]], align 468; ORIGINS-NEXT: [[TMP9:%.*]] = getelementptr i32, ptr [[TMP7]], i32 269; ORIGINS-NEXT: store i32 [[TMP1]], ptr [[TMP9]], align 470; ORIGINS-NEXT: [[TMP10:%.*]] = getelementptr i32, ptr [[TMP7]], i32 371; ORIGINS-NEXT: store i32 [[TMP1]], ptr [[TMP10]], align 472; ORIGINS-NEXT: [[TMP11:%.*]] = getelementptr i32, ptr [[TMP7]], i32 473; ORIGINS-NEXT: store i32 [[TMP1]], ptr [[TMP11]], align 474; ORIGINS-NEXT: [[TMP12:%.*]] = getelementptr i32, ptr [[TMP7]], i32 575; ORIGINS-NEXT: store i32 [[TMP1]], ptr [[TMP12]], align 476; ORIGINS-NEXT: [[TMP13:%.*]] = getelementptr i32, ptr [[TMP7]], i32 677; ORIGINS-NEXT: store i32 [[TMP1]], ptr [[TMP13]], align 478; ORIGINS-NEXT: [[TMP14:%.*]] = getelementptr i32, ptr [[TMP7]], i32 779; ORIGINS-NEXT: store i32 [[TMP1]], ptr [[TMP14]], align 480; ORIGINS-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> [[V:%.*]], ptr align 1 [[P]], <4 x i1> [[MASK]])81; ORIGINS-NEXT: ret void82;83entry:84 tail call void @llvm.masked.store.v4i64.p0(<4 x i64> %v, ptr %p, i32 1, <4 x i1> %mask)85 ret void86}87 88define <4 x double> @Load(ptr %p, <4 x double> %v, <4 x i1> %mask) sanitize_memory {89; CHECK-LABEL: @Load(90; CHECK-NEXT: entry:91; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 892; CHECK-NEXT: call void @llvm.donothing()93; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i6494; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 8796093022208095; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr96; CHECK-NEXT: [[_MSMASKEDLD:%.*]] = call <4 x i64> @llvm.masked.load.v4i64.p0(ptr align 1 [[TMP3]], <4 x i1> [[MASK:%.*]], <4 x i64> [[TMP0]])97; CHECK-NEXT: [[X:%.*]] = call <4 x double> @llvm.masked.load.v4f64.p0(ptr align 1 [[P]], <4 x i1> [[MASK]], <4 x double> [[V:%.*]])98; CHECK-NEXT: store <4 x i64> [[_MSMASKEDLD]], ptr @__msan_retval_tls, align 899; CHECK-NEXT: ret <4 x double> [[X]]100;101; ADDR-LABEL: @Load(102; ADDR-NEXT: entry:103; ADDR-NEXT: [[TMP0:%.*]] = load i64, ptr @__msan_param_tls, align 8104; ADDR-NEXT: [[TMP1:%.*]] = load <4 x i1>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 40), align 8105; ADDR-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8106; ADDR-NEXT: call void @llvm.donothing()107; ADDR-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[P:%.*]] to i64108; ADDR-NEXT: [[TMP4:%.*]] = xor i64 [[TMP3]], 87960930222080109; ADDR-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr110; ADDR-NEXT: [[_MSMASKEDLD:%.*]] = call <4 x i64> @llvm.masked.load.v4i64.p0(ptr align 1 [[TMP5]], <4 x i1> [[MASK:%.*]], <4 x i64> [[TMP2]])111; ADDR-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP0]], 0112; ADDR-NEXT: [[TMP6:%.*]] = bitcast <4 x i1> [[TMP1]] to i4113; ADDR-NEXT: [[_MSCMP1:%.*]] = icmp ne i4 [[TMP6]], 0114; ADDR-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]115; ADDR-NEXT: br i1 [[_MSOR]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]116; ADDR: 7:117; ADDR-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]]118; ADDR-NEXT: unreachable119; ADDR: 8:120; ADDR-NEXT: [[X:%.*]] = call <4 x double> @llvm.masked.load.v4f64.p0(ptr align 1 [[P]], <4 x i1> [[MASK]], <4 x double> [[V:%.*]])121; ADDR-NEXT: store <4 x i64> [[_MSMASKEDLD]], ptr @__msan_retval_tls, align 8122; ADDR-NEXT: ret <4 x double> [[X]]123;124; ORIGINS-LABEL: @Load(125; ORIGINS-NEXT: entry:126; ORIGINS-NEXT: [[TMP0:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8127; ORIGINS-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_origin_tls, i64 8), align 4128; ORIGINS-NEXT: call void @llvm.donothing()129; ORIGINS-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[P:%.*]] to i64130; ORIGINS-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080131; ORIGINS-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr132; ORIGINS-NEXT: [[TMP5:%.*]] = add i64 [[TMP3]], 17592186044416133; ORIGINS-NEXT: [[TMP6:%.*]] = and i64 [[TMP5]], -4134; ORIGINS-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr135; ORIGINS-NEXT: [[_MSMASKEDLD:%.*]] = call <4 x i64> @llvm.masked.load.v4i64.p0(ptr align 1 [[TMP4]], <4 x i1> [[MASK:%.*]], <4 x i64> [[TMP0]])136; ORIGINS-NEXT: [[TMP8:%.*]] = sub <4 x i1> zeroinitializer, [[MASK]]137; ORIGINS-NEXT: [[TMP9:%.*]] = sext <4 x i1> [[TMP8]] to <4 x i64>138; ORIGINS-NEXT: [[TMP10:%.*]] = and <4 x i64> [[TMP0]], [[TMP9]]139; ORIGINS-NEXT: [[TMP11:%.*]] = bitcast <4 x i64> [[TMP10]] to i256140; ORIGINS-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP11]], 0141; ORIGINS-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP7]], align 4142; ORIGINS-NEXT: [[TMP13:%.*]] = select i1 [[_MSCMP]], i32 [[TMP1]], i32 [[TMP12]]143; ORIGINS-NEXT: [[X:%.*]] = call <4 x double> @llvm.masked.load.v4f64.p0(ptr align 1 [[P]], <4 x i1> [[MASK]], <4 x double> [[V:%.*]])144; ORIGINS-NEXT: store <4 x i64> [[_MSMASKEDLD]], ptr @__msan_retval_tls, align 8145; ORIGINS-NEXT: store i32 [[TMP13]], ptr @__msan_retval_origin_tls, align 4146; ORIGINS-NEXT: ret <4 x double> [[X]]147;148entry:149 %x = call <4 x double> @llvm.masked.load.v4f64.p0(ptr %p, i32 1, <4 x i1> %mask, <4 x double> %v)150 ret <4 x double> %x151}152 153define void @StoreNoSanitize(ptr %p, <4 x i64> %v, <4 x i1> %mask) {154; CHECK-LABEL: @StoreNoSanitize(155; CHECK-NEXT: entry:156; CHECK-NEXT: call void @llvm.donothing()157; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[P:%.*]] to i64158; CHECK-NEXT: [[TMP1:%.*]] = xor i64 [[TMP0]], 87960930222080159; CHECK-NEXT: [[TMP2:%.*]] = inttoptr i64 [[TMP1]] to ptr160; CHECK-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> zeroinitializer, ptr align 1 [[TMP2]], <4 x i1> [[MASK:%.*]])161; CHECK-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> [[V:%.*]], ptr align 1 [[P]], <4 x i1> [[MASK]])162; CHECK-NEXT: ret void163;164; ADDR-LABEL: @StoreNoSanitize(165; ADDR-NEXT: entry:166; ADDR-NEXT: call void @llvm.donothing()167; ADDR-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[P:%.*]] to i64168; ADDR-NEXT: [[TMP1:%.*]] = xor i64 [[TMP0]], 87960930222080169; ADDR-NEXT: [[TMP2:%.*]] = inttoptr i64 [[TMP1]] to ptr170; ADDR-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> zeroinitializer, ptr align 1 [[TMP2]], <4 x i1> [[MASK:%.*]])171; ADDR-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> [[V:%.*]], ptr align 1 [[P]], <4 x i1> [[MASK]])172; ADDR-NEXT: ret void173;174; ORIGINS-LABEL: @StoreNoSanitize(175; ORIGINS-NEXT: entry:176; ORIGINS-NEXT: call void @llvm.donothing()177; ORIGINS-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[P:%.*]] to i64178; ORIGINS-NEXT: [[TMP1:%.*]] = xor i64 [[TMP0]], 87960930222080179; ORIGINS-NEXT: [[TMP2:%.*]] = inttoptr i64 [[TMP1]] to ptr180; ORIGINS-NEXT: [[TMP3:%.*]] = add i64 [[TMP1]], 17592186044416181; ORIGINS-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], -4182; ORIGINS-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr183; ORIGINS-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> zeroinitializer, ptr align 1 [[TMP2]], <4 x i1> [[MASK:%.*]])184; ORIGINS-NEXT: store i32 0, ptr [[TMP5]], align 4185; ORIGINS-NEXT: [[TMP6:%.*]] = getelementptr i32, ptr [[TMP5]], i32 1186; ORIGINS-NEXT: store i32 0, ptr [[TMP6]], align 4187; ORIGINS-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[TMP5]], i32 2188; ORIGINS-NEXT: store i32 0, ptr [[TMP7]], align 4189; ORIGINS-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[TMP5]], i32 3190; ORIGINS-NEXT: store i32 0, ptr [[TMP8]], align 4191; ORIGINS-NEXT: [[TMP9:%.*]] = getelementptr i32, ptr [[TMP5]], i32 4192; ORIGINS-NEXT: store i32 0, ptr [[TMP9]], align 4193; ORIGINS-NEXT: [[TMP10:%.*]] = getelementptr i32, ptr [[TMP5]], i32 5194; ORIGINS-NEXT: store i32 0, ptr [[TMP10]], align 4195; ORIGINS-NEXT: [[TMP11:%.*]] = getelementptr i32, ptr [[TMP5]], i32 6196; ORIGINS-NEXT: store i32 0, ptr [[TMP11]], align 4197; ORIGINS-NEXT: [[TMP12:%.*]] = getelementptr i32, ptr [[TMP5]], i32 7198; ORIGINS-NEXT: store i32 0, ptr [[TMP12]], align 4199; ORIGINS-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> [[V:%.*]], ptr align 1 [[P]], <4 x i1> [[MASK]])200; ORIGINS-NEXT: ret void201;202entry:203 tail call void @llvm.masked.store.v4i64.p0(<4 x i64> %v, ptr %p, i32 1, <4 x i1> %mask)204 ret void205}206 207define <4 x double> @LoadNoSanitize(ptr %p, <4 x double> %v, <4 x i1> %mask) {208; CHECK-LABEL: @LoadNoSanitize(209; CHECK-NEXT: entry:210; CHECK-NEXT: call void @llvm.donothing()211; CHECK-NEXT: [[X:%.*]] = call <4 x double> @llvm.masked.load.v4f64.p0(ptr align 1 [[P:%.*]], <4 x i1> [[MASK:%.*]], <4 x double> [[V:%.*]])212; CHECK-NEXT: store <4 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8213; CHECK-NEXT: ret <4 x double> [[X]]214;215; ADDR-LABEL: @LoadNoSanitize(216; ADDR-NEXT: entry:217; ADDR-NEXT: call void @llvm.donothing()218; ADDR-NEXT: [[X:%.*]] = call <4 x double> @llvm.masked.load.v4f64.p0(ptr align 1 [[P:%.*]], <4 x i1> [[MASK:%.*]], <4 x double> [[V:%.*]])219; ADDR-NEXT: store <4 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8220; ADDR-NEXT: ret <4 x double> [[X]]221;222; ORIGINS-LABEL: @LoadNoSanitize(223; ORIGINS-NEXT: entry:224; ORIGINS-NEXT: call void @llvm.donothing()225; ORIGINS-NEXT: [[X:%.*]] = call <4 x double> @llvm.masked.load.v4f64.p0(ptr align 1 [[P:%.*]], <4 x i1> [[MASK:%.*]], <4 x double> [[V:%.*]])226; ORIGINS-NEXT: store <4 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8227; ORIGINS-NEXT: store i32 0, ptr @__msan_retval_origin_tls, align 4228; ORIGINS-NEXT: ret <4 x double> [[X]]229;230entry:231 %x = call <4 x double> @llvm.masked.load.v4f64.p0(ptr %p, i32 1, <4 x i1> %mask, <4 x double> %v)232 ret <4 x double> %x233}234 235; FIXME: Provide real implementation.236define <16 x float> @Gather(<16 x ptr> %ptrs, <16 x i1> %mask, <16 x float> %passthru) sanitize_memory {237; CHECK-LABEL: @Gather(238; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 136), align 8239; CHECK-NEXT: call void @llvm.donothing()240; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint <16 x ptr> [[PTRS:%.*]] to <16 x i64>241; CHECK-NEXT: [[TMP3:%.*]] = xor <16 x i64> [[TMP2]], splat (i64 87960930222080)242; CHECK-NEXT: [[TMP4:%.*]] = inttoptr <16 x i64> [[TMP3]] to <16 x ptr>243; CHECK-NEXT: [[_MSMASKEDGATHER:%.*]] = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> align 4 [[TMP4]], <16 x i1> [[MASK:%.*]], <16 x i32> [[TMP1]])244; CHECK-NEXT: [[RET:%.*]] = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> align 4 [[PTRS]], <16 x i1> [[MASK]], <16 x float> [[PASSTHRU:%.*]])245; CHECK-NEXT: store <16 x i32> [[_MSMASKEDGATHER]], ptr @__msan_retval_tls, align 8246; CHECK-NEXT: ret <16 x float> [[RET]]247;248; ADDR-LABEL: @Gather(249; ADDR-NEXT: [[TMP1:%.*]] = load <16 x i1>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 128), align 8250; ADDR-NEXT: [[TMP2:%.*]] = load <16 x i64>, ptr @__msan_param_tls, align 8251; ADDR-NEXT: [[TMP3:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 136), align 8252; ADDR-NEXT: call void @llvm.donothing()253; ADDR-NEXT: [[_MSMASKEDPTRS:%.*]] = select <16 x i1> [[MASK:%.*]], <16 x i64> [[TMP2]], <16 x i64> zeroinitializer254; ADDR-NEXT: [[TMP4:%.*]] = ptrtoint <16 x ptr> [[PTRS:%.*]] to <16 x i64>255; ADDR-NEXT: [[TMP5:%.*]] = xor <16 x i64> [[TMP4]], splat (i64 87960930222080)256; ADDR-NEXT: [[TMP6:%.*]] = inttoptr <16 x i64> [[TMP5]] to <16 x ptr>257; ADDR-NEXT: [[_MSMASKEDGATHER:%.*]] = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> align 4 [[TMP6]], <16 x i1> [[MASK]], <16 x i32> [[TMP3]])258; ADDR-NEXT: [[TMP7:%.*]] = bitcast <16 x i1> [[TMP1]] to i16259; ADDR-NEXT: [[_MSCMP:%.*]] = icmp ne i16 [[TMP7]], 0260; ADDR-NEXT: [[TMP8:%.*]] = bitcast <16 x i64> [[_MSMASKEDPTRS]] to i1024261; ADDR-NEXT: [[_MSCMP1:%.*]] = icmp ne i1024 [[TMP8]], 0262; ADDR-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]263; ADDR-NEXT: br i1 [[_MSOR]], label [[TMP9:%.*]], label [[TMP10:%.*]], !prof [[PROF1]]264; ADDR: 9:265; ADDR-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]]266; ADDR-NEXT: unreachable267; ADDR: 10:268; ADDR-NEXT: [[RET:%.*]] = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> align 4 [[PTRS]], <16 x i1> [[MASK]], <16 x float> [[PASSTHRU:%.*]])269; ADDR-NEXT: store <16 x i32> [[_MSMASKEDGATHER]], ptr @__msan_retval_tls, align 8270; ADDR-NEXT: ret <16 x float> [[RET]]271;272; ORIGINS-LABEL: @Gather(273; ORIGINS-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 136), align 8274; ORIGINS-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_origin_tls, i64 136), align 4275; ORIGINS-NEXT: call void @llvm.donothing()276; ORIGINS-NEXT: [[TMP3:%.*]] = ptrtoint <16 x ptr> [[PTRS:%.*]] to <16 x i64>277; ORIGINS-NEXT: [[TMP4:%.*]] = xor <16 x i64> [[TMP3]], splat (i64 87960930222080)278; ORIGINS-NEXT: [[TMP5:%.*]] = inttoptr <16 x i64> [[TMP4]] to <16 x ptr>279; ORIGINS-NEXT: [[TMP6:%.*]] = add <16 x i64> [[TMP4]], splat (i64 17592186044416)280; ORIGINS-NEXT: [[TMP7:%.*]] = inttoptr <16 x i64> [[TMP6]] to <16 x ptr>281; ORIGINS-NEXT: [[_MSMASKEDGATHER:%.*]] = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> align 4 [[TMP5]], <16 x i1> [[MASK:%.*]], <16 x i32> [[TMP1]])282; ORIGINS-NEXT: [[RET:%.*]] = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> align 4 [[PTRS]], <16 x i1> [[MASK]], <16 x float> [[PASSTHRU:%.*]])283; ORIGINS-NEXT: store <16 x i32> [[_MSMASKEDGATHER]], ptr @__msan_retval_tls, align 8284; ORIGINS-NEXT: store i32 0, ptr @__msan_retval_origin_tls, align 4285; ORIGINS-NEXT: ret <16 x float> [[RET]]286;287 %ret = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %ptrs, i32 4, <16 x i1> %mask, <16 x float> %passthru)288 ret <16 x float> %ret289}290 291define <16 x float> @GatherNoSanitize(<16 x ptr> %ptrs, <16 x i1> %mask, <16 x float> %passthru) {292; CHECK-LABEL: @GatherNoSanitize(293; CHECK-NEXT: call void @llvm.donothing()294; CHECK-NEXT: [[RET:%.*]] = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> align 4 [[PTRS:%.*]], <16 x i1> [[MASK:%.*]], <16 x float> [[PASSTHRU:%.*]])295; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8296; CHECK-NEXT: ret <16 x float> [[RET]]297;298; ADDR-LABEL: @GatherNoSanitize(299; ADDR-NEXT: call void @llvm.donothing()300; ADDR-NEXT: [[_MSMASKEDPTRS:%.*]] = select <16 x i1> [[MASK:%.*]], <16 x i64> zeroinitializer, <16 x i64> zeroinitializer301; ADDR-NEXT: [[RET:%.*]] = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> align 4 [[PTRS:%.*]], <16 x i1> [[MASK]], <16 x float> [[PASSTHRU:%.*]])302; ADDR-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8303; ADDR-NEXT: ret <16 x float> [[RET]]304;305; ORIGINS-LABEL: @GatherNoSanitize(306; ORIGINS-NEXT: call void @llvm.donothing()307; ORIGINS-NEXT: [[RET:%.*]] = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> align 4 [[PTRS:%.*]], <16 x i1> [[MASK:%.*]], <16 x float> [[PASSTHRU:%.*]])308; ORIGINS-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8309; ORIGINS-NEXT: store i32 0, ptr @__msan_retval_origin_tls, align 4310; ORIGINS-NEXT: ret <16 x float> [[RET]]311;312 %ret = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %ptrs, i32 4, <16 x i1> %mask, <16 x float> %passthru)313 ret <16 x float> %ret314}315 316; FIXME: Provide real implementation.317define void @Scatter(<8 x i32> %value, <8 x ptr> %ptrs, <8 x i1> %mask) sanitize_memory {318; CHECK-LABEL: @Scatter(319; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8320; CHECK-NEXT: call void @llvm.donothing()321; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint <8 x ptr> [[PTRS:%.*]] to <8 x i64>322; CHECK-NEXT: [[TMP3:%.*]] = xor <8 x i64> [[TMP2]], splat (i64 87960930222080)323; CHECK-NEXT: [[TMP4:%.*]] = inttoptr <8 x i64> [[TMP3]] to <8 x ptr>324; CHECK-NEXT: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> [[TMP1]], <8 x ptr> align 8 [[TMP4]], <8 x i1> [[MASK:%.*]])325; CHECK-NEXT: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> [[VALUE:%.*]], <8 x ptr> align 8 [[PTRS]], <8 x i1> [[MASK]])326; CHECK-NEXT: ret void327;328; ADDR-LABEL: @Scatter(329; ADDR-NEXT: [[TMP1:%.*]] = load <8 x i1>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 96), align 8330; ADDR-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8331; ADDR-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8332; ADDR-NEXT: call void @llvm.donothing()333; ADDR-NEXT: [[_MSMASKEDPTRS:%.*]] = select <8 x i1> [[MASK:%.*]], <8 x i64> [[TMP2]], <8 x i64> zeroinitializer334; ADDR-NEXT: [[TMP4:%.*]] = ptrtoint <8 x ptr> [[PTRS:%.*]] to <8 x i64>335; ADDR-NEXT: [[TMP5:%.*]] = xor <8 x i64> [[TMP4]], splat (i64 87960930222080)336; ADDR-NEXT: [[TMP6:%.*]] = inttoptr <8 x i64> [[TMP5]] to <8 x ptr>337; ADDR-NEXT: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> [[TMP3]], <8 x ptr> align 8 [[TMP6]], <8 x i1> [[MASK]])338; ADDR-NEXT: [[TMP7:%.*]] = bitcast <8 x i1> [[TMP1]] to i8339; ADDR-NEXT: [[_MSCMP:%.*]] = icmp ne i8 [[TMP7]], 0340; ADDR-NEXT: [[TMP8:%.*]] = bitcast <8 x i64> [[_MSMASKEDPTRS]] to i512341; ADDR-NEXT: [[_MSCMP1:%.*]] = icmp ne i512 [[TMP8]], 0342; ADDR-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]343; ADDR-NEXT: br i1 [[_MSOR]], label [[TMP9:%.*]], label [[TMP10:%.*]], !prof [[PROF1]]344; ADDR: 9:345; ADDR-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]]346; ADDR-NEXT: unreachable347; ADDR: 10:348; ADDR-NEXT: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> [[VALUE:%.*]], <8 x ptr> align 8 [[PTRS]], <8 x i1> [[MASK]])349; ADDR-NEXT: ret void350;351; ORIGINS-LABEL: @Scatter(352; ORIGINS-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8353; ORIGINS-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4354; ORIGINS-NEXT: call void @llvm.donothing()355; ORIGINS-NEXT: [[TMP3:%.*]] = ptrtoint <8 x ptr> [[PTRS:%.*]] to <8 x i64>356; ORIGINS-NEXT: [[TMP4:%.*]] = xor <8 x i64> [[TMP3]], splat (i64 87960930222080)357; ORIGINS-NEXT: [[TMP5:%.*]] = inttoptr <8 x i64> [[TMP4]] to <8 x ptr>358; ORIGINS-NEXT: [[TMP6:%.*]] = add <8 x i64> [[TMP4]], splat (i64 17592186044416)359; ORIGINS-NEXT: [[TMP7:%.*]] = inttoptr <8 x i64> [[TMP6]] to <8 x ptr>360; ORIGINS-NEXT: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> [[TMP1]], <8 x ptr> align 8 [[TMP5]], <8 x i1> [[MASK:%.*]])361; ORIGINS-NEXT: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> [[VALUE:%.*]], <8 x ptr> align 8 [[PTRS]], <8 x i1> [[MASK]])362; ORIGINS-NEXT: ret void363;364 call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> %value, <8 x ptr> %ptrs, i32 8, <8 x i1> %mask)365 ret void366}367 368define void @ScatterNoSanitize(<8 x i32> %value, <8 x ptr> %ptrs, <8 x i1> %mask) {369; CHECK-LABEL: @ScatterNoSanitize(370; CHECK-NEXT: call void @llvm.donothing()371; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint <8 x ptr> [[PTRS:%.*]] to <8 x i64>372; CHECK-NEXT: [[TMP2:%.*]] = xor <8 x i64> [[TMP1]], splat (i64 87960930222080)373; CHECK-NEXT: [[TMP3:%.*]] = inttoptr <8 x i64> [[TMP2]] to <8 x ptr>374; CHECK-NEXT: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> zeroinitializer, <8 x ptr> align 8 [[TMP3]], <8 x i1> [[MASK:%.*]])375; CHECK-NEXT: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> [[VALUE:%.*]], <8 x ptr> align 8 [[PTRS]], <8 x i1> [[MASK]])376; CHECK-NEXT: ret void377;378; ADDR-LABEL: @ScatterNoSanitize(379; ADDR-NEXT: call void @llvm.donothing()380; ADDR-NEXT: [[_MSMASKEDPTRS:%.*]] = select <8 x i1> [[MASK:%.*]], <8 x i64> zeroinitializer, <8 x i64> zeroinitializer381; ADDR-NEXT: [[TMP1:%.*]] = ptrtoint <8 x ptr> [[PTRS:%.*]] to <8 x i64>382; ADDR-NEXT: [[TMP2:%.*]] = xor <8 x i64> [[TMP1]], splat (i64 87960930222080)383; ADDR-NEXT: [[TMP3:%.*]] = inttoptr <8 x i64> [[TMP2]] to <8 x ptr>384; ADDR-NEXT: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> zeroinitializer, <8 x ptr> align 8 [[TMP3]], <8 x i1> [[MASK]])385; ADDR-NEXT: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> [[VALUE:%.*]], <8 x ptr> align 8 [[PTRS]], <8 x i1> [[MASK]])386; ADDR-NEXT: ret void387;388; ORIGINS-LABEL: @ScatterNoSanitize(389; ORIGINS-NEXT: call void @llvm.donothing()390; ORIGINS-NEXT: [[TMP1:%.*]] = ptrtoint <8 x ptr> [[PTRS:%.*]] to <8 x i64>391; ORIGINS-NEXT: [[TMP2:%.*]] = xor <8 x i64> [[TMP1]], splat (i64 87960930222080)392; ORIGINS-NEXT: [[TMP3:%.*]] = inttoptr <8 x i64> [[TMP2]] to <8 x ptr>393; ORIGINS-NEXT: [[TMP4:%.*]] = add <8 x i64> [[TMP2]], splat (i64 17592186044416)394; ORIGINS-NEXT: [[TMP5:%.*]] = inttoptr <8 x i64> [[TMP4]] to <8 x ptr>395; ORIGINS-NEXT: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> zeroinitializer, <8 x ptr> align 8 [[TMP3]], <8 x i1> [[MASK:%.*]])396; ORIGINS-NEXT: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> [[VALUE:%.*]], <8 x ptr> align 8 [[PTRS]], <8 x i1> [[MASK]])397; ORIGINS-NEXT: ret void398;399 call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> %value, <8 x ptr> %ptrs, i32 8, <8 x i1> %mask)400 ret void401}402 403; FIXME: Provide real implementation.404define <16 x float> @ExpandLoad(ptr %ptr, <16 x i1> %mask, <16 x float> %passthru) sanitize_memory {405; CHECK-LABEL: @ExpandLoad(406; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8407; CHECK-NEXT: call void @llvm.donothing()408; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[PTR:%.*]] to i64409; CHECK-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080410; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr411; CHECK-NEXT: [[_MSMASKEDEXPLOAD:%.*]] = call <16 x i32> @llvm.masked.expandload.v16i32(ptr [[TMP4]], <16 x i1> [[MASK:%.*]], <16 x i32> [[TMP1]])412; CHECK-NEXT: [[RET:%.*]] = call <16 x float> @llvm.masked.expandload.v16f32(ptr [[PTR]], <16 x i1> [[MASK]], <16 x float> [[PASSTHRU:%.*]])413; CHECK-NEXT: store <16 x i32> [[_MSMASKEDEXPLOAD]], ptr @__msan_retval_tls, align 8414; CHECK-NEXT: ret <16 x float> [[RET]]415;416; ADDR-LABEL: @ExpandLoad(417; ADDR-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8418; ADDR-NEXT: [[TMP2:%.*]] = load <16 x i1>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8419; ADDR-NEXT: [[TMP3:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8420; ADDR-NEXT: call void @llvm.donothing()421; ADDR-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[PTR:%.*]] to i64422; ADDR-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 87960930222080423; ADDR-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr424; ADDR-NEXT: [[_MSMASKEDEXPLOAD:%.*]] = call <16 x i32> @llvm.masked.expandload.v16i32(ptr [[TMP6]], <16 x i1> [[MASK:%.*]], <16 x i32> [[TMP3]])425; ADDR-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0426; ADDR-NEXT: [[TMP7:%.*]] = bitcast <16 x i1> [[TMP2]] to i16427; ADDR-NEXT: [[_MSCMP1:%.*]] = icmp ne i16 [[TMP7]], 0428; ADDR-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]429; ADDR-NEXT: br i1 [[_MSOR]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]430; ADDR: 8:431; ADDR-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]]432; ADDR-NEXT: unreachable433; ADDR: 9:434; ADDR-NEXT: [[RET:%.*]] = call <16 x float> @llvm.masked.expandload.v16f32(ptr [[PTR]], <16 x i1> [[MASK]], <16 x float> [[PASSTHRU:%.*]])435; ADDR-NEXT: store <16 x i32> [[_MSMASKEDEXPLOAD]], ptr @__msan_retval_tls, align 8436; ADDR-NEXT: ret <16 x float> [[RET]]437;438; ORIGINS-LABEL: @ExpandLoad(439; ORIGINS-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8440; ORIGINS-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_origin_tls, i64 16), align 4441; ORIGINS-NEXT: call void @llvm.donothing()442; ORIGINS-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[PTR:%.*]] to i64443; ORIGINS-NEXT: [[TMP4:%.*]] = xor i64 [[TMP3]], 87960930222080444; ORIGINS-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr445; ORIGINS-NEXT: [[TMP6:%.*]] = add i64 [[TMP4]], 17592186044416446; ORIGINS-NEXT: [[TMP7:%.*]] = and i64 [[TMP6]], -4447; ORIGINS-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr448; ORIGINS-NEXT: [[_MSMASKEDEXPLOAD:%.*]] = call <16 x i32> @llvm.masked.expandload.v16i32(ptr [[TMP5]], <16 x i1> [[MASK:%.*]], <16 x i32> [[TMP1]])449; ORIGINS-NEXT: [[RET:%.*]] = call <16 x float> @llvm.masked.expandload.v16f32(ptr [[PTR]], <16 x i1> [[MASK]], <16 x float> [[PASSTHRU:%.*]])450; ORIGINS-NEXT: store <16 x i32> [[_MSMASKEDEXPLOAD]], ptr @__msan_retval_tls, align 8451; ORIGINS-NEXT: store i32 0, ptr @__msan_retval_origin_tls, align 4452; ORIGINS-NEXT: ret <16 x float> [[RET]]453;454 %ret = call <16 x float> @llvm.masked.expandload.v16f32(ptr %ptr, <16 x i1> %mask, <16 x float> %passthru)455 ret <16 x float> %ret456}457 458define <16 x float> @ExpandLoadNoSanitize(ptr %ptr, <16 x i1> %mask, <16 x float> %passthru) {459; CHECK-LABEL: @ExpandLoadNoSanitize(460; CHECK-NEXT: call void @llvm.donothing()461; CHECK-NEXT: [[RET:%.*]] = call <16 x float> @llvm.masked.expandload.v16f32(ptr [[PTR:%.*]], <16 x i1> [[MASK:%.*]], <16 x float> [[PASSTHRU:%.*]])462; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8463; CHECK-NEXT: ret <16 x float> [[RET]]464;465; ADDR-LABEL: @ExpandLoadNoSanitize(466; ADDR-NEXT: call void @llvm.donothing()467; ADDR-NEXT: [[RET:%.*]] = call <16 x float> @llvm.masked.expandload.v16f32(ptr [[PTR:%.*]], <16 x i1> [[MASK:%.*]], <16 x float> [[PASSTHRU:%.*]])468; ADDR-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8469; ADDR-NEXT: ret <16 x float> [[RET]]470;471; ORIGINS-LABEL: @ExpandLoadNoSanitize(472; ORIGINS-NEXT: call void @llvm.donothing()473; ORIGINS-NEXT: [[RET:%.*]] = call <16 x float> @llvm.masked.expandload.v16f32(ptr [[PTR:%.*]], <16 x i1> [[MASK:%.*]], <16 x float> [[PASSTHRU:%.*]])474; ORIGINS-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8475; ORIGINS-NEXT: store i32 0, ptr @__msan_retval_origin_tls, align 4476; ORIGINS-NEXT: ret <16 x float> [[RET]]477;478 %ret = call <16 x float> @llvm.masked.expandload.v16f32(ptr %ptr, <16 x i1> %mask, <16 x float> %passthru)479 ret <16 x float> %ret480}481 482; FIXME: Provide real implementation.483define void @CompressStore(<16 x float> %value, ptr %ptr, <16 x i1> %mask) sanitize_memory {484; CHECK-LABEL: @CompressStore(485; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 8486; CHECK-NEXT: call void @llvm.donothing()487; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[PTR:%.*]] to i64488; CHECK-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080489; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr490; CHECK-NEXT: call void @llvm.masked.compressstore.v16i32(<16 x i32> [[TMP1]], ptr [[TMP4]], <16 x i1> [[MASK:%.*]])491; CHECK-NEXT: call void @llvm.masked.compressstore.v16f32(<16 x float> [[VALUE:%.*]], ptr [[PTR]], <16 x i1> [[MASK]])492; CHECK-NEXT: ret void493;494; ADDR-LABEL: @CompressStore(495; ADDR-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 8496; ADDR-NEXT: [[TMP2:%.*]] = load <16 x i1>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 72), align 8497; ADDR-NEXT: [[TMP3:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 8498; ADDR-NEXT: call void @llvm.donothing()499; ADDR-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[PTR:%.*]] to i64500; ADDR-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 87960930222080501; ADDR-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr502; ADDR-NEXT: call void @llvm.masked.compressstore.v16i32(<16 x i32> [[TMP3]], ptr [[TMP6]], <16 x i1> [[MASK:%.*]])503; ADDR-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0504; ADDR-NEXT: [[TMP7:%.*]] = bitcast <16 x i1> [[TMP2]] to i16505; ADDR-NEXT: [[_MSCMP1:%.*]] = icmp ne i16 [[TMP7]], 0506; ADDR-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]507; ADDR-NEXT: br i1 [[_MSOR]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]508; ADDR: 8:509; ADDR-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]]510; ADDR-NEXT: unreachable511; ADDR: 9:512; ADDR-NEXT: call void @llvm.masked.compressstore.v16f32(<16 x float> [[VALUE:%.*]], ptr [[PTR]], <16 x i1> [[MASK]])513; ADDR-NEXT: ret void514;515; ORIGINS-LABEL: @CompressStore(516; ORIGINS-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 8517; ORIGINS-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4518; ORIGINS-NEXT: call void @llvm.donothing()519; ORIGINS-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[PTR:%.*]] to i64520; ORIGINS-NEXT: [[TMP4:%.*]] = xor i64 [[TMP3]], 87960930222080521; ORIGINS-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr522; ORIGINS-NEXT: [[TMP6:%.*]] = add i64 [[TMP4]], 17592186044416523; ORIGINS-NEXT: [[TMP7:%.*]] = and i64 [[TMP6]], -4524; ORIGINS-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr525; ORIGINS-NEXT: call void @llvm.masked.compressstore.v16i32(<16 x i32> [[TMP1]], ptr [[TMP5]], <16 x i1> [[MASK:%.*]])526; ORIGINS-NEXT: call void @llvm.masked.compressstore.v16f32(<16 x float> [[VALUE:%.*]], ptr [[PTR]], <16 x i1> [[MASK]])527; ORIGINS-NEXT: ret void528;529 call void @llvm.masked.compressstore.v16f32(<16 x float> %value, ptr %ptr, <16 x i1> %mask)530 ret void531}532 533define void @CompressStoreNoSanitize(<16 x float> %value, ptr %ptr, <16 x i1> %mask) {534; CHECK-LABEL: @CompressStoreNoSanitize(535; CHECK-NEXT: call void @llvm.donothing()536; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[PTR:%.*]] to i64537; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080538; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr539; CHECK-NEXT: call void @llvm.masked.compressstore.v16i32(<16 x i32> zeroinitializer, ptr [[TMP3]], <16 x i1> [[MASK:%.*]])540; CHECK-NEXT: call void @llvm.masked.compressstore.v16f32(<16 x float> [[VALUE:%.*]], ptr [[PTR]], <16 x i1> [[MASK]])541; CHECK-NEXT: ret void542;543; ADDR-LABEL: @CompressStoreNoSanitize(544; ADDR-NEXT: call void @llvm.donothing()545; ADDR-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[PTR:%.*]] to i64546; ADDR-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080547; ADDR-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr548; ADDR-NEXT: call void @llvm.masked.compressstore.v16i32(<16 x i32> zeroinitializer, ptr [[TMP3]], <16 x i1> [[MASK:%.*]])549; ADDR-NEXT: call void @llvm.masked.compressstore.v16f32(<16 x float> [[VALUE:%.*]], ptr [[PTR]], <16 x i1> [[MASK]])550; ADDR-NEXT: ret void551;552; ORIGINS-LABEL: @CompressStoreNoSanitize(553; ORIGINS-NEXT: call void @llvm.donothing()554; ORIGINS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[PTR:%.*]] to i64555; ORIGINS-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080556; ORIGINS-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr557; ORIGINS-NEXT: [[TMP4:%.*]] = add i64 [[TMP2]], 17592186044416558; ORIGINS-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], -4559; ORIGINS-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr560; ORIGINS-NEXT: call void @llvm.masked.compressstore.v16i32(<16 x i32> zeroinitializer, ptr [[TMP3]], <16 x i1> [[MASK:%.*]])561; ORIGINS-NEXT: call void @llvm.masked.compressstore.v16f32(<16 x float> [[VALUE:%.*]], ptr [[PTR]], <16 x i1> [[MASK]])562; ORIGINS-NEXT: ret void563;564 call void @llvm.masked.compressstore.v16f32(<16 x float> %value, ptr %ptr, <16 x i1> %mask)565 ret void566}567