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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -passes='module(msan)' -msan-instrumentation-with-call-threshold=0 -msan-track-origins=1 -S | FileCheck %s3 4target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"5target triple = "x86_64-unknown-linux-gnu"6 7!llvm.module.flags = !{!0}8 9!0 = !{i32 2, !"Debug Info Version", i32 3}10!2 = distinct !DISubprogram(name: "t", scope: !3, file: !3, line: 4, type: !4, spFlags: DISPFlagDefinition, unit: !6)11!3 = !DIFile(filename: "tmp/noundef.cpp", directory: "/")12!4 = !DISubroutineType(types: !5)13!5 = !{}14!6 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !3, isOptimized: false, runtimeVersion: 0, emissionKind: NoDebug)15!10 = !DILocation(line: 9, column: 0, scope: !2)16!11 = !DILocation(line: 9, column: 1, scope: !2)17!12 = !DILocation(line: 9, column: 2, scope: !2)18!13 = !DILocation(line: 9, column: 3, scope: !2)19!14 = !DILocation(line: 9, column: 4, scope: !2)20!15 = !DILocation(line: 9, column: 5, scope: !2)21 22define void @Store(ptr nocapture %p, i32 %x) nounwind uwtable sanitize_memory {23; CHECK-LABEL: @Store(24; CHECK-NEXT: entry:25; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__msan_param_tls, align 8, !dbg [[DBG2:![0-9]+]]26; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4, !dbg [[DBG2]]27; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8, !dbg [[DBG2]]28; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_origin_tls, i64 8), align 4, !dbg [[DBG2]]29; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG2]]30; CHECK-NEXT: call void @__msan_maybe_warning_8(i64 zeroext [[TMP0]], i32 zeroext [[TMP1]]), !dbg [[DBG2]]31; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64, !dbg [[DBG2]]32; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 87960930222080, !dbg [[DBG2]]33; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr, !dbg [[DBG2]]34; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[TMP5]], 17592186044416, !dbg [[DBG2]]35; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr, !dbg [[DBG2]]36; CHECK-NEXT: store i32 [[TMP2]], ptr [[TMP6]], align 4, !dbg [[DBG2]]37; CHECK-NEXT: call void @__msan_maybe_store_origin_4(i32 zeroext [[TMP2]], ptr [[P]], i32 zeroext [[TMP3]]), !dbg [[DBG2]]38; CHECK-NEXT: store i32 [[X:%.*]], ptr [[P]], align 4, !dbg [[DBG2]]39; CHECK-NEXT: ret void40;41entry:42 store i32 %x, ptr %p, align 4, !dbg !1043 ret void44}45 46define void @LoadAndCmp(ptr nocapture %a) nounwind uwtable sanitize_memory {47; CHECK-LABEL: @LoadAndCmp(48; CHECK-NEXT: entry:49; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__msan_param_tls, align 8, !dbg [[DBG2]]50; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4, !dbg [[DBG2]]51; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG2]]52; CHECK-NEXT: call void @__msan_maybe_warning_8(i64 zeroext [[TMP0]], i32 zeroext [[TMP1]]), !dbg [[DBG2]]53; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A:%.*]], align 4, !dbg [[DBG2]]54; CHECK-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[A]] to i64, !dbg [[DBG2]]55; CHECK-NEXT: [[TMP4:%.*]] = xor i64 [[TMP3]], 87960930222080, !dbg [[DBG2]]56; CHECK-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr, !dbg [[DBG2]]57; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP4]], 17592186044416, !dbg [[DBG2]]58; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr, !dbg [[DBG2]]59; CHECK-NEXT: [[_MSLD:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG2]]60; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4, !dbg [[DBG2]]61; CHECK-NEXT: [[TMP9:%.*]] = xor i32 [[TMP2]], 0, !dbg [[DBG8:![0-9]+]]62; CHECK-NEXT: [[TMP10:%.*]] = or i32 [[_MSLD]], 0, !dbg [[DBG8]]63; CHECK-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0, !dbg [[DBG8]]64; CHECK-NEXT: [[TMP12:%.*]] = xor i32 [[TMP10]], -1, !dbg [[DBG8]]65; CHECK-NEXT: [[TMP13:%.*]] = and i32 [[TMP12]], [[TMP9]], !dbg [[DBG8]]66; CHECK-NEXT: [[TMP14:%.*]] = icmp eq i32 [[TMP13]], 0, !dbg [[DBG8]]67; CHECK-NEXT: [[_MSPROP_ICMP:%.*]] = and i1 [[TMP11]], [[TMP14]], !dbg [[DBG8]]68; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[TMP2]], 0, !dbg [[DBG8]]69; CHECK-NEXT: [[TMP15:%.*]] = zext i1 [[_MSPROP_ICMP]] to i8, !dbg [[DBG9:![0-9]+]]70; CHECK-NEXT: call void @__msan_maybe_warning_1(i8 zeroext [[TMP15]], i32 zeroext [[TMP8]]), !dbg [[DBG9]]71; CHECK-NEXT: br i1 [[TOBOOL]], label [[IF_END:%.*]], label [[IF_THEN:%.*]], !dbg [[DBG9]]72; CHECK: if.then:73; CHECK-NEXT: store i64 0, ptr @__msan_va_arg_overflow_size_tls, align 874; CHECK-NEXT: tail call void (...) @foo() #[[ATTR5:[0-9]+]]75; CHECK-NEXT: br label [[IF_END]]76; CHECK: if.end:77; CHECK-NEXT: ret void78;79entry:80 %0 = load i32, ptr %a, align 4, !dbg !1081 %tobool = icmp eq i32 %0, 0, !dbg !1182 br i1 %tobool, label %if.end, label %if.then, !dbg !1283 84if.then: tail call void (...) @foo() nounwind85 br label %if.end86 87if.end: ret void88}89 90declare void @foo(...)91 92define i32 @ReturnInt() nounwind uwtable readnone sanitize_memory {93; CHECK-LABEL: @ReturnInt(94; CHECK-NEXT: entry:95; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG2]]96; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8, !dbg [[DBG2]]97; CHECK-NEXT: store i32 0, ptr @__msan_retval_origin_tls, align 4, !dbg [[DBG2]]98; CHECK-NEXT: ret i32 123, !dbg [[DBG2]]99;100entry:101 ret i32 123, !dbg !10102}103 104define void @CopyRetVal(ptr nocapture %a) nounwind uwtable sanitize_memory {105; CHECK-LABEL: @CopyRetVal(106; CHECK-NEXT: entry:107; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__msan_param_tls, align 8, !dbg [[DBG2]]108; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4, !dbg [[DBG2]]109; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG2]]110; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8, !dbg [[DBG2]]111; CHECK-NEXT: [[CALL:%.*]] = tail call i32 @ReturnInt() #[[ATTR5]], !dbg [[DBG2]]112; CHECK-NEXT: [[_MSRET:%.*]] = load i32, ptr @__msan_retval_tls, align 8, !dbg [[DBG8]]113; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_retval_origin_tls, align 4, !dbg [[DBG8]]114; CHECK-NEXT: call void @__msan_maybe_warning_8(i64 zeroext [[TMP0]], i32 zeroext [[TMP1]]), !dbg [[DBG8]]115; CHECK-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[A:%.*]] to i64, !dbg [[DBG8]]116; CHECK-NEXT: [[TMP4:%.*]] = xor i64 [[TMP3]], 87960930222080, !dbg [[DBG8]]117; CHECK-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr, !dbg [[DBG8]]118; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP4]], 17592186044416, !dbg [[DBG8]]119; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr, !dbg [[DBG8]]120; CHECK-NEXT: store i32 [[_MSRET]], ptr [[TMP5]], align 4, !dbg [[DBG8]]121; CHECK-NEXT: call void @__msan_maybe_store_origin_4(i32 zeroext [[_MSRET]], ptr [[A]], i32 zeroext [[TMP2]]), !dbg [[DBG8]]122; CHECK-NEXT: store i32 [[CALL]], ptr [[A]], align 4, !dbg [[DBG8]]123; CHECK-NEXT: ret void124;125entry:126 %call = tail call i32 @ReturnInt() nounwind, !dbg !10127 store i32 %call, ptr %a, align 4, !dbg !11128 ret void129}130 131 132 133define void @SExt(ptr nocapture %a, ptr nocapture %b) nounwind uwtable sanitize_memory {134; CHECK-LABEL: @SExt(135; CHECK-NEXT: entry:136; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8, !dbg [[DBG2]]137; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_origin_tls, i64 8), align 4, !dbg [[DBG2]]138; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_param_tls, align 8, !dbg [[DBG2]]139; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4, !dbg [[DBG2]]140; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG2]]141; CHECK-NEXT: call void @__msan_maybe_warning_8(i64 zeroext [[TMP0]], i32 zeroext [[TMP1]]), !dbg [[DBG2]]142; CHECK-NEXT: [[TMP4:%.*]] = load i16, ptr [[B:%.*]], align 2, !dbg [[DBG2]]143; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[B]] to i64, !dbg [[DBG2]]144; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 87960930222080, !dbg [[DBG2]]145; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr, !dbg [[DBG2]]146; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[TMP6]], 17592186044416, !dbg [[DBG2]]147; CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], -4, !dbg [[DBG2]]148; CHECK-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP9]] to ptr, !dbg [[DBG2]]149; CHECK-NEXT: [[_MSLD:%.*]] = load i16, ptr [[TMP7]], align 2, !dbg [[DBG2]]150; CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4, !dbg [[DBG2]]151; CHECK-NEXT: [[_MSPROP:%.*]] = sext i16 [[_MSLD]] to i32, !dbg [[DBG8]]152; CHECK-NEXT: [[TMP12:%.*]] = sext i16 [[TMP4]] to i32, !dbg [[DBG8]]153; CHECK-NEXT: call void @__msan_maybe_warning_8(i64 zeroext [[TMP2]], i32 zeroext [[TMP3]]), !dbg [[DBG9]]154; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[A:%.*]] to i64, !dbg [[DBG9]]155; CHECK-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], 87960930222080, !dbg [[DBG9]]156; CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP14]] to ptr, !dbg [[DBG9]]157; CHECK-NEXT: [[TMP16:%.*]] = add i64 [[TMP14]], 17592186044416, !dbg [[DBG9]]158; CHECK-NEXT: [[TMP17:%.*]] = inttoptr i64 [[TMP16]] to ptr, !dbg [[DBG9]]159; CHECK-NEXT: store i32 [[_MSPROP]], ptr [[TMP15]], align 4, !dbg [[DBG9]]160; CHECK-NEXT: call void @__msan_maybe_store_origin_4(i32 zeroext [[_MSPROP]], ptr [[A]], i32 zeroext [[TMP11]]), !dbg [[DBG9]]161; CHECK-NEXT: store i32 [[TMP12]], ptr [[A]], align 4, !dbg [[DBG9]]162; CHECK-NEXT: ret void163;164entry:165 %0 = load i16, ptr %b, align 2, !dbg !10166 %1 = sext i16 %0 to i32, !dbg !11167 store i32 %1, ptr %a, align 4, !dbg !12168 ret void169}170 171define void @MemSet(ptr nocapture %x) nounwind uwtable sanitize_memory {172; CHECK-LABEL: @MemSet(173; CHECK-NEXT: entry:174; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG2]]175; CHECK-NEXT: [[TMP0:%.*]] = call ptr @__msan_memset(ptr [[X:%.*]], i32 42, i64 10), !dbg [[DBG2]]176; CHECK-NEXT: ret void177;178entry:179 call void @llvm.memset.p0.i64(ptr %x, i8 42, i64 10, i1 false), !dbg !10180 ret void181}182 183declare void @llvm.memset.p0.i64(ptr nocapture, i8, i64, i1) nounwind184 185 186 187define void @MemCpy(ptr nocapture %x, ptr nocapture %y) nounwind uwtable sanitize_memory {188; CHECK-LABEL: @MemCpy(189; CHECK-NEXT: entry:190; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8, !dbg [[DBG2]]191; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_origin_tls, i64 8), align 4, !dbg [[DBG2]]192; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG2]]193; CHECK-NEXT: [[TMP2:%.*]] = call ptr @__msan_memcpy(ptr [[X:%.*]], ptr [[Y:%.*]], i64 10), !dbg [[DBG2]]194; CHECK-NEXT: ret void195;196entry:197 call void @llvm.memcpy.p0.p0.i64(ptr %x, ptr %y, i64 10, i1 false), !dbg !10198 ret void199}200 201declare void @llvm.memcpy.p0.p0.i64(ptr nocapture, ptr nocapture, i64, i1) nounwind202 203 204define void @MemSetInline(ptr nocapture %x) nounwind uwtable sanitize_memory {205; CHECK-LABEL: @MemSetInline(206; CHECK-NEXT: entry:207; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG2]]208; CHECK-NEXT: [[TMP0:%.*]] = call ptr @__msan_memset(ptr [[X:%.*]], i32 42, i64 10), !dbg [[DBG2]]209; CHECK-NEXT: ret void210;211entry:212 call void @llvm.memset.inline.p0.i64(ptr %x, i8 42, i64 10, i1 false), !dbg !10213 ret void214}215 216declare void @llvm.memset.inline.p0.i64(ptr nocapture, i8, i64, i1) nounwind217 218 219define void @MemCpyInline(ptr nocapture %x, ptr nocapture %y) nounwind uwtable sanitize_memory {220; CHECK-LABEL: @MemCpyInline(221; CHECK-NEXT: entry:222; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8, !dbg [[DBG2]]223; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_origin_tls, i64 8), align 4, !dbg [[DBG2]]224; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG2]]225; CHECK-NEXT: [[TMP2:%.*]] = call ptr @__msan_memcpy(ptr [[X:%.*]], ptr [[Y:%.*]], i64 10), !dbg [[DBG2]]226; CHECK-NEXT: ret void227;228entry:229 call void @llvm.memcpy.inline.p0.p0.i64(ptr %x, ptr %y, i64 10, i1 false), !dbg !10230 ret void231}232 233declare void @llvm.memcpy.inline.p0.p0.i64(ptr nocapture, ptr nocapture, i64, i1) nounwind234 235 236define void @MemMove(ptr nocapture %x, ptr nocapture %y) nounwind uwtable sanitize_memory {237; CHECK-LABEL: @MemMove(238; CHECK-NEXT: entry:239; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8, !dbg [[DBG2]]240; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_origin_tls, i64 8), align 4, !dbg [[DBG2]]241; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG2]]242; CHECK-NEXT: [[TMP2:%.*]] = call ptr @__msan_memmove(ptr [[X:%.*]], ptr [[Y:%.*]], i64 10), !dbg [[DBG2]]243; CHECK-NEXT: ret void244;245entry:246 call void @llvm.memmove.p0.p0.i64(ptr %x, ptr %y, i64 10, i1 false), !dbg !10247 ret void248}249 250declare void @llvm.memmove.p0.p0.i64(ptr nocapture, ptr nocapture, i64, i1) nounwind251 252 253declare void @llvm.memset.element.unordered.atomic.p0.i64(ptr nocapture writeonly, i8, i64, i32) nounwind254declare void @llvm.memmove.element.unordered.atomic.p0.p0.i64(ptr nocapture writeonly, ptr nocapture readonly, i64, i32) nounwind255declare void @llvm.memcpy.element.unordered.atomic.p0.p0.i64(ptr nocapture writeonly, ptr nocapture readonly, i64, i32) nounwind256 257define void @atomic_memcpy(ptr nocapture %x, ptr nocapture %y) nounwind {258; CHECK-LABEL: @atomic_memcpy(259; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG2]]260; CHECK-NEXT: call void @llvm.memcpy.element.unordered.atomic.p0.p0.i64(ptr align 1 [[X:%.*]], ptr align 2 [[Y:%.*]], i64 16, i32 1), !dbg [[DBG2]]261; CHECK-NEXT: ret void262;263 call void @llvm.memcpy.element.unordered.atomic.p0.p0.i64(ptr align 1 %x, ptr align 2 %y, i64 16, i32 1), !dbg !10264 ret void265}266 267define void @atomic_memmove(ptr nocapture %x, ptr nocapture %y) nounwind {268; CHECK-LABEL: @atomic_memmove(269; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG2]]270; CHECK-NEXT: call void @llvm.memmove.element.unordered.atomic.p0.p0.i64(ptr align 1 [[X:%.*]], ptr align 2 [[Y:%.*]], i64 16, i32 1), !dbg [[DBG2]]271; CHECK-NEXT: ret void272;273 call void @llvm.memmove.element.unordered.atomic.p0.p0.i64(ptr align 1 %x, ptr align 2 %y, i64 16, i32 1), !dbg !10274 ret void275}276 277define void @atomic_memset(ptr nocapture %x) nounwind {278; CHECK-LABEL: @atomic_memset(279; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG2]]280; CHECK-NEXT: call void @llvm.memset.element.unordered.atomic.p0.i64(ptr align 1 [[X:%.*]], i8 88, i64 16, i32 1), !dbg [[DBG2]]281; CHECK-NEXT: ret void282;283 call void @llvm.memset.element.unordered.atomic.p0.i64(ptr align 1 %x, i8 88, i64 16, i32 1), !dbg !10284 ret void285}286 287 288 289 290define i32 @Select(i32 %a, i32 %b, i1 %c) nounwind uwtable readnone sanitize_memory {291; CHECK-LABEL: @Select(292; CHECK-NEXT: entry:293; CHECK-NEXT: [[TMP0:%.*]] = load i1, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8, !dbg [[DBG2]]294; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_origin_tls, i64 16), align 4, !dbg [[DBG2]]295; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_tls, align 8, !dbg [[DBG2]]296; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4, !dbg [[DBG2]]297; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8, !dbg [[DBG2]]298; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_origin_tls, i64 8), align 4, !dbg [[DBG2]]299; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG2]]300; CHECK-NEXT: [[TMP6:%.*]] = select i1 [[C:%.*]], i32 [[TMP2]], i32 [[TMP4]], !dbg [[DBG2]]301; CHECK-NEXT: [[TMP7:%.*]] = xor i32 [[A:%.*]], [[B:%.*]], !dbg [[DBG2]]302; CHECK-NEXT: [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP2]], !dbg [[DBG2]]303; CHECK-NEXT: [[TMP9:%.*]] = or i32 [[TMP8]], [[TMP4]], !dbg [[DBG2]]304; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select i1 [[TMP0]], i32 [[TMP9]], i32 [[TMP6]], !dbg [[DBG2]]305; CHECK-NEXT: [[TMP10:%.*]] = select i1 [[C]], i32 [[TMP3]], i32 [[TMP5]], !dbg [[DBG2]]306; CHECK-NEXT: [[TMP11:%.*]] = select i1 [[TMP0]], i32 [[TMP1]], i32 [[TMP10]], !dbg [[DBG2]]307; CHECK-NEXT: [[COND:%.*]] = select i1 [[C]], i32 [[A]], i32 [[B]], !dbg [[DBG2]]308; CHECK-NEXT: store i32 [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 8309; CHECK-NEXT: store i32 [[TMP11]], ptr @__msan_retval_origin_tls, align 4310; CHECK-NEXT: ret i32 [[COND]]311;312entry:313 %cond = select i1 %c, i32 %a, i32 %b, !dbg !10314 ret i32 %cond315}316 317 318 319 320define <8 x i16> @SelectVector(<8 x i16> %a, <8 x i16> %b, <8 x i1> %c) nounwind uwtable readnone sanitize_memory {321; CHECK-LABEL: @SelectVector(322; CHECK-NEXT: entry:323; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i1>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8, !dbg [[DBG2]]324; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_origin_tls, i64 32), align 4, !dbg [[DBG2]]325; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8, !dbg [[DBG2]]326; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4, !dbg [[DBG2]]327; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8, !dbg [[DBG2]]328; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_origin_tls, i64 16), align 4, !dbg [[DBG2]]329; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG2]]330; CHECK-NEXT: [[TMP6:%.*]] = select <8 x i1> [[C:%.*]], <8 x i16> [[TMP2]], <8 x i16> [[TMP4]], !dbg [[DBG2]]331; CHECK-NEXT: [[TMP7:%.*]] = xor <8 x i16> [[A:%.*]], [[B:%.*]], !dbg [[DBG2]]332; CHECK-NEXT: [[TMP8:%.*]] = or <8 x i16> [[TMP7]], [[TMP2]], !dbg [[DBG2]]333; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i16> [[TMP8]], [[TMP4]], !dbg [[DBG2]]334; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP0]], <8 x i16> [[TMP9]], <8 x i16> [[TMP6]], !dbg [[DBG2]]335; CHECK-NEXT: [[TMP10:%.*]] = bitcast <8 x i1> [[C]] to i8, !dbg [[DBG2]]336; CHECK-NEXT: [[TMP11:%.*]] = icmp ne i8 [[TMP10]], 0, !dbg [[DBG2]]337; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x i1> [[TMP0]] to i8, !dbg [[DBG2]]338; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i8 [[TMP12]], 0, !dbg [[DBG2]]339; CHECK-NEXT: [[TMP14:%.*]] = select i1 [[TMP11]], i32 [[TMP3]], i32 [[TMP5]], !dbg [[DBG2]]340; CHECK-NEXT: [[TMP15:%.*]] = select i1 [[TMP13]], i32 [[TMP1]], i32 [[TMP14]], !dbg [[DBG2]]341; CHECK-NEXT: [[COND:%.*]] = select <8 x i1> [[C]], <8 x i16> [[A]], <8 x i16> [[B]], !dbg [[DBG2]]342; CHECK-NEXT: store <8 x i16> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 8343; CHECK-NEXT: store i32 [[TMP15]], ptr @__msan_retval_origin_tls, align 4344; CHECK-NEXT: ret <8 x i16> [[COND]]345;346entry:347 %cond = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b, !dbg !10348 ret <8 x i16> %cond349}350 351 352 353 354define ptr @IntToPtr(i64 %x) nounwind uwtable readnone sanitize_memory {355; CHECK-LABEL: @IntToPtr(356; CHECK-NEXT: entry:357; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__msan_param_tls, align 8, !dbg [[DBG2]]358; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4, !dbg [[DBG2]]359; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG2]]360; CHECK-NEXT: [[TMP2:%.*]] = inttoptr i64 [[X:%.*]] to ptr, !dbg [[DBG2]]361; CHECK-NEXT: store i64 [[TMP0]], ptr @__msan_retval_tls, align 8362; CHECK-NEXT: store i32 [[TMP1]], ptr @__msan_retval_origin_tls, align 4363; CHECK-NEXT: ret ptr [[TMP2]]364;365entry:366 %0 = inttoptr i64 %x to ptr, !dbg !10367 ret ptr %0368}369 370 371 372 373 374define i32 @Div(i32 %a, i32 %b) nounwind uwtable readnone sanitize_memory {375; CHECK-LABEL: @Div(376; CHECK-NEXT: entry:377; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8, !dbg [[DBG2]]378; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_origin_tls, i64 8), align 4, !dbg [[DBG2]]379; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_tls, align 8, !dbg [[DBG2]]380; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4, !dbg [[DBG2]]381; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG2]]382; CHECK-NEXT: call void @__msan_maybe_warning_4(i32 zeroext [[TMP0]], i32 zeroext [[TMP1]]), !dbg [[DBG2]]383; CHECK-NEXT: [[DIV:%.*]] = udiv i32 [[A:%.*]], [[B:%.*]], !dbg [[DBG2]]384; CHECK-NEXT: store i32 [[TMP2]], ptr @__msan_retval_tls, align 8385; CHECK-NEXT: store i32 [[TMP3]], ptr @__msan_retval_origin_tls, align 4386; CHECK-NEXT: ret i32 [[DIV]]387;388entry:389 %div = udiv i32 %a, %b, !dbg !10390 ret i32 %div391}392 393 394 395 396 397 398 399define i32 @ShadowLoadAlignmentLarge() nounwind uwtable sanitize_memory {400; CHECK-LABEL: @ShadowLoadAlignmentLarge(401; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG2]]402; CHECK-NEXT: [[Y:%.*]] = alloca i32, align 64, !dbg [[DBG2]]403; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[Y]] to i64, !dbg [[DBG2]]404; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080, !dbg [[DBG2]]405; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr, !dbg [[DBG2]]406; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[TMP2]], 17592186044416, !dbg [[DBG2]]407; CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], -4, !dbg [[DBG2]]408; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr, !dbg [[DBG2]]409; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 64 [[TMP3]], i8 -1, i64 4, i1 false), !dbg [[DBG2]]410; CHECK-NEXT: call void @__msan_set_alloca_origin_with_descr(ptr [[Y]], i64 4, ptr @[[GLOB0:[0-9]+]], ptr @[[GLOB1:[0-9]+]]), !dbg [[DBG2]]411; CHECK-NEXT: [[TMP8:%.*]] = load volatile i32, ptr [[Y]], align 64, !dbg [[DBG8]]412; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[Y]] to i64, !dbg [[DBG8]]413; CHECK-NEXT: [[TMP9:%.*]] = xor i64 [[TMP13]], 87960930222080, !dbg [[DBG8]]414; CHECK-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP9]] to ptr, !dbg [[DBG8]]415; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[TMP9]], 17592186044416, !dbg [[DBG8]]416; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr, !dbg [[DBG8]]417; CHECK-NEXT: [[_MSLD:%.*]] = load i32, ptr [[TMP10]], align 64, !dbg [[DBG8]]418; CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP12]], align 64, !dbg [[DBG8]]419; CHECK-NEXT: store i32 [[_MSLD]], ptr @__msan_retval_tls, align 8420; CHECK-NEXT: store i32 [[TMP14]], ptr @__msan_retval_origin_tls, align 4421; CHECK-NEXT: ret i32 [[TMP8]]422;423 %y = alloca i32, align 64, !dbg !10424 %1 = load volatile i32, ptr %y, align 64, !dbg !11425 ret i32 %1426}427 428 429 430define i32 @ExtractElement(<4 x i32> %vec, i32 %idx) sanitize_memory {431; CHECK-LABEL: @ExtractElement(432; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8, !dbg [[DBG2]]433; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_origin_tls, i64 16), align 4, !dbg [[DBG2]]434; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8, !dbg [[DBG2]]435; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4, !dbg [[DBG2]]436; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG2]]437; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <4 x i32> [[TMP3]], i32 [[IDX:%.*]], !dbg [[DBG2]]438; CHECK-NEXT: call void @__msan_maybe_warning_4(i32 zeroext [[TMP1]], i32 zeroext [[TMP2]]), !dbg [[DBG2]]439; CHECK-NEXT: [[X:%.*]] = extractelement <4 x i32> [[VEC:%.*]], i32 [[IDX]], !dbg [[DBG2]]440; CHECK-NEXT: store i32 [[_MSPROP]], ptr @__msan_retval_tls, align 8441; CHECK-NEXT: store i32 [[TMP4]], ptr @__msan_retval_origin_tls, align 4442; CHECK-NEXT: ret i32 [[X]]443;444 %x = extractelement <4 x i32> %vec, i32 %idx, !dbg !10445 ret i32 %x446}447 448 449define <4 x i32> @InsertElement(<4 x i32> %vec, i32 %idx, i32 %x) sanitize_memory {450; CHECK-LABEL: @InsertElement(451; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8, !dbg [[DBG2]]452; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_origin_tls, i64 16), align 4, !dbg [[DBG2]]453; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8, !dbg [[DBG2]]454; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4, !dbg [[DBG2]]455; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 8, !dbg [[DBG2]]456; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_origin_tls, i64 24), align 4, !dbg [[DBG2]]457; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG2]]458; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[TMP5]], i32 [[IDX:%.*]], !dbg [[DBG2]]459; CHECK-NEXT: [[TMP7:%.*]] = icmp ne i32 [[TMP5]], 0, !dbg [[DBG2]]460; CHECK-NEXT: [[TMP8:%.*]] = select i1 [[TMP7]], i32 [[TMP6]], i32 [[TMP4]], !dbg [[DBG2]]461; CHECK-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP1]], 0, !dbg [[DBG2]]462; CHECK-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], i32 [[TMP2]], i32 [[TMP8]], !dbg [[DBG2]]463; CHECK-NEXT: call void @__msan_maybe_warning_4(i32 zeroext [[TMP1]], i32 zeroext [[TMP2]]), !dbg [[DBG2]]464; CHECK-NEXT: [[VEC1:%.*]] = insertelement <4 x i32> [[VEC:%.*]], i32 [[X:%.*]], i32 [[IDX]], !dbg [[DBG2]]465; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8466; CHECK-NEXT: store i32 [[TMP10]], ptr @__msan_retval_origin_tls, align 4467; CHECK-NEXT: ret <4 x i32> [[VEC1]]468;469 %vec1 = insertelement <4 x i32> %vec, i32 %x, i32 %idx, !dbg !10470 ret <4 x i32> %vec1471}472 473 474define <4 x i32> @ShuffleVector(<4 x i32> %vec, <4 x i32> %vec1) sanitize_memory {475; CHECK-LABEL: @ShuffleVector(476; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8, !dbg [[DBG2]]477; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4, !dbg [[DBG2]]478; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8, !dbg [[DBG2]]479; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_origin_tls, i64 16), align 4, !dbg [[DBG2]]480; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG2]]481; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> [[TMP3]], <4 x i32> <i32 0, i32 4, i32 1, i32 5>, !dbg [[DBG2]]482; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP3]] to i128, !dbg [[DBG2]]483; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i128 [[TMP5]], 0, !dbg [[DBG2]]484; CHECK-NEXT: [[TMP7:%.*]] = select i1 [[TMP6]], i32 [[TMP4]], i32 [[TMP2]], !dbg [[DBG2]]485; CHECK-NEXT: [[VEC2:%.*]] = shufflevector <4 x i32> [[VEC:%.*]], <4 x i32> [[VEC1:%.*]], <4 x i32> <i32 0, i32 4, i32 1, i32 5>, !dbg [[DBG2]]486; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8487; CHECK-NEXT: store i32 [[TMP7]], ptr @__msan_retval_origin_tls, align 4488; CHECK-NEXT: ret <4 x i32> [[VEC2]]489;490 %vec2 = shufflevector <4 x i32> %vec, <4 x i32> %vec1, <4 x i32> <i32 0, i32 4, i32 1, i32 5>, !dbg !10491 ret <4 x i32> %vec2492}493 494 495 496%struct.__va_list_tag = type { i32, i32, ptr, ptr }497declare void @llvm.va_start(ptr) nounwind498 499define void @VAStart(i32 %x, ...) sanitize_memory {500; CHECK-LABEL: @VAStart(501; CHECK-NEXT: entry:502; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8, !dbg [[DBG2]]503; CHECK-NEXT: [[TMP1:%.*]] = add i64 176, [[TMP0]], !dbg [[DBG2]]504; CHECK-NEXT: [[TMP2:%.*]] = alloca i8, i64 [[TMP1]], align 8, !dbg [[DBG2]]505; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP2]], i8 0, i64 [[TMP1]], i1 false), !dbg [[DBG2]]506; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP1]], i64 800), !dbg [[DBG2]]507; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP2]], ptr align 8 @__msan_va_arg_tls, i64 [[TMP3]], i1 false), !dbg [[DBG2]]508; CHECK-NEXT: [[TMP4:%.*]] = alloca i8, i64 [[TMP1]], align 8, !dbg [[DBG2]]509; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP4]], ptr align 8 @__msan_va_arg_origin_tls, i64 [[TMP3]], i1 false), !dbg [[DBG2]]510; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr @__msan_param_tls, align 8, !dbg [[DBG2]]511; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4, !dbg [[DBG2]]512; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG2]]513; CHECK-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4, !dbg [[DBG2]]514; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[X_ADDR]] to i64, !dbg [[DBG2]]515; CHECK-NEXT: [[TMP8:%.*]] = xor i64 [[TMP7]], 87960930222080, !dbg [[DBG2]]516; CHECK-NEXT: [[TMP9:%.*]] = inttoptr i64 [[TMP8]] to ptr, !dbg [[DBG2]]517; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[TMP8]], 17592186044416, !dbg [[DBG2]]518; CHECK-NEXT: [[TMP11:%.*]] = and i64 [[TMP10]], -4, !dbg [[DBG2]]519; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr, !dbg [[DBG2]]520; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[TMP9]], i8 -1, i64 4, i1 false), !dbg [[DBG2]]521; CHECK-NEXT: call void @__msan_set_alloca_origin_with_descr(ptr [[X_ADDR]], i64 4, ptr @[[GLOB2:[0-9]+]], ptr @[[GLOB3:[0-9]+]]), !dbg [[DBG2]]522; CHECK-NEXT: [[VA:%.*]] = alloca [1 x %struct.__va_list_tag], align 16, !dbg [[DBG8]]523; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[VA]] to i64, !dbg [[DBG8]]524; CHECK-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], 87960930222080, !dbg [[DBG8]]525; CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP14]] to ptr, !dbg [[DBG8]]526; CHECK-NEXT: [[TMP16:%.*]] = add i64 [[TMP14]], 17592186044416, !dbg [[DBG8]]527; CHECK-NEXT: [[TMP17:%.*]] = and i64 [[TMP16]], -4, !dbg [[DBG8]]528; CHECK-NEXT: [[TMP18:%.*]] = inttoptr i64 [[TMP17]] to ptr, !dbg [[DBG8]]529; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[TMP15]], i8 -1, i64 24, i1 false), !dbg [[DBG8]]530; CHECK-NEXT: call void @__msan_set_alloca_origin_with_descr(ptr [[VA]], i64 24, ptr @[[GLOB4:[0-9]+]], ptr @[[GLOB5:[0-9]+]]), !dbg [[DBG8]]531; CHECK-NEXT: [[TMP19:%.*]] = ptrtoint ptr [[X_ADDR]] to i64, !dbg [[DBG9]]532; CHECK-NEXT: [[TMP20:%.*]] = xor i64 [[TMP19]], 87960930222080, !dbg [[DBG9]]533; CHECK-NEXT: [[TMP21:%.*]] = inttoptr i64 [[TMP20]] to ptr, !dbg [[DBG9]]534; CHECK-NEXT: [[TMP22:%.*]] = add i64 [[TMP20]], 17592186044416, !dbg [[DBG9]]535; CHECK-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP22]] to ptr, !dbg [[DBG9]]536; CHECK-NEXT: store i32 [[TMP5]], ptr [[TMP21]], align 4, !dbg [[DBG9]]537; CHECK-NEXT: call void @__msan_maybe_store_origin_4(i32 zeroext [[TMP5]], ptr [[X_ADDR]], i32 zeroext [[TMP6]]), !dbg [[DBG9]]538; CHECK-NEXT: store i32 [[X:%.*]], ptr [[X_ADDR]], align 4, !dbg [[DBG9]]539; CHECK-NEXT: [[TMP24:%.*]] = ptrtoint ptr [[VA]] to i64, !dbg [[DBG10:![0-9]+]]540; CHECK-NEXT: [[TMP25:%.*]] = xor i64 [[TMP24]], 87960930222080, !dbg [[DBG10]]541; CHECK-NEXT: [[TMP26:%.*]] = inttoptr i64 [[TMP25]] to ptr, !dbg [[DBG10]]542; CHECK-NEXT: [[TMP27:%.*]] = add i64 [[TMP25]], 17592186044416, !dbg [[DBG10]]543; CHECK-NEXT: [[TMP28:%.*]] = inttoptr i64 [[TMP27]] to ptr, !dbg [[DBG10]]544; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP26]], i8 0, i64 24, i1 false), !dbg [[DBG10]]545; CHECK-NEXT: call void @llvm.va_start.p0(ptr [[VA]]), !dbg [[DBG10]]546; CHECK-NEXT: [[TMP29:%.*]] = getelementptr i8, ptr [[VA]], i64 16, !dbg [[DBG10]]547; CHECK-NEXT: [[TMP30:%.*]] = load ptr, ptr [[TMP29]], align 8, !dbg [[DBG10]]548; CHECK-NEXT: [[TMP31:%.*]] = ptrtoint ptr [[TMP30]] to i64, !dbg [[DBG10]]549; CHECK-NEXT: [[TMP32:%.*]] = xor i64 [[TMP31]], 87960930222080, !dbg [[DBG10]]550; CHECK-NEXT: [[TMP33:%.*]] = inttoptr i64 [[TMP32]] to ptr, !dbg [[DBG10]]551; CHECK-NEXT: [[TMP34:%.*]] = add i64 [[TMP32]], 17592186044416, !dbg [[DBG10]]552; CHECK-NEXT: [[TMP35:%.*]] = inttoptr i64 [[TMP34]] to ptr, !dbg [[DBG10]]553; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[TMP33]], ptr align 16 [[TMP2]], i64 176, i1 false), !dbg [[DBG10]]554; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[TMP35]], ptr align 16 [[TMP4]], i64 176, i1 false), !dbg [[DBG10]]555; CHECK-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[VA]], i64 8, !dbg [[DBG10]]556; CHECK-NEXT: [[TMP37:%.*]] = load ptr, ptr [[TMP36]], align 8, !dbg [[DBG10]]557; CHECK-NEXT: [[TMP38:%.*]] = ptrtoint ptr [[TMP37]] to i64, !dbg [[DBG10]]558; CHECK-NEXT: [[TMP39:%.*]] = xor i64 [[TMP38]], 87960930222080, !dbg [[DBG10]]559; CHECK-NEXT: [[TMP40:%.*]] = inttoptr i64 [[TMP39]] to ptr, !dbg [[DBG10]]560; CHECK-NEXT: [[TMP41:%.*]] = add i64 [[TMP39]], 17592186044416, !dbg [[DBG10]]561; CHECK-NEXT: [[TMP42:%.*]] = inttoptr i64 [[TMP41]] to ptr, !dbg [[DBG10]]562; CHECK-NEXT: [[TMP43:%.*]] = getelementptr i8, ptr [[TMP2]], i32 176, !dbg [[DBG10]]563; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[TMP40]], ptr align 16 [[TMP43]], i64 [[TMP0]], i1 false), !dbg [[DBG10]]564; CHECK-NEXT: [[TMP44:%.*]] = getelementptr i8, ptr [[TMP4]], i32 176, !dbg [[DBG10]]565; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[TMP42]], ptr align 16 [[TMP44]], i64 [[TMP0]], i1 false), !dbg [[DBG10]]566; CHECK-NEXT: ret void567;568entry:569 %x.addr = alloca i32, align 4, !dbg !10570 %va = alloca [1 x %struct.__va_list_tag], align 16, !dbg !11571 store i32 %x, ptr %x.addr, align 4, !dbg !12572 call void @llvm.va_start(ptr %va), !dbg !15573 ret void574}575 576 577 578define i32 @NoSanitizeMemory(i32 %x) uwtable {579; CHECK-LABEL: @NoSanitizeMemory(580; CHECK-NEXT: entry:581; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG2]]582; CHECK-NEXT: [[TMP0:%.*]] = xor i32 [[X:%.*]], 0, !dbg [[DBG2]]583; CHECK-NEXT: [[TMP1:%.*]] = and i32 -1, [[TMP0]], !dbg [[DBG2]]584; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0, !dbg [[DBG2]]585; CHECK-NEXT: [[_MSPROP_ICMP:%.*]] = and i1 false, [[TMP2]], !dbg [[DBG2]]586; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[X]], 0, !dbg [[DBG2]]587; CHECK-NEXT: br i1 [[TOBOOL]], label [[IF_END:%.*]], label [[IF_THEN:%.*]], !dbg [[DBG8]]588; CHECK: if.then:589; CHECK-NEXT: tail call void @bar(), !dbg [[DBG9]]590; CHECK-NEXT: br label [[IF_END]]591; CHECK: if.end:592; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8593; CHECK-NEXT: store i32 0, ptr @__msan_retval_origin_tls, align 4594; CHECK-NEXT: ret i32 [[X]]595;596entry:597 %tobool = icmp eq i32 %x, 0, !dbg !10598 br i1 %tobool, label %if.end, label %if.then, !dbg !11599 600if.then: tail call void @bar(), !dbg !12601 br label %if.end602 603if.end: ret i32 %x604}605 606declare void @bar()607 608 609 610 611define i32 @NoSanitizeMemoryAlloca() {612; CHECK-LABEL: @NoSanitizeMemoryAlloca(613; CHECK-NEXT: entry:614; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG2]]615; CHECK-NEXT: [[P:%.*]] = alloca i32, align 4, !dbg [[DBG2]]616; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[P]] to i64, !dbg [[DBG2]]617; CHECK-NEXT: [[TMP1:%.*]] = xor i64 [[TMP0]], 87960930222080, !dbg [[DBG2]]618; CHECK-NEXT: [[TMP2:%.*]] = inttoptr i64 [[TMP1]] to ptr, !dbg [[DBG2]]619; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[TMP1]], 17592186044416, !dbg [[DBG2]]620; CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], -4, !dbg [[DBG2]]621; CHECK-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr, !dbg [[DBG2]]622; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[TMP2]], i8 0, i64 4, i1 false), !dbg [[DBG2]]623; CHECK-NEXT: store i64 0, ptr @__msan_param_tls, align 8, !dbg [[DBG8]]624; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8, !dbg [[DBG8]]625; CHECK-NEXT: [[X:%.*]] = call i32 @NoSanitizeMemoryAllocaHelper(ptr [[P]]), !dbg [[DBG8]]626; CHECK-NEXT: [[_MSRET:%.*]] = load i32, ptr @__msan_retval_tls, align 8627; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr @__msan_retval_origin_tls, align 4628; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8629; CHECK-NEXT: store i32 0, ptr @__msan_retval_origin_tls, align 4630; CHECK-NEXT: ret i32 [[X]]631;632entry:633 %p = alloca i32, align 4, !dbg !10634 %x = call i32 @NoSanitizeMemoryAllocaHelper(ptr %p), !dbg !11635 ret i32 %x636}637 638declare i32 @NoSanitizeMemoryAllocaHelper(ptr %p)639 640 641 642 643define i32 @NoSanitizeMemoryUndef() {644; CHECK-LABEL: @NoSanitizeMemoryUndef(645; CHECK-NEXT: entry:646; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG2]]647; CHECK-NEXT: store i32 0, ptr @__msan_param_tls, align 8, !dbg [[DBG2]]648; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8, !dbg [[DBG2]]649; CHECK-NEXT: [[X:%.*]] = call i32 @NoSanitizeMemoryUndefHelper(i32 undef), !dbg [[DBG2]]650; CHECK-NEXT: [[_MSRET:%.*]] = load i32, ptr @__msan_retval_tls, align 8651; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @__msan_retval_origin_tls, align 4652; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8653; CHECK-NEXT: store i32 0, ptr @__msan_retval_origin_tls, align 4654; CHECK-NEXT: ret i32 [[X]]655;656entry:657 %x = call i32 @NoSanitizeMemoryUndefHelper(i32 undef), !dbg !10658 ret i32 %x659}660 661declare i32 @NoSanitizeMemoryUndefHelper(i32 %x)662 663declare void @llvm.lifetime.start.p0(ptr nocapture %1)664declare void @llvm.lifetime.end.p0(ptr nocapture %1)665declare void @foo8(ptr nocapture)666 667 668define void @msan() sanitize_memory {669; CHECK-LABEL: @msan(670; CHECK-NEXT: entry:671; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG2]]672; CHECK-NEXT: [[TEXT:%.*]] = alloca i8, align 1, !dbg [[DBG2]]673; CHECK-NEXT: call void @llvm.lifetime.start.p0(ptr [[TEXT]]), !dbg [[DBG8]]674; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[TEXT]] to i64, !dbg [[DBG8]]675; CHECK-NEXT: [[TMP1:%.*]] = xor i64 [[TMP0]], 87960930222080, !dbg [[DBG8]]676; CHECK-NEXT: [[TMP2:%.*]] = inttoptr i64 [[TMP1]] to ptr, !dbg [[DBG8]]677; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[TMP1]], 17592186044416, !dbg [[DBG8]]678; CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], -4, !dbg [[DBG8]]679; CHECK-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr, !dbg [[DBG8]]680; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP2]], i8 -1, i64 1, i1 false), !dbg [[DBG8]]681; CHECK-NEXT: call void @__msan_set_alloca_origin_with_descr(ptr [[TEXT]], i64 1, ptr @[[GLOB6:[0-9]+]], ptr @[[GLOB7:[0-9]+]]), !dbg [[DBG8]]682; CHECK-NEXT: store i64 0, ptr @__msan_param_tls, align 8, !dbg [[DBG9]]683; CHECK-NEXT: call void @foo8(ptr [[TEXT]]), !dbg [[DBG9]]684; CHECK-NEXT: call void @llvm.lifetime.end.p0(ptr [[TEXT]]), !dbg [[DBG11:![0-9]+]]685; CHECK-NEXT: ret void, !dbg [[DBG12:![0-9]+]]686;687entry:688 %text = alloca i8, align 1, !dbg !10689 call void @llvm.lifetime.start.p0(ptr %text), !dbg !11690 call void @foo8(ptr %text), !dbg !12691 call void @llvm.lifetime.end.p0(ptr %text), !dbg !13692 ret void, !dbg !14693}694