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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt < %s -msan-check-access-address=0 -msan-track-origins=1 -S -passes='module(msan)' 2>&1 | FileCheck -allow-deprecated-dag-overlap --check-prefix=CHECK %s3 4target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"5target triple = "x86_64-unknown-linux-gnu"6 7declare i32 @llvm.vector.reduce.add(<3 x i32>)8declare i32 @llvm.vector.reduce.and(<3 x i32>)9declare i32 @llvm.vector.reduce.or(<3 x i32>)10 11define i32 @reduce_add() sanitize_memory {12; CHECK-LABEL: define i32 @reduce_add(13; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {14; CHECK-NEXT: call void @llvm.donothing()15; CHECK-NEXT: [[P:%.*]] = inttoptr i64 0 to ptr16; CHECK-NEXT: [[O:%.*]] = load <3 x i32>, ptr [[P]], align 1617; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i6418; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 8796093022208019; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr20; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[TMP2]], 1759218604441621; CHECK-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr22; CHECK-NEXT: [[_MSLD:%.*]] = load <3 x i32>, ptr [[TMP3]], align 1623; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 1624; CHECK-NEXT: [[TMP7:%.*]] = call i32 @llvm.vector.reduce.or.v3i32(<3 x i32> [[_MSLD]])25; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.vector.reduce.add.v3i32(<3 x i32> [[O]])26; CHECK-NEXT: store i32 [[TMP7]], ptr @__msan_retval_tls, align 827; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_origin_tls, align 428; CHECK-NEXT: ret i32 [[R]]29;30 %p = inttoptr i64 0 to ptr31 %o = load <3 x i32>, ptr %p32 %r = call i32 @llvm.vector.reduce.add(<3 x i32> %o)33 ret i32 %r34}35 36define i32 @reduce_and() sanitize_memory {37; CHECK-LABEL: define i32 @reduce_and(38; CHECK-SAME: ) #[[ATTR0]] {39; CHECK-NEXT: call void @llvm.donothing()40; CHECK-NEXT: [[P:%.*]] = inttoptr i64 0 to ptr41; CHECK-NEXT: [[O:%.*]] = load <3 x i32>, ptr [[P]], align 1642; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i6443; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 8796093022208044; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr45; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[TMP2]], 1759218604441646; CHECK-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr47; CHECK-NEXT: [[_MSLD:%.*]] = load <3 x i32>, ptr [[TMP3]], align 1648; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 1649; CHECK-NEXT: [[TMP7:%.*]] = or <3 x i32> [[O]], [[_MSLD]]50; CHECK-NEXT: [[TMP8:%.*]] = call i32 @llvm.vector.reduce.and.v3i32(<3 x i32> [[TMP7]])51; CHECK-NEXT: [[TMP9:%.*]] = call i32 @llvm.vector.reduce.or.v3i32(<3 x i32> [[_MSLD]])52; CHECK-NEXT: [[TMP10:%.*]] = and i32 [[TMP8]], [[TMP9]]53; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.vector.reduce.and.v3i32(<3 x i32> [[O]])54; CHECK-NEXT: store i32 [[TMP10]], ptr @__msan_retval_tls, align 855; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_origin_tls, align 456; CHECK-NEXT: ret i32 [[R]]57;58 %p = inttoptr i64 0 to ptr59 %o = load <3 x i32>, ptr %p60 %r = call i32 @llvm.vector.reduce.and(<3 x i32> %o)61 ret i32 %r62}63 64define i32 @reduce_or() sanitize_memory {65; CHECK-LABEL: define i32 @reduce_or(66; CHECK-SAME: ) #[[ATTR0]] {67; CHECK-NEXT: call void @llvm.donothing()68; CHECK-NEXT: [[P:%.*]] = inttoptr i64 0 to ptr69; CHECK-NEXT: [[O:%.*]] = load <3 x i32>, ptr [[P]], align 1670; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i6471; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 8796093022208072; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr73; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[TMP2]], 1759218604441674; CHECK-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr75; CHECK-NEXT: [[_MSLD:%.*]] = load <3 x i32>, ptr [[TMP3]], align 1676; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 1677; CHECK-NEXT: [[TMP7:%.*]] = xor <3 x i32> [[O]], splat (i32 -1)78; CHECK-NEXT: [[TMP8:%.*]] = or <3 x i32> [[TMP7]], [[_MSLD]]79; CHECK-NEXT: [[TMP9:%.*]] = call i32 @llvm.vector.reduce.and.v3i32(<3 x i32> [[TMP8]])80; CHECK-NEXT: [[TMP10:%.*]] = call i32 @llvm.vector.reduce.or.v3i32(<3 x i32> [[_MSLD]])81; CHECK-NEXT: [[TMP11:%.*]] = and i32 [[TMP9]], [[TMP10]]82; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.vector.reduce.or.v3i32(<3 x i32> [[O]])83; CHECK-NEXT: store i32 [[TMP11]], ptr @__msan_retval_tls, align 884; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_origin_tls, align 485; CHECK-NEXT: ret i32 [[R]]86;87 %p = inttoptr i64 0 to ptr88 %o = load <3 x i32>, ptr %p89 %r = call i32 @llvm.vector.reduce.or(<3 x i32> %o)90 ret i32 %r91}92