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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -msan-check-access-address=0 -S -passes=msan 2>&1 | FileCheck %s --implicit-check-not="call void @__msan_warning"3; RUN: opt < %s -msan-check-access-address=1 -S -passes=msan 2>&1 | FileCheck %s --check-prefixes=ADDR --implicit-check-not="call void @__msan_warning"4; RUN: opt < %s -msan-check-access-address=0 -msan-track-origins=1 -S -passes=msan 2>&1 | FileCheck %s --check-prefixes=ORIGINS --implicit-check-not="call void @__msan_warning"5 6target triple = "x86_64-unknown-linux-gnu"7target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"8 9define void @load.v1i32(ptr %p) sanitize_memory {10; CHECK-LABEL: @load.v1i32(11; CHECK-NEXT: call void @llvm.donothing()12; CHECK-NEXT: [[TMP1:%.*]] = load <1 x i32>, ptr [[P:%.*]], align 413; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[P]] to i6414; CHECK-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 8796093022208015; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr16; CHECK-NEXT: [[_MSLD:%.*]] = load <1 x i32>, ptr [[TMP4]], align 417; CHECK-NEXT: ret void18;19; ADDR-LABEL: @load.v1i32(20; ADDR-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 821; ADDR-NEXT: call void @llvm.donothing()22; ADDR-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 023; ADDR-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1:![0-9]+]]24; ADDR: 2:25; ADDR-NEXT: call void @__msan_warning_noreturn() #[[ATTR3:[0-9]+]]26; ADDR-NEXT: unreachable27; ADDR: 3:28; ADDR-NEXT: [[TMP4:%.*]] = load <1 x i32>, ptr [[P:%.*]], align 429; ADDR-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[P]] to i6430; ADDR-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 8796093022208031; ADDR-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr32; ADDR-NEXT: [[_MSLD:%.*]] = load <1 x i32>, ptr [[TMP7]], align 433; ADDR-NEXT: ret void34;35; ORIGINS-LABEL: @load.v1i32(36; ORIGINS-NEXT: call void @llvm.donothing()37; ORIGINS-NEXT: [[TMP1:%.*]] = load <1 x i32>, ptr [[P:%.*]], align 438; ORIGINS-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[P]] to i6439; ORIGINS-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 8796093022208040; ORIGINS-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr41; ORIGINS-NEXT: [[TMP5:%.*]] = add i64 [[TMP3]], 1759218604441642; ORIGINS-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr43; ORIGINS-NEXT: [[_MSLD:%.*]] = load <1 x i32>, ptr [[TMP4]], align 444; ORIGINS-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 445; ORIGINS-NEXT: ret void46;47 load <1 x i32>, ptr %p48 ret void49}50 51define void @load.v2i32(ptr %p) sanitize_memory {52; CHECK-LABEL: @load.v2i32(53; CHECK-NEXT: call void @llvm.donothing()54; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[P:%.*]], align 855; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[P]] to i6456; CHECK-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 8796093022208057; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr58; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP4]], align 859; CHECK-NEXT: ret void60;61; ADDR-LABEL: @load.v2i32(62; ADDR-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 863; ADDR-NEXT: call void @llvm.donothing()64; ADDR-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 065; ADDR-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]66; ADDR: 2:67; ADDR-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]68; ADDR-NEXT: unreachable69; ADDR: 3:70; ADDR-NEXT: [[TMP4:%.*]] = load <2 x i32>, ptr [[P:%.*]], align 871; ADDR-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[P]] to i6472; ADDR-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 8796093022208073; ADDR-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr74; ADDR-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 875; ADDR-NEXT: ret void76;77; ORIGINS-LABEL: @load.v2i32(78; ORIGINS-NEXT: call void @llvm.donothing()79; ORIGINS-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[P:%.*]], align 880; ORIGINS-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[P]] to i6481; ORIGINS-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 8796093022208082; ORIGINS-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr83; ORIGINS-NEXT: [[TMP5:%.*]] = add i64 [[TMP3]], 1759218604441684; ORIGINS-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr85; ORIGINS-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP4]], align 886; ORIGINS-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 887; ORIGINS-NEXT: ret void88;89 load <2 x i32>, ptr %p90 ret void91}92 93define void @load.v4i32(ptr %p) sanitize_memory {94; CHECK-LABEL: @load.v4i32(95; CHECK-NEXT: call void @llvm.donothing()96; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[P:%.*]], align 1697; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[P]] to i6498; CHECK-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 8796093022208099; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr100; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP4]], align 16101; CHECK-NEXT: ret void102;103; ADDR-LABEL: @load.v4i32(104; ADDR-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8105; ADDR-NEXT: call void @llvm.donothing()106; ADDR-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0107; ADDR-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]108; ADDR: 2:109; ADDR-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]110; ADDR-NEXT: unreachable111; ADDR: 3:112; ADDR-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr [[P:%.*]], align 16113; ADDR-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[P]] to i64114; ADDR-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 87960930222080115; ADDR-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr116; ADDR-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 16117; ADDR-NEXT: ret void118;119; ORIGINS-LABEL: @load.v4i32(120; ORIGINS-NEXT: call void @llvm.donothing()121; ORIGINS-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[P:%.*]], align 16122; ORIGINS-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[P]] to i64123; ORIGINS-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080124; ORIGINS-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr125; ORIGINS-NEXT: [[TMP5:%.*]] = add i64 [[TMP3]], 17592186044416126; ORIGINS-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr127; ORIGINS-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP4]], align 16128; ORIGINS-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 16129; ORIGINS-NEXT: ret void130;131 load <4 x i32>, ptr %p132 ret void133}134 135define void @load.v8i32(ptr %p) sanitize_memory {136; CHECK-LABEL: @load.v8i32(137; CHECK-NEXT: call void @llvm.donothing()138; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr [[P:%.*]], align 32139; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[P]] to i64140; CHECK-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080141; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr142; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i32>, ptr [[TMP4]], align 32143; CHECK-NEXT: ret void144;145; ADDR-LABEL: @load.v8i32(146; ADDR-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8147; ADDR-NEXT: call void @llvm.donothing()148; ADDR-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0149; ADDR-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]150; ADDR: 2:151; ADDR-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]152; ADDR-NEXT: unreachable153; ADDR: 3:154; ADDR-NEXT: [[TMP4:%.*]] = load <8 x i32>, ptr [[P:%.*]], align 32155; ADDR-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[P]] to i64156; ADDR-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 87960930222080157; ADDR-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr158; ADDR-NEXT: [[_MSLD:%.*]] = load <8 x i32>, ptr [[TMP7]], align 32159; ADDR-NEXT: ret void160;161; ORIGINS-LABEL: @load.v8i32(162; ORIGINS-NEXT: call void @llvm.donothing()163; ORIGINS-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr [[P:%.*]], align 32164; ORIGINS-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[P]] to i64165; ORIGINS-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080166; ORIGINS-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr167; ORIGINS-NEXT: [[TMP5:%.*]] = add i64 [[TMP3]], 17592186044416168; ORIGINS-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr169; ORIGINS-NEXT: [[_MSLD:%.*]] = load <8 x i32>, ptr [[TMP4]], align 32170; ORIGINS-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 32171; ORIGINS-NEXT: ret void172;173 load <8 x i32>, ptr %p174 ret void175}176 177define void @load.v16i32(ptr %p) sanitize_memory {178; CHECK-LABEL: @load.v16i32(179; CHECK-NEXT: call void @llvm.donothing()180; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr [[P:%.*]], align 64181; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[P]] to i64182; CHECK-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080183; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr184; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i32>, ptr [[TMP4]], align 64185; CHECK-NEXT: ret void186;187; ADDR-LABEL: @load.v16i32(188; ADDR-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8189; ADDR-NEXT: call void @llvm.donothing()190; ADDR-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0191; ADDR-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]192; ADDR: 2:193; ADDR-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]194; ADDR-NEXT: unreachable195; ADDR: 3:196; ADDR-NEXT: [[TMP4:%.*]] = load <16 x i32>, ptr [[P:%.*]], align 64197; ADDR-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[P]] to i64198; ADDR-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 87960930222080199; ADDR-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr200; ADDR-NEXT: [[_MSLD:%.*]] = load <16 x i32>, ptr [[TMP7]], align 64201; ADDR-NEXT: ret void202;203; ORIGINS-LABEL: @load.v16i32(204; ORIGINS-NEXT: call void @llvm.donothing()205; ORIGINS-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr [[P:%.*]], align 64206; ORIGINS-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[P]] to i64207; ORIGINS-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080208; ORIGINS-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr209; ORIGINS-NEXT: [[TMP5:%.*]] = add i64 [[TMP3]], 17592186044416210; ORIGINS-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr211; ORIGINS-NEXT: [[_MSLD:%.*]] = load <16 x i32>, ptr [[TMP4]], align 64212; ORIGINS-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 64213; ORIGINS-NEXT: ret void214;215 load <16 x i32>, ptr %p216 ret void217}218 219 220define void @store.v1i32(ptr %p) sanitize_memory {221; CHECK-LABEL: @store.v1i32(222; CHECK-NEXT: call void @llvm.donothing()223; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64224; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080225; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr226; CHECK-NEXT: store <1 x i32> zeroinitializer, ptr [[TMP3]], align 4227; CHECK-NEXT: store <1 x i32> zeroinitializer, ptr [[P]], align 4228; CHECK-NEXT: ret void229;230; ADDR-LABEL: @store.v1i32(231; ADDR-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8232; ADDR-NEXT: call void @llvm.donothing()233; ADDR-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0234; ADDR-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]235; ADDR: 2:236; ADDR-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]237; ADDR-NEXT: unreachable238; ADDR: 3:239; ADDR-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64240; ADDR-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 87960930222080241; ADDR-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr242; ADDR-NEXT: store <1 x i32> zeroinitializer, ptr [[TMP6]], align 4243; ADDR-NEXT: store <1 x i32> zeroinitializer, ptr [[P]], align 4244; ADDR-NEXT: ret void245;246; ORIGINS-LABEL: @store.v1i32(247; ORIGINS-NEXT: call void @llvm.donothing()248; ORIGINS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64249; ORIGINS-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080250; ORIGINS-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr251; ORIGINS-NEXT: [[TMP4:%.*]] = add i64 [[TMP2]], 17592186044416252; ORIGINS-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr253; ORIGINS-NEXT: store <1 x i32> zeroinitializer, ptr [[TMP3]], align 4254; ORIGINS-NEXT: store <1 x i32> zeroinitializer, ptr [[P]], align 4255; ORIGINS-NEXT: ret void256;257 store <1 x i32> zeroinitializer, ptr %p258 ret void259}260 261define void @store.v2i32(ptr %p) sanitize_memory {262; CHECK-LABEL: @store.v2i32(263; CHECK-NEXT: call void @llvm.donothing()264; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64265; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080266; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr267; CHECK-NEXT: store <2 x i32> zeroinitializer, ptr [[TMP3]], align 8268; CHECK-NEXT: store <2 x i32> zeroinitializer, ptr [[P]], align 8269; CHECK-NEXT: ret void270;271; ADDR-LABEL: @store.v2i32(272; ADDR-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8273; ADDR-NEXT: call void @llvm.donothing()274; ADDR-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0275; ADDR-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]276; ADDR: 2:277; ADDR-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]278; ADDR-NEXT: unreachable279; ADDR: 3:280; ADDR-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64281; ADDR-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 87960930222080282; ADDR-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr283; ADDR-NEXT: store <2 x i32> zeroinitializer, ptr [[TMP6]], align 8284; ADDR-NEXT: store <2 x i32> zeroinitializer, ptr [[P]], align 8285; ADDR-NEXT: ret void286;287; ORIGINS-LABEL: @store.v2i32(288; ORIGINS-NEXT: call void @llvm.donothing()289; ORIGINS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64290; ORIGINS-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080291; ORIGINS-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr292; ORIGINS-NEXT: [[TMP4:%.*]] = add i64 [[TMP2]], 17592186044416293; ORIGINS-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr294; ORIGINS-NEXT: store <2 x i32> zeroinitializer, ptr [[TMP3]], align 8295; ORIGINS-NEXT: store <2 x i32> zeroinitializer, ptr [[P]], align 8296; ORIGINS-NEXT: ret void297;298 store <2 x i32> zeroinitializer, ptr %p299 ret void300}301 302define void @store.v4i32(ptr %p) sanitize_memory {303; CHECK-LABEL: @store.v4i32(304; CHECK-NEXT: call void @llvm.donothing()305; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64306; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080307; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr308; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr [[TMP3]], align 16309; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr [[P]], align 16310; CHECK-NEXT: ret void311;312; ADDR-LABEL: @store.v4i32(313; ADDR-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8314; ADDR-NEXT: call void @llvm.donothing()315; ADDR-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0316; ADDR-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]317; ADDR: 2:318; ADDR-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]319; ADDR-NEXT: unreachable320; ADDR: 3:321; ADDR-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64322; ADDR-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 87960930222080323; ADDR-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr324; ADDR-NEXT: store <4 x i32> zeroinitializer, ptr [[TMP6]], align 16325; ADDR-NEXT: store <4 x i32> zeroinitializer, ptr [[P]], align 16326; ADDR-NEXT: ret void327;328; ORIGINS-LABEL: @store.v4i32(329; ORIGINS-NEXT: call void @llvm.donothing()330; ORIGINS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64331; ORIGINS-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080332; ORIGINS-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr333; ORIGINS-NEXT: [[TMP4:%.*]] = add i64 [[TMP2]], 17592186044416334; ORIGINS-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr335; ORIGINS-NEXT: store <4 x i32> zeroinitializer, ptr [[TMP3]], align 16336; ORIGINS-NEXT: store <4 x i32> zeroinitializer, ptr [[P]], align 16337; ORIGINS-NEXT: ret void338;339 store <4 x i32> zeroinitializer, ptr %p340 ret void341}342 343define void @store.v8i32(ptr %p) sanitize_memory {344; CHECK-LABEL: @store.v8i32(345; CHECK-NEXT: call void @llvm.donothing()346; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64347; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080348; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr349; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr [[TMP3]], align 32350; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr [[P]], align 32351; CHECK-NEXT: ret void352;353; ADDR-LABEL: @store.v8i32(354; ADDR-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8355; ADDR-NEXT: call void @llvm.donothing()356; ADDR-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0357; ADDR-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]358; ADDR: 2:359; ADDR-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]360; ADDR-NEXT: unreachable361; ADDR: 3:362; ADDR-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64363; ADDR-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 87960930222080364; ADDR-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr365; ADDR-NEXT: store <8 x i32> zeroinitializer, ptr [[TMP6]], align 32366; ADDR-NEXT: store <8 x i32> zeroinitializer, ptr [[P]], align 32367; ADDR-NEXT: ret void368;369; ORIGINS-LABEL: @store.v8i32(370; ORIGINS-NEXT: call void @llvm.donothing()371; ORIGINS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64372; ORIGINS-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080373; ORIGINS-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr374; ORIGINS-NEXT: [[TMP4:%.*]] = add i64 [[TMP2]], 17592186044416375; ORIGINS-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr376; ORIGINS-NEXT: store <8 x i32> zeroinitializer, ptr [[TMP3]], align 32377; ORIGINS-NEXT: store <8 x i32> zeroinitializer, ptr [[P]], align 32378; ORIGINS-NEXT: ret void379;380 store <8 x i32> zeroinitializer, ptr %p381 ret void382}383 384define void @store.v16i32(ptr %p) sanitize_memory {385; CHECK-LABEL: @store.v16i32(386; CHECK-NEXT: call void @llvm.donothing()387; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64388; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080389; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr390; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr [[TMP3]], align 64391; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr [[P]], align 64392; CHECK-NEXT: ret void393;394; ADDR-LABEL: @store.v16i32(395; ADDR-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8396; ADDR-NEXT: call void @llvm.donothing()397; ADDR-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0398; ADDR-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]399; ADDR: 2:400; ADDR-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]401; ADDR-NEXT: unreachable402; ADDR: 3:403; ADDR-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64404; ADDR-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 87960930222080405; ADDR-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr406; ADDR-NEXT: store <16 x i32> zeroinitializer, ptr [[TMP6]], align 64407; ADDR-NEXT: store <16 x i32> zeroinitializer, ptr [[P]], align 64408; ADDR-NEXT: ret void409;410; ORIGINS-LABEL: @store.v16i32(411; ORIGINS-NEXT: call void @llvm.donothing()412; ORIGINS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64413; ORIGINS-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080414; ORIGINS-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr415; ORIGINS-NEXT: [[TMP4:%.*]] = add i64 [[TMP2]], 17592186044416416; ORIGINS-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr417; ORIGINS-NEXT: store <16 x i32> zeroinitializer, ptr [[TMP3]], align 64418; ORIGINS-NEXT: store <16 x i32> zeroinitializer, ptr [[P]], align 64419; ORIGINS-NEXT: ret void420;421 store <16 x i32> zeroinitializer, ptr %p422 ret void423}424 425define void @load.nxv1i32(ptr %p) sanitize_memory {426; CHECK-LABEL: @load.nxv1i32(427; CHECK-NEXT: call void @llvm.donothing()428; CHECK-NEXT: [[TMP1:%.*]] = load <vscale x 1 x i32>, ptr [[P:%.*]], align 4429; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[P]] to i64430; CHECK-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080431; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr432; CHECK-NEXT: [[_MSLD:%.*]] = load <vscale x 1 x i32>, ptr [[TMP4]], align 4433; CHECK-NEXT: ret void434;435; ADDR-LABEL: @load.nxv1i32(436; ADDR-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8437; ADDR-NEXT: call void @llvm.donothing()438; ADDR-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0439; ADDR-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]440; ADDR: 2:441; ADDR-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]442; ADDR-NEXT: unreachable443; ADDR: 3:444; ADDR-NEXT: [[TMP4:%.*]] = load <vscale x 1 x i32>, ptr [[P:%.*]], align 4445; ADDR-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[P]] to i64446; ADDR-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 87960930222080447; ADDR-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr448; ADDR-NEXT: [[_MSLD:%.*]] = load <vscale x 1 x i32>, ptr [[TMP7]], align 4449; ADDR-NEXT: ret void450;451; ORIGINS-LABEL: @load.nxv1i32(452; ORIGINS-NEXT: call void @llvm.donothing()453; ORIGINS-NEXT: [[TMP1:%.*]] = load <vscale x 1 x i32>, ptr [[P:%.*]], align 4454; ORIGINS-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[P]] to i64455; ORIGINS-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080456; ORIGINS-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr457; ORIGINS-NEXT: [[TMP5:%.*]] = add i64 [[TMP3]], 17592186044416458; ORIGINS-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr459; ORIGINS-NEXT: [[_MSLD:%.*]] = load <vscale x 1 x i32>, ptr [[TMP4]], align 4460; ORIGINS-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4461; ORIGINS-NEXT: ret void462;463 load <vscale x 1 x i32>, ptr %p464 ret void465}466 467define void @load.nxv2i32(ptr %p) sanitize_memory {468; CHECK-LABEL: @load.nxv2i32(469; CHECK-NEXT: call void @llvm.donothing()470; CHECK-NEXT: [[TMP1:%.*]] = load <vscale x 2 x i32>, ptr [[P:%.*]], align 8471; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[P]] to i64472; CHECK-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080473; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr474; CHECK-NEXT: [[_MSLD:%.*]] = load <vscale x 2 x i32>, ptr [[TMP4]], align 8475; CHECK-NEXT: ret void476;477; ADDR-LABEL: @load.nxv2i32(478; ADDR-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8479; ADDR-NEXT: call void @llvm.donothing()480; ADDR-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0481; ADDR-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]482; ADDR: 2:483; ADDR-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]484; ADDR-NEXT: unreachable485; ADDR: 3:486; ADDR-NEXT: [[TMP4:%.*]] = load <vscale x 2 x i32>, ptr [[P:%.*]], align 8487; ADDR-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[P]] to i64488; ADDR-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 87960930222080489; ADDR-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr490; ADDR-NEXT: [[_MSLD:%.*]] = load <vscale x 2 x i32>, ptr [[TMP7]], align 8491; ADDR-NEXT: ret void492;493; ORIGINS-LABEL: @load.nxv2i32(494; ORIGINS-NEXT: call void @llvm.donothing()495; ORIGINS-NEXT: [[TMP1:%.*]] = load <vscale x 2 x i32>, ptr [[P:%.*]], align 8496; ORIGINS-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[P]] to i64497; ORIGINS-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080498; ORIGINS-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr499; ORIGINS-NEXT: [[TMP5:%.*]] = add i64 [[TMP3]], 17592186044416500; ORIGINS-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr501; ORIGINS-NEXT: [[_MSLD:%.*]] = load <vscale x 2 x i32>, ptr [[TMP4]], align 8502; ORIGINS-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 8503; ORIGINS-NEXT: ret void504;505 load <vscale x 2 x i32>, ptr %p506 ret void507}508 509define void @load.nxv4i32(ptr %p) sanitize_memory {510; CHECK-LABEL: @load.nxv4i32(511; CHECK-NEXT: call void @llvm.donothing()512; CHECK-NEXT: [[TMP1:%.*]] = load <vscale x 4 x i32>, ptr [[P:%.*]], align 16513; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[P]] to i64514; CHECK-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080515; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr516; CHECK-NEXT: [[_MSLD:%.*]] = load <vscale x 4 x i32>, ptr [[TMP4]], align 16517; CHECK-NEXT: ret void518;519; ADDR-LABEL: @load.nxv4i32(520; ADDR-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8521; ADDR-NEXT: call void @llvm.donothing()522; ADDR-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0523; ADDR-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]524; ADDR: 2:525; ADDR-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]526; ADDR-NEXT: unreachable527; ADDR: 3:528; ADDR-NEXT: [[TMP4:%.*]] = load <vscale x 4 x i32>, ptr [[P:%.*]], align 16529; ADDR-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[P]] to i64530; ADDR-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 87960930222080531; ADDR-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr532; ADDR-NEXT: [[_MSLD:%.*]] = load <vscale x 4 x i32>, ptr [[TMP7]], align 16533; ADDR-NEXT: ret void534;535; ORIGINS-LABEL: @load.nxv4i32(536; ORIGINS-NEXT: call void @llvm.donothing()537; ORIGINS-NEXT: [[TMP1:%.*]] = load <vscale x 4 x i32>, ptr [[P:%.*]], align 16538; ORIGINS-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[P]] to i64539; ORIGINS-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080540; ORIGINS-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr541; ORIGINS-NEXT: [[TMP5:%.*]] = add i64 [[TMP3]], 17592186044416542; ORIGINS-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr543; ORIGINS-NEXT: [[_MSLD:%.*]] = load <vscale x 4 x i32>, ptr [[TMP4]], align 16544; ORIGINS-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 16545; ORIGINS-NEXT: ret void546;547 load <vscale x 4 x i32>, ptr %p548 ret void549}550 551define void @load.nxv8i32(ptr %p) sanitize_memory {552; CHECK-LABEL: @load.nxv8i32(553; CHECK-NEXT: call void @llvm.donothing()554; CHECK-NEXT: [[TMP1:%.*]] = load <vscale x 8 x i32>, ptr [[P:%.*]], align 32555; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[P]] to i64556; CHECK-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080557; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr558; CHECK-NEXT: [[_MSLD:%.*]] = load <vscale x 8 x i32>, ptr [[TMP4]], align 32559; CHECK-NEXT: ret void560;561; ADDR-LABEL: @load.nxv8i32(562; ADDR-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8563; ADDR-NEXT: call void @llvm.donothing()564; ADDR-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0565; ADDR-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]566; ADDR: 2:567; ADDR-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]568; ADDR-NEXT: unreachable569; ADDR: 3:570; ADDR-NEXT: [[TMP4:%.*]] = load <vscale x 8 x i32>, ptr [[P:%.*]], align 32571; ADDR-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[P]] to i64572; ADDR-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 87960930222080573; ADDR-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr574; ADDR-NEXT: [[_MSLD:%.*]] = load <vscale x 8 x i32>, ptr [[TMP7]], align 32575; ADDR-NEXT: ret void576;577; ORIGINS-LABEL: @load.nxv8i32(578; ORIGINS-NEXT: call void @llvm.donothing()579; ORIGINS-NEXT: [[TMP1:%.*]] = load <vscale x 8 x i32>, ptr [[P:%.*]], align 32580; ORIGINS-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[P]] to i64581; ORIGINS-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080582; ORIGINS-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr583; ORIGINS-NEXT: [[TMP5:%.*]] = add i64 [[TMP3]], 17592186044416584; ORIGINS-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr585; ORIGINS-NEXT: [[_MSLD:%.*]] = load <vscale x 8 x i32>, ptr [[TMP4]], align 32586; ORIGINS-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 32587; ORIGINS-NEXT: ret void588;589 load <vscale x 8 x i32>, ptr %p590 ret void591}592 593define void @load.nxv16i32(ptr %p) sanitize_memory {594; CHECK-LABEL: @load.nxv16i32(595; CHECK-NEXT: call void @llvm.donothing()596; CHECK-NEXT: [[TMP1:%.*]] = load <vscale x 16 x i32>, ptr [[P:%.*]], align 64597; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[P]] to i64598; CHECK-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080599; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr600; CHECK-NEXT: [[_MSLD:%.*]] = load <vscale x 16 x i32>, ptr [[TMP4]], align 64601; CHECK-NEXT: ret void602;603; ADDR-LABEL: @load.nxv16i32(604; ADDR-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8605; ADDR-NEXT: call void @llvm.donothing()606; ADDR-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0607; ADDR-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]608; ADDR: 2:609; ADDR-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]610; ADDR-NEXT: unreachable611; ADDR: 3:612; ADDR-NEXT: [[TMP4:%.*]] = load <vscale x 16 x i32>, ptr [[P:%.*]], align 64613; ADDR-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[P]] to i64614; ADDR-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 87960930222080615; ADDR-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr616; ADDR-NEXT: [[_MSLD:%.*]] = load <vscale x 16 x i32>, ptr [[TMP7]], align 64617; ADDR-NEXT: ret void618;619; ORIGINS-LABEL: @load.nxv16i32(620; ORIGINS-NEXT: call void @llvm.donothing()621; ORIGINS-NEXT: [[TMP1:%.*]] = load <vscale x 16 x i32>, ptr [[P:%.*]], align 64622; ORIGINS-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[P]] to i64623; ORIGINS-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080624; ORIGINS-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr625; ORIGINS-NEXT: [[TMP5:%.*]] = add i64 [[TMP3]], 17592186044416626; ORIGINS-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr627; ORIGINS-NEXT: [[_MSLD:%.*]] = load <vscale x 16 x i32>, ptr [[TMP4]], align 64628; ORIGINS-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 64629; ORIGINS-NEXT: ret void630;631 load <vscale x 16 x i32>, ptr %p632 ret void633}634 635 636define void @store.nxv1i32(ptr %p) sanitize_memory {637; CHECK-LABEL: @store.nxv1i32(638; CHECK-NEXT: call void @llvm.donothing()639; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64640; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080641; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr642; CHECK-NEXT: store <vscale x 1 x i32> zeroinitializer, ptr [[TMP3]], align 4643; CHECK-NEXT: store <vscale x 1 x i32> zeroinitializer, ptr [[P]], align 4644; CHECK-NEXT: ret void645;646; ADDR-LABEL: @store.nxv1i32(647; ADDR-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8648; ADDR-NEXT: call void @llvm.donothing()649; ADDR-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0650; ADDR-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]651; ADDR: 2:652; ADDR-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]653; ADDR-NEXT: unreachable654; ADDR: 3:655; ADDR-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64656; ADDR-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 87960930222080657; ADDR-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr658; ADDR-NEXT: store <vscale x 1 x i32> zeroinitializer, ptr [[TMP6]], align 4659; ADDR-NEXT: store <vscale x 1 x i32> zeroinitializer, ptr [[P]], align 4660; ADDR-NEXT: ret void661;662; ORIGINS-LABEL: @store.nxv1i32(663; ORIGINS-NEXT: call void @llvm.donothing()664; ORIGINS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64665; ORIGINS-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080666; ORIGINS-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr667; ORIGINS-NEXT: [[TMP4:%.*]] = add i64 [[TMP2]], 17592186044416668; ORIGINS-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr669; ORIGINS-NEXT: store <vscale x 1 x i32> zeroinitializer, ptr [[TMP3]], align 4670; ORIGINS-NEXT: [[TMP6:%.*]] = call i32 @llvm.vector.reduce.or.nxv1i32(<vscale x 1 x i32> zeroinitializer)671; ORIGINS-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP6]], 0672; ORIGINS-NEXT: br i1 [[_MSCMP]], label [[TMP7:%.*]], label [[TMP13:%.*]], !prof [[PROF1:![0-9]+]]673; ORIGINS: 7:674; ORIGINS-NEXT: [[TMP8:%.*]] = call i64 @llvm.vscale.i64()675; ORIGINS-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 4676; ORIGINS-NEXT: [[TMP10:%.*]] = add i64 [[TMP9]], 3677; ORIGINS-NEXT: [[TMP11:%.*]] = udiv i64 [[TMP10]], 4678; ORIGINS-NEXT: br label [[DOTSPLIT:%.*]]679; ORIGINS: .split:680; ORIGINS-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP7]] ], [ [[IV_NEXT:%.*]], [[DOTSPLIT]] ]681; ORIGINS-NEXT: [[TMP12:%.*]] = getelementptr i32, ptr [[TMP5]], i64 [[IV]]682; ORIGINS-NEXT: store i32 0, ptr [[TMP12]], align 4683; ORIGINS-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1684; ORIGINS-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP11]]685; ORIGINS-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]686; ORIGINS: .split.split:687; ORIGINS-NEXT: br label [[TMP13]]688; ORIGINS: 13:689; ORIGINS-NEXT: store <vscale x 1 x i32> zeroinitializer, ptr [[P]], align 4690; ORIGINS-NEXT: ret void691;692 store <vscale x 1 x i32> zeroinitializer, ptr %p693 ret void694}695 696define void @store.nxv2i32(ptr %p) sanitize_memory {697; CHECK-LABEL: @store.nxv2i32(698; CHECK-NEXT: call void @llvm.donothing()699; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64700; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080701; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr702; CHECK-NEXT: store <vscale x 2 x i32> zeroinitializer, ptr [[TMP3]], align 8703; CHECK-NEXT: store <vscale x 2 x i32> zeroinitializer, ptr [[P]], align 8704; CHECK-NEXT: ret void705;706; ADDR-LABEL: @store.nxv2i32(707; ADDR-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8708; ADDR-NEXT: call void @llvm.donothing()709; ADDR-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0710; ADDR-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]711; ADDR: 2:712; ADDR-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]713; ADDR-NEXT: unreachable714; ADDR: 3:715; ADDR-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64716; ADDR-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 87960930222080717; ADDR-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr718; ADDR-NEXT: store <vscale x 2 x i32> zeroinitializer, ptr [[TMP6]], align 8719; ADDR-NEXT: store <vscale x 2 x i32> zeroinitializer, ptr [[P]], align 8720; ADDR-NEXT: ret void721;722; ORIGINS-LABEL: @store.nxv2i32(723; ORIGINS-NEXT: call void @llvm.donothing()724; ORIGINS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64725; ORIGINS-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080726; ORIGINS-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr727; ORIGINS-NEXT: [[TMP4:%.*]] = add i64 [[TMP2]], 17592186044416728; ORIGINS-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr729; ORIGINS-NEXT: store <vscale x 2 x i32> zeroinitializer, ptr [[TMP3]], align 8730; ORIGINS-NEXT: [[TMP6:%.*]] = call i32 @llvm.vector.reduce.or.nxv2i32(<vscale x 2 x i32> zeroinitializer)731; ORIGINS-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP6]], 0732; ORIGINS-NEXT: br i1 [[_MSCMP]], label [[TMP7:%.*]], label [[TMP13:%.*]], !prof [[PROF1]]733; ORIGINS: 7:734; ORIGINS-NEXT: [[TMP8:%.*]] = call i64 @llvm.vscale.i64()735; ORIGINS-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 8736; ORIGINS-NEXT: [[TMP10:%.*]] = add i64 [[TMP9]], 3737; ORIGINS-NEXT: [[TMP11:%.*]] = udiv i64 [[TMP10]], 4738; ORIGINS-NEXT: br label [[DOTSPLIT:%.*]]739; ORIGINS: .split:740; ORIGINS-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP7]] ], [ [[IV_NEXT:%.*]], [[DOTSPLIT]] ]741; ORIGINS-NEXT: [[TMP12:%.*]] = getelementptr i32, ptr [[TMP5]], i64 [[IV]]742; ORIGINS-NEXT: store i32 0, ptr [[TMP12]], align 4743; ORIGINS-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1744; ORIGINS-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP11]]745; ORIGINS-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]746; ORIGINS: .split.split:747; ORIGINS-NEXT: br label [[TMP13]]748; ORIGINS: 13:749; ORIGINS-NEXT: store <vscale x 2 x i32> zeroinitializer, ptr [[P]], align 8750; ORIGINS-NEXT: ret void751;752 store <vscale x 2 x i32> zeroinitializer, ptr %p753 ret void754}755 756define void @store.nxv4i32(ptr %p) sanitize_memory {757; CHECK-LABEL: @store.nxv4i32(758; CHECK-NEXT: call void @llvm.donothing()759; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64760; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080761; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr762; CHECK-NEXT: store <vscale x 4 x i32> zeroinitializer, ptr [[TMP3]], align 16763; CHECK-NEXT: store <vscale x 4 x i32> zeroinitializer, ptr [[P]], align 16764; CHECK-NEXT: ret void765;766; ADDR-LABEL: @store.nxv4i32(767; ADDR-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8768; ADDR-NEXT: call void @llvm.donothing()769; ADDR-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0770; ADDR-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]771; ADDR: 2:772; ADDR-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]773; ADDR-NEXT: unreachable774; ADDR: 3:775; ADDR-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64776; ADDR-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 87960930222080777; ADDR-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr778; ADDR-NEXT: store <vscale x 4 x i32> zeroinitializer, ptr [[TMP6]], align 16779; ADDR-NEXT: store <vscale x 4 x i32> zeroinitializer, ptr [[P]], align 16780; ADDR-NEXT: ret void781;782; ORIGINS-LABEL: @store.nxv4i32(783; ORIGINS-NEXT: call void @llvm.donothing()784; ORIGINS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64785; ORIGINS-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080786; ORIGINS-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr787; ORIGINS-NEXT: [[TMP4:%.*]] = add i64 [[TMP2]], 17592186044416788; ORIGINS-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr789; ORIGINS-NEXT: store <vscale x 4 x i32> zeroinitializer, ptr [[TMP3]], align 16790; ORIGINS-NEXT: [[TMP6:%.*]] = call i32 @llvm.vector.reduce.or.nxv4i32(<vscale x 4 x i32> zeroinitializer)791; ORIGINS-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP6]], 0792; ORIGINS-NEXT: br i1 [[_MSCMP]], label [[TMP7:%.*]], label [[TMP13:%.*]], !prof [[PROF1]]793; ORIGINS: 7:794; ORIGINS-NEXT: [[TMP8:%.*]] = call i64 @llvm.vscale.i64()795; ORIGINS-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 16796; ORIGINS-NEXT: [[TMP10:%.*]] = add i64 [[TMP9]], 3797; ORIGINS-NEXT: [[TMP11:%.*]] = udiv i64 [[TMP10]], 4798; ORIGINS-NEXT: br label [[DOTSPLIT:%.*]]799; ORIGINS: .split:800; ORIGINS-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP7]] ], [ [[IV_NEXT:%.*]], [[DOTSPLIT]] ]801; ORIGINS-NEXT: [[TMP12:%.*]] = getelementptr i32, ptr [[TMP5]], i64 [[IV]]802; ORIGINS-NEXT: store i32 0, ptr [[TMP12]], align 4803; ORIGINS-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1804; ORIGINS-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP11]]805; ORIGINS-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]806; ORIGINS: .split.split:807; ORIGINS-NEXT: br label [[TMP13]]808; ORIGINS: 13:809; ORIGINS-NEXT: store <vscale x 4 x i32> zeroinitializer, ptr [[P]], align 16810; ORIGINS-NEXT: ret void811;812 store <vscale x 4 x i32> zeroinitializer, ptr %p813 ret void814}815 816define void @store.nxv8i32(ptr %p) sanitize_memory {817; CHECK-LABEL: @store.nxv8i32(818; CHECK-NEXT: call void @llvm.donothing()819; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64820; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080821; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr822; CHECK-NEXT: store <vscale x 8 x i32> zeroinitializer, ptr [[TMP3]], align 32823; CHECK-NEXT: store <vscale x 8 x i32> zeroinitializer, ptr [[P]], align 32824; CHECK-NEXT: ret void825;826; ADDR-LABEL: @store.nxv8i32(827; ADDR-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8828; ADDR-NEXT: call void @llvm.donothing()829; ADDR-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0830; ADDR-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]831; ADDR: 2:832; ADDR-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]833; ADDR-NEXT: unreachable834; ADDR: 3:835; ADDR-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64836; ADDR-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 87960930222080837; ADDR-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr838; ADDR-NEXT: store <vscale x 8 x i32> zeroinitializer, ptr [[TMP6]], align 32839; ADDR-NEXT: store <vscale x 8 x i32> zeroinitializer, ptr [[P]], align 32840; ADDR-NEXT: ret void841;842; ORIGINS-LABEL: @store.nxv8i32(843; ORIGINS-NEXT: call void @llvm.donothing()844; ORIGINS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64845; ORIGINS-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080846; ORIGINS-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr847; ORIGINS-NEXT: [[TMP4:%.*]] = add i64 [[TMP2]], 17592186044416848; ORIGINS-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr849; ORIGINS-NEXT: store <vscale x 8 x i32> zeroinitializer, ptr [[TMP3]], align 32850; ORIGINS-NEXT: [[TMP6:%.*]] = call i32 @llvm.vector.reduce.or.nxv8i32(<vscale x 8 x i32> zeroinitializer)851; ORIGINS-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP6]], 0852; ORIGINS-NEXT: br i1 [[_MSCMP]], label [[TMP7:%.*]], label [[TMP13:%.*]], !prof [[PROF1]]853; ORIGINS: 7:854; ORIGINS-NEXT: [[TMP8:%.*]] = call i64 @llvm.vscale.i64()855; ORIGINS-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 32856; ORIGINS-NEXT: [[TMP10:%.*]] = add i64 [[TMP9]], 3857; ORIGINS-NEXT: [[TMP11:%.*]] = udiv i64 [[TMP10]], 4858; ORIGINS-NEXT: br label [[DOTSPLIT:%.*]]859; ORIGINS: .split:860; ORIGINS-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP7]] ], [ [[IV_NEXT:%.*]], [[DOTSPLIT]] ]861; ORIGINS-NEXT: [[TMP12:%.*]] = getelementptr i32, ptr [[TMP5]], i64 [[IV]]862; ORIGINS-NEXT: store i32 0, ptr [[TMP12]], align 4863; ORIGINS-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1864; ORIGINS-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP11]]865; ORIGINS-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]866; ORIGINS: .split.split:867; ORIGINS-NEXT: br label [[TMP13]]868; ORIGINS: 13:869; ORIGINS-NEXT: store <vscale x 8 x i32> zeroinitializer, ptr [[P]], align 32870; ORIGINS-NEXT: ret void871;872 store <vscale x 8 x i32> zeroinitializer, ptr %p873 ret void874}875 876define void @store.nxv16i32(ptr %p) sanitize_memory {877; CHECK-LABEL: @store.nxv16i32(878; CHECK-NEXT: call void @llvm.donothing()879; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64880; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080881; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr882; CHECK-NEXT: store <vscale x 16 x i32> zeroinitializer, ptr [[TMP3]], align 64883; CHECK-NEXT: store <vscale x 16 x i32> zeroinitializer, ptr [[P]], align 64884; CHECK-NEXT: ret void885;886; ADDR-LABEL: @store.nxv16i32(887; ADDR-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8888; ADDR-NEXT: call void @llvm.donothing()889; ADDR-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0890; ADDR-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]891; ADDR: 2:892; ADDR-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]893; ADDR-NEXT: unreachable894; ADDR: 3:895; ADDR-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64896; ADDR-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 87960930222080897; ADDR-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr898; ADDR-NEXT: store <vscale x 16 x i32> zeroinitializer, ptr [[TMP6]], align 64899; ADDR-NEXT: store <vscale x 16 x i32> zeroinitializer, ptr [[P]], align 64900; ADDR-NEXT: ret void901;902; ORIGINS-LABEL: @store.nxv16i32(903; ORIGINS-NEXT: call void @llvm.donothing()904; ORIGINS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64905; ORIGINS-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080906; ORIGINS-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr907; ORIGINS-NEXT: [[TMP4:%.*]] = add i64 [[TMP2]], 17592186044416908; ORIGINS-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr909; ORIGINS-NEXT: store <vscale x 16 x i32> zeroinitializer, ptr [[TMP3]], align 64910; ORIGINS-NEXT: [[TMP6:%.*]] = call i32 @llvm.vector.reduce.or.nxv16i32(<vscale x 16 x i32> zeroinitializer)911; ORIGINS-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP6]], 0912; ORIGINS-NEXT: br i1 [[_MSCMP]], label [[TMP7:%.*]], label [[TMP13:%.*]], !prof [[PROF1]]913; ORIGINS: 7:914; ORIGINS-NEXT: [[TMP8:%.*]] = call i64 @llvm.vscale.i64()915; ORIGINS-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 64916; ORIGINS-NEXT: [[TMP10:%.*]] = add i64 [[TMP9]], 3917; ORIGINS-NEXT: [[TMP11:%.*]] = udiv i64 [[TMP10]], 4918; ORIGINS-NEXT: br label [[DOTSPLIT:%.*]]919; ORIGINS: .split:920; ORIGINS-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP7]] ], [ [[IV_NEXT:%.*]], [[DOTSPLIT]] ]921; ORIGINS-NEXT: [[TMP12:%.*]] = getelementptr i32, ptr [[TMP5]], i64 [[IV]]922; ORIGINS-NEXT: store i32 0, ptr [[TMP12]], align 4923; ORIGINS-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1924; ORIGINS-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP11]]925; ORIGINS-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]926; ORIGINS: .split.split:927; ORIGINS-NEXT: br label [[TMP13]]928; ORIGINS: 13:929; ORIGINS-NEXT: store <vscale x 16 x i32> zeroinitializer, ptr [[P]], align 64930; ORIGINS-NEXT: ret void931;932 store <vscale x 16 x i32> zeroinitializer, ptr %p933 ret void934}935