273 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 42; RUN: opt < %s -passes=msan -S | FileCheck %s3;4; Forked from llvm/test/CodeGen/X86/vector-reduce-fmul.ll5;6; Currently handled incorrectly by visitInstruction:7; - llvm.vector.reduce.fmul8 9target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"10target triple = "x86_64-unknown-linux-gnu"11 12define float @test_v2f32(float %a0, <2 x float> %a1) #0 {13; CHECK-LABEL: define float @test_v2f32(14; CHECK-SAME: float [[A0:%.*]], <2 x float> [[A1:%.*]]) #[[ATTR0:[0-9]+]] {15; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 816; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 817; CHECK-NEXT: call void @llvm.donothing()18; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> [[TMP2]])19; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP1]], [[TMP3]]20; CHECK-NEXT: [[TMP6:%.*]] = call float @llvm.vector.reduce.fmul.v2f32(float [[A0]], <2 x float> [[A1]])21; CHECK-NEXT: store i32 [[TMP4]], ptr @__msan_retval_tls, align 822; CHECK-NEXT: ret float [[TMP6]]23;24 %1 = call float @llvm.vector.reduce.fmul.f32.v2f32(float %a0, <2 x float> %a1)25 ret float %126}27 28define float @test_v4f32(float %a0, <4 x float> %a1) #0 {29; CHECK-LABEL: define float @test_v4f32(30; CHECK-SAME: float [[A0:%.*]], <4 x float> [[A1:%.*]]) #[[ATTR0]] {31; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 832; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 833; CHECK-NEXT: call void @llvm.donothing()34; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[TMP2]])35; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP1]], [[TMP3]]36; CHECK-NEXT: [[TMP6:%.*]] = call float @llvm.vector.reduce.fmul.v4f32(float [[A0]], <4 x float> [[A1]])37; CHECK-NEXT: store i32 [[TMP4]], ptr @__msan_retval_tls, align 838; CHECK-NEXT: ret float [[TMP6]]39;40 %1 = call float @llvm.vector.reduce.fmul.f32.v4f32(float %a0, <4 x float> %a1)41 ret float %142}43 44define float @test_v8f32(float %a0, <8 x float> %a1) #0 {45; CHECK-LABEL: define float @test_v8f32(46; CHECK-SAME: float [[A0:%.*]], <8 x float> [[A1:%.*]]) #[[ATTR0]] {47; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 848; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 849; CHECK-NEXT: call void @llvm.donothing()50; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> [[TMP2]])51; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP1]], [[TMP3]]52; CHECK-NEXT: [[TMP6:%.*]] = call float @llvm.vector.reduce.fmul.v8f32(float [[A0]], <8 x float> [[A1]])53; CHECK-NEXT: store i32 [[TMP4]], ptr @__msan_retval_tls, align 854; CHECK-NEXT: ret float [[TMP6]]55;56 %1 = call float @llvm.vector.reduce.fmul.f32.v8f32(float %a0, <8 x float> %a1)57 ret float %158}59 60define float @test_v16f32(float %a0, <16 x float> %a1) #0 {61; CHECK-LABEL: define float @test_v16f32(62; CHECK-SAME: float [[A0:%.*]], <16 x float> [[A1:%.*]]) #[[ATTR0]] {63; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 864; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 865; CHECK-NEXT: call void @llvm.donothing()66; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.vector.reduce.or.v16i32(<16 x i32> [[TMP2]])67; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP1]], [[TMP3]]68; CHECK-NEXT: [[TMP6:%.*]] = call float @llvm.vector.reduce.fmul.v16f32(float [[A0]], <16 x float> [[A1]])69; CHECK-NEXT: store i32 [[TMP4]], ptr @__msan_retval_tls, align 870; CHECK-NEXT: ret float [[TMP6]]71;72 %1 = call float @llvm.vector.reduce.fmul.f32.v16f32(float %a0, <16 x float> %a1)73 ret float %174}75 76 77define float @test_v2f32_one(<2 x float> %a0) #0 {78; CHECK-LABEL: define float @test_v2f32_one(79; CHECK-SAME: <2 x float> [[A0:%.*]]) #[[ATTR0]] {80; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 881; CHECK-NEXT: call void @llvm.donothing()82; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> [[TMP1]])83; CHECK-NEXT: [[TMP3:%.*]] = or i32 0, [[TMP2]]84; CHECK-NEXT: [[TMP5:%.*]] = call float @llvm.vector.reduce.fmul.v2f32(float 1.000000e+00, <2 x float> [[A0]])85; CHECK-NEXT: store i32 [[TMP3]], ptr @__msan_retval_tls, align 886; CHECK-NEXT: ret float [[TMP5]]87;88 %1 = call float @llvm.vector.reduce.fmul.f32.v2f32(float 1.0, <2 x float> %a0)89 ret float %190}91 92define float @test_v4f32_one(<4 x float> %a0) #0 {93; CHECK-LABEL: define float @test_v4f32_one(94; CHECK-SAME: <4 x float> [[A0:%.*]]) #[[ATTR0]] {95; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 896; CHECK-NEXT: call void @llvm.donothing()97; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[TMP1]])98; CHECK-NEXT: [[TMP3:%.*]] = or i32 0, [[TMP2]]99; CHECK-NEXT: [[TMP5:%.*]] = call float @llvm.vector.reduce.fmul.v4f32(float 1.000000e+00, <4 x float> [[A0]])100; CHECK-NEXT: store i32 [[TMP3]], ptr @__msan_retval_tls, align 8101; CHECK-NEXT: ret float [[TMP5]]102;103 %1 = call float @llvm.vector.reduce.fmul.f32.v4f32(float 1.0, <4 x float> %a0)104 ret float %1105}106 107define float @test_v8f32_one(<8 x float> %a0) #0 {108; CHECK-LABEL: define float @test_v8f32_one(109; CHECK-SAME: <8 x float> [[A0:%.*]]) #[[ATTR0]] {110; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8111; CHECK-NEXT: call void @llvm.donothing()112; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> [[TMP1]])113; CHECK-NEXT: [[TMP3:%.*]] = or i32 0, [[TMP2]]114; CHECK-NEXT: [[TMP5:%.*]] = call float @llvm.vector.reduce.fmul.v8f32(float 1.000000e+00, <8 x float> [[A0]])115; CHECK-NEXT: store i32 [[TMP3]], ptr @__msan_retval_tls, align 8116; CHECK-NEXT: ret float [[TMP5]]117;118 %1 = call float @llvm.vector.reduce.fmul.f32.v8f32(float 1.0, <8 x float> %a0)119 ret float %1120}121 122define float @test_v16f32_one(<16 x float> %a0) #0 {123; CHECK-LABEL: define float @test_v16f32_one(124; CHECK-SAME: <16 x float> [[A0:%.*]]) #[[ATTR0]] {125; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 8126; CHECK-NEXT: call void @llvm.donothing()127; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.or.v16i32(<16 x i32> [[TMP1]])128; CHECK-NEXT: [[TMP3:%.*]] = or i32 0, [[TMP2]]129; CHECK-NEXT: [[TMP5:%.*]] = call float @llvm.vector.reduce.fmul.v16f32(float 1.000000e+00, <16 x float> [[A0]])130; CHECK-NEXT: store i32 [[TMP3]], ptr @__msan_retval_tls, align 8131; CHECK-NEXT: ret float [[TMP5]]132;133 %1 = call float @llvm.vector.reduce.fmul.f32.v16f32(float 1.0, <16 x float> %a0)134 ret float %1135}136 137define double @test_v2f64(double %a0, <2 x double> %a1) #0 {138; CHECK-LABEL: define double @test_v2f64(139; CHECK-SAME: double [[A0:%.*]], <2 x double> [[A1:%.*]]) #[[ATTR0]] {140; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8141; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8142; CHECK-NEXT: call void @llvm.donothing()143; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> [[TMP2]])144; CHECK-NEXT: [[TMP4:%.*]] = or i64 [[TMP1]], [[TMP3]]145; CHECK-NEXT: [[TMP6:%.*]] = call double @llvm.vector.reduce.fmul.v2f64(double [[A0]], <2 x double> [[A1]])146; CHECK-NEXT: store i64 [[TMP4]], ptr @__msan_retval_tls, align 8147; CHECK-NEXT: ret double [[TMP6]]148;149 %1 = call double @llvm.vector.reduce.fmul.f64.v2f64(double %a0, <2 x double> %a1)150 ret double %1151}152 153define double @test_v4f64(double %a0, <4 x double> %a1) #0 {154; CHECK-LABEL: define double @test_v4f64(155; CHECK-SAME: double [[A0:%.*]], <4 x double> [[A1:%.*]]) #[[ATTR0]] {156; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8157; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8158; CHECK-NEXT: call void @llvm.donothing()159; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vector.reduce.or.v4i64(<4 x i64> [[TMP2]])160; CHECK-NEXT: [[TMP4:%.*]] = or i64 [[TMP1]], [[TMP3]]161; CHECK-NEXT: [[TMP6:%.*]] = call double @llvm.vector.reduce.fmul.v4f64(double [[A0]], <4 x double> [[A1]])162; CHECK-NEXT: store i64 [[TMP4]], ptr @__msan_retval_tls, align 8163; CHECK-NEXT: ret double [[TMP6]]164;165 %1 = call double @llvm.vector.reduce.fmul.f64.v4f64(double %a0, <4 x double> %a1)166 ret double %1167}168 169define double @test_v8f64(double %a0, <8 x double> %a1) #0 {170; CHECK-LABEL: define double @test_v8f64(171; CHECK-SAME: double [[A0:%.*]], <8 x double> [[A1:%.*]]) #[[ATTR0]] {172; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8173; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8174; CHECK-NEXT: call void @llvm.donothing()175; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vector.reduce.or.v8i64(<8 x i64> [[TMP2]])176; CHECK-NEXT: [[TMP4:%.*]] = or i64 [[TMP1]], [[TMP3]]177; CHECK-NEXT: [[TMP6:%.*]] = call double @llvm.vector.reduce.fmul.v8f64(double [[A0]], <8 x double> [[A1]])178; CHECK-NEXT: store i64 [[TMP4]], ptr @__msan_retval_tls, align 8179; CHECK-NEXT: ret double [[TMP6]]180;181 %1 = call double @llvm.vector.reduce.fmul.f64.v8f64(double %a0, <8 x double> %a1)182 ret double %1183}184 185define double @test_v16f64(double %a0, <16 x double> %a1) #0 {186; CHECK-LABEL: define double @test_v16f64(187; CHECK-SAME: double [[A0:%.*]], <16 x double> [[A1:%.*]]) #[[ATTR0]] {188; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8189; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8190; CHECK-NEXT: call void @llvm.donothing()191; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vector.reduce.or.v16i64(<16 x i64> [[TMP2]])192; CHECK-NEXT: [[TMP4:%.*]] = or i64 [[TMP1]], [[TMP3]]193; CHECK-NEXT: [[TMP6:%.*]] = call double @llvm.vector.reduce.fmul.v16f64(double [[A0]], <16 x double> [[A1]])194; CHECK-NEXT: store i64 [[TMP4]], ptr @__msan_retval_tls, align 8195; CHECK-NEXT: ret double [[TMP6]]196;197 %1 = call double @llvm.vector.reduce.fmul.f64.v16f64(double %a0, <16 x double> %a1)198 ret double %1199}200 201 202define double @test_v2f64_one(<2 x double> %a0) #0 {203; CHECK-LABEL: define double @test_v2f64_one(204; CHECK-SAME: <2 x double> [[A0:%.*]]) #[[ATTR0]] {205; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8206; CHECK-NEXT: call void @llvm.donothing()207; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> [[TMP1]])208; CHECK-NEXT: [[TMP3:%.*]] = or i64 0, [[TMP2]]209; CHECK-NEXT: [[TMP5:%.*]] = call double @llvm.vector.reduce.fmul.v2f64(double 1.000000e+00, <2 x double> [[A0]])210; CHECK-NEXT: store i64 [[TMP3]], ptr @__msan_retval_tls, align 8211; CHECK-NEXT: ret double [[TMP5]]212;213 %1 = call double @llvm.vector.reduce.fmul.f64.v2f64(double 1.0, <2 x double> %a0)214 ret double %1215}216 217define double @test_v4f64_one(<4 x double> %a0) #0 {218; CHECK-LABEL: define double @test_v4f64_one(219; CHECK-SAME: <4 x double> [[A0:%.*]]) #[[ATTR0]] {220; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8221; CHECK-NEXT: call void @llvm.donothing()222; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.vector.reduce.or.v4i64(<4 x i64> [[TMP1]])223; CHECK-NEXT: [[TMP3:%.*]] = or i64 0, [[TMP2]]224; CHECK-NEXT: [[TMP5:%.*]] = call double @llvm.vector.reduce.fmul.v4f64(double 1.000000e+00, <4 x double> [[A0]])225; CHECK-NEXT: store i64 [[TMP3]], ptr @__msan_retval_tls, align 8226; CHECK-NEXT: ret double [[TMP5]]227;228 %1 = call double @llvm.vector.reduce.fmul.f64.v4f64(double 1.0, <4 x double> %a0)229 ret double %1230}231 232define double @test_v8f64_one(<8 x double> %a0) #0 {233; CHECK-LABEL: define double @test_v8f64_one(234; CHECK-SAME: <8 x double> [[A0:%.*]]) #[[ATTR0]] {235; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 8236; CHECK-NEXT: call void @llvm.donothing()237; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.vector.reduce.or.v8i64(<8 x i64> [[TMP1]])238; CHECK-NEXT: [[TMP3:%.*]] = or i64 0, [[TMP2]]239; CHECK-NEXT: [[TMP5:%.*]] = call double @llvm.vector.reduce.fmul.v8f64(double 1.000000e+00, <8 x double> [[A0]])240; CHECK-NEXT: store i64 [[TMP3]], ptr @__msan_retval_tls, align 8241; CHECK-NEXT: ret double [[TMP5]]242;243 %1 = call double @llvm.vector.reduce.fmul.f64.v8f64(double 1.0, <8 x double> %a0)244 ret double %1245}246 247define double @test_v16f64_one(<16 x double> %a0) #0 {248; CHECK-LABEL: define double @test_v16f64_one(249; CHECK-SAME: <16 x double> [[A0:%.*]]) #[[ATTR0]] {250; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i64>, ptr @__msan_param_tls, align 8251; CHECK-NEXT: call void @llvm.donothing()252; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.vector.reduce.or.v16i64(<16 x i64> [[TMP1]])253; CHECK-NEXT: [[TMP3:%.*]] = or i64 0, [[TMP2]]254; CHECK-NEXT: [[TMP5:%.*]] = call double @llvm.vector.reduce.fmul.v16f64(double 1.000000e+00, <16 x double> [[A0]])255; CHECK-NEXT: store i64 [[TMP3]], ptr @__msan_retval_tls, align 8256; CHECK-NEXT: ret double [[TMP5]]257;258 %1 = call double @llvm.vector.reduce.fmul.f64.v16f64(double 1.0, <16 x double> %a0)259 ret double %1260}261 262declare float @llvm.vector.reduce.fmul.f32.v2f32(float, <2 x float>)263declare float @llvm.vector.reduce.fmul.f32.v4f32(float, <4 x float>)264declare float @llvm.vector.reduce.fmul.f32.v8f32(float, <8 x float>)265declare float @llvm.vector.reduce.fmul.f32.v16f32(float, <16 x float>)266 267declare double @llvm.vector.reduce.fmul.f64.v2f64(double, <2 x double>)268declare double @llvm.vector.reduce.fmul.f64.v4f64(double, <4 x double>)269declare double @llvm.vector.reduce.fmul.f64.v8f64(double, <8 x double>)270declare double @llvm.vector.reduce.fmul.f64.v16f64(double, <16 x double>)271 272attributes #0 = { sanitize_memory }273