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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 42; RUN: opt < %s -S -msan-check-access-address=0 -passes="msan" 2>&1 | FileCheck %s3; RUN: opt < %s -S -msan-check-access-address=0 -passes="msan" -msan-track-origins=2 2>&1 | FileCheck %s --check-prefixes=ORIGIN4 5target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"6target triple = "x86_64-unknown-linux-gnu"7 8define void @test_load_store_i32(ptr %a, ptr %b) sanitize_memory {9; CHECK-LABEL: define void @test_load_store_i32(10; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0:[0-9]+]] {11; CHECK-NEXT: call void @llvm.donothing()12; CHECK-NEXT: [[TMP1:%.*]] = load <vscale x 4 x i32>, ptr [[A]], align 1613; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[A]] to i6414; CHECK-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 8796093022208015; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr16; CHECK-NEXT: [[_MSLD:%.*]] = load <vscale x 4 x i32>, ptr [[TMP4]], align 1617; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[B]] to i6418; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 8796093022208019; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr20; CHECK-NEXT: store <vscale x 4 x i32> [[_MSLD]], ptr [[TMP7]], align 1621; CHECK-NEXT: store <vscale x 4 x i32> [[TMP1]], ptr [[B]], align 1622; CHECK-NEXT: ret void23;24; ORIGIN-LABEL: define void @test_load_store_i32(25; ORIGIN-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0:[0-9]+]] {26; ORIGIN-NEXT: call void @llvm.donothing()27; ORIGIN-NEXT: [[TMP1:%.*]] = load <vscale x 4 x i32>, ptr [[A]], align 1628; ORIGIN-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[A]] to i6429; ORIGIN-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 8796093022208030; ORIGIN-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr31; ORIGIN-NEXT: [[TMP5:%.*]] = add i64 [[TMP3]], 1759218604441632; ORIGIN-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr33; ORIGIN-NEXT: [[_MSLD:%.*]] = load <vscale x 4 x i32>, ptr [[TMP4]], align 1634; ORIGIN-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 1635; ORIGIN-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[B]] to i6436; ORIGIN-NEXT: [[TMP9:%.*]] = xor i64 [[TMP8]], 8796093022208037; ORIGIN-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP9]] to ptr38; ORIGIN-NEXT: [[TMP11:%.*]] = add i64 [[TMP9]], 1759218604441639; ORIGIN-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr40; ORIGIN-NEXT: store <vscale x 4 x i32> [[_MSLD]], ptr [[TMP10]], align 1641; ORIGIN-NEXT: [[TMP13:%.*]] = call i32 @llvm.vector.reduce.or.nxv4i32(<vscale x 4 x i32> [[_MSLD]])42; ORIGIN-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP13]], 043; ORIGIN-NEXT: br i1 [[_MSCMP]], label [[TMP14:%.*]], label [[TMP21:%.*]], !prof [[PROF1:![0-9]+]]44; ORIGIN: 14:45; ORIGIN-NEXT: [[TMP15:%.*]] = call i32 @__msan_chain_origin(i32 [[TMP7]])46; ORIGIN-NEXT: [[TMP16:%.*]] = call i64 @llvm.vscale.i64()47; ORIGIN-NEXT: [[TMP17:%.*]] = mul nuw i64 [[TMP16]], 1648; ORIGIN-NEXT: [[TMP18:%.*]] = add i64 [[TMP17]], 349; ORIGIN-NEXT: [[TMP19:%.*]] = udiv i64 [[TMP18]], 450; ORIGIN-NEXT: br label [[DOTSPLIT:%.*]]51; ORIGIN: .split:52; ORIGIN-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV_NEXT:%.*]], [[DOTSPLIT]] ]53; ORIGIN-NEXT: [[TMP20:%.*]] = getelementptr i32, ptr [[TMP12]], i64 [[IV]]54; ORIGIN-NEXT: store i32 [[TMP15]], ptr [[TMP20]], align 455; ORIGIN-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 156; ORIGIN-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP19]]57; ORIGIN-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]58; ORIGIN: .split.split:59; ORIGIN-NEXT: br label [[TMP21]]60; ORIGIN: 21:61; ORIGIN-NEXT: store <vscale x 4 x i32> [[TMP1]], ptr [[B]], align 1662; ORIGIN-NEXT: ret void63;64 %1 = load <vscale x 4 x i32>, ptr %a65 store <vscale x 4 x i32> %1, ptr %b66 ret void67}68 69define void @test_load_store_add_int(ptr %a, ptr %b) sanitize_memory {70; CHECK-LABEL: define void @test_load_store_add_int(71; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {72; CHECK-NEXT: call void @llvm.donothing()73; CHECK-NEXT: [[TMP1:%.*]] = load <vscale x 8 x i64>, ptr [[A]], align 6474; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[A]] to i6475; CHECK-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 8796093022208076; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr77; CHECK-NEXT: [[_MSLD:%.*]] = load <vscale x 8 x i64>, ptr [[TMP4]], align 6478; CHECK-NEXT: [[TMP5:%.*]] = load <vscale x 8 x i64>, ptr [[B]], align 6479; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[B]] to i6480; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 8796093022208081; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr82; CHECK-NEXT: [[_MSLD1:%.*]] = load <vscale x 8 x i64>, ptr [[TMP8]], align 6483; CHECK-NEXT: [[_MSPROP:%.*]] = or <vscale x 8 x i64> [[_MSLD]], [[_MSLD1]]84; CHECK-NEXT: [[TMP9:%.*]] = add <vscale x 8 x i64> [[TMP1]], [[TMP5]]85; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i6486; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 8796093022208087; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr88; CHECK-NEXT: store <vscale x 8 x i64> [[_MSLD1]], ptr [[TMP12]], align 6489; CHECK-NEXT: store <vscale x 8 x i64> [[TMP5]], ptr [[B]], align 6490; CHECK-NEXT: ret void91;92; ORIGIN-LABEL: define void @test_load_store_add_int(93; ORIGIN-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {94; ORIGIN-NEXT: call void @llvm.donothing()95; ORIGIN-NEXT: [[TMP1:%.*]] = load <vscale x 8 x i64>, ptr [[A]], align 6496; ORIGIN-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[A]] to i6497; ORIGIN-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 8796093022208098; ORIGIN-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr99; ORIGIN-NEXT: [[TMP5:%.*]] = add i64 [[TMP3]], 17592186044416100; ORIGIN-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr101; ORIGIN-NEXT: [[_MSLD:%.*]] = load <vscale x 8 x i64>, ptr [[TMP4]], align 64102; ORIGIN-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 64103; ORIGIN-NEXT: [[TMP8:%.*]] = load <vscale x 8 x i64>, ptr [[B]], align 64104; ORIGIN-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[B]] to i64105; ORIGIN-NEXT: [[TMP10:%.*]] = xor i64 [[TMP9]], 87960930222080106; ORIGIN-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to ptr107; ORIGIN-NEXT: [[TMP12:%.*]] = add i64 [[TMP10]], 17592186044416108; ORIGIN-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to ptr109; ORIGIN-NEXT: [[_MSLD1:%.*]] = load <vscale x 8 x i64>, ptr [[TMP11]], align 64110; ORIGIN-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 64111; ORIGIN-NEXT: [[_MSPROP:%.*]] = or <vscale x 8 x i64> [[_MSLD]], [[_MSLD1]]112; ORIGIN-NEXT: [[TMP15:%.*]] = call i64 @llvm.vector.reduce.or.nxv8i64(<vscale x 8 x i64> [[_MSLD1]])113; ORIGIN-NEXT: [[TMP16:%.*]] = icmp ne i64 [[TMP15]], 0114; ORIGIN-NEXT: [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[TMP14]], i32 [[TMP7]]115; ORIGIN-NEXT: [[TMP18:%.*]] = add <vscale x 8 x i64> [[TMP1]], [[TMP8]]116; ORIGIN-NEXT: [[TMP19:%.*]] = ptrtoint ptr [[B]] to i64117; ORIGIN-NEXT: [[TMP20:%.*]] = xor i64 [[TMP19]], 87960930222080118; ORIGIN-NEXT: [[TMP21:%.*]] = inttoptr i64 [[TMP20]] to ptr119; ORIGIN-NEXT: [[TMP22:%.*]] = add i64 [[TMP20]], 17592186044416120; ORIGIN-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP22]] to ptr121; ORIGIN-NEXT: store <vscale x 8 x i64> [[_MSLD1]], ptr [[TMP21]], align 64122; ORIGIN-NEXT: [[TMP24:%.*]] = call i64 @llvm.vector.reduce.or.nxv8i64(<vscale x 8 x i64> [[_MSLD1]])123; ORIGIN-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP24]], 0124; ORIGIN-NEXT: br i1 [[_MSCMP]], label [[TMP25:%.*]], label [[TMP32:%.*]], !prof [[PROF1]]125; ORIGIN: 25:126; ORIGIN-NEXT: [[TMP26:%.*]] = call i32 @__msan_chain_origin(i32 [[TMP14]])127; ORIGIN-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()128; ORIGIN-NEXT: [[TMP28:%.*]] = mul nuw i64 [[TMP27]], 64129; ORIGIN-NEXT: [[TMP29:%.*]] = add i64 [[TMP28]], 3130; ORIGIN-NEXT: [[TMP30:%.*]] = udiv i64 [[TMP29]], 4131; ORIGIN-NEXT: br label [[DOTSPLIT:%.*]]132; ORIGIN: .split:133; ORIGIN-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP25]] ], [ [[IV_NEXT:%.*]], [[DOTSPLIT]] ]134; ORIGIN-NEXT: [[TMP31:%.*]] = getelementptr i32, ptr [[TMP23]], i64 [[IV]]135; ORIGIN-NEXT: store i32 [[TMP26]], ptr [[TMP31]], align 4136; ORIGIN-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1137; ORIGIN-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP30]]138; ORIGIN-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]139; ORIGIN: .split.split:140; ORIGIN-NEXT: br label [[TMP32]]141; ORIGIN: 32:142; ORIGIN-NEXT: store <vscale x 8 x i64> [[TMP8]], ptr [[B]], align 64143; ORIGIN-NEXT: ret void144;145 %1 = load <vscale x 8 x i64>, ptr %a146 %2 = load <vscale x 8 x i64>, ptr %b147 %3 = add <vscale x 8 x i64> %1, %2148 store <vscale x 8 x i64> %2, ptr %b149 ret void150}151 152define void @test_load_store_float(ptr %a, ptr %b) sanitize_memory {153; CHECK-LABEL: define void @test_load_store_float(154; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {155; CHECK-NEXT: call void @llvm.donothing()156; CHECK-NEXT: [[TMP1:%.*]] = load <vscale x 4 x float>, ptr [[A]], align 16157; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[A]] to i64158; CHECK-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080159; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr160; CHECK-NEXT: [[_MSLD:%.*]] = load <vscale x 4 x i32>, ptr [[TMP4]], align 16161; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[B]] to i64162; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 87960930222080163; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr164; CHECK-NEXT: store <vscale x 4 x i32> [[_MSLD]], ptr [[TMP7]], align 16165; CHECK-NEXT: store <vscale x 4 x float> [[TMP1]], ptr [[B]], align 16166; CHECK-NEXT: ret void167;168; ORIGIN-LABEL: define void @test_load_store_float(169; ORIGIN-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {170; ORIGIN-NEXT: call void @llvm.donothing()171; ORIGIN-NEXT: [[TMP1:%.*]] = load <vscale x 4 x float>, ptr [[A]], align 16172; ORIGIN-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[A]] to i64173; ORIGIN-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080174; ORIGIN-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr175; ORIGIN-NEXT: [[TMP5:%.*]] = add i64 [[TMP3]], 17592186044416176; ORIGIN-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr177; ORIGIN-NEXT: [[_MSLD:%.*]] = load <vscale x 4 x i32>, ptr [[TMP4]], align 16178; ORIGIN-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 16179; ORIGIN-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[B]] to i64180; ORIGIN-NEXT: [[TMP9:%.*]] = xor i64 [[TMP8]], 87960930222080181; ORIGIN-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP9]] to ptr182; ORIGIN-NEXT: [[TMP11:%.*]] = add i64 [[TMP9]], 17592186044416183; ORIGIN-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr184; ORIGIN-NEXT: store <vscale x 4 x i32> [[_MSLD]], ptr [[TMP10]], align 16185; ORIGIN-NEXT: [[TMP13:%.*]] = call i32 @llvm.vector.reduce.or.nxv4i32(<vscale x 4 x i32> [[_MSLD]])186; ORIGIN-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP13]], 0187; ORIGIN-NEXT: br i1 [[_MSCMP]], label [[TMP14:%.*]], label [[TMP21:%.*]], !prof [[PROF1]]188; ORIGIN: 14:189; ORIGIN-NEXT: [[TMP15:%.*]] = call i32 @__msan_chain_origin(i32 [[TMP7]])190; ORIGIN-NEXT: [[TMP16:%.*]] = call i64 @llvm.vscale.i64()191; ORIGIN-NEXT: [[TMP17:%.*]] = mul nuw i64 [[TMP16]], 16192; ORIGIN-NEXT: [[TMP18:%.*]] = add i64 [[TMP17]], 3193; ORIGIN-NEXT: [[TMP19:%.*]] = udiv i64 [[TMP18]], 4194; ORIGIN-NEXT: br label [[DOTSPLIT:%.*]]195; ORIGIN: .split:196; ORIGIN-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV_NEXT:%.*]], [[DOTSPLIT]] ]197; ORIGIN-NEXT: [[TMP20:%.*]] = getelementptr i32, ptr [[TMP12]], i64 [[IV]]198; ORIGIN-NEXT: store i32 [[TMP15]], ptr [[TMP20]], align 4199; ORIGIN-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1200; ORIGIN-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP19]]201; ORIGIN-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]202; ORIGIN: .split.split:203; ORIGIN-NEXT: br label [[TMP21]]204; ORIGIN: 21:205; ORIGIN-NEXT: store <vscale x 4 x float> [[TMP1]], ptr [[B]], align 16206; ORIGIN-NEXT: ret void207;208 %1 = load <vscale x 4 x float>, ptr %a209 store <vscale x 4 x float> %1, ptr %b210 ret void211}212 213define void @test_load_store_add_float(ptr %a, ptr %b) sanitize_memory {214; CHECK-LABEL: define void @test_load_store_add_float(215; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {216; CHECK-NEXT: call void @llvm.donothing()217; CHECK-NEXT: [[TMP1:%.*]] = load <vscale x 2 x float>, ptr [[A]], align 8218; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[A]] to i64219; CHECK-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080220; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr221; CHECK-NEXT: [[_MSLD:%.*]] = load <vscale x 2 x i32>, ptr [[TMP4]], align 8222; CHECK-NEXT: [[TMP5:%.*]] = load <vscale x 2 x float>, ptr [[B]], align 8223; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[B]] to i64224; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 87960930222080225; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr226; CHECK-NEXT: [[_MSLD1:%.*]] = load <vscale x 2 x i32>, ptr [[TMP8]], align 8227; CHECK-NEXT: [[_MSPROP:%.*]] = or <vscale x 2 x i32> [[_MSLD]], [[_MSLD1]]228; CHECK-NEXT: [[TMP9:%.*]] = fadd <vscale x 2 x float> [[TMP1]], [[TMP5]]229; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64230; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 87960930222080231; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr232; CHECK-NEXT: store <vscale x 2 x i32> [[_MSLD1]], ptr [[TMP12]], align 8233; CHECK-NEXT: store <vscale x 2 x float> [[TMP5]], ptr [[B]], align 8234; CHECK-NEXT: ret void235;236; ORIGIN-LABEL: define void @test_load_store_add_float(237; ORIGIN-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {238; ORIGIN-NEXT: call void @llvm.donothing()239; ORIGIN-NEXT: [[TMP1:%.*]] = load <vscale x 2 x float>, ptr [[A]], align 8240; ORIGIN-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[A]] to i64241; ORIGIN-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080242; ORIGIN-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr243; ORIGIN-NEXT: [[TMP5:%.*]] = add i64 [[TMP3]], 17592186044416244; ORIGIN-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr245; ORIGIN-NEXT: [[_MSLD:%.*]] = load <vscale x 2 x i32>, ptr [[TMP4]], align 8246; ORIGIN-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 8247; ORIGIN-NEXT: [[TMP8:%.*]] = load <vscale x 2 x float>, ptr [[B]], align 8248; ORIGIN-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[B]] to i64249; ORIGIN-NEXT: [[TMP10:%.*]] = xor i64 [[TMP9]], 87960930222080250; ORIGIN-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to ptr251; ORIGIN-NEXT: [[TMP12:%.*]] = add i64 [[TMP10]], 17592186044416252; ORIGIN-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to ptr253; ORIGIN-NEXT: [[_MSLD1:%.*]] = load <vscale x 2 x i32>, ptr [[TMP11]], align 8254; ORIGIN-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 8255; ORIGIN-NEXT: [[_MSPROP:%.*]] = or <vscale x 2 x i32> [[_MSLD]], [[_MSLD1]]256; ORIGIN-NEXT: [[TMP15:%.*]] = call i32 @llvm.vector.reduce.or.nxv2i32(<vscale x 2 x i32> [[_MSLD1]])257; ORIGIN-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0258; ORIGIN-NEXT: [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[TMP14]], i32 [[TMP7]]259; ORIGIN-NEXT: [[TMP18:%.*]] = fadd <vscale x 2 x float> [[TMP1]], [[TMP8]]260; ORIGIN-NEXT: [[TMP19:%.*]] = ptrtoint ptr [[B]] to i64261; ORIGIN-NEXT: [[TMP20:%.*]] = xor i64 [[TMP19]], 87960930222080262; ORIGIN-NEXT: [[TMP21:%.*]] = inttoptr i64 [[TMP20]] to ptr263; ORIGIN-NEXT: [[TMP22:%.*]] = add i64 [[TMP20]], 17592186044416264; ORIGIN-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP22]] to ptr265; ORIGIN-NEXT: store <vscale x 2 x i32> [[_MSLD1]], ptr [[TMP21]], align 8266; ORIGIN-NEXT: [[TMP24:%.*]] = call i32 @llvm.vector.reduce.or.nxv2i32(<vscale x 2 x i32> [[_MSLD1]])267; ORIGIN-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP24]], 0268; ORIGIN-NEXT: br i1 [[_MSCMP]], label [[TMP25:%.*]], label [[TMP32:%.*]], !prof [[PROF1]]269; ORIGIN: 25:270; ORIGIN-NEXT: [[TMP26:%.*]] = call i32 @__msan_chain_origin(i32 [[TMP14]])271; ORIGIN-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64()272; ORIGIN-NEXT: [[TMP28:%.*]] = mul nuw i64 [[TMP27]], 8273; ORIGIN-NEXT: [[TMP29:%.*]] = add i64 [[TMP28]], 3274; ORIGIN-NEXT: [[TMP30:%.*]] = udiv i64 [[TMP29]], 4275; ORIGIN-NEXT: br label [[DOTSPLIT:%.*]]276; ORIGIN: .split:277; ORIGIN-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP25]] ], [ [[IV_NEXT:%.*]], [[DOTSPLIT]] ]278; ORIGIN-NEXT: [[TMP31:%.*]] = getelementptr i32, ptr [[TMP23]], i64 [[IV]]279; ORIGIN-NEXT: store i32 [[TMP26]], ptr [[TMP31]], align 4280; ORIGIN-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1281; ORIGIN-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP30]]282; ORIGIN-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]283; ORIGIN: .split.split:284; ORIGIN-NEXT: br label [[TMP32]]285; ORIGIN: 32:286; ORIGIN-NEXT: store <vscale x 2 x float> [[TMP8]], ptr [[B]], align 8287; ORIGIN-NEXT: ret void288;289 %1 = load <vscale x 2 x float>, ptr %a290 %2 = load <vscale x 2 x float>, ptr %b291 %3 = fadd <vscale x 2 x float> %1, %2292 store <vscale x 2 x float> %2, ptr %b293 ret void294}295 296define <vscale x 2 x float> @fn_ret(ptr %a) sanitize_memory {297; CHECK-LABEL: define <vscale x 2 x float> @fn_ret(298; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {299; CHECK-NEXT: call void @llvm.donothing()300; CHECK-NEXT: [[TMP1:%.*]] = load <vscale x 2 x float>, ptr [[A]], align 8301; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[A]] to i64302; CHECK-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080303; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr304; CHECK-NEXT: [[_MSLD:%.*]] = load <vscale x 2 x i32>, ptr [[TMP4]], align 8305; CHECK-NEXT: store <vscale x 2 x i32> [[_MSLD]], ptr @__msan_retval_tls, align 8306; CHECK-NEXT: ret <vscale x 2 x float> [[TMP1]]307;308; ORIGIN-LABEL: define <vscale x 2 x float> @fn_ret(309; ORIGIN-SAME: ptr [[A:%.*]]) #[[ATTR0]] {310; ORIGIN-NEXT: call void @llvm.donothing()311; ORIGIN-NEXT: [[TMP1:%.*]] = load <vscale x 2 x float>, ptr [[A]], align 8312; ORIGIN-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[A]] to i64313; ORIGIN-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080314; ORIGIN-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr315; ORIGIN-NEXT: [[TMP5:%.*]] = add i64 [[TMP3]], 17592186044416316; ORIGIN-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr317; ORIGIN-NEXT: [[_MSLD:%.*]] = load <vscale x 2 x i32>, ptr [[TMP4]], align 8318; ORIGIN-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 8319; ORIGIN-NEXT: store <vscale x 2 x i32> [[_MSLD]], ptr @__msan_retval_tls, align 8320; ORIGIN-NEXT: store i32 [[TMP7]], ptr @__msan_retval_origin_tls, align 4321; ORIGIN-NEXT: ret <vscale x 2 x float> [[TMP1]]322;323 %1 = load <vscale x 2 x float>, ptr %a324 ret <vscale x 2 x float> %1325}326 327define void @test_ret(ptr %a, ptr %b) sanitize_memory {328; CHECK-LABEL: define void @test_ret(329; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {330; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8331; CHECK-NEXT: call void @llvm.donothing()332; CHECK-NEXT: store i64 [[TMP1]], ptr @__msan_param_tls, align 8333; CHECK-NEXT: store <vscale x 2 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8334; CHECK-NEXT: [[TMP5:%.*]] = call <vscale x 2 x float> @fn_ret(ptr [[A]])335; CHECK-NEXT: [[_MSRET:%.*]] = load <vscale x 2 x i32>, ptr @__msan_retval_tls, align 8336; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[B]] to i64337; CHECK-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080338; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr339; CHECK-NEXT: store <vscale x 2 x i32> [[_MSRET]], ptr [[TMP4]], align 8340; CHECK-NEXT: store <vscale x 2 x float> [[TMP5]], ptr [[B]], align 8341; CHECK-NEXT: ret void342;343; ORIGIN-LABEL: define void @test_ret(344; ORIGIN-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {345; ORIGIN-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8346; ORIGIN-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4347; ORIGIN-NEXT: call void @llvm.donothing()348; ORIGIN-NEXT: store i64 [[TMP1]], ptr @__msan_param_tls, align 8349; ORIGIN-NEXT: store i32 [[TMP2]], ptr @__msan_param_origin_tls, align 4350; ORIGIN-NEXT: store <vscale x 2 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8351; ORIGIN-NEXT: [[TMP3:%.*]] = call <vscale x 2 x float> @fn_ret(ptr [[A]])352; ORIGIN-NEXT: [[_MSRET:%.*]] = load <vscale x 2 x i32>, ptr @__msan_retval_tls, align 8353; ORIGIN-NEXT: [[TMP4:%.*]] = load i32, ptr @__msan_retval_origin_tls, align 4354; ORIGIN-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[B]] to i64355; ORIGIN-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 87960930222080356; ORIGIN-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr357; ORIGIN-NEXT: [[TMP8:%.*]] = add i64 [[TMP6]], 17592186044416358; ORIGIN-NEXT: [[TMP9:%.*]] = inttoptr i64 [[TMP8]] to ptr359; ORIGIN-NEXT: store <vscale x 2 x i32> [[_MSRET]], ptr [[TMP7]], align 8360; ORIGIN-NEXT: [[TMP10:%.*]] = call i32 @llvm.vector.reduce.or.nxv2i32(<vscale x 2 x i32> [[_MSRET]])361; ORIGIN-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP10]], 0362; ORIGIN-NEXT: br i1 [[_MSCMP]], label [[TMP11:%.*]], label [[TMP18:%.*]], !prof [[PROF1]]363; ORIGIN: 11:364; ORIGIN-NEXT: [[TMP12:%.*]] = call i32 @__msan_chain_origin(i32 [[TMP4]])365; ORIGIN-NEXT: [[TMP13:%.*]] = call i64 @llvm.vscale.i64()366; ORIGIN-NEXT: [[TMP14:%.*]] = mul nuw i64 [[TMP13]], 8367; ORIGIN-NEXT: [[TMP15:%.*]] = add i64 [[TMP14]], 3368; ORIGIN-NEXT: [[TMP16:%.*]] = udiv i64 [[TMP15]], 4369; ORIGIN-NEXT: br label [[DOTSPLIT:%.*]]370; ORIGIN: .split:371; ORIGIN-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP11]] ], [ [[IV_NEXT:%.*]], [[DOTSPLIT]] ]372; ORIGIN-NEXT: [[TMP17:%.*]] = getelementptr i32, ptr [[TMP9]], i64 [[IV]]373; ORIGIN-NEXT: store i32 [[TMP12]], ptr [[TMP17]], align 4374; ORIGIN-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1375; ORIGIN-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP16]]376; ORIGIN-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]377; ORIGIN: .split.split:378; ORIGIN-NEXT: br label [[TMP18]]379; ORIGIN: 18:380; ORIGIN-NEXT: store <vscale x 2 x float> [[TMP3]], ptr [[B]], align 8381; ORIGIN-NEXT: ret void382;383 %1 = call <vscale x 2 x float> @fn_ret(ptr %a)384 store <vscale x 2 x float> %1, ptr %b385 ret void386}387 388define void @fn_param(<vscale x 2 x float> %a, ptr %b) sanitize_memory {389; CHECK-LABEL: define void @fn_param(390; CHECK-SAME: <vscale x 2 x float> [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {391; CHECK-NEXT: call void @llvm.donothing()392; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[B]] to i64393; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080394; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr395; CHECK-NEXT: store <vscale x 2 x i32> zeroinitializer, ptr [[TMP3]], align 8396; CHECK-NEXT: store <vscale x 2 x float> [[A]], ptr [[B]], align 8397; CHECK-NEXT: ret void398;399; ORIGIN-LABEL: define void @fn_param(400; ORIGIN-SAME: <vscale x 2 x float> [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {401; ORIGIN-NEXT: call void @llvm.donothing()402; ORIGIN-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[B]] to i64403; ORIGIN-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080404; ORIGIN-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr405; ORIGIN-NEXT: [[TMP4:%.*]] = add i64 [[TMP2]], 17592186044416406; ORIGIN-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr407; ORIGIN-NEXT: store <vscale x 2 x i32> zeroinitializer, ptr [[TMP3]], align 8408; ORIGIN-NEXT: [[TMP6:%.*]] = call i32 @llvm.vector.reduce.or.nxv2i32(<vscale x 2 x i32> zeroinitializer)409; ORIGIN-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP6]], 0410; ORIGIN-NEXT: br i1 [[_MSCMP]], label [[TMP7:%.*]], label [[TMP14:%.*]], !prof [[PROF1]]411; ORIGIN: 7:412; ORIGIN-NEXT: [[TMP8:%.*]] = call i32 @__msan_chain_origin(i32 0)413; ORIGIN-NEXT: [[TMP9:%.*]] = call i64 @llvm.vscale.i64()414; ORIGIN-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP9]], 8415; ORIGIN-NEXT: [[TMP11:%.*]] = add i64 [[TMP10]], 3416; ORIGIN-NEXT: [[TMP12:%.*]] = udiv i64 [[TMP11]], 4417; ORIGIN-NEXT: br label [[DOTSPLIT:%.*]]418; ORIGIN: .split:419; ORIGIN-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP7]] ], [ [[IV_NEXT:%.*]], [[DOTSPLIT]] ]420; ORIGIN-NEXT: [[TMP13:%.*]] = getelementptr i32, ptr [[TMP5]], i64 [[IV]]421; ORIGIN-NEXT: store i32 [[TMP8]], ptr [[TMP13]], align 4422; ORIGIN-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1423; ORIGIN-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP12]]424; ORIGIN-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]425; ORIGIN: .split.split:426; ORIGIN-NEXT: br label [[TMP14]]427; ORIGIN: 14:428; ORIGIN-NEXT: store <vscale x 2 x float> [[A]], ptr [[B]], align 8429; ORIGIN-NEXT: ret void430;431 store <vscale x 2 x float> %a, ptr %b432 ret void433}434 435define void @test_param(ptr %a, ptr %b) sanitize_memory {436; CHECK-LABEL: define void @test_param(437; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {438; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8439; CHECK-NEXT: call void @llvm.donothing()440; CHECK-NEXT: [[TMP2:%.*]] = load <vscale x 2 x float>, ptr [[A]], align 8441; CHECK-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[A]] to i64442; CHECK-NEXT: [[TMP4:%.*]] = xor i64 [[TMP3]], 87960930222080443; CHECK-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr444; CHECK-NEXT: [[_MSLD:%.*]] = load <vscale x 2 x i32>, ptr [[TMP5]], align 8445; CHECK-NEXT: store i64 [[TMP1]], ptr @__msan_param_tls, align 8446; CHECK-NEXT: [[TMP6:%.*]] = call i32 @llvm.vector.reduce.or.nxv2i32(<vscale x 2 x i32> [[_MSLD]])447; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP6]], 0448; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1:![0-9]+]]449; CHECK: 7:450; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5:[0-9]+]]451; CHECK-NEXT: unreachable452; CHECK: 8:453; CHECK-NEXT: call void @fn_param(<vscale x 2 x float> [[TMP2]], ptr [[B]])454; CHECK-NEXT: ret void455;456; ORIGIN-LABEL: define void @test_param(457; ORIGIN-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {458; ORIGIN-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8459; ORIGIN-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_origin_tls, i64 8), align 4460; ORIGIN-NEXT: call void @llvm.donothing()461; ORIGIN-NEXT: [[TMP3:%.*]] = load <vscale x 2 x float>, ptr [[A]], align 8462; ORIGIN-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i64463; ORIGIN-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 87960930222080464; ORIGIN-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr465; ORIGIN-NEXT: [[TMP7:%.*]] = add i64 [[TMP5]], 17592186044416466; ORIGIN-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr467; ORIGIN-NEXT: [[_MSLD:%.*]] = load <vscale x 2 x i32>, ptr [[TMP6]], align 8468; ORIGIN-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 8469; ORIGIN-NEXT: store i64 [[TMP1]], ptr @__msan_param_tls, align 8470; ORIGIN-NEXT: store i32 [[TMP2]], ptr @__msan_param_origin_tls, align 4471; ORIGIN-NEXT: [[TMP10:%.*]] = call i32 @llvm.vector.reduce.or.nxv2i32(<vscale x 2 x i32> [[_MSLD]])472; ORIGIN-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP10]], 0473; ORIGIN-NEXT: br i1 [[_MSCMP]], label [[TMP11:%.*]], label [[TMP12:%.*]], !prof [[PROF1]]474; ORIGIN: 11:475; ORIGIN-NEXT: call void @__msan_warning_with_origin_noreturn(i32 [[TMP9]]) #[[ATTR5:[0-9]+]]476; ORIGIN-NEXT: unreachable477; ORIGIN: 12:478; ORIGIN-NEXT: call void @fn_param(<vscale x 2 x float> [[TMP3]], ptr [[B]])479; ORIGIN-NEXT: ret void480;481 %1 = load <vscale x 2 x float>, ptr %a482 call void @fn_param(<vscale x 2 x float> %1, ptr %b)483 ret void484}485 486define void @test_alloca1() sanitize_memory {487; CHECK-LABEL: define void @test_alloca1(488; CHECK-SAME: ) #[[ATTR0]] {489; CHECK-NEXT: entry:490; CHECK-NEXT: call void @llvm.donothing()491; CHECK-NEXT: [[X:%.*]] = alloca <vscale x 64 x i1>, align 4492; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()493; CHECK-NEXT: [[TMP1:%.*]] = mul nuw i64 [[TMP0]], 8494; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[X]] to i64495; CHECK-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080496; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr497; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[TMP4]], i8 -1, i64 [[TMP1]], i1 false)498; CHECK-NEXT: ret void499;500; ORIGIN-LABEL: define void @test_alloca1(501; ORIGIN-SAME: ) #[[ATTR0]] {502; ORIGIN-NEXT: entry:503; ORIGIN-NEXT: call void @llvm.donothing()504; ORIGIN-NEXT: [[X:%.*]] = alloca <vscale x 64 x i1>, align 4505; ORIGIN-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()506; ORIGIN-NEXT: [[TMP1:%.*]] = mul nuw i64 [[TMP0]], 8507; ORIGIN-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[X]] to i64508; ORIGIN-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080509; ORIGIN-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr510; ORIGIN-NEXT: [[TMP5:%.*]] = add i64 [[TMP3]], 17592186044416511; ORIGIN-NEXT: [[TMP6:%.*]] = and i64 [[TMP5]], -4512; ORIGIN-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr513; ORIGIN-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[TMP4]], i8 -1, i64 [[TMP1]], i1 false)514; ORIGIN-NEXT: call void @__msan_set_alloca_origin_with_descr(ptr [[X]], i64 [[TMP1]], ptr @[[GLOB0:[0-9]+]], ptr @[[GLOB1:[0-9]+]])515; ORIGIN-NEXT: ret void516;517entry:518 %x = alloca <vscale x 64 x i1>, align 4519 ret void520}521 522define void @test_alloca2() sanitize_memory {523; CHECK-LABEL: define void @test_alloca2(524; CHECK-SAME: ) #[[ATTR0]] {525; CHECK-NEXT: entry:526; CHECK-NEXT: call void @llvm.donothing()527; CHECK-NEXT: [[X:%.*]] = alloca <vscale x 64 x double>, align 4528; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()529; CHECK-NEXT: [[TMP1:%.*]] = mul nuw i64 [[TMP0]], 512530; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[X]] to i64531; CHECK-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080532; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr533; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[TMP4]], i8 -1, i64 [[TMP1]], i1 false)534; CHECK-NEXT: ret void535;536; ORIGIN-LABEL: define void @test_alloca2(537; ORIGIN-SAME: ) #[[ATTR0]] {538; ORIGIN-NEXT: entry:539; ORIGIN-NEXT: call void @llvm.donothing()540; ORIGIN-NEXT: [[X:%.*]] = alloca <vscale x 64 x double>, align 4541; ORIGIN-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()542; ORIGIN-NEXT: [[TMP1:%.*]] = mul nuw i64 [[TMP0]], 512543; ORIGIN-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[X]] to i64544; ORIGIN-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080545; ORIGIN-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr546; ORIGIN-NEXT: [[TMP5:%.*]] = add i64 [[TMP3]], 17592186044416547; ORIGIN-NEXT: [[TMP6:%.*]] = and i64 [[TMP5]], -4548; ORIGIN-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr549; ORIGIN-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[TMP4]], i8 -1, i64 [[TMP1]], i1 false)550; ORIGIN-NEXT: call void @__msan_set_alloca_origin_with_descr(ptr [[X]], i64 [[TMP1]], ptr @[[GLOB2:[0-9]+]], ptr @[[GLOB3:[0-9]+]])551; ORIGIN-NEXT: ret void552;553entry:554 %x = alloca <vscale x 64 x double>, align 4555 ret void556}557 558define void @test_alloca3() sanitize_memory {559; CHECK-LABEL: define void @test_alloca3(560; CHECK-SAME: ) #[[ATTR0]] {561; CHECK-NEXT: entry:562; CHECK-NEXT: call void @llvm.donothing()563; CHECK-NEXT: [[X:%.*]] = alloca <vscale x 1 x i1>, align 4564; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()565; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[X]] to i64566; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080567; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr568; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[TMP3]], i8 -1, i64 [[TMP0]], i1 false)569; CHECK-NEXT: ret void570;571; ORIGIN-LABEL: define void @test_alloca3(572; ORIGIN-SAME: ) #[[ATTR0]] {573; ORIGIN-NEXT: entry:574; ORIGIN-NEXT: call void @llvm.donothing()575; ORIGIN-NEXT: [[X:%.*]] = alloca <vscale x 1 x i1>, align 4576; ORIGIN-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()577; ORIGIN-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[X]] to i64578; ORIGIN-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080579; ORIGIN-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr580; ORIGIN-NEXT: [[TMP4:%.*]] = add i64 [[TMP2]], 17592186044416581; ORIGIN-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], -4582; ORIGIN-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr583; ORIGIN-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[TMP3]], i8 -1, i64 [[TMP0]], i1 false)584; ORIGIN-NEXT: call void @__msan_set_alloca_origin_with_descr(ptr [[X]], i64 [[TMP0]], ptr @[[GLOB4:[0-9]+]], ptr @[[GLOB5:[0-9]+]])585; ORIGIN-NEXT: ret void586;587entry:588 %x = alloca <vscale x 1 x i1>, align 4589 ret void590}591 592;.593; CHECK: [[PROF1]] = !{!"branch_weights", i32 1, i32 1048575}594;.595; ORIGIN: [[PROF1]] = !{!"branch_weights", i32 1, i32 1048575}596;.597