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1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-b16b16 2>&1 < %s | FileCheck %s2 3// --------------------------------------------------------------------------//4// Invalid predicate register5 6bfmopa za1.h, p8/m, p5/m, z12.h, z11.h7// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)8// CHECK-NEXT: bfmopa za1.h, p8/m, p5/m, z12.h, z11.h9// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:10 11bfmopa za1.h, p5/m, p8/m, z12.h, z11.h12// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)13// CHECK-NEXT: bfmopa za1.h, p5/m, p8/m, z12.h, z11.h14// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:15 16bfmopa za1.h, p5.h, p5/m, z12.h, z11.h17// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)18// CHECK-NEXT: bfmopa za1.h, p5.h, p5/m, z12.h, z11.h19// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:20 21// --------------------------------------------------------------------------//22// Invalid matrix operand23 24bfmopa za2.h, p5/m, p5/m, z12.h, z11.h25// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction26// CHECK-NEXT: bfmopa za2.h, p5/m, p5/m, z12.h, z11.h27// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:28 29// --------------------------------------------------------------------------//30// Invalid register suffixes31 32bfmopa za1.h, p5/m, p5/m, z12.h, z11.b33// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width34// CHECK-NEXT: bfmopa za1.h, p5/m, p5/m, z12.h, z11.b35// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:36