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1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s2 3// --------------------------------------------------------------------------//4// Invalid vector list5 6fclamp {z0.h-z2.h}, z0.h, z0.h7// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction8// CHECK-NEXT: fclamp {z0.h-z2.h}, z0.h, z0.h9// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:10 11fclamp {z0.d-z4.d}, z5.d, z6.d12// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors13// CHECK-NEXT: fclamp {z0.d-z4.d}, z5.d, z6.d14// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:15 16fclamp {z23.s-z24.s}, z13.s, z8.s17// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element type18// CHECK-NEXT: fclamp {z23.s-z24.s}, z13.s, z8.s19// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:20 21fclamp {z21.h-z24.h}, z10.h, z21.h22// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element type23// CHECK-NEXT: fclamp {z21.h-z24.h}, z10.h, z21.h24// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:25 26 27// --------------------------------------------------------------------------//28// Invalid Register Suffix29 30fclamp {z0.h-z1.h}, z0.h, z4.s31// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width32// CHECK-NEXT: fclamp {z0.h-z1.h}, z0.h, z4.s33// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:34 35fclamp {z0.s-z3.s}, z5.d, z6.d36// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width37// CHECK-NEXT: fclamp {z0.s-z3.s}, z5.d, z6.d38// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:39