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1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s2 3// --------------------------------------------------------------------------//4// Invalid vector list5 6fmax {z0.d, z1.d}, {z0.d-z2.d}, z0.d7// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction8// CHECK-NEXT: fmax {z0.d, z1.d}, {z0.d-z2.d}, z0.d9// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:10 11fmax {z1.s-z2.s}, {z0.s, z1.s}, z0.s12// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element type13// CHECK-NEXT: fmax {z1.s-z2.s}, {z0.s, z1.s}, z0.s14// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:15 16// --------------------------------------------------------------------------//17// Invalid single register18 19fmax {z0.h, z1.h}, {z2.h-z3.h}, z31.h20// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h21// CHECK-NEXT: fmax {z0.h, z1.h}, {z2.h-z3.h}, z31.h22// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:23 24// --------------------------------------------------------------------------//25// Invalid Register Suffix26 27fmax {z0.h, z1.h}, {z2.h-z3.h}, z14.d28// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h29// CHECK-NEXT: fmax {z0.h, z1.h}, {z2.h-z3.h}, z14.d30// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:31