75 lines · plain
1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s2 3// --------------------------------------------------------------------------//4// Invalid vector list5 6fmlsl za.s[w11, 6:7, vgx2], {z12.h-z14.h}, z8.h[3]7// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction8// CHECK-NEXT: fmlsl za.s[w11, 6:7, vgx2], {z12.h-z14.h}, z8.h[3]9// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:10 11fmlsl za.s[w11, 6:7, vgx4], {z12.h-z17.h}, z7.h12// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors13// CHECK-NEXT: fmlsl za.s[w11, 6:7, vgx4], {z12.h-z17.h}, z7.h14// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:15 16fmlsl za.s[w10, 2:3, vgx2], {z10.h-z11.h}, {z21.h-z22.h}17// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types18// CHECK-NEXT: fmlsl za.s[w10, 2:3, vgx2], {z10.h-z11.h}, {z21.h-z22.h}19// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:20 21// --------------------------------------------------------------------------//22// Invalid indexed-vector register23 24fmlsl za.s[w8, 0:1], z0.h, z17.h[0]25// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h26// CHECK-NEXT: fmlsl za.s[w8, 0:1], z0.h, z17.h[0]27// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:28 29fmlsl za.s[w8, 0:1], z0.h, z30.h30// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h31// CHECK-NEXT: fmlsl za.s[w8, 0:1], z0.h, z30.h32// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:33 34// --------------------------------------------------------------------------//35// Invalid vector select register36 37fmlsl za.s[w7, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}38// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]39// CHECK-NEXT: fmlsl za.s[w7, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}40// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:41 42fmlsl za.s[w12, 6:7, vgx4], {z12.h-z15.h}, z8.h[0]43// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]44// CHECK-NEXT: fmlsl za.s[w12, 6:7, vgx4], {z12.h-z15.h}, z8.h[0]45// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:46 47// --------------------------------------------------------------------------//48// Invalid vector select offset49 50fmlsl za.s[w8, 6:9, vgx2], {z12.h-z13.h}, {z8.h-z9.h}51// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction52// CHECK-NEXT: fmlsl za.s[w8, 6:9, vgx2], {z12.h-z13.h}, {z8.h-z9.h}53// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:54 55fmlsl za.s[w8, 9:10, vgx2], {z12.h-z13.h}, {z8.h-z9.h}56// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector select offset must be an immediate range of the form <immf>:<imml>, where the first immediate is a multiple of 2 in the range [0, 6] or [0, 14] depending on the instruction, and the second immediate is immf + 1.57// CHECK-NEXT: fmlsl za.s[w8, 9:10, vgx2], {z12.h-z13.h}, {z8.h-z9.h}58// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:59 60// --------------------------------------------------------------------------//61// Invalid Register Suffix62 63fmlsl za.h[w8, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}64// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .s65// CHECK-NEXT: fmlsl za.h[w8, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}66// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:67 68// --------------------------------------------------------------------------//69// Invalid vector lane index70 71fmlsl za.s[w11, 6:7, vgx4], {z12.h-z15.h}, z8.h[8]72// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].73// CHECK-NEXT: fmlsl za.s[w11, 6:7, vgx4], {z12.h-z15.h}, z8.h[8]74// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:75