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1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s2 3// --------------------------------------------------------------------------//4// Invalid vector list5 6smlal za.s[w8, 0:1, vgx2], {z0.h-z2.h}, z0.h[0]7// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction8// CHECK-NEXT: smlal za.s[w8, 0:1, vgx2], {z0.h-z2.h}, z0.h[0]9// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:10 11smlal za.s[w9, 6:7], {z13.h-z16.h}, {z9.h-z12.h}12// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction13// CHECK-NEXT: smlal za.s[w9, 6:7], {z13.h-z16.h}, {z9.h-z12.h}14// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:15 16// --------------------------------------------------------------------------//17// Invalid indexed-vector register18 19smlal za.s[w11, 14:15], z31.h, z15.b[7]20// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h21// CHECK-NEXT: smlal za.s[w11, 14:15], z31.h, z15.b[7]22// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:23 24smlal za.s[w11, 6:7, vgx2], {z12.h-z13.h}, z31.h[7]25// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h26// CHECK-NEXT: smlal za.s[w11, 6:7, vgx2], {z12.h-z13.h}, z31.h[7]27// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:28 29// --------------------------------------------------------------------------//30// Invalid vector select register31 32smlal za.s[w7, 6:7], {z12.h-z13.h}, {z8.h-z9.h}33// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]34// CHECK-NEXT: smlal za.s[w7, 6:7], {z12.h-z13.h}, {z8.h-z9.h}35// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:36 37smlal za.s[w12, 6:7, vgx4], {z12.h-z15.h}, z8.h[0]38// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]39// CHECK-NEXT: smlal za.s[w12, 6:7, vgx4], {z12.h-z15.h}, z8.h[0]40// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:41 42// --------------------------------------------------------------------------//43// Invalid vector select offset44 45smlal za.s[w11, 4:8], {z30.h-z31.h}, z15.h[15]46// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction47// CHECK-NEXT: smlal za.s[w11, 4:8], {z30.h-z31.h}, z15.h[15]48// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:49 50smlal za.s[w8, 10:12], z17.h, z0.h51// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction52// CHECK-NEXT: smlal za.s[w8, 10:12], z17.h, z0.h53// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:54 55// --------------------------------------------------------------------------//56// Invalid Register Suffix57 58smlal za.b[w8, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}59// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .s60// CHECK-NEXT: smlal za.b[w8, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}61// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:62 63// --------------------------------------------------------------------------//64// Invalid vector lane index65 66smlal za.s[w11, 6:7, vgx4], {z12.h-z15.h}, z8.h[8]67// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].68// CHECK-NEXT: smlal za.s[w11, 6:7, vgx4], {z12.h-z15.h}, z8.h[8]69// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:70 71smlal za.s[w11, 6:7, vgx4], {z12.h-z15.h}, z8.h[-1]72// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].73// CHECK-NEXT: smlal za.s[w11, 6:7, vgx4], {z12.h-z15.h}, z8.h[-1]74// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:75