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1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s2 3// --------------------------------------------------------------------------//4// Invalid vector list5 6sqcvtu z0.h, {z0.s-z2.s}7// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction8// CHECK-NEXT: sqcvtu z0.h, {z0.s-z2.s}9// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:10 11sqcvtu z0.b, {z1.s-z4.s}12// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element type13// CHECK-NEXT: sqcvtu z0.b, {z1.s-z4.s}14// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:15 16sqcvtu z0.h, {z1.d-z2.d}17// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction18// CHECK-NEXT: sqcvtu z0.h, {z1.d-z2.d}19// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:20 21// --------------------------------------------------------------------------//22// Invalid Register Suffix23 24sqcvtu z0.s, {z0.s-z1.s}25// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width26// CHECK-NEXT: sqcvtu z0.s, {z0.s-z1.s}27// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:28