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1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sme-i16i64 2>&1 < %s | FileCheck %s2 3// --------------------------------------------------------------------------//4// Invalid vector list5 6sqdmulh {z0.h-z2.h}, {z0.h-z1.h}, z0.h7// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction8// CHECK-NEXT: sqdmulh {z0.h-z2.h}, {z0.h-z1.h}, z0.h9// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:10 11sqdmulh {z28.s-z31.s}, {z0.s-z4.s}, z15.s12// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors13// CHECK-NEXT: sqdmulh {z28.s-z31.s}, {z0.s-z4.s}, z15.s14// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:15 16sqdmulh {z1.d-z4.d}, {z0.d-z3.d}, z0.d17// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types18// CHECK-NEXT: sqdmulh {z1.d-z4.d}, {z0.d-z3.d}, z0.d19// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:20 21sqdmulh {z28.b-z29.b}, {z1.b-z2.b}, z15.b22// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types23// CHECK-NEXT: sqdmulh {z28.b-z29.b}, {z1.b-z2.b}, z15.b24// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:25 26sqdmulh {z28.h-z29.h}, {z1.h-z2.h}, z15.b27// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types28// CHECK-NEXT: sqdmulh {z28.h-z29.h}, {z1.h-z2.h}, z15.b29// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:30 31sqdmulh {z1.d-z4.d}, {z1.d-z4.d}, {z8.d-z11.d}32// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types33// CHECK-NEXT: sqdmulh {z1.d-z4.d}, {z1.d-z4.d}, {z8.d-z11.d}34// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:35 36sqdmulh {z1.d-z2.d}, {z1.d-z2.d}, {z2.d-z3.d}37// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types38// CHECK-NEXT: sqdmulh {z1.d-z2.d}, {z1.d-z2.d}, {z2.d-z3.d}39// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}40 41// --------------------------------------------------------------------------//42// Invalid single vector register43 44sqdmulh {z28.b-z29.b}, {z0.b-z1.b}, z16.b45// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b46// CHECK-NEXT: sqdmulh {z28.b-z29.b}, {z0.b-z1.b}, z16.b47// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:48 49// --------------------------------------------------------------------------//50// Invalid register suffix51 52sqdmulh {z0.d-z3.d}, {z0.d-z3.d}, z0.b53// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.d..z15.d54// CHECK-NEXT: sqdmulh {z0.d-z3.d}, {z0.d-z3.d}, z0.b55// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:56 57sqdmulh {z0.d-z3.h}, {z0.d-z3.d}, z0.b58// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix59// CHECK-NEXT: sqdmulh {z0.d-z3.h}, {z0.d-z3.d}, z0.b60// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:61 62// --------------------------------------------------------------------------//63// The tied operands must match, even for vector groups.64 65sqdmulh {z0.s-z1.s}, {z2.s-z3.s}, z15.s66// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register list67// CHECK-NEXT: sqdmulh {z0.s-z1.s}, {z2.s-z3.s}, z15.s68// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:69 70sqdmulh {z0.s,z1.s}, {z2.s,z3.s}, z15.s71// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register list72// CHECK-NEXT: sqdmulh {z0.s,z1.s}, {z2.s,z3.s}, z15.s73// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:74 75sqdmulh {z0.s,z1.s}, {z0.s,z2.s}, z15.s76// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction77// CHECK-NEXT: sqdmulh {z0.s,z1.s}, {z0.s,z2.s}, z15.s78// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:79 80sqdmulh {z0.s,z1.s}, {z0.s,z1.s,z2.s}, z15.s81// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction82// CHECK-NEXT: sqdmulh {z0.s,z1.s}, {z0.s,z1.s,z2.s}, z15.s83// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:84 85sqdmulh {z0.s,z1.s}, {z0.d,z1.d}, z15.s86// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction87// CHECK-NEXT: sqdmulh {z0.s,z1.s}, {z0.d,z1.d}, z15.s88// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:89 90sqdmulh {z2.d,z3.d}, {z0.d,z1.d}, {z4.d,z5.d}91// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register list92// CHECK-NEXT: sqdmulh {z2.d,z3.d}, {z0.d,z1.d}, {z4.d,z5.d}93// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:94 95sqdmulh {z0.d-z3.d}, {z4.d-z7.d}, {z0.d-z3.d}96// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register list97// CHECK-NEXT: sqdmulh {z0.d-z3.d}, {z4.d-z7.d}, {z0.d-z3.d}98// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:99