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1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s2 3// --------------------------------------------------------------------------//4// Invalid select register5 6udot za.s[w7, 0, vgx4], {z0.h-z3.h}, z0.h[0]7// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]8// CHECK-NEXT: udot za.s[w7, 0, vgx4], {z0.h-z3.h}, z0.h[0]9// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:10 11udot za.s[w12, 0, vgx2], {z0.h-z1.h}, z0.h[0]12// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]13// CHECK-NEXT: udot za.s[w12, 0, vgx2], {z0.h-z1.h}, z0.h[0]14// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:15 16// --------------------------------------------------------------------------//17// Invalid select offset18 19udot za.s[w8, 8], {z0.h-z1.h}, z0.h[0]20// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].21// CHECK-NEXT: udot za.s[w8, 8], {z0.h-z1.h}, z0.h[0]22// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:23 24udot za.s[w8, -1], {z0.h-z1.h}, z0.h[0]25// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].26// CHECK-NEXT: udot za.s[w8, -1], {z0.h-z1.h}, z0.h[0]27// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:28 29// --------------------------------------------------------------------------//30// Out of range element index31 32udot za.s[w8, 0], {z0.h-z1.h}, z0.h[4]33// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].34// CHECK-NEXT: udot za.s[w8, 0], {z0.h-z1.h}, z0.h[4]35// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:36 37udot za.s[w8, 0], {z0.h-z3.h}, z0.h[4]38// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].39// CHECK-NEXT: udot za.s[w8, 0], {z0.h-z3.h}, z0.h[4]40// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:41 42// --------------------------------------------------------------------------//43// ZPR range constraint44 45udot za.s[w8, 5], {z0.h-z1.h}, z16.h[0]46// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h47// CHECK-NEXT: udot za.s[w8, 5], {z0.h-z1.h}, z16.h[0]48// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:49 50udot za.s[w8, 5], {z0.h-z3.h}, z16.h[0]51// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h52// CHECK-NEXT: udot za.s[w8, 5], {z0.h-z3.h}, z16.h[0]53// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:54