31 lines · plain
1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s2 3// --------------------------------------------------------------------------//4// Invalid vector list5 6umin {z0.h, z1.h}, {z0.h-z2.h}, z0.h7// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction8// CHECK-NEXT: umin {z0.h, z1.h}, {z0.h-z2.h}, z0.h9// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:10 11umin {z1.d-z2.d}, {z0.d, z1.d}, z0.d12// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element type13// CHECK-NEXT: umin {z1.d-z2.d}, {z0.d, z1.d}, z0.d14// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:15 16// --------------------------------------------------------------------------//17// Invalid single register18 19umin {z0.b, z1.b}, {z2.b-z3.b}, z31.b20// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b21// CHECK-NEXT: umin {z0.b, z1.b}, {z2.b-z3.b}, z31.b22// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:23 24// --------------------------------------------------------------------------//25// Invalid Register Suffix26 27umin {z0.b, z1.b}, {z2.b-z3.b}, z14.d28// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b29// CHECK-NEXT: umin {z0.b, z1.b}, {z2.b-z3.b}, z14.d30// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:31