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1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s2 3// --------------------------------------------------------------------------//4// Invalid vector list5 6urshl {z0.h-z2.h}, {z0.h-z1.h}, z0.h7// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction8// CHECK-NEXT: urshl {z0.h-z2.h}, {z0.h-z1.h}, z0.h9// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:10 11urshl {z0.s-z1.s}, {z2.s-z4.s}, z0.s12// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction13// CHECK-NEXT: urshl {z0.s-z1.s}, {z2.s-z4.s}, z0.s14// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:15 16urshl {z20.d-z23.d}, {z20.d-z23.d}, {z8.d-z12.d}17// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors18// CHECK-NEXT: urshl {z20.d-z23.d}, {z20.d-z23.d}, {z8.d-z12.d}19// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:20 21urshl {z29.b-z30.b}, {z30.b-z31.b}, z15.b22// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types23// CHECK-NEXT: urshl {z29.b-z30.b}, {z30.b-z31.b}, z15.b24// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:25 26urshl {z20.h-z23.h}, {z21.h-z24.h}, {z8.h-z11.h}27// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types28// CHECK-NEXT: urshl {z20.h-z23.h}, {z21.h-z24.h}, {z8.h-z11.h}29// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:30 31urshl {z28.b-z31.b}, {z28.b-z31.b}, {z27.b-z30.b}32// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types33// CHECK-NEXT: urshl {z28.b-z31.b}, {z28.b-z31.b}, {z27.b-z30.b}34// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:35 36// --------------------------------------------------------------------------//37// Invalid Single Register38 39urshl {z20.h-z21.h}, {z20.h-z21.h}, z16.h40// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h41// CHECK-NEXT: urshl {z20.h-z21.h}, {z20.h-z21.h}, z16.h42// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:43 44// --------------------------------------------------------------------------//45// Invalid Register Suffix46 47urshl {z0.d-z3.d}, {z0.d-z3.d}, z0.s48// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.d..z15.d49// CHECK-NEXT: urshl {z0.d-z3.d}, {z0.d-z3.d}, z0.s50// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:51