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1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s2 3// --------------------------------------------------------------------------//4// Invalid select register5 6usdot za.s[w7, 0, vgx2], {z0.b-z1.b}, z0.b[0]7// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]8// CHECK-NEXT: usdot za.s[w7, 0, vgx2], {z0.b-z1.b}, z0.b[0]9// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:10 11usdot za.s[w12, 0, vgx4], {z0.b-z3.b}, z0.b[0]12// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]13// CHECK-NEXT: usdot za.s[w12, 0, vgx4], {z0.b-z3.b}, z0.b[0]14// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:15 16// --------------------------------------------------------------------------//17// Invalid select offset18 19usdot za.s[w8, 16], {z0.b-z1.b}, z0.b[0]20// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].21// CHECK-NEXT: usdot za.s[w8, 16], {z0.b-z1.b}, z0.b[0]22// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:23 24// --------------------------------------------------------------------------//25// Out of range element index26 27usdot za.s[w8, 0], {z0.b-z1.b}, z0.b[4]28// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].29// CHECK-NEXT: usdot za.s[w8, 0], {z0.b-z1.b}, z0.b[4]30// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:31 32usdot za.s[w8, 0], {z0.b-z3.b}, z0.b[4]33// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].34// CHECK-NEXT: usdot za.s[w8, 0], {z0.b-z3.b}, z0.b[4]35// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:36 37// --------------------------------------------------------------------------//38// ZPR range constraint39 40usdot za.s[w8, 5], {z0.b-z1.b}, z16.b[0]41// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b42// CHECK-NEXT: usdot za.s[w8, 5], {z0.b-z1.b}, z16.b[0]43// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:44 45usdot za.s[w8, 5], {z0.b-z3.b}, z16.b[0]46// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b47// CHECK-NEXT: usdot za.s[w8, 5], {z0.b-z3.b}, z16.b[0]48// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:49