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1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 2>&1 < %s | FileCheck %s2 3// --------------------------------------------------------------------------//4// Invalid vector list5 6fcvt z0.h, {z0.s-z2.s}7// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction8// CHECK-NEXT: fcvt z0.h, {z0.s-z2.s}9// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:10 11fcvt {z0.s-z2.s}, z0.h12// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction13// CHECK-NEXT: fcvt {z0.s-z2.s}, z0.h14// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:15 16fcvt z0.h, {z1.s-z2.s}17// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types18// CHECK-NEXT: fcvt z0.h, {z1.s-z2.s}19// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:20 21fcvt {z1.s-z2.s}, z0.h22// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types23// CHECK-NEXT: fcvt {z1.s-z2.s}, z0.h24// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:25 26// --------------------------------------------------------------------------//27// Invalid Register Suffix28 29fcvt z0.s, {z0.s-z1.s}30// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction31// CHECK-NEXT: fcvt z0.s, {z0.s-z1.s}32// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:33 34fcvt z0.h, {z0.h-z1.h}35// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction36// CHECK-NEXT: fcvt z0.h, {z0.h-z1.h}37// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:38 39fcvt {z0.s-z1.s}, z0.s40// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width41// CHECK-NEXT: fcvt {z0.s-z1.s}, z0.s42// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:43 44fcvt {z0.h-z1.h}, z0.h45// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction46// CHECK-NEXT: fcvt {z0.h-z1.h}, z0.h47// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:48