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1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 2>&1 < %s | FileCheck %s2 3// --------------------------------------------------------------------------//4// Invalid vector list5 6fcvtl {z0.s-z2.s}, z0.h7// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction8// CHECK-NEXT: fcvtl {z0.s-z2.s}, z0.h9// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:10 11fcvtl z0.h, {z1.s-z2.s}12// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected13// CHECK-NEXT: fcvtl z0.h, {z1.s-z2.s}14// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:15 16fcvtl {z1.s-z2.s}, z0.h17// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types18// CHECK-NEXT: fcvtl {z1.s-z2.s}, z0.h19// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:20 21// --------------------------------------------------------------------------//22// Invalid Register Suffix23 24fcvtl {z0.s-z1.s}, z0.s25// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width26// CHECK-NEXT: fcvtl {z0.s-z1.s}, z0.s27// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:28 29fcvtl {z0.h-z1.h}, z0.h30// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction31// CHECK-NEXT: fcvtl {z0.h-z1.h}, z0.h32// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:33