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1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 2>&1 < %s | FileCheck %s2// --------------------------------------------------------------------------//3// Out of range index offset4 5fsub za.d[w8, 8, vgx2], {z0.d-z1.d}6// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .s7// CHECK-NEXT: fsub za.d[w8, 8, vgx2], {z0.d-z1.d}8// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:9 10fsub za.s[w8, -1, vgx4], {z0.s-z3.s}11// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].12// CHECK-NEXT: fsub za.s[w8, -1, vgx4], {z0.s-z3.s}13// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:14 15// --------------------------------------------------------------------------//16// Invalid vector select register17 18fsub za.h[w7, 7, vgx4], {z0.h-z3.h}19// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]20// CHECK-NEXT: fsub za.h[w7, 7, vgx4], {z0.h-z3.h}21// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:22 23fsub za.s[w12, 7, vgx2], {z0.s-z1.s}24// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]25// CHECK-NEXT: fsub za.s[w12, 7, vgx2], {z0.s-z1.s}26// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:27 28// --------------------------------------------------------------------------//29// Invalid vector list30 31fsub za.d[w8, 0, vgx4], {z0.d-z4.d}32// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors33// CHECK-NEXT: fsub za.d[w8, 0, vgx4], {z0.d-z4.d}34// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:35 36fsub za.h[w8, 0, vgx2], {z1.h-z2.h}37// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types38// CHECK-NEXT: fsub za.h[w8, 0, vgx2], {z1.h-z2.h}39// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:40 41fsub za.s[w8, 0, vgx4], {z1.s-z4.s}42// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types43// CHECK-NEXT: fsub za.s[w8, 0, vgx4], {z1.s-z4.s}44// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:45