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1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-mop4,+sme-i16i64 2>&1 < %s| FileCheck %s2 3// ------------------------------------------------------------------------- //4// Invalid tile5//6// expected: .s => za0-za3, .d => za0-za77 8sumop4a za4.s, z0.b, z16.b9// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction10// CHECK-NEXT: sumop4a za4.s, z0.b, z16.b11// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:12 13sumop4a za8.d, z0.h, z16.h14// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction15// CHECK-NEXT: sumop4a za8.d, z0.h, z16.h16// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:17 18// ------------------------------------------------------------------------- //19// Invalid first operand (expected z0..z15)20 21sumop4a za0.d, z16.h, z16.h22// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h23// CHECK-NEXT: sumop4a za0.d, z16.h, z16.h24// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:25 26sumop4a za0.d, {z16.h-z17.h}, z16.h27// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types28// CHECK-NEXT: sumop4a za0.d, {z16.h-z17.h}, z16.h29// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:30 31// ------------------------------------------------------------------------- //32// Invalid second operand (expected z16..z31)33 34sumop4a za0.d, z14.h, z14.h35// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h36// CHECK-NEXT: sumop4a za0.d, z14.h, z14.h37// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:38 39sumop4a za0.d, z14.h, {z14.h-z15.h}40// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types41// CHECK-NEXT: sumop4a za0.d, z14.h, {z14.h-z15.h}42// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:43 44 45// ------------------------------------------------------------------------- //46// Invalid ZPR type suffix47//48// expected: .s => .b, .d => .h49 50sumop4a za3.s, z0.h, z16.b51// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.b..z14.b52// CHECK-NEXT: sumop4a za3.s, z0.h, z16.b53// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:54 55sumop4a za3.s, z0.b, z16.s56// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.b..z30.b57// CHECK-NEXT: sumop4a za3.s, z0.b, z16.s58// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:59 60sumop4a za3.d, z0.h, z16.b61// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h62// CHECK-NEXT: sumop4a za3.d, z0.h, z16.b63// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:64 65sumop4a za3.d, z0.s, z16.h66// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h67// CHECK-NEXT: sumop4a za3.d, z0.s, z16.h68// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:69