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1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s2 3 4// ------------------------------------------------------------------------- //5// Tied operands must match6 7fdivr z0.h, p7/m, z1.h, z31.h8// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register9// CHECK-NEXT: fdivr z0.h, p7/m, z1.h, z31.h10// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:11 12 13// ------------------------------------------------------------------------- //14// Invalid element widths.15 16fdivr z0.b, p7/m, z0.b, z31.b17// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width18// CHECK-NEXT: fdivr z0.b, p7/m, z0.b, z31.b19// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:20 21fdivr z0.h, p7/m, z0.h, z31.s22// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width23// CHECK-NEXT: fdivr z0.h, p7/m, z0.h, z31.s24// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:25 26 27// ------------------------------------------------------------------------- //28// Invalid predicate29 30fdivr z0.h, p8/m, z0.h, z31.h31// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)32// CHECK-NEXT: fdivr z0.h, p8/m, z0.h, z31.h33// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:34