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1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s2 3// --------------------------------------------------------------------------//4// Immediate out of lower bound [-128, 112].5 6ld1rqw z0.s, p0/z, [x0, #-144]7// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 16 in range [-128, 112].8// CHECK-NEXT: ld1rqw z0.s, p0/z, [x0, #-144]9// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:10 11ld1rqw z0.s, p0/z, [x0, #-129]12// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 16 in range [-128, 112].13// CHECK-NEXT: ld1rqw z0.s, p0/z, [x0, #-129]14// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:15 16ld1rqw z0.s, p0/z, [x0, #113]17// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 16 in range [-128, 112].18// CHECK-NEXT: ld1rqw z0.s, p0/z, [x0, #113]19// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:20 21ld1rqw z0.s, p0/z, [x0, #128]22// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 16 in range [-128, 112].23// CHECK-NEXT: ld1rqw z0.s, p0/z, [x0, #128]24// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:25 26ld1rqw z0.s, p0/z, [x0, #12]27// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 16 in range [-128, 112].28// CHECK-NEXT: ld1rqw z0.s, p0/z, [x0, #12]29// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:30 31 32// --------------------------------------------------------------------------//33// Invalid immediate suffix34 35ld1rqw z0.s, p0/z, [x0, #16, MUL VL]36// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand37// CHECK-NEXT: ld1rqw z0.s, p0/z, [x0, #16, MUL VL]38// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:39 40 41// --------------------------------------------------------------------------//42// Invalid destination register width.43 44ld1rqw z0.b, p0/z, [x0, x1, lsl #2]45// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width46// CHECK-NEXT: ld1rqw z0.b, p0/z, [x0, x1, lsl #2]47// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:48 49ld1rqw z0.h, p0/z, [x0, x1, lsl #2]50// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width51// CHECK-NEXT: ld1rqw z0.h, p0/z, [x0, x1, lsl #2]52// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:53 54ld1rqw z0.d, p0/z, [x0, x1, lsl #2]55// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width56// CHECK-NEXT: ld1rqw z0.d, p0/z, [x0, x1, lsl #2]57// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:58 59 60// --------------------------------------------------------------------------//61// Invalid scalar + scalar addressing modes62 63ld1rqw z0.s, p0/z, [x0, xzr, lsl #2]64// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'65// CHECK-NEXT: ld1rqw z0.s, p0/z, [x0, xzr, lsl #2]66// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:67 68ld1rqw z0.s, p0/z, [x0, x1, lsl #3]69// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'70// CHECK-NEXT: ld1rqw z0.s, p0/z, [x0, x1, lsl #3]71// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:72 73ld1rqw z0.s, p0/z, [x0, w1, lsl #2]74// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'75// CHECK-NEXT: ld1rqw z0.s, p0/z, [x0, w1, lsl #2]76// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:77 78ld1rqw z0.s, p0/z, [x0, w1, uxtw #1]79// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'80// CHECK-NEXT: ld1rqw z0.s, p0/z, [x0, w1, uxtw #1]81// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:82 83 84// --------------------------------------------------------------------------//85// Negative tests for instructions that are incompatible with movprfx86 87movprfx z23.s, p3/z, z30.s88ld1rqw { z23.s }, p3/z, [x13, #112]89// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov90// CHECK-NEXT: ld1rqw { z23.s }, p3/z, [x13, #112]91// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:92 93movprfx z23, z3094ld1rqw { z23.s }, p3/z, [x13, #112]95// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov96// CHECK-NEXT: ld1rqw { z23.s }, p3/z, [x13, #112]97// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:98