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1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s2 3 4// --------------------------------------------------------------------------//5// Immediate out of lower bound [-32, 28].6 7ld4d {z12.d, z13.d, z14.d, z15.d}, p4/z, [x12, #-36, MUL VL]8// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28].9// CHECK-NEXT: ld4d {z12.d, z13.d, z14.d, z15.d}, p4/z, [x12, #-36, MUL VL]10// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:11 12ld4d {z7.d, z8.d, z9.d, z10.d}, p3/z, [x1, #32, MUL VL]13// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28].14// CHECK-NEXT: ld4d {z7.d, z8.d, z9.d, z10.d}, p3/z, [x1, #32, MUL VL]15// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:16 17 18// --------------------------------------------------------------------------//19// Immediate not a multiple of four.20 21ld4d {z12.d, z13.d, z14.d, z15.d}, p4/z, [x12, #-7, MUL VL]22// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28].23// CHECK-NEXT: ld4d {z12.d, z13.d, z14.d, z15.d}, p4/z, [x12, #-7, MUL VL]24// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:25 26ld4d {z7.d, z8.d, z9.d, z10.d}, p3/z, [x1, #5, MUL VL]27// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28].28// CHECK-NEXT: ld4d {z7.d, z8.d, z9.d, z10.d}, p3/z, [x1, #5, MUL VL]29// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:30 31 32// --------------------------------------------------------------------------//33// Invalid scalar + scalar addressing modes34 35ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, x0]36// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'37// CHECK-NEXT: ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, x0]38// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:39 40ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, xzr]41// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'42// CHECK-NEXT: ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, xzr]43// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:44 45ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, x0, lsl #2]46// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'47// CHECK-NEXT: ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, x0, lsl #2]48// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:49 50ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, w0]51// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'52// CHECK-NEXT: ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, w0]53// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:54 55ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, w0, uxtw]56// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'57// CHECK-NEXT: ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, w0, uxtw]58// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:59 60 61// --------------------------------------------------------------------------//62// error: invalid restricted predicate register, expected p0..p7 (without element suffix)63 64ld4d {z2.d, z3.d, z4.d, z5.d}, p8/z, [x15, #10, MUL VL]65// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)66// CHECK-NEXT: ld4d {z2.d, z3.d, z4.d, z5.d}, p8/z, [x15, #10, MUL VL]67// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:68 69 70// --------------------------------------------------------------------------//71// Invalid vector list.72 73ld4d { }, p0/z, [x0]74// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected75// CHECK-NEXT: ld4d { }, p0/z, [x0]76// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:77 78ld4d { z0.d, z1.d, z2.d, z3.d, z4.d }, p0/z, [x0]79// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors80// CHECK-NEXT: ld4d { z0.d, z1.d, z2.d, z3.d, z4.d }, p0/z, [x0]81// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:82 83ld4d { z0.d, z1.d, z2.d, z3.b }, p0/z, [x0]84// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix85// CHECK-NEXT: ld4d { z0.d, z1.d, z2.d, z3.b }, p0/z, [x0]86// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:87 88ld4d { z0.d, z1.d, z3.d, z5.d }, p0/z, [x0]89// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride90// CHECK-NEXT: ld4d { z0.d, z1.d, z3.d, z5.d }, p0/z, [x0]91// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:92 93ld4d { v0.2d, v1.2d, v2.2d }, p0/z, [x0]94// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand95// CHECK-NEXT: ld4d { v0.2d, v1.2d, v2.2d }, p0/z, [x0]96// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:97 98 99// --------------------------------------------------------------------------//100// Negative tests for instructions that are incompatible with movprfx101 102movprfx z21.d, p5/z, z28.d103ld4d { z21.d, z22.d, z23.d, z24.d }, p5/z, [x10, #20, mul vl]104// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov105// CHECK-NEXT: ld4d { z21.d, z22.d, z23.d, z24.d }, p5/z, [x10, #20, mul vl]106// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:107 108movprfx z21, z28109ld4d { z21.d, z22.d, z23.d, z24.d }, p5/z, [x10, #20, mul vl]110// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov111// CHECK-NEXT: ld4d { z21.d, z22.d, z23.d, z24.d }, p5/z, [x10, #20, mul vl]112// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:113