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1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve,+f32mm,+f64mm 2>&1 < %s | FileCheck %s2 3// --------------------------------------------------------------------------//4// FMMLA (SVE)5 6// Mis-matched element size7 8fmmla z0.d, z1.s, z2.s9// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width10fmmla z0.s, z1.d, z2.s11// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width12fmmla z0.s, z1.s, z2.d13// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width14 15 16// --------------------------------------------------------------------------//17// LD1RO (SVE, scalar plus immediate)18 19// Immediate too high (>224)20ld1rob { z0.b }, p1/z, [x2, #256]21// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 32 in range [-256, 224].22ld1roh { z0.h }, p1/z, [x2, #256]23// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 32 in range [-256, 224].24ld1row { z0.s }, p1/z, [x2, #256]25// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 32 in range [-256, 224].26ld1rod { z0.d }, p1/z, [x2, #256]27// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 32 in range [-256, 224].28 29// Immediate too low (<-256)30ld1rob { z0.b }, p1/z, [x2, #-288]31// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 32 in range [-256, 224].32ld1roh { z0.h }, p1/z, [x2, #-288]33// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 32 in range [-256, 224].34ld1row { z0.s }, p1/z, [x2, #-288]35// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 32 in range [-256, 224].36ld1rod { z0.d }, p1/z, [x2, #-288]37// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 32 in range [-256, 224].38 39// Immediate not a multiple of 3240ld1rob { z0.b }, p1/z, [x2, #16]41// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 32 in range [-256, 224].42ld1roh { z0.h }, p1/z, [x2, #16]43// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 32 in range [-256, 224].44ld1row { z0.s }, p1/z, [x2, #16]45// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 32 in range [-256, 224].46ld1rod { z0.d }, p1/z, [x2, #16]47// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 32 in range [-256, 224].48 49// Prediate register too high50ld1rob { z0.b }, p8/z, [x2]51// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)52ld1roh { z0.h }, p8/z, [x2]53// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)54ld1row { z0.s }, p8/z, [x2]55// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)56ld1rod { z0.d }, p8/z, [x2]57// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)58 59 60// --------------------------------------------------------------------------//61// LD1RO (SVE, scalar plus scalar)62 63// Shift amount not matched to data width64ld1rob { z0.b }, p1/z, [x2, x3, lsl #1]65// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift66ld1roh { z0.h }, p1/z, [x2, x3, lsl #0]67// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'68ld1row { z0.s }, p1/z, [x2, x3, lsl #3]69// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'70ld1rod { z0.d }, p1/z, [x2, x3, lsl #2]71// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'72 73// Prediate register too high74ld1rob { z0.b }, p8/z, [x2, x3, lsl #0]75// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)76ld1roh { z0.h }, p8/z, [x2, x3, lsl #1]77// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)78ld1row { z0.s }, p8/z, [x2, x3, lsl #2]79// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)80ld1rod { z0.d }, p8/z, [x2, x3, lsl #3]81// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)82