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1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s2 3// --------------------------------------------------------------------------//4// Immediate not compatible with encode/decode function.5 6orn z5.b, z5.b, #0xfa7// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate8// CHECK-NEXT: orn z5.b, z5.b, #0xfa9// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:10 11orn z5.b, z5.b, #0xfff912// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate13// CHECK-NEXT: orn z5.b, z5.b, #0xfff914// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:15 16orn z5.h, z5.h, #0xfffa17// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate18// CHECK-NEXT: orn z5.h, z5.h, #0xfffa19// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:20 21orn z5.h, z5.h, #0xfffffff922// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate23// CHECK-NEXT: orn z5.h, z5.h, #0xfffffff924// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:25 26orn z5.s, z5.s, #0xfffffffa27// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate28// CHECK-NEXT: orn z5.s, z5.s, #0xfffffffa29// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:30 31orn z5.s, z5.s, #0xffffffffffffff932// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate33// CHECK-NEXT: orn z5.s, z5.s, #0xffffffffffffff934// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:35 36orn z15.d, z15.d, #0xfffffffffffffffa37// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate38// CHECK-NEXT: orn z15.d, z15.d, #0xfffffffffffffffa39// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:40 41// --------------------------------------------------------------------------//42// Source and Destination Registers must match43 44orn z7.d, z8.d, #25445// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register46// CHECK-NEXT: orn z7.d, z8.d, #25447// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:48 49orn z7.d, z8.d, #25450// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register51// CHECK-NEXT: orn z7.d, z8.d, #25452// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:53 54 55// --------------------------------------------------------------------------//56// Predicate register must have .b suffix57 58orn p0.h, p0/z, p0.h, p1.h59// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.60// CHECK-NEXT: orn p0.h, p0/z, p0.h, p1.h61// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:62 63orn p0.s, p0/z, p0.s, p1.s64// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.65// CHECK-NEXT: orn p0.s, p0/z, p0.s, p1.s66// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:67 68orn p0.d, p0/z, p0.d, p1.d69// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.70// CHECK-NEXT: orn p0.d, p0/z, p0.d, p1.d71// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:72 73// --------------------------------------------------------------------------//74// Operation only has zeroing predicate behaviour (p0/z).75 76orn p0.b, p0/m, p1.b, p2.b77// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand78// CHECK-NEXT: orn p0.b, p0/m, p1.b, p2.b79// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:80 81 82// --------------------------------------------------------------------------//83// Negative tests for instructions that are incompatible with movprfx84 85movprfx z0.d, p0/z, z7.d86orn z0.d, z0.d, #0x687// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx88// CHECK-NEXT: orn z0.d, z0.d, #0x689// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:90