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1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s2 3// --------------------------------------------------------------------------//4// Immediate out of upper bound [-8, 7].5 6st1b z10.b, p4, [x8, #-9, MUL VL]7// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].8// CHECK-NEXT: st1b z10.b, p4, [x8, #-9, MUL VL]9// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:10 11st1b z18.b, p4, [x24, #8, MUL VL]12// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].13// CHECK-NEXT: st1b z18.b, p4, [x24, #8, MUL VL]14// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:15 16st1b z11.h, p0, [x23, #-9, MUL VL]17// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].18// CHECK-NEXT: st1b z11.h, p0, [x23, #-9, MUL VL]19// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:20 21st1b z24.h, p3, [x1, #8, MUL VL]22// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].23// CHECK-NEXT: st1b z24.h, p3, [x1, #8, MUL VL]24// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:25 26st1b z6.s, p5, [x23, #-9, MUL VL]27// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].28// CHECK-NEXT: st1b z6.s, p5, [x23, #-9, MUL VL]29// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:30 31st1b z16.s, p6, [x14, #8, MUL VL]32// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].33// CHECK-NEXT: st1b z16.s, p6, [x14, #8, MUL VL]34// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:35 36st1b z26.d, p2, [x7, #-9, MUL VL]37// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].38// CHECK-NEXT: st1b z26.d, p2, [x7, #-9, MUL VL]39// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:40 41st1b z27.d, p1, [x12, #8, MUL VL]42// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].43// CHECK-NEXT: st1b z27.d, p1, [x12, #8, MUL VL]44// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:45 46// --------------------------------------------------------------------------//47// Invalid predicate48 49st1b z12.b, p8, [x27, #6, MUL VL]50// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)51// CHECK-NEXT: st1b z12.b, p8, [x27, #6, MUL VL]52// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:53 54st1b z23.h, p8, [x20, #1, MUL VL]55// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)56// CHECK-NEXT: st1b z23.h, p8, [x20, #1, MUL VL]57// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:58 59st1b z6.s, p8, [x0, #8, MUL VL]60// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)61// CHECK-NEXT: st1b z6.s, p8, [x0, #8, MUL VL]62// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:63 64st1b z14.d, p8, [x6, #5, MUL VL]65// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)66// CHECK-NEXT: st1b z14.d, p8, [x6, #5, MUL VL]67// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:68 69st1b z14.d, p7.b, [x6, #5, MUL VL]70// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)71// CHECK-NEXT: st1b z14.d, p7.b, [x6, #5, MUL VL]72// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:73 74st1b z14.d, p7.q, [x6, #5, MUL VL]75// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)76// CHECK-NEXT: st1b z14.d, p7.q, [x6, #5, MUL VL]77// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:78 79// --------------------------------------------------------------------------//80// Invalid vector list81 82st1b { }, p0, [x0]83// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected84// CHECK-NEXT: st1b { }, p0, [x0]85// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:86 87st1b { z1.b, z2.b }, p0, [x0]88// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand89// CHECK-NEXT: st1b { z1.b, z2.b }, p0, [x0]90// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:91 92st1b { v0.16b }, p0, [x0]93// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand94// CHECK-NEXT: st1b { v0.16b }, p0, [x0]95// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:96 97 98// --------------------------------------------------------------------------//99// Invalid scalar + scalar addressing modes100 101st1b z0.b, p0, [x0, xzr]102// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift103// CHECK-NEXT: st1b z0.b, p0, [x0, xzr]104// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:105 106st1b z0.b, p0, [x0, x0, lsl #1]107// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift108// CHECK-NEXT: st1b z0.b, p0, [x0, x0, lsl #1]109// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:110 111st1b z0.b, p0, [x0, w0]112// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift113// CHECK-NEXT: st1b z0.b, p0, [x0, w0]114// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:115 116st1b z0.b, p0, [x0, w0, uxtw]117// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift118// CHECK-NEXT: st1b z0.b, p0, [x0, w0, uxtw]119// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:120 121 122// --------------------------------------------------------------------------//123// Invalid scalar + vector addressing modes124 125st1b z0.d, p0, [x0, z0.b]126// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand127// CHECK-NEXT: st1b z0.d, p0, [x0, z0.b]128// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:129 130st1b z0.d, p0, [x0, z0.h]131// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand132// CHECK-NEXT: st1b z0.d, p0, [x0, z0.h]133// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:134 135st1b z0.d, p0, [x0, z0.s]136// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand137// CHECK-NEXT: st1b z0.d, p0, [x0, z0.s]138// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:139 140st1b z0.s, p0, [x0, z0.s]141// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'142// CHECK-NEXT: st1b z0.s, p0, [x0, z0.s]143// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:144 145st1b z0.s, p0, [x0, z0.s, uxtw #1]146// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'147// CHECK-NEXT: st1b z0.s, p0, [x0, z0.s, uxtw #1]148// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:149 150st1b z0.s, p0, [x0, z0.s, lsl #0]151// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'152// CHECK-NEXT: st1b z0.s, p0, [x0, z0.s, lsl #0]153// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:154 155st1b z0.d, p0, [x0, z0.d, lsl #1]156// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'157// CHECK-NEXT: st1b z0.d, p0, [x0, z0.d, lsl #1]158// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:159 160st1b z0.d, p0, [x0, z0.d, sxtw #1]161// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'162// CHECK-NEXT: st1b z0.d, p0, [x0, z0.d, sxtw #1]163// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:164 165 166// --------------------------------------------------------------------------//167// Invalid vector + immediate addressing modes168 169st1b z0.s, p0, [z0.s, #-1]170// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].171// CHECK-NEXT: st1b z0.s, p0, [z0.s, #-1]172// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:173 174st1b z0.s, p0, [z0.s, #32]175// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].176// CHECK-NEXT: st1b z0.s, p0, [z0.s, #32]177// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:178 179st1b z0.d, p0, [z0.d, #-1]180// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].181// CHECK-NEXT: st1b z0.d, p0, [z0.d, #-1]182// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:183 184st1b z0.d, p0, [z0.d, #32]185// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].186// CHECK-NEXT: st1b z0.d, p0, [z0.d, #32]187// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:188 189 190// --------------------------------------------------------------------------//191// Negative tests for instructions that are incompatible with movprfx192 193movprfx z31.d, p7/z, z6.d194st1b { z31.d }, p7, [z31.d, #31]195// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov196// CHECK-NEXT: st1b { z31.d }, p7, [z31.d, #31]197// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:198 199movprfx z31, z6200st1b { z31.d }, p7, [z31.d, #31]201// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov202// CHECK-NEXT: st1b { z31.d }, p7, [z31.d, #31]203// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:204