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1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s2 3 4// --------------------------------------------------------------------------//5// Immediate out of lower bound [-32, 28].6 7st4w {z12.s, z13.s, z14.s, z15.s}, p4, [x12, #-36, MUL VL]8// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28].9// CHECK-NEXT: st4w {z12.s, z13.s, z14.s, z15.s}, p4, [x12, #-36, MUL VL]10// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:11 12st4w {z7.s, z8.s, z9.s, z10.s}, p3, [x1, #32, MUL VL]13// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28].14// CHECK-NEXT: st4w {z7.s, z8.s, z9.s, z10.s}, p3, [x1, #32, MUL VL]15// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:16 17 18// --------------------------------------------------------------------------//19// Immediate not a multiple of four.20 21st4w {z12.s, z13.s, z14.s, z15.s}, p4, [x12, #-7, MUL VL]22// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28].23// CHECK-NEXT: st4w {z12.s, z13.s, z14.s, z15.s}, p4, [x12, #-7, MUL VL]24// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:25 26st4w {z7.s, z8.s, z9.s, z10.s}, p3, [x1, #5, MUL VL]27// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28].28// CHECK-NEXT: st4w {z7.s, z8.s, z9.s, z10.s}, p3, [x1, #5, MUL VL]29// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:30 31 32// --------------------------------------------------------------------------//33// Invalid scalar + scalar addressing modes34 35st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, x0]36// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'37// CHECK-NEXT: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, x0]38// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:39 40st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, xzr]41// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'42// CHECK-NEXT: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, xzr]43// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:44 45st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, x0, lsl #3]46// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'47// CHECK-NEXT: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, x0, lsl #3]48// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:49 50st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, w0]51// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'52// CHECK-NEXT: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, w0]53// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:54 55st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, w0, uxtw]56// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'57// CHECK-NEXT: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, w0, uxtw]58// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:59 60 61// --------------------------------------------------------------------------//62// Invalid predicate63 64st4w {z2.s, z3.s, z4.s, z5.s}, p8, [x15, #10, MUL VL]65// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)66// CHECK-NEXT: st4w {z2.s, z3.s, z4.s, z5.s}, p8, [x15, #10, MUL VL]67// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:68 69st4w {z2.s, z3.s, z4.s, z5.s}, p7.b, [x15, #10, MUL VL]70// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)71// CHECK-NEXT: st4w {z2.s, z3.s, z4.s, z5.s}, p7.b, [x15, #10, MUL VL]72// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:73 74st4w {z2.s, z3.s, z4.s, z5.s}, p7.q, [x15, #10, MUL VL]75// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)76// CHECK-NEXT: st4w {z2.s, z3.s, z4.s, z5.s}, p7.q, [x15, #10, MUL VL]77// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:78 79 80// --------------------------------------------------------------------------//81// Invalid vector list.82 83st4w { }, p0, [x0]84// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected85// CHECK-NEXT: st4w { }, p0, [x0]86// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:87 88st4w { z0.s, z1.s, z2.s, z3.s, z4.s }, p0, [x0]89// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors90// CHECK-NEXT: st4w { z0.s, z1.s, z2.s, z3.s, z4.s }, p0, [x0]91// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:92 93st4w { z0.s, z1.s, z2.s, z3.d }, p0, [x0]94// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix95// CHECK-NEXT: st4w { z0.s, z1.s, z2.s, z3.d }, p0, [x0]96// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:97 98st4w { z0.s, z1.s, z3.s, z5.s }, p0, [x0]99// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride100// CHECK-NEXT: st4w { z0.s, z1.s, z3.s, z5.s }, p0, [x0]101// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:102 103st4w { v0.4s, v1.4s, v2.4s }, p0, [x0]104// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand105// CHECK-NEXT: st4w { v0.4s, v1.4s, v2.4s }, p0, [x0]106// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:107 108 109// --------------------------------------------------------------------------//110// Negative tests for instructions that are incompatible with movprfx111 112movprfx z21.s, p5/z, z28.s113st4w { z21.s, z22.s, z23.s, z24.s }, p5, [x10, #20, mul vl]114// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov115// CHECK-NEXT: st4w { z21.s, z22.s, z23.s, z24.s }, p5, [x10, #20, mul vl]116// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:117 118movprfx z21, z28119st4w { z21.s, z22.s, z23.s, z24.s }, p5, [x10, #20, mul vl]120// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov121// CHECK-NEXT: st4w { z21.s, z22.s, z23.s, z24.s }, p5, [x10, #20, mul vl]122// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:123