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1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s2 3// --------------------------------------------------------------------------//4// Source and Destination Registers must match5 6fmaxp z0.h, p0/m, z1.h, z2.h7// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register8// CHECK-NEXT: fmaxp z0.h, p0/m, z1.h, z2.h9// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:10 11 12// --------------------------------------------------------------------------//13// Invalid element width14 15fmaxp z0.b, p0/m, z0.b, z1.b16// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width17// CHECK-NEXT: fmaxp z0.b, p0/m, z0.b, z1.b18// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:19 20 21// --------------------------------------------------------------------------//22// Element sizes must match23 24fmaxp z0.h, p0/m, z0.s, z1.s25// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width26// CHECK-NEXT: fmaxp z0.h, p0/m, z0.s, z1.s27// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:28 29fmaxp z0.h, p0/m, z0.h, z1.s30// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width31// CHECK-NEXT: fmaxp z0.h, p0/m, z0.h, z1.s32// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:33 34 35// --------------------------------------------------------------------------//36// Invalid predicate operation37 38fmaxp z0.h, p0/z, z0.h, z1.h39// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction40// CHECK-NEXT: fmaxp z0.h, p0/z, z0.h, z1.h41// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:42 43 44// --------------------------------------------------------------------------//45// Predicate not in restricted predicate range46 47fmaxp z0.h, p8/m, z0.h, z1.h48// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)49// CHECK-NEXT: fmaxp z0.h, p8/m, z0.h, z1.h50// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:51