38 lines · plain
1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s2 3// --------------------------------------------------------------------------//4// Source and Destination Registers must match5 6sminp z0.b, p0/m, z1.b, z2.b7// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register8// CHECK-NEXT: sminp z0.b, p0/m, z1.b, z2.b9// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:10 11 12// --------------------------------------------------------------------------//13// Element sizes must match14 15sminp z0.b, p0/m, z0.d, z1.d16// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width17// CHECK-NEXT: sminp z0.b, p0/m, z0.d, z1.d18// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:19 20sminp z0.b, p0/m, z0.b, z1.h21// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width22// CHECK-NEXT: sminp z0.b, p0/m, z0.b, z1.h23// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:24 25 26// --------------------------------------------------------------------------//27// Invalid predicate28 29sminp z0.b, p0/z, z0.b, z1.b30// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction31// CHECK-NEXT: sminp z0.b, p0/z, z0.b, z1.b32// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:33 34sminp z0.b, p8/m, z0.b, z1.b35// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)36// CHECK-NEXT: sminp z0.b, p8/m, z0.b, z1.b37// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:38