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1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1,+sve-b16b16 2>&1 < %s | FileCheck %s2 3// --------------------------------------------------------------------------//4// Invalid predicate register5 6bfmax z23.h, p8/m, z23.h, z13.h7// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)8// CHECK-NEXT: bfmax z23.h, p8/m, z23.h, z13.h9// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:10 11bfmax z23.h, p1/z, z23.h, z13.h12// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction13// CHECK-NEXT: bfmax z23.h, p1/z, z23.h, z13.h14// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:15 16// --------------------------------------------------------------------------//17// Invalid vector suffix18 19bfmax z23.h, p1/z, z23.s, z13.s20// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction21// CHECK-NEXT: bfmax z23.h, p1/z, z23.s, z13.s22// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:23 24bfmax z23.s, z23.h, z13.h25// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width26// CHECK-NEXT: bfmax z23.s, z23.h, z13.h27// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:28